drivers/mtd/nand/rtc_from4.c

   1 /*
   2  *  drivers/mtd/nand/rtc_from4.c
   3  *
   4  *  Copyright (C) 2004  Red Hat, Inc.
   5  *
   6  *  Derived from drivers/mtd/nand/spia.c
   7  *       Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
   8  *
   9  * $Id: rtc_from4.c,v 1.10 2005/11/07 11:14:31 gleixner Exp $
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  *
  15  * Overview:
  16  *   This is a device driver for the AG-AND flash device found on the
  17  *   Renesas Technology Corp. Flash ROM 4-slot interface board (FROM_BOARD4),
  18  *   which utilizes the Renesas HN29V1G91T-30 part.
  19  *   This chip is a 1 GBibit (128MiB x 8 bits) AG-AND flash device.
  20  */
  21
  22 #include <linux/delay.h>
  23 #include <linux/kernel.h>
  24 #include <linux/init.h>
  25 #include <linux/slab.h>
  26 #include <linux/rslib.h>
  27 #include <linux/module.h>
  28 #include <linux/mtd/compatmac.h>
  29 #include <linux/mtd/mtd.h>
  30 #include <linux/mtd/nand.h>
  31 #include <linux/mtd/partitions.h>
  32 #include <asm/io.h>
  33
  34 /*
  35  * MTD structure for Renesas board
  36  */
  37 static struct mtd_info *rtc_from4_mtd = NULL;
  38
  39 #define RTC_FROM4_MAX_CHIPS     2
  40
  41 /* HS77x9 processor register defines */
  42 #define SH77X9_BCR1     ((volatile unsigned short *)(0xFFFFFF60))
  43 #define SH77X9_BCR2     ((volatile unsigned short *)(0xFFFFFF62))
  44 #define SH77X9_WCR1     ((volatile unsigned short *)(0xFFFFFF64))
  45 #define SH77X9_WCR2     ((volatile unsigned short *)(0xFFFFFF66))
  46 #define SH77X9_MCR      ((volatile unsigned short *)(0xFFFFFF68))
  47 #define SH77X9_PCR      ((volatile unsigned short *)(0xFFFFFF6C))
  48 #define SH77X9_FRQCR    ((volatile unsigned short *)(0xFFFFFF80))
  49
  50 /*
  51  * Values specific to the Renesas Technology Corp. FROM_BOARD4 (used with HS77x9 processor)
  52  */
  53 /* Address where flash is mapped */
  54 #define RTC_FROM4_FIO_BASE      0x14000000
  55
  56 /* CLE and ALE are tied to address lines 5 & 4, respectively */
  57 #define RTC_FROM4_CLE           (1 << 5)
  58 #define RTC_FROM4_ALE           (1 << 4)
  59
  60 /* address lines A24-A22 used for chip selection */
  61 #define RTC_FROM4_NAND_ADDR_SLOT3       (0x00800000)
  62 #define RTC_FROM4_NAND_ADDR_SLOT4       (0x00C00000)
  63 #define RTC_FROM4_NAND_ADDR_FPGA        (0x01000000)
  64 /* mask address lines A24-A22 used for chip selection */
  65 #define RTC_FROM4_NAND_ADDR_MASK        (RTC_FROM4_NAND_ADDR_SLOT3 | RTC_FROM4_NAND_ADDR_SLOT4 | RTC_FROM4_NAND_ADDR_FPGA)
  66
  67 /* FPGA status register for checking device ready (bit zero) */
  68 #define RTC_FROM4_FPGA_SR               (RTC_FROM4_NAND_ADDR_FPGA | 0x00000002)
  69 #define RTC_FROM4_DEVICE_READY          0x0001
  70
  71 /* FPGA Reed-Solomon ECC Control register */
  72
  73 #define RTC_FROM4_RS_ECC_CTL            (RTC_FROM4_NAND_ADDR_FPGA | 0x00000050)
  74 #define RTC_FROM4_RS_ECC_CTL_CLR        (1 << 7)
  75 #define RTC_FROM4_RS_ECC_CTL_GEN        (1 << 6)
  76 #define RTC_FROM4_RS_ECC_CTL_FD_E       (1 << 5)
  77
  78 /* FPGA Reed-Solomon ECC code base */
  79 #define RTC_FROM4_RS_ECC                (RTC_FROM4_NAND_ADDR_FPGA | 0x00000060)
  80 #define RTC_FROM4_RS_ECCN               (RTC_FROM4_NAND_ADDR_FPGA | 0x00000080)
  81
  82 /* FPGA Reed-Solomon ECC check register */
  83 #define RTC_FROM4_RS_ECC_CHK            (RTC_FROM4_NAND_ADDR_FPGA | 0x00000070)
  84 #define RTC_FROM4_RS_ECC_CHK_ERROR      (1 << 7)
  85
  86 #define ERR_STAT_ECC_AVAILABLE          0x20
  87
  88 /* Undefine for software ECC */
  89 #define RTC_FROM4_HWECC 1
  90
  91 /* Define as 1 for no virtual erase blocks (in JFFS2) */
  92 #define RTC_FROM4_NO_VIRTBLOCKS 0
  93
  94 /*
  95  * Module stuff
  96  */
  97 static void __iomem *rtc_from4_fio_base = (void *)P2SEGADDR(RTC_FROM4_FIO_BASE);
  98
  99 static const struct mtd_partition partition_info[] = {
 100         {
 101          .name = "Renesas flash partition 1",
 102          .offset = 0,
 103          .size = MTDPART_SIZ_FULL},
 104 };
 105
 106 #define NUM_PARTITIONS 1
 107
 108 /*
 109  *      hardware specific flash bbt decriptors
 110  *      Note: this is to allow debugging by disabling
 111  *              NAND_BBT_CREATE and/or NAND_BBT_WRITE
 112  *
 113  */
 114 static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' };
 115 static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' };
 116
 117 static struct nand_bbt_descr rtc_from4_bbt_main_descr = {
 118         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
 119                 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
 120         .offs = 40,
 121         .len = 4,
 122         .veroffs = 44,
 123         .maxblocks = 4,
 124         .pattern = bbt_pattern
 125 };
 126
 127 static struct nand_bbt_descr rtc_from4_bbt_mirror_descr = {
 128         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
 129                 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
 130         .offs = 40,
 131         .len = 4,
 132         .veroffs = 44,
 133         .maxblocks = 4,
 134         .pattern = mirror_pattern
 135 };
 136
 137 #ifdef RTC_FROM4_HWECC
 138
 139 /* the Reed Solomon control structure */
 140 static struct rs_control *rs_decoder;
 141
 142 /*
 143  *      hardware specific Out Of Band information
 144  */
 145 static struct nand_ecclayout rtc_from4_nand_oobinfo = {
 146         .eccbytes = 32,
 147         .eccpos = {
 148                    0, 1, 2, 3, 4, 5, 6, 7,
 149                    8, 9, 10, 11, 12, 13, 14, 15,
 150                    16, 17, 18, 19, 20, 21, 22, 23,
 151                    24, 25, 26, 27, 28, 29, 30, 31},
 152         .oobfree = {{32, 32}}
 153 };
 154
 155 /* Aargh. I missed the reversed bit order, when I
 156  * was talking to Renesas about the FPGA.
 157  *
 158  * The table is used for bit reordering and inversion
 159  * of the ecc byte which we get from the FPGA
 160  */
 161 static uint8_t revbits[256] = {
 162         0x00, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0,
 163         0x10, 0x90, 0x50, 0xd0, 0x30, 0xb0, 0x70, 0xf0,
 164         0x08, 0x88, 0x48, 0xc8, 0x28, 0xa8, 0x68, 0xe8,
 165         0x18, 0x98, 0x58, 0xd8, 0x38, 0xb8, 0x78, 0xf8,
 166         0x04, 0x84, 0x44, 0xc4, 0x24, 0xa4, 0x64, 0xe4,
 167         0x14, 0x94, 0x54, 0xd4, 0x34, 0xb4, 0x74, 0xf4,
 168         0x0c, 0x8c, 0x4c, 0xcc, 0x2c, 0xac, 0x6c, 0xec,
 169         0x1c, 0x9c, 0x5c, 0xdc, 0x3c, 0xbc, 0x7c, 0xfc,
 170         0x02, 0x82, 0x42, 0xc2, 0x22, 0xa2, 0x62, 0xe2,
 171         0x12, 0x92, 0x52, 0xd2, 0x32, 0xb2, 0x72, 0xf2,
 172         0x0a, 0x8a, 0x4a, 0xca, 0x2a, 0xaa, 0x6a, 0xea,
 173         0x1a, 0x9a, 0x5a, 0xda, 0x3a, 0xba, 0x7a, 0xfa,
 174         0x06, 0x86, 0x46, 0xc6, 0x26, 0xa6, 0x66, 0xe6,
 175         0x16, 0x96, 0x56, 0xd6, 0x36, 0xb6, 0x76, 0xf6,
 176         0x0e, 0x8e, 0x4e, 0xce, 0x2e, 0xae, 0x6e, 0xee,
 177         0x1e, 0x9e, 0x5e, 0xde, 0x3e, 0xbe, 0x7e, 0xfe,
 178         0x01, 0x81, 0x41, 0xc1, 0x21, 0xa1, 0x61, 0xe1,
 179         0x11, 0x91, 0x51, 0xd1, 0x31, 0xb1, 0x71, 0xf1,
 180         0x09, 0x89, 0x49, 0xc9, 0x29, 0xa9, 0x69, 0xe9,
 181         0x19, 0x99, 0x59, 0xd9, 0x39, 0xb9, 0x79, 0xf9,
 182         0x05, 0x85, 0x45, 0xc5, 0x25, 0xa5, 0x65, 0xe5,
 183         0x15, 0x95, 0x55, 0xd5, 0x35, 0xb5, 0x75, 0xf5,
 184         0x0d, 0x8d, 0x4d, 0xcd, 0x2d, 0xad, 0x6d, 0xed,
 185         0x1d, 0x9d, 0x5d, 0xdd, 0x3d, 0xbd, 0x7d, 0xfd,
 186         0x03, 0x83, 0x43, 0xc3, 0x23, 0xa3, 0x63, 0xe3,
 187         0x13, 0x93, 0x53, 0xd3, 0x33, 0xb3, 0x73, 0xf3,
 188         0x0b, 0x8b, 0x4b, 0xcb, 0x2b, 0xab, 0x6b, 0xeb,
 189         0x1b, 0x9b, 0x5b, 0xdb, 0x3b, 0xbb, 0x7b, 0xfb,
 190         0x07, 0x87, 0x47, 0xc7, 0x27, 0xa7, 0x67, 0xe7,
 191         0x17, 0x97, 0x57, 0xd7, 0x37, 0xb7, 0x77, 0xf7,
 192         0x0f, 0x8f, 0x4f, 0xcf, 0x2f, 0xaf, 0x6f, 0xef,
 193         0x1f, 0x9f, 0x5f, 0xdf, 0x3f, 0xbf, 0x7f, 0xff,
 194 };
 195
 196 #endif
 197
 198 /*
 199  * rtc_from4_hwcontrol - hardware specific access to control-lines
 200  * @mtd:        MTD device structure
 201  * @cmd:        hardware control command
 202  *
 203  * Address lines (A5 and A4) are used to control Command and Address Latch
 204  * Enable on this board, so set the read/write address appropriately.
 205  *
 206  * Chip Enable is also controlled by the Chip Select (CS5) and
 207  * Address lines (A24-A22), so no action is required here.
 208  *
 209  */
 210 static void rtc_from4_hwcontrol(struct mtd_info *mtd, int cmd,
 211                                 unsigned int ctrl)
 212 {
 213         struct nand_chip *chip = (mtd->priv);
 214
 215         if (cmd == NAND_CMD_NONE)
 216                 return;
 217
 218         if (ctrl & NAND_CLE)
 219                 writeb(cmd, chip->IO_ADDR_W | RTC_FROM4_CLE);
 220         else
 221                 writeb(cmd, chip->IO_ADDR_W | RTC_FROM4_ALE);
 222 }
 223
 224 /*
 225  * rtc_from4_nand_select_chip - hardware specific chip select
 226  * @mtd:        MTD device structure
 227  * @chip:       Chip to select (0 == slot 3, 1 == slot 4)
 228  *
 229  * The chip select is based on address lines A24-A22.
 230  * This driver uses flash slots 3 and 4 (A23-A22).
 231  *
 232  */
 233 static void rtc_from4_nand_select_chip(struct mtd_info *mtd, int chip)
 234 {
 235         struct nand_chip *this = mtd->priv;
 236
 237         this->IO_ADDR_R = (void __iomem *)((unsigned long)this->IO_ADDR_R & ~RTC_FROM4_NAND_ADDR_MASK);
 238         this->IO_ADDR_W = (void __iomem *)((unsigned long)this->IO_ADDR_W & ~RTC_FROM4_NAND_ADDR_MASK);
 239
 240         switch (chip) {
 241
 242         case 0:         /* select slot 3 chip */
 243                 this->IO_ADDR_R = (void __iomem *)((unsigned long)this->IO_ADDR_R | RTC_FROM4_NAND_ADDR_SLOT3);
 244                 this->IO_ADDR_W = (void __iomem *)((unsigned long)this->IO_ADDR_W | RTC_FROM4_NAND_ADDR_SLOT3);
 245                 break;
 246         case 1:         /* select slot 4 chip */
 247                 this->IO_ADDR_R = (void __iomem *)((unsigned long)this->IO_ADDR_R | RTC_FROM4_NAND_ADDR_SLOT4);
 248                 this->IO_ADDR_W = (void __iomem *)((unsigned long)this->IO_ADDR_W | RTC_FROM4_NAND_ADDR_SLOT4);
 249                 break;
 250
 251         }
 252 }
 253
 254 /*
 255  * rtc_from4_nand_device_ready - hardware specific ready/busy check
 256  * @mtd:        MTD device structure
 257  *
 258  * This board provides the Ready/Busy state in the status register
 259  * of the FPGA.  Bit zero indicates the RDY(1)/BSY(0) signal.
 260  *
 261  */
 262 static int rtc_from4_nand_device_ready(struct mtd_info *mtd)
 263 {
 264         unsigned short status;
 265
 266         status = *((volatile unsigned short *)(rtc_from4_fio_base + RTC_FROM4_FPGA_SR));
 267
 268         return (status & RTC_FROM4_DEVICE_READY);
 269
 270 }
 271
 272 /*
 273  * deplete - code to perform device recovery in case there was a power loss
 274  * @mtd:        MTD device structure
 275  * @chip:       Chip to select (0 == slot 3, 1 == slot 4)
 276  *
 277  * If there was a sudden loss of power during an erase operation, a
 278  * "device recovery" operation must be performed when power is restored
 279  * to ensure correct operation.  This routine performs the required steps
 280  * for the requested chip.
 281  *
 282  * See page 86 of the data sheet for details.
 283  *
 284  */
 285 static void deplete(struct mtd_info *mtd, int chip)
 286 {
 287         struct nand_chip *this = mtd->priv;
 288
 289         /* wait until device is ready */
 290         while (!this->dev_ready(mtd)) ;
 291
 292         this->select_chip(mtd, chip);
 293
 294         /* Send the commands for device recovery, phase 1 */
 295         this->cmdfunc(mtd, NAND_CMD_DEPLETE1, 0x0000, 0x0000);
 296         this->cmdfunc(mtd, NAND_CMD_DEPLETE2, -1, -1);
 297
 298         /* Send the commands for device recovery, phase 2 */
 299         this->cmdfunc(mtd, NAND_CMD_DEPLETE1, 0x0000, 0x0004);
 300         this->cmdfunc(mtd, NAND_CMD_DEPLETE2, -1, -1);
 301
 302 }
 303
 304 #ifdef RTC_FROM4_HWECC
 305 /*
 306  * rtc_from4_enable_hwecc - hardware specific hardware ECC enable function
 307  * @mtd:        MTD device structure
 308  * @mode:       I/O mode; read or write
 309  *
 310  * enable hardware ECC for data read or write
 311  *
 312  */
 313 static void rtc_from4_enable_hwecc(struct mtd_info *mtd, int mode)
 314 {
 315         volatile unsigned short *rs_ecc_ctl = (volatile unsigned short *)(rtc_from4_fio_base + RTC_FROM4_RS_ECC_CTL);
 316         unsigned short status;
 317
 318         switch (mode) {
 319         case NAND_ECC_READ:
 320                 status = RTC_FROM4_RS_ECC_CTL_CLR | RTC_FROM4_RS_ECC_CTL_FD_E;
 321
 322                 *rs_ecc_ctl = status;
 323                 break;
 324
 325         case NAND_ECC_READSYN:
 326                 status = 0x00;
 327
 328                 *rs_ecc_ctl = status;
 329                 break;
 330
 331         case NAND_ECC_WRITE:
 332                 status = RTC_FROM4_RS_ECC_CTL_CLR | RTC_FROM4_RS_ECC_CTL_GEN | RTC_FROM4_RS_ECC_CTL_FD_E;
 333
 334                 *rs_ecc_ctl = status;
 335                 break;
 336
 337         default:
 338                 BUG();
 339                 break;
 340         }
 341
 342 }
 343
 344 /*
 345  * rtc_from4_calculate_ecc - hardware specific code to read ECC code
 346  * @mtd:        MTD device structure
 347  * @dat:        buffer containing the data to generate ECC codes
 348  * @ecc_code    ECC codes calculated
 349  *
 350  * The ECC code is calculated by the FPGA.  All we have to do is read the values
 351  * from the FPGA registers.
 352  *
 353  * Note: We read from the inverted registers, since data is inverted before
 354  * the code is calculated. So all 0xff data (blank page) results in all 0xff rs code
 355  *
 356  */
 357 static void rtc_from4_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
 358 {
 359         volatile unsigned short *rs_eccn = (volatile unsigned short *)(rtc_from4_fio_base + RTC_FROM4_RS_ECCN);
 360         unsigned short value;
 361         int i;
 362
 363         for (i = 0; i < 8; i++) {
 364                 value = *rs_eccn;
 365                 ecc_code[i] = (unsigned char)value;
 366                 rs_eccn++;
 367         }
 368         ecc_code[7] |= 0x0f;    /* set the last four bits (not used) */
 369 }
 370
 371 /*
 372  * rtc_from4_correct_data - hardware specific code to correct data using ECC code
 373  * @mtd:        MTD device structure
 374  * @buf:        buffer containing the data to generate ECC codes
 375  * @ecc1        ECC codes read
 376  * @ecc2        ECC codes calculated
 377  *
 378  * The FPGA tells us fast, if there's an error or not. If no, we go back happy
 379  * else we read the ecc results from the fpga and call the rs library to decode
 380  * and hopefully correct the error.
 381  *
 382  */
 383 static int rtc_from4_correct_data(struct mtd_info *mtd, const u_char *buf, u_char *ecc1, u_char *ecc2)
 384 {
 385         int i, j, res;
 386         unsigned short status;
 387         uint16_t par[6], syn[6];
 388         uint8_t ecc[8];
 389         volatile unsigned short *rs_ecc;
 390
 391         status = *((volatile unsigned short *)(rtc_from4_fio_base + RTC_FROM4_RS_ECC_CHK));
 392
 393         if (!(status & RTC_FROM4_RS_ECC_CHK_ERROR)) {
 394                 return 0;
 395         }
 396
 397         /* Read the syndrom pattern from the FPGA and correct the bitorder */
 398         rs_ecc = (volatile unsigned short *)(rtc_from4_fio_base + RTC_FROM4_RS_ECC);
 399         for (i = 0; i < 8; i++) {
 400                 ecc[i] = revbits[(*rs_ecc) & 0xFF];
 401                 rs_ecc++;
 402         }
 403
 404         /* convert into 6 10bit syndrome fields */
 405         par[5] = rs_decoder->index_of[(((uint16_t) ecc[0] >> 0) & 0x0ff) | (((uint16_t) ecc[1] << 8) & 0x300)];
 406         par[4] = rs_decoder->index_of[(((uint16_t) ecc[1] >> 2) & 0x03f) | (((uint16_t) ecc[2] << 6) & 0x3c0)];
 407         par[3] = rs_decoder->index_of[(((uint16_t) ecc[2] >> 4) & 0x00f) | (((uint16_t) ecc[3] << 4) & 0x3f0)];
 408         par[2] = rs_decoder->index_of[(((uint16_t) ecc[3] >> 6) & 0x003) | (((uint16_t) ecc[4] << 2) & 0x3fc)];
 409         par[1] = rs_decoder->index_of[(((uint16_t) ecc[5] >> 0) & 0x0ff) | (((uint16_t) ecc[6] << 8) & 0x300)];
 410         par[0] = (((uint16_t) ecc[6] >> 2) & 0x03f) | (((uint16_t) ecc[7] << 6) & 0x3c0);
 411
 412         /* Convert to computable syndrome */
 413         for (i = 0; i < 6; i++) {
 414                 syn[i] = par[0];
 415                 for (j = 1; j < 6; j++)
 416                         if (par[j] != rs_decoder->nn)
 417                                 syn[i] ^= rs_decoder->alpha_to[rs_modnn(rs_decoder, par[j] + i * j)];
 418
 419                 /* Convert to index form */
 420                 syn[i] = rs_decoder->index_of[syn[i]];
 421         }
 422
 423         /* Let the library code do its magic. */
 424         res = decode_rs8(rs_decoder, (uint8_t *) buf, par, 512, syn, 0, NULL, 0xff, NULL);
 425         if (res > 0) {
 426                 DEBUG(MTD_DEBUG_LEVEL0, "rtc_from4_correct_data: " "ECC corrected %d errors on read\n", res);
 427         }
 428         return res;
 429 }
 430
 431 /**
 432  * rtc_from4_errstat - perform additional error status checks
 433  * @mtd:        MTD device structure
 434  * @this:       NAND chip structure
 435  * @state:      state or the operation
 436  * @status:     status code returned from read status
 437  * @page:       startpage inside the chip, must be called with (page & this->pagemask)
 438  *
 439  * Perform additional error status checks on erase and write failures
 440  * to determine if errors are correctable.  For this device, correctable
 441  * 1-bit errors on erase and write are considered acceptable.
 442  *
 443  * note: see pages 34..37 of data sheet for details.
 444  *
 445  */
 446 static int rtc_from4_errstat(struct mtd_info *mtd, struct nand_chip *this,
 447                              int state, int status, int page)
 448 {
 449         int er_stat = 0;
 450         int rtn, retlen;
 451         size_t len;
 452         uint8_t *buf;
 453         int i;
 454
 455         this->cmdfunc(mtd, NAND_CMD_STATUS_CLEAR, -1, -1);
 456
 457         if (state == FL_ERASING) {
 458
 459                 for (i = 0; i < 4; i++) {
 460                         if (!(status & 1 << (i + 1)))
 461                                 continue;
 462                         this->cmdfunc(mtd, (NAND_CMD_STATUS_ERROR + i + 1),
 463                                       -1, -1);
 464                         rtn = this->read_byte(mtd);
 465                         this->cmdfunc(mtd, NAND_CMD_STATUS_RESET, -1, -1);
 466
 467                         /* err_ecc_not_avail */
 468                         if (!(rtn & ERR_STAT_ECC_AVAILABLE))
 469                                 er_stat |= 1 << (i + 1);
 470                 }
 471
 472         } else if (state == FL_WRITING) {
 473
 474                 unsigned long corrected = mtd->ecc_stats.corrected;
 475
 476                 /* single bank write logic */
 477                 this->cmdfunc(mtd, NAND_CMD_STATUS_ERROR, -1, -1);
 478                 rtn = this->read_byte(mtd);
 479                 this->cmdfunc(mtd, NAND_CMD_STATUS_RESET, -1, -1);
 480
 481                 if (!(rtn & ERR_STAT_ECC_AVAILABLE)) {
 482                         /* err_ecc_not_avail */
 483                         er_stat |= 1 << 1;
 484                         goto out;
 485                 }
 486
 487                 len = mtd->writesize;
 488                 buf = kmalloc(len, GFP_KERNEL);
 489                 if (!buf) {
 490                         printk(KERN_ERR "rtc_from4_errstat: Out of memory!\n");
 491                         er_stat = 1;
 492                         goto out;
 493                 }
 494
 495                 /* recovery read */
 496                 rtn = nand_do_read(mtd, page, len, &retlen, buf);
 497
 498                 /* if read failed or > 1-bit error corrected */
 499                 if (rtn || (mtd->ecc_stats.corrected - corrected) > 1) {
 500                         er_stat |= 1 << 1;
 501                 kfree(buf);
 502         }
 503
 504         rtn = status;
 505         if (er_stat == 0) {     /* if ECC is available   */
 506                 rtn = (status & ~NAND_STATUS_FAIL);     /*   clear the error bit */
 507         }
 508
 509         return rtn;
 510 }
 511 #endif
 512
 513 /*
 514  * Main initialization routine
 515  */
 516 static int __init rtc_from4_init(void)
 517 {
 518         struct nand_chip *this;
 519         unsigned short bcr1, bcr2, wcr2;
 520         int i;
 521
 522         /* Allocate memory for MTD device structure and private data */
 523         rtc_from4_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL);
 524         if (!rtc_from4_mtd) {
 525                 printk("Unable to allocate Renesas NAND MTD device structure.\n");
 526                 return -ENOMEM;
 527         }
 528
 529         /* Get pointer to private data */
 530         this = (struct nand_chip *)(&rtc_from4_mtd[1]);
 531
 532         /* Initialize structures */
 533         memset(rtc_from4_mtd, 0, sizeof(struct mtd_info));
 534         memset(this, 0, sizeof(struct nand_chip));
 535
 536         /* Link the private data with the MTD structure */
 537         rtc_from4_mtd->priv = this;
 538         rtc_from4_mtd->owner = THIS_MODULE;
 539
 540         /* set area 5 as PCMCIA mode to clear the spec of tDH(Data hold time;9ns min) */
 541         bcr1 = *SH77X9_BCR1 & ~0x0002;
 542         bcr1 |= 0x0002;
 543         *SH77X9_BCR1 = bcr1;
 544
 545         /* set */
 546         bcr2 = *SH77X9_BCR2 & ~0x0c00;
 547         bcr2 |= 0x0800;
 548         *SH77X9_BCR2 = bcr2;
 549
 550         /* set area 5 wait states */
 551         wcr2 = *SH77X9_WCR2 & ~0x1c00;
 552         wcr2 |= 0x1c00;
 553         *SH77X9_WCR2 = wcr2;
 554
 555         /* Set address of NAND IO lines */
 556         this->IO_ADDR_R = rtc_from4_fio_base;
 557         this->IO_ADDR_W = rtc_from4_fio_base;
 558         /* Set address of hardware control function */
 559         this->cmd_ctrl = rtc_from4_hwcontrol;
 560         /* Set address of chip select function */
 561         this->select_chip = rtc_from4_nand_select_chip;
 562         /* command delay time (in us) */
 563         this->chip_delay = 100;
 564         /* return the status of the Ready/Busy line */
 565         this->dev_ready = rtc_from4_nand_device_ready;
 566
 567 #ifdef RTC_FROM4_HWECC
 568         printk(KERN_INFO "rtc_from4_init: using hardware ECC detection.\n");
 569
 570         this->ecc.mode = NAND_ECC_HW_SYNDROME;
 571         this->ecc.size = 512;
 572         this->ecc.bytes = 8;
 573         /* return the status of extra status and ECC checks */
 574         this->errstat = rtc_from4_errstat;
 575         /* set the nand_oobinfo to support FPGA H/W error detection */
 576         this->ecc.layout = &rtc_from4_nand_oobinfo;
 577         this->ecc.hwctl = rtc_from4_enable_hwecc;
 578         this->ecc.calculate = rtc_from4_calculate_ecc;
 579         this->ecc.correct = rtc_from4_correct_data;
 580 #else
 581         printk(KERN_INFO "rtc_from4_init: using software ECC detection.\n");
 582
 583         this->ecc.mode = NAND_ECC_SOFT;
 584 #endif
 585
 586         /* set the bad block tables to support debugging */
 587         this->bbt_td = &rtc_from4_bbt_main_descr;
 588         this->bbt_md = &rtc_from4_bbt_mirror_descr;
 589
 590         /* Scan to find existence of the device */
 591         if (nand_scan(rtc_from4_mtd, RTC_FROM4_MAX_CHIPS)) {
 592                 kfree(rtc_from4_mtd);
 593                 return -ENXIO;
 594         }
 595
 596         /* Perform 'device recovery' for each chip in case there was a power loss. */
 597         for (i = 0; i < this->numchips; i++) {
 598                 deplete(rtc_from4_mtd, i);
 599         }
 600
 601 #if RTC_FROM4_NO_VIRTBLOCKS
 602         /* use a smaller erase block to minimize wasted space when a block is bad */
 603         /* note: this uses eight times as much RAM as using the default and makes */
 604         /*       mounts take four times as long. */
 605         rtc_from4_mtd->flags |= MTD_NO_VIRTBLOCKS;
 606 #endif
 607
 608         /* Register the partitions */
 609         add_mtd_partitions(rtc_from4_mtd, partition_info, NUM_PARTITIONS);
 610
 611 #ifdef RTC_FROM4_HWECC
 612         /* We could create the decoder on demand, if memory is a concern.
 613          * This way we have it handy, if an error happens
 614          *
 615          * Symbolsize is 10 (bits)
 616          * Primitve polynomial is x^10+x^3+1
 617          * first consecutive root is 0
 618          * primitve element to generate roots = 1
 619          * generator polinomial degree = 6
 620          */
 621         rs_decoder = init_rs(10, 0x409, 0, 1, 6);
 622         if (!rs_decoder) {
 623                 printk(KERN_ERR "Could not create a RS decoder\n");
 624                 nand_release(rtc_from4_mtd);
 625                 kfree(rtc_from4_mtd);
 626                 return -ENOMEM;
 627         }
 628 #endif
 629         /* Return happy */
 630         return 0;
 631 }
 632
 633 module_init(rtc_from4_init);
 634
 635 /*
 636  * Clean up routine
 637  */
 638 static void __exit rtc_from4_cleanup(void)
 639 {
 640         /* Release resource, unregister partitions */
 641         nand_release(rtc_from4_mtd);
 642
 643         /* Free the MTD device structure */
 644         kfree(rtc_from4_mtd);
 645
 646 #ifdef RTC_FROM4_HWECC
 647         /* Free the reed solomon resources */
 648         if (rs_decoder) {
 649                 free_rs(rs_decoder);
 650         }
 651 #endif
 652 }
 653
 654 module_exit(rtc_from4_cleanup);
 655
 656 MODULE_LICENSE("GPL");
 657 MODULE_AUTHOR("d.marlin <dmarlin@redhat.com");
 658 MODULE_DESCRIPTION("Board-specific glue layer for AG-AND flash on Renesas FROM_BOARD4");