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[PATCH] x86-64: Extend clear_irq_vector
[linux-2.6/verdex.git] / arch / x86_64 / kernel / io_apic.c
blobf71461b1f03d13bc8c5650964ac31ce6c166f4dd
1 /*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
22
23 #include <linux/mm.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/smp_lock.h>
29 #include <linux/pci.h>
30 #include <linux/mc146818rtc.h>
31 #include <linux/acpi.h>
32 #include <linux/sysdev.h>
33 #include <linux/msi.h>
34 #include <linux/htirq.h>
35 #ifdef CONFIG_ACPI
36 #include <acpi/acpi_bus.h>
37 #endif
38
39 #include <asm/io.h>
40 #include <asm/smp.h>
41 #include <asm/desc.h>
42 #include <asm/proto.h>
43 #include <asm/mach_apic.h>
44 #include <asm/acpi.h>
45 #include <asm/dma.h>
46 #include <asm/nmi.h>
47 #include <asm/msidef.h>
48 #include <asm/hypertransport.h>
49
50 static int assign_irq_vector(int irq, cpumask_t mask, cpumask_t *result);
51
52 #define __apicdebuginit __init
53
54 int sis_apic_bug; /* not actually supported, dummy for compile */
55
56 static int no_timer_check;
57
58 static int disable_timer_pin_1 __initdata;
59
60 int timer_over_8254 __initdata = 1;
61
62 /* Where if anywhere is the i8259 connect in external int mode */
63 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
64
65 static DEFINE_SPINLOCK(ioapic_lock);
66 DEFINE_SPINLOCK(vector_lock);
67
68 /*
69 * # of IRQ routing registers
70 */
71 int nr_ioapic_registers[MAX_IO_APICS];
72
73 /*
74 * Rough estimation of how many shared IRQs there are, can
75 * be changed anytime.
76 */
77 #define MAX_PLUS_SHARED_IRQS NR_IRQ_VECTORS
78 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
79
80 /*
81 * This is performance-critical, we want to do it O(1)
82 *
83 * the indexing order of this array favors 1:1 mappings
84 * between pins and IRQs.
85 */
86
87 static struct irq_pin_list {
88 short apic, pin, next;
89 } irq_2_pin[PIN_MAP_SIZE];
90
91 struct io_apic {
92 unsigned int index;
93 unsigned int unused[3];
94 unsigned int data;
95 };
96
97 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
98 {
99 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
100 + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK);
101 }
102
103 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
104 {
105 struct io_apic __iomem *io_apic = io_apic_base(apic);
106 writel(reg, &io_apic->index);
107 return readl(&io_apic->data);
108 }
109
110 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
111 {
112 struct io_apic __iomem *io_apic = io_apic_base(apic);
113 writel(reg, &io_apic->index);
114 writel(value, &io_apic->data);
115 }
116
117 /*
118 * Re-write a value: to be used for read-modify-write
119 * cycles where the read already set up the index register.
120 */
121 static inline void io_apic_modify(unsigned int apic, unsigned int value)
122 {
123 struct io_apic __iomem *io_apic = io_apic_base(apic);
124 writel(value, &io_apic->data);
125 }
126
127 /*
128 * Synchronize the IO-APIC and the CPU by doing
129 * a dummy read from the IO-APIC
130 */
131 static inline void io_apic_sync(unsigned int apic)
132 {
133 struct io_apic __iomem *io_apic = io_apic_base(apic);
134 readl(&io_apic->data);
135 }
136
137 #define __DO_ACTION(R, ACTION, FINAL) \
138 \
139 { \
140 int pin; \
141 struct irq_pin_list *entry = irq_2_pin + irq; \
142 \
143 BUG_ON(irq >= NR_IRQS); \
144 for (;;) { \
145 unsigned int reg; \
146 pin = entry->pin; \
147 if (pin == -1) \
148 break; \
149 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
150 reg ACTION; \
151 io_apic_modify(entry->apic, reg); \
152 if (!entry->next) \
153 break; \
154 entry = irq_2_pin + entry->next; \
155 } \
156 FINAL; \
157 }
158
159 union entry_union {
160 struct { u32 w1, w2; };
161 struct IO_APIC_route_entry entry;
162 };
163
164 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
165 {
166 union entry_union eu;
167 unsigned long flags;
168 spin_lock_irqsave(&ioapic_lock, flags);
169 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
170 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
171 spin_unlock_irqrestore(&ioapic_lock, flags);
172 return eu.entry;
173 }
174
175 /*
176 * When we write a new IO APIC routing entry, we need to write the high
177 * word first! If the mask bit in the low word is clear, we will enable
178 * the interrupt, and we need to make sure the entry is fully populated
179 * before that happens.
180 */
181 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
182 {
183 unsigned long flags;
184 union entry_union eu;
185 eu.entry = e;
186 spin_lock_irqsave(&ioapic_lock, flags);
187 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
188 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
189 spin_unlock_irqrestore(&ioapic_lock, flags);
190 }
191
192 /*
193 * When we mask an IO APIC routing entry, we need to write the low
194 * word first, in order to set the mask bit before we change the
195 * high bits!
196 */
197 static void ioapic_mask_entry(int apic, int pin)
198 {
199 unsigned long flags;
200 union entry_union eu = { .entry.mask = 1 };
201
202 spin_lock_irqsave(&ioapic_lock, flags);
203 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
204 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
205 spin_unlock_irqrestore(&ioapic_lock, flags);
206 }
207
208 #ifdef CONFIG_SMP
209 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector)
210 {
211 int apic, pin;
212 struct irq_pin_list *entry = irq_2_pin + irq;
213
214 BUG_ON(irq >= NR_IRQS);
215 for (;;) {
216 unsigned int reg;
217 apic = entry->apic;
218 pin = entry->pin;
219 if (pin == -1)
220 break;
221 io_apic_write(apic, 0x11 + pin*2, dest);
222 reg = io_apic_read(apic, 0x10 + pin*2);
223 reg &= ~0x000000ff;
224 reg |= vector;
225 io_apic_modify(apic, reg);
226 if (!entry->next)
227 break;
228 entry = irq_2_pin + entry->next;
229 }
230 }
231
232 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
233 {
234 unsigned long flags;
235 unsigned int dest;
236 cpumask_t tmp;
237 int vector;
238
239 cpus_and(tmp, mask, cpu_online_map);
240 if (cpus_empty(tmp))
241 tmp = TARGET_CPUS;
242
243 cpus_and(mask, tmp, CPU_MASK_ALL);
244
245 vector = assign_irq_vector(irq, mask, &tmp);
246 if (vector < 0)
247 return;
248
249 dest = cpu_mask_to_apicid(tmp);
250
251 /*
252 * Only the high 8 bits are valid.
253 */
254 dest = SET_APIC_LOGICAL_ID(dest);
255
256 spin_lock_irqsave(&ioapic_lock, flags);
257 __target_IO_APIC_irq(irq, dest, vector);
258 set_native_irq_info(irq, mask);
259 spin_unlock_irqrestore(&ioapic_lock, flags);
260 }
261 #endif
262
263 /*
264 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
265 * shared ISA-space IRQs, so we have to support them. We are super
266 * fast in the common case, and fast for shared ISA-space IRQs.
267 */
268 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
269 {
270 static int first_free_entry = NR_IRQS;
271 struct irq_pin_list *entry = irq_2_pin + irq;
272
273 BUG_ON(irq >= NR_IRQS);
274 while (entry->next)
275 entry = irq_2_pin + entry->next;
276
277 if (entry->pin != -1) {
278 entry->next = first_free_entry;
279 entry = irq_2_pin + entry->next;
280 if (++first_free_entry >= PIN_MAP_SIZE)
281 panic("io_apic.c: ran out of irq_2_pin entries!");
282 }
283 entry->apic = apic;
284 entry->pin = pin;
285 }
286
287
288 #define DO_ACTION(name,R,ACTION, FINAL) \
289 \
290 static void name##_IO_APIC_irq (unsigned int irq) \
291 __DO_ACTION(R, ACTION, FINAL)
292
293 DO_ACTION( __mask, 0, |= 0x00010000, io_apic_sync(entry->apic) )
294 /* mask = 1 */
295 DO_ACTION( __unmask, 0, &= 0xfffeffff, )
296 /* mask = 0 */
297
298 static void mask_IO_APIC_irq (unsigned int irq)
299 {
300 unsigned long flags;
301
302 spin_lock_irqsave(&ioapic_lock, flags);
303 __mask_IO_APIC_irq(irq);
304 spin_unlock_irqrestore(&ioapic_lock, flags);
305 }
306
307 static void unmask_IO_APIC_irq (unsigned int irq)
308 {
309 unsigned long flags;
310
311 spin_lock_irqsave(&ioapic_lock, flags);
312 __unmask_IO_APIC_irq(irq);
313 spin_unlock_irqrestore(&ioapic_lock, flags);
314 }
315
316 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
317 {
318 struct IO_APIC_route_entry entry;
319
320 /* Check delivery_mode to be sure we're not clearing an SMI pin */
321 entry = ioapic_read_entry(apic, pin);
322 if (entry.delivery_mode == dest_SMI)
323 return;
324 /*
325 * Disable it in the IO-APIC irq-routing table:
326 */
327 ioapic_mask_entry(apic, pin);
328 }
329
330 static void clear_IO_APIC (void)
331 {
332 int apic, pin;
333
334 for (apic = 0; apic < nr_ioapics; apic++)
335 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
336 clear_IO_APIC_pin(apic, pin);
337 }
338
339 int skip_ioapic_setup;
340 int ioapic_force;
341
342 /* dummy parsing: see setup.c */
343
344 static int __init disable_ioapic_setup(char *str)
345 {
346 skip_ioapic_setup = 1;
347 return 0;
348 }
349 early_param("noapic", disable_ioapic_setup);
350
351 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
352 static int __init disable_timer_pin_setup(char *arg)
353 {
354 disable_timer_pin_1 = 1;
355 return 1;
356 }
357 __setup("disable_timer_pin_1", disable_timer_pin_setup);
358
359 static int __init setup_disable_8254_timer(char *s)
360 {
361 timer_over_8254 = -1;
362 return 1;
363 }
364 static int __init setup_enable_8254_timer(char *s)
365 {
366 timer_over_8254 = 2;
367 return 1;
368 }
369
370 __setup("disable_8254_timer", setup_disable_8254_timer);
371 __setup("enable_8254_timer", setup_enable_8254_timer);
372
373
374 /*
375 * Find the IRQ entry number of a certain pin.
376 */
377 static int find_irq_entry(int apic, int pin, int type)
378 {
379 int i;
380
381 for (i = 0; i < mp_irq_entries; i++)
382 if (mp_irqs[i].mpc_irqtype == type &&
383 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
384 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
385 mp_irqs[i].mpc_dstirq == pin)
386 return i;
387
388 return -1;
389 }
390
391 /*
392 * Find the pin to which IRQ[irq] (ISA) is connected
393 */
394 static int __init find_isa_irq_pin(int irq, int type)
395 {
396 int i;
397
398 for (i = 0; i < mp_irq_entries; i++) {
399 int lbus = mp_irqs[i].mpc_srcbus;
400
401 if (test_bit(lbus, mp_bus_not_pci) &&
402 (mp_irqs[i].mpc_irqtype == type) &&
403 (mp_irqs[i].mpc_srcbusirq == irq))
404
405 return mp_irqs[i].mpc_dstirq;
406 }
407 return -1;
408 }
409
410 static int __init find_isa_irq_apic(int irq, int type)
411 {
412 int i;
413
414 for (i = 0; i < mp_irq_entries; i++) {
415 int lbus = mp_irqs[i].mpc_srcbus;
416
417 if (test_bit(lbus, mp_bus_not_pci) &&
418 (mp_irqs[i].mpc_irqtype == type) &&
419 (mp_irqs[i].mpc_srcbusirq == irq))
420 break;
421 }
422 if (i < mp_irq_entries) {
423 int apic;
424 for(apic = 0; apic < nr_ioapics; apic++) {
425 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
426 return apic;
427 }
428 }
429
430 return -1;
431 }
432
433 /*
434 * Find a specific PCI IRQ entry.
435 * Not an __init, possibly needed by modules
436 */
437 static int pin_2_irq(int idx, int apic, int pin);
438
439 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
440 {
441 int apic, i, best_guess = -1;
442
443 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
444 bus, slot, pin);
445 if (mp_bus_id_to_pci_bus[bus] == -1) {
446 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
447 return -1;
448 }
449 for (i = 0; i < mp_irq_entries; i++) {
450 int lbus = mp_irqs[i].mpc_srcbus;
451
452 for (apic = 0; apic < nr_ioapics; apic++)
453 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
454 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
455 break;
456
457 if (!test_bit(lbus, mp_bus_not_pci) &&
458 !mp_irqs[i].mpc_irqtype &&
459 (bus == lbus) &&
460 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
461 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
462
463 if (!(apic || IO_APIC_IRQ(irq)))
464 continue;
465
466 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
467 return irq;
468 /*
469 * Use the first all-but-pin matching entry as a
470 * best-guess fuzzy result for broken mptables.
471 */
472 if (best_guess < 0)
473 best_guess = irq;
474 }
475 }
476 BUG_ON(best_guess >= NR_IRQS);
477 return best_guess;
478 }
479
480 /* ISA interrupts are always polarity zero edge triggered,
481 * when listed as conforming in the MP table. */
482
483 #define default_ISA_trigger(idx) (0)
484 #define default_ISA_polarity(idx) (0)
485
486 /* PCI interrupts are always polarity one level triggered,
487 * when listed as conforming in the MP table. */
488
489 #define default_PCI_trigger(idx) (1)
490 #define default_PCI_polarity(idx) (1)
491
492 static int __init MPBIOS_polarity(int idx)
493 {
494 int bus = mp_irqs[idx].mpc_srcbus;
495 int polarity;
496
497 /*
498 * Determine IRQ line polarity (high active or low active):
499 */
500 switch (mp_irqs[idx].mpc_irqflag & 3)
501 {
502 case 0: /* conforms, ie. bus-type dependent polarity */
503 if (test_bit(bus, mp_bus_not_pci))
504 polarity = default_ISA_polarity(idx);
505 else
506 polarity = default_PCI_polarity(idx);
507 break;
508 case 1: /* high active */
509 {
510 polarity = 0;
511 break;
512 }
513 case 2: /* reserved */
514 {
515 printk(KERN_WARNING "broken BIOS!!\n");
516 polarity = 1;
517 break;
518 }
519 case 3: /* low active */
520 {
521 polarity = 1;
522 break;
523 }
524 default: /* invalid */
525 {
526 printk(KERN_WARNING "broken BIOS!!\n");
527 polarity = 1;
528 break;
529 }
530 }
531 return polarity;
532 }
533
534 static int MPBIOS_trigger(int idx)
535 {
536 int bus = mp_irqs[idx].mpc_srcbus;
537 int trigger;
538
539 /*
540 * Determine IRQ trigger mode (edge or level sensitive):
541 */
542 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
543 {
544 case 0: /* conforms, ie. bus-type dependent */
545 if (test_bit(bus, mp_bus_not_pci))
546 trigger = default_ISA_trigger(idx);
547 else
548 trigger = default_PCI_trigger(idx);
549 break;
550 case 1: /* edge */
551 {
552 trigger = 0;
553 break;
554 }
555 case 2: /* reserved */
556 {
557 printk(KERN_WARNING "broken BIOS!!\n");
558 trigger = 1;
559 break;
560 }
561 case 3: /* level */
562 {
563 trigger = 1;
564 break;
565 }
566 default: /* invalid */
567 {
568 printk(KERN_WARNING "broken BIOS!!\n");
569 trigger = 0;
570 break;
571 }
572 }
573 return trigger;
574 }
575
576 static inline int irq_polarity(int idx)
577 {
578 return MPBIOS_polarity(idx);
579 }
580
581 static inline int irq_trigger(int idx)
582 {
583 return MPBIOS_trigger(idx);
584 }
585
586 static int pin_2_irq(int idx, int apic, int pin)
587 {
588 int irq, i;
589 int bus = mp_irqs[idx].mpc_srcbus;
590
591 /*
592 * Debugging check, we are in big trouble if this message pops up!
593 */
594 if (mp_irqs[idx].mpc_dstirq != pin)
595 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
596
597 if (test_bit(bus, mp_bus_not_pci)) {
598 irq = mp_irqs[idx].mpc_srcbusirq;
599 } else {
600 /*
601 * PCI IRQs are mapped in order
602 */
603 i = irq = 0;
604 while (i < apic)
605 irq += nr_ioapic_registers[i++];
606 irq += pin;
607 }
608 BUG_ON(irq >= NR_IRQS);
609 return irq;
610 }
611
612 static inline int IO_APIC_irq_trigger(int irq)
613 {
614 int apic, idx, pin;
615
616 for (apic = 0; apic < nr_ioapics; apic++) {
617 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
618 idx = find_irq_entry(apic,pin,mp_INT);
619 if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
620 return irq_trigger(idx);
621 }
622 }
623 /*
624 * nonexistent IRQs are edge default
625 */
626 return 0;
627 }
628
629 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
630 static u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = {
631 [0] = FIRST_EXTERNAL_VECTOR + 0,
632 [1] = FIRST_EXTERNAL_VECTOR + 1,
633 [2] = FIRST_EXTERNAL_VECTOR + 2,
634 [3] = FIRST_EXTERNAL_VECTOR + 3,
635 [4] = FIRST_EXTERNAL_VECTOR + 4,
636 [5] = FIRST_EXTERNAL_VECTOR + 5,
637 [6] = FIRST_EXTERNAL_VECTOR + 6,
638 [7] = FIRST_EXTERNAL_VECTOR + 7,
639 [8] = FIRST_EXTERNAL_VECTOR + 8,
640 [9] = FIRST_EXTERNAL_VECTOR + 9,
641 [10] = FIRST_EXTERNAL_VECTOR + 10,
642 [11] = FIRST_EXTERNAL_VECTOR + 11,
643 [12] = FIRST_EXTERNAL_VECTOR + 12,
644 [13] = FIRST_EXTERNAL_VECTOR + 13,
645 [14] = FIRST_EXTERNAL_VECTOR + 14,
646 [15] = FIRST_EXTERNAL_VECTOR + 15,
647 };
648
649 static cpumask_t irq_domain[NR_IRQ_VECTORS] __read_mostly = {
650 [0] = CPU_MASK_ALL,
651 [1] = CPU_MASK_ALL,
652 [2] = CPU_MASK_ALL,
653 [3] = CPU_MASK_ALL,
654 [4] = CPU_MASK_ALL,
655 [5] = CPU_MASK_ALL,
656 [6] = CPU_MASK_ALL,
657 [7] = CPU_MASK_ALL,
658 [8] = CPU_MASK_ALL,
659 [9] = CPU_MASK_ALL,
660 [10] = CPU_MASK_ALL,
661 [11] = CPU_MASK_ALL,
662 [12] = CPU_MASK_ALL,
663 [13] = CPU_MASK_ALL,
664 [14] = CPU_MASK_ALL,
665 [15] = CPU_MASK_ALL,
666 };
667
668 static int __assign_irq_vector(int irq, cpumask_t mask, cpumask_t *result)
669 {
670 /*
671 * NOTE! The local APIC isn't very good at handling
672 * multiple interrupts at the same interrupt level.
673 * As the interrupt level is determined by taking the
674 * vector number and shifting that right by 4, we
675 * want to spread these out a bit so that they don't
676 * all fall in the same interrupt level.
677 *
678 * Also, we've got to be careful not to trash gate
679 * 0x80, because int 0x80 is hm, kind of importantish. ;)
680 */
681 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
682 int old_vector = -1;
683 int cpu;
684
685 BUG_ON((unsigned)irq >= NR_IRQ_VECTORS);
686
687 /* Only try and allocate irqs on cpus that are present */
688 cpus_and(mask, mask, cpu_online_map);
689
690 if (irq_vector[irq] > 0)
691 old_vector = irq_vector[irq];
692 if (old_vector > 0) {
693 cpus_and(*result, irq_domain[irq], mask);
694 if (!cpus_empty(*result))
695 return old_vector;
696 }
697
698 for_each_cpu_mask(cpu, mask) {
699 cpumask_t domain, new_mask;
700 int new_cpu;
701 int vector, offset;
702
703 domain = vector_allocation_domain(cpu);
704 cpus_and(new_mask, domain, cpu_online_map);
705
706 vector = current_vector;
707 offset = current_offset;
708 next:
709 vector += 8;
710 if (vector >= FIRST_SYSTEM_VECTOR) {
711 /* If we run out of vectors on large boxen, must share them. */
712 offset = (offset + 1) % 8;
713 vector = FIRST_DEVICE_VECTOR + offset;
714 }
715 if (unlikely(current_vector == vector))
716 continue;
717 if (vector == IA32_SYSCALL_VECTOR)
718 goto next;
719 for_each_cpu_mask(new_cpu, new_mask)
720 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
721 goto next;
722 /* Found one! */
723 current_vector = vector;
724 current_offset = offset;
725 if (old_vector >= 0) {
726 cpumask_t old_mask;
727 int old_cpu;
728 cpus_and(old_mask, irq_domain[irq], cpu_online_map);
729 for_each_cpu_mask(old_cpu, old_mask)
730 per_cpu(vector_irq, old_cpu)[old_vector] = -1;
731 }
732 for_each_cpu_mask(new_cpu, new_mask)
733 per_cpu(vector_irq, new_cpu)[vector] = irq;
734 irq_vector[irq] = vector;
735 irq_domain[irq] = domain;
736 cpus_and(*result, domain, mask);
737 return vector;
738 }
739 return -ENOSPC;
740 }
741
742 static int assign_irq_vector(int irq, cpumask_t mask, cpumask_t *result)
743 {
744 int vector;
745 unsigned long flags;
746
747 spin_lock_irqsave(&vector_lock, flags);
748 vector = __assign_irq_vector(irq, mask, result);
749 spin_unlock_irqrestore(&vector_lock, flags);
750 return vector;
751 }
752
753 static void __clear_irq_vector(int irq)
754 {
755 cpumask_t mask;
756 int cpu, vector;
757
758 BUG_ON(!irq_vector[irq]);
759
760 vector = irq_vector[irq];
761 cpus_and(mask, irq_domain[irq], cpu_online_map);
762 for_each_cpu_mask(cpu, mask)
763 per_cpu(vector_irq, cpu)[vector] = -1;
764
765 irq_vector[irq] = 0;
766 irq_domain[irq] = CPU_MASK_NONE;
767 }
768
769 void __setup_vector_irq(int cpu)
770 {
771 /* Initialize vector_irq on a new cpu */
772 /* This function must be called with vector_lock held */
773 int irq, vector;
774
775 /* Mark the inuse vectors */
776 for (irq = 0; irq < NR_IRQ_VECTORS; ++irq) {
777 if (!cpu_isset(cpu, irq_domain[irq]))
778 continue;
779 vector = irq_vector[irq];
780 per_cpu(vector_irq, cpu)[vector] = irq;
781 }
782 /* Mark the free vectors */
783 for (vector = 0; vector < NR_VECTORS; ++vector) {
784 irq = per_cpu(vector_irq, cpu)[vector];
785 if (irq < 0)
786 continue;
787 if (!cpu_isset(cpu, irq_domain[irq]))
788 per_cpu(vector_irq, cpu)[vector] = -1;
789 }
790 }
791
792
793 extern void (*interrupt[NR_IRQS])(void);
794
795 static struct irq_chip ioapic_chip;
796
797 #define IOAPIC_AUTO -1
798 #define IOAPIC_EDGE 0
799 #define IOAPIC_LEVEL 1
800
801 static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
802 {
803 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
804 trigger == IOAPIC_LEVEL)
805 set_irq_chip_and_handler_name(irq, &ioapic_chip,
806 handle_fasteoi_irq, "fasteoi");
807 else {
808 irq_desc[irq].status |= IRQ_DELAYED_DISABLE;
809 set_irq_chip_and_handler_name(irq, &ioapic_chip,
810 handle_edge_irq, "edge");
811 }
812 }
813
814 static void __init setup_IO_APIC_irqs(void)
815 {
816 struct IO_APIC_route_entry entry;
817 int apic, pin, idx, irq, first_notcon = 1, vector;
818 unsigned long flags;
819
820 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
821
822 for (apic = 0; apic < nr_ioapics; apic++) {
823 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
824
825 /*
826 * add it to the IO-APIC irq-routing table:
827 */
828 memset(&entry,0,sizeof(entry));
829
830 entry.delivery_mode = INT_DELIVERY_MODE;
831 entry.dest_mode = INT_DEST_MODE;
832 entry.mask = 0; /* enable IRQ */
833 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
834
835 idx = find_irq_entry(apic,pin,mp_INT);
836 if (idx == -1) {
837 if (first_notcon) {
838 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
839 first_notcon = 0;
840 } else
841 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
842 continue;
843 }
844
845 entry.trigger = irq_trigger(idx);
846 entry.polarity = irq_polarity(idx);
847
848 if (irq_trigger(idx)) {
849 entry.trigger = 1;
850 entry.mask = 1;
851 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
852 }
853
854 irq = pin_2_irq(idx, apic, pin);
855 add_pin_to_irq(irq, apic, pin);
856
857 if (!apic && !IO_APIC_IRQ(irq))
858 continue;
859
860 if (IO_APIC_IRQ(irq)) {
861 cpumask_t mask;
862 vector = assign_irq_vector(irq, TARGET_CPUS, &mask);
863 if (vector < 0)
864 continue;
865
866 entry.dest.logical.logical_dest = cpu_mask_to_apicid(mask);
867 entry.vector = vector;
868
869 ioapic_register_intr(irq, vector, IOAPIC_AUTO);
870 if (!apic && (irq < 16))
871 disable_8259A_irq(irq);
872 }
873 ioapic_write_entry(apic, pin, entry);
874
875 spin_lock_irqsave(&ioapic_lock, flags);
876 set_native_irq_info(irq, TARGET_CPUS);
877 spin_unlock_irqrestore(&ioapic_lock, flags);
878 }
879 }
880
881 if (!first_notcon)
882 apic_printk(APIC_VERBOSE," not connected.\n");
883 }
884
885 /*
886 * Set up the 8259A-master output pin as broadcast to all
887 * CPUs.
888 */
889 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
890 {
891 struct IO_APIC_route_entry entry;
892 unsigned long flags;
893
894 memset(&entry,0,sizeof(entry));
895
896 disable_8259A_irq(0);
897
898 /* mask LVT0 */
899 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
900
901 /*
902 * We use logical delivery to get the timer IRQ
903 * to the first CPU.
904 */
905 entry.dest_mode = INT_DEST_MODE;
906 entry.mask = 0; /* unmask IRQ now */
907 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
908 entry.delivery_mode = INT_DELIVERY_MODE;
909 entry.polarity = 0;
910 entry.trigger = 0;
911 entry.vector = vector;
912
913 /*
914 * The timer IRQ doesn't have to know that behind the
915 * scene we have a 8259A-master in AEOI mode ...
916 */
917 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
918
919 /*
920 * Add it to the IO-APIC irq-routing table:
921 */
922 spin_lock_irqsave(&ioapic_lock, flags);
923 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
924 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
925 spin_unlock_irqrestore(&ioapic_lock, flags);
926
927 enable_8259A_irq(0);
928 }
929
930 void __init UNEXPECTED_IO_APIC(void)
931 {
932 }
933
934 void __apicdebuginit print_IO_APIC(void)
935 {
936 int apic, i;
937 union IO_APIC_reg_00 reg_00;
938 union IO_APIC_reg_01 reg_01;
939 union IO_APIC_reg_02 reg_02;
940 unsigned long flags;
941
942 if (apic_verbosity == APIC_QUIET)
943 return;
944
945 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
946 for (i = 0; i < nr_ioapics; i++)
947 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
948 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
949
950 /*
951 * We are a bit conservative about what we expect. We have to
952 * know about every hardware change ASAP.
953 */
954 printk(KERN_INFO "testing the IO APIC.......................\n");
955
956 for (apic = 0; apic < nr_ioapics; apic++) {
957
958 spin_lock_irqsave(&ioapic_lock, flags);
959 reg_00.raw = io_apic_read(apic, 0);
960 reg_01.raw = io_apic_read(apic, 1);
961 if (reg_01.bits.version >= 0x10)
962 reg_02.raw = io_apic_read(apic, 2);
963 spin_unlock_irqrestore(&ioapic_lock, flags);
964
965 printk("\n");
966 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
967 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
968 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
969 if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
970 UNEXPECTED_IO_APIC();
971
972 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
973 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
974 if ( (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
975 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
976 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
977 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
978 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
979 (reg_01.bits.entries != 0x2E) &&
980 (reg_01.bits.entries != 0x3F) &&
981 (reg_01.bits.entries != 0x03)
982 )
983 UNEXPECTED_IO_APIC();
984
985 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
986 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
987 if ( (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
988 (reg_01.bits.version != 0x02) && /* 82801BA IO-APICs (ICH2) */
989 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
990 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
991 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
992 (reg_01.bits.version != 0x20) /* Intel P64H (82806 AA) */
993 )
994 UNEXPECTED_IO_APIC();
995 if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
996 UNEXPECTED_IO_APIC();
997
998 if (reg_01.bits.version >= 0x10) {
999 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1000 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1001 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
1002 UNEXPECTED_IO_APIC();
1003 }
1004
1005 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1006
1007 printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1008 " Stat Dest Deli Vect: \n");
1009
1010 for (i = 0; i <= reg_01.bits.entries; i++) {
1011 struct IO_APIC_route_entry entry;
1012
1013 entry = ioapic_read_entry(apic, i);
1014
1015 printk(KERN_DEBUG " %02x %03X %02X ",
1016 i,
1017 entry.dest.logical.logical_dest,
1018 entry.dest.physical.physical_dest
1019 );
1020
1021 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1022 entry.mask,
1023 entry.trigger,
1024 entry.irr,
1025 entry.polarity,
1026 entry.delivery_status,
1027 entry.dest_mode,
1028 entry.delivery_mode,
1029 entry.vector
1030 );
1031 }
1032 }
1033 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1034 for (i = 0; i < NR_IRQS; i++) {
1035 struct irq_pin_list *entry = irq_2_pin + i;
1036 if (entry->pin < 0)
1037 continue;
1038 printk(KERN_DEBUG "IRQ%d ", i);
1039 for (;;) {
1040 printk("-> %d:%d", entry->apic, entry->pin);
1041 if (!entry->next)
1042 break;
1043 entry = irq_2_pin + entry->next;
1044 }
1045 printk("\n");
1046 }
1047
1048 printk(KERN_INFO ".................................... done.\n");
1049
1050 return;
1051 }
1052
1053 #if 0
1054
1055 static __apicdebuginit void print_APIC_bitfield (int base)
1056 {
1057 unsigned int v;
1058 int i, j;
1059
1060 if (apic_verbosity == APIC_QUIET)
1061 return;
1062
1063 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1064 for (i = 0; i < 8; i++) {
1065 v = apic_read(base + i*0x10);
1066 for (j = 0; j < 32; j++) {
1067 if (v & (1<<j))
1068 printk("1");
1069 else
1070 printk("0");
1071 }
1072 printk("\n");
1073 }
1074 }
1075
1076 void __apicdebuginit print_local_APIC(void * dummy)
1077 {
1078 unsigned int v, ver, maxlvt;
1079
1080 if (apic_verbosity == APIC_QUIET)
1081 return;
1082
1083 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1084 smp_processor_id(), hard_smp_processor_id());
1085 v = apic_read(APIC_ID);
1086 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v));
1087 v = apic_read(APIC_LVR);
1088 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1089 ver = GET_APIC_VERSION(v);
1090 maxlvt = get_maxlvt();
1091
1092 v = apic_read(APIC_TASKPRI);
1093 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1094
1095 v = apic_read(APIC_ARBPRI);
1096 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1097 v & APIC_ARBPRI_MASK);
1098 v = apic_read(APIC_PROCPRI);
1099 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1100
1101 v = apic_read(APIC_EOI);
1102 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1103 v = apic_read(APIC_RRR);
1104 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1105 v = apic_read(APIC_LDR);
1106 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1107 v = apic_read(APIC_DFR);
1108 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1109 v = apic_read(APIC_SPIV);
1110 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1111
1112 printk(KERN_DEBUG "... APIC ISR field:\n");
1113 print_APIC_bitfield(APIC_ISR);
1114 printk(KERN_DEBUG "... APIC TMR field:\n");
1115 print_APIC_bitfield(APIC_TMR);
1116 printk(KERN_DEBUG "... APIC IRR field:\n");
1117 print_APIC_bitfield(APIC_IRR);
1118
1119 v = apic_read(APIC_ESR);
1120 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1121
1122 v = apic_read(APIC_ICR);
1123 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1124 v = apic_read(APIC_ICR2);
1125 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1126
1127 v = apic_read(APIC_LVTT);
1128 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1129
1130 if (maxlvt > 3) { /* PC is LVT#4. */
1131 v = apic_read(APIC_LVTPC);
1132 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1133 }
1134 v = apic_read(APIC_LVT0);
1135 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1136 v = apic_read(APIC_LVT1);
1137 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1138
1139 if (maxlvt > 2) { /* ERR is LVT#3. */
1140 v = apic_read(APIC_LVTERR);
1141 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1142 }
1143
1144 v = apic_read(APIC_TMICT);
1145 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1146 v = apic_read(APIC_TMCCT);
1147 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1148 v = apic_read(APIC_TDCR);
1149 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1150 printk("\n");
1151 }
1152
1153 void print_all_local_APICs (void)
1154 {
1155 on_each_cpu(print_local_APIC, NULL, 1, 1);
1156 }
1157
1158 void __apicdebuginit print_PIC(void)
1159 {
1160 unsigned int v;
1161 unsigned long flags;
1162
1163 if (apic_verbosity == APIC_QUIET)
1164 return;
1165
1166 printk(KERN_DEBUG "\nprinting PIC contents\n");
1167
1168 spin_lock_irqsave(&i8259A_lock, flags);
1169
1170 v = inb(0xa1) << 8 | inb(0x21);
1171 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1172
1173 v = inb(0xa0) << 8 | inb(0x20);
1174 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1175
1176 outb(0x0b,0xa0);
1177 outb(0x0b,0x20);
1178 v = inb(0xa0) << 8 | inb(0x20);
1179 outb(0x0a,0xa0);
1180 outb(0x0a,0x20);
1181
1182 spin_unlock_irqrestore(&i8259A_lock, flags);
1183
1184 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1185
1186 v = inb(0x4d1) << 8 | inb(0x4d0);
1187 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1188 }
1189
1190 #endif /* 0 */
1191
1192 static void __init enable_IO_APIC(void)
1193 {
1194 union IO_APIC_reg_01 reg_01;
1195 int i8259_apic, i8259_pin;
1196 int i, apic;
1197 unsigned long flags;
1198
1199 for (i = 0; i < PIN_MAP_SIZE; i++) {
1200 irq_2_pin[i].pin = -1;
1201 irq_2_pin[i].next = 0;
1202 }
1203
1204 /*
1205 * The number of IO-APIC IRQ registers (== #pins):
1206 */
1207 for (apic = 0; apic < nr_ioapics; apic++) {
1208 spin_lock_irqsave(&ioapic_lock, flags);
1209 reg_01.raw = io_apic_read(apic, 1);
1210 spin_unlock_irqrestore(&ioapic_lock, flags);
1211 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1212 }
1213 for(apic = 0; apic < nr_ioapics; apic++) {
1214 int pin;
1215 /* See if any of the pins is in ExtINT mode */
1216 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1217 struct IO_APIC_route_entry entry;
1218 entry = ioapic_read_entry(apic, pin);
1219
1220 /* If the interrupt line is enabled and in ExtInt mode
1221 * I have found the pin where the i8259 is connected.
1222 */
1223 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1224 ioapic_i8259.apic = apic;
1225 ioapic_i8259.pin = pin;
1226 goto found_i8259;
1227 }
1228 }
1229 }
1230 found_i8259:
1231 /* Look to see what if the MP table has reported the ExtINT */
1232 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1233 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1234 /* Trust the MP table if nothing is setup in the hardware */
1235 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1236 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1237 ioapic_i8259.pin = i8259_pin;
1238 ioapic_i8259.apic = i8259_apic;
1239 }
1240 /* Complain if the MP table and the hardware disagree */
1241 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1242 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1243 {
1244 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1245 }
1246
1247 /*
1248 * Do not trust the IO-APIC being empty at bootup
1249 */
1250 clear_IO_APIC();
1251 }
1252
1253 /*
1254 * Not an __init, needed by the reboot code
1255 */
1256 void disable_IO_APIC(void)
1257 {
1258 /*
1259 * Clear the IO-APIC before rebooting:
1260 */
1261 clear_IO_APIC();
1262
1263 /*
1264 * If the i8259 is routed through an IOAPIC
1265 * Put that IOAPIC in virtual wire mode
1266 * so legacy interrupts can be delivered.
1267 */
1268 if (ioapic_i8259.pin != -1) {
1269 struct IO_APIC_route_entry entry;
1270
1271 memset(&entry, 0, sizeof(entry));
1272 entry.mask = 0; /* Enabled */
1273 entry.trigger = 0; /* Edge */
1274 entry.irr = 0;
1275 entry.polarity = 0; /* High */
1276 entry.delivery_status = 0;
1277 entry.dest_mode = 0; /* Physical */
1278 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1279 entry.vector = 0;
1280 entry.dest.physical.physical_dest =
1281 GET_APIC_ID(apic_read(APIC_ID));
1282
1283 /*
1284 * Add it to the IO-APIC irq-routing table:
1285 */
1286 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1287 }
1288
1289 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1290 }
1291
1292 /*
1293 * There is a nasty bug in some older SMP boards, their mptable lies
1294 * about the timer IRQ. We do the following to work around the situation:
1295 *
1296 * - timer IRQ defaults to IO-APIC IRQ
1297 * - if this function detects that timer IRQs are defunct, then we fall
1298 * back to ISA timer IRQs
1299 */
1300 static int __init timer_irq_works(void)
1301 {
1302 unsigned long t1 = jiffies;
1303
1304 local_irq_enable();
1305 /* Let ten ticks pass... */
1306 mdelay((10 * 1000) / HZ);
1307
1308 /*
1309 * Expect a few ticks at least, to be sure some possible
1310 * glue logic does not lock up after one or two first
1311 * ticks in a non-ExtINT mode. Also the local APIC
1312 * might have cached one ExtINT interrupt. Finally, at
1313 * least one tick may be lost due to delays.
1314 */
1315
1316 /* jiffies wrap? */
1317 if (jiffies - t1 > 4)
1318 return 1;
1319 return 0;
1320 }
1321
1322 /*
1323 * In the SMP+IOAPIC case it might happen that there are an unspecified
1324 * number of pending IRQ events unhandled. These cases are very rare,
1325 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1326 * better to do it this way as thus we do not have to be aware of
1327 * 'pending' interrupts in the IRQ path, except at this point.
1328 */
1329 /*
1330 * Edge triggered needs to resend any interrupt
1331 * that was delayed but this is now handled in the device
1332 * independent code.
1333 */
1334
1335 /*
1336 * Starting up a edge-triggered IO-APIC interrupt is
1337 * nasty - we need to make sure that we get the edge.
1338 * If it is already asserted for some reason, we need
1339 * return 1 to indicate that is was pending.
1340 *
1341 * This is not complete - we should be able to fake
1342 * an edge even if it isn't on the 8259A...
1343 */
1344
1345 static unsigned int startup_ioapic_irq(unsigned int irq)
1346 {
1347 int was_pending = 0;
1348 unsigned long flags;
1349
1350 spin_lock_irqsave(&ioapic_lock, flags);
1351 if (irq < 16) {
1352 disable_8259A_irq(irq);
1353 if (i8259A_irq_pending(irq))
1354 was_pending = 1;
1355 }
1356 __unmask_IO_APIC_irq(irq);
1357 spin_unlock_irqrestore(&ioapic_lock, flags);
1358
1359 return was_pending;
1360 }
1361
1362 static int ioapic_retrigger_irq(unsigned int irq)
1363 {
1364 cpumask_t mask;
1365 unsigned vector;
1366 unsigned long flags;
1367
1368 spin_lock_irqsave(&vector_lock, flags);
1369 vector = irq_vector[irq];
1370 cpus_clear(mask);
1371 cpu_set(first_cpu(irq_domain[irq]), mask);
1372
1373 send_IPI_mask(mask, vector);
1374 spin_unlock_irqrestore(&vector_lock, flags);
1375
1376 return 1;
1377 }
1378
1379 /*
1380 * Level and edge triggered IO-APIC interrupts need different handling,
1381 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1382 * handled with the level-triggered descriptor, but that one has slightly
1383 * more overhead. Level-triggered interrupts cannot be handled with the
1384 * edge-triggered handler, without risking IRQ storms and other ugly
1385 * races.
1386 */
1387
1388 static void ack_apic_edge(unsigned int irq)
1389 {
1390 move_native_irq(irq);
1391 ack_APIC_irq();
1392 }
1393
1394 static void ack_apic_level(unsigned int irq)
1395 {
1396 int do_unmask_irq = 0;
1397
1398 #if defined(CONFIG_GENERIC_PENDING_IRQ) || defined(CONFIG_IRQBALANCE)
1399 /* If we are moving the irq we need to mask it */
1400 if (unlikely(irq_desc[irq].status & IRQ_MOVE_PENDING)) {
1401 do_unmask_irq = 1;
1402 mask_IO_APIC_irq(irq);
1403 }
1404 #endif
1405
1406 /*
1407 * We must acknowledge the irq before we move it or the acknowledge will
1408 * not propogate properly.
1409 */
1410 ack_APIC_irq();
1411
1412 /* Now we can move and renable the irq */
1413 move_masked_irq(irq);
1414 if (unlikely(do_unmask_irq))
1415 unmask_IO_APIC_irq(irq);
1416 }
1417
1418 static struct irq_chip ioapic_chip __read_mostly = {
1419 .name = "IO-APIC",
1420 .startup = startup_ioapic_irq,
1421 .mask = mask_IO_APIC_irq,
1422 .unmask = unmask_IO_APIC_irq,
1423 .ack = ack_apic_edge,
1424 .eoi = ack_apic_level,
1425 #ifdef CONFIG_SMP
1426 .set_affinity = set_ioapic_affinity_irq,
1427 #endif
1428 .retrigger = ioapic_retrigger_irq,
1429 };
1430
1431 static inline void init_IO_APIC_traps(void)
1432 {
1433 int irq;
1434
1435 /*
1436 * NOTE! The local APIC isn't very good at handling
1437 * multiple interrupts at the same interrupt level.
1438 * As the interrupt level is determined by taking the
1439 * vector number and shifting that right by 4, we
1440 * want to spread these out a bit so that they don't
1441 * all fall in the same interrupt level.
1442 *
1443 * Also, we've got to be careful not to trash gate
1444 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1445 */
1446 for (irq = 0; irq < NR_IRQS ; irq++) {
1447 int tmp = irq;
1448 if (IO_APIC_IRQ(tmp) && !irq_vector[tmp]) {
1449 /*
1450 * Hmm.. We don't have an entry for this,
1451 * so default to an old-fashioned 8259
1452 * interrupt if we can..
1453 */
1454 if (irq < 16)
1455 make_8259A_irq(irq);
1456 else
1457 /* Strange. Oh, well.. */
1458 irq_desc[irq].chip = &no_irq_chip;
1459 }
1460 }
1461 }
1462
1463 static void enable_lapic_irq (unsigned int irq)
1464 {
1465 unsigned long v;
1466
1467 v = apic_read(APIC_LVT0);
1468 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1469 }
1470
1471 static void disable_lapic_irq (unsigned int irq)
1472 {
1473 unsigned long v;
1474
1475 v = apic_read(APIC_LVT0);
1476 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1477 }
1478
1479 static void ack_lapic_irq (unsigned int irq)
1480 {
1481 ack_APIC_irq();
1482 }
1483
1484 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1485
1486 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
1487 .typename = "local-APIC-edge",
1488 .startup = NULL, /* startup_irq() not used for IRQ0 */
1489 .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1490 .enable = enable_lapic_irq,
1491 .disable = disable_lapic_irq,
1492 .ack = ack_lapic_irq,
1493 .end = end_lapic_irq,
1494 };
1495
1496 static void setup_nmi (void)
1497 {
1498 /*
1499 * Dirty trick to enable the NMI watchdog ...
1500 * We put the 8259A master into AEOI mode and
1501 * unmask on all local APICs LVT0 as NMI.
1502 *
1503 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1504 * is from Maciej W. Rozycki - so we do not have to EOI from
1505 * the NMI handler or the timer interrupt.
1506 */
1507 printk(KERN_INFO "activating NMI Watchdog ...");
1508
1509 enable_NMI_through_LVT0(NULL);
1510
1511 printk(" done.\n");
1512 }
1513
1514 /*
1515 * This looks a bit hackish but it's about the only one way of sending
1516 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1517 * not support the ExtINT mode, unfortunately. We need to send these
1518 * cycles as some i82489DX-based boards have glue logic that keeps the
1519 * 8259A interrupt line asserted until INTA. --macro
1520 */
1521 static inline void unlock_ExtINT_logic(void)
1522 {
1523 int apic, pin, i;
1524 struct IO_APIC_route_entry entry0, entry1;
1525 unsigned char save_control, save_freq_select;
1526 unsigned long flags;
1527
1528 pin = find_isa_irq_pin(8, mp_INT);
1529 apic = find_isa_irq_apic(8, mp_INT);
1530 if (pin == -1)
1531 return;
1532
1533 spin_lock_irqsave(&ioapic_lock, flags);
1534 *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1535 *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1536 spin_unlock_irqrestore(&ioapic_lock, flags);
1537 clear_IO_APIC_pin(apic, pin);
1538
1539 memset(&entry1, 0, sizeof(entry1));
1540
1541 entry1.dest_mode = 0; /* physical delivery */
1542 entry1.mask = 0; /* unmask IRQ now */
1543 entry1.dest.physical.physical_dest = hard_smp_processor_id();
1544 entry1.delivery_mode = dest_ExtINT;
1545 entry1.polarity = entry0.polarity;
1546 entry1.trigger = 0;
1547 entry1.vector = 0;
1548
1549 spin_lock_irqsave(&ioapic_lock, flags);
1550 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1551 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1552 spin_unlock_irqrestore(&ioapic_lock, flags);
1553
1554 save_control = CMOS_READ(RTC_CONTROL);
1555 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1556 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1557 RTC_FREQ_SELECT);
1558 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1559
1560 i = 100;
1561 while (i-- > 0) {
1562 mdelay(10);
1563 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1564 i -= 10;
1565 }
1566
1567 CMOS_WRITE(save_control, RTC_CONTROL);
1568 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1569 clear_IO_APIC_pin(apic, pin);
1570
1571 spin_lock_irqsave(&ioapic_lock, flags);
1572 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1573 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1574 spin_unlock_irqrestore(&ioapic_lock, flags);
1575 }
1576
1577 /*
1578 * This code may look a bit paranoid, but it's supposed to cooperate with
1579 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1580 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1581 * fanatically on his truly buggy board.
1582 *
1583 * FIXME: really need to revamp this for modern platforms only.
1584 */
1585 static inline void check_timer(void)
1586 {
1587 int apic1, pin1, apic2, pin2;
1588 int vector;
1589 cpumask_t mask;
1590
1591 /*
1592 * get/set the timer IRQ vector:
1593 */
1594 disable_8259A_irq(0);
1595 vector = assign_irq_vector(0, TARGET_CPUS, &mask);
1596
1597 /*
1598 * Subtle, code in do_timer_interrupt() expects an AEOI
1599 * mode for the 8259A whenever interrupts are routed
1600 * through I/O APICs. Also IRQ0 has to be enabled in
1601 * the 8259A which implies the virtual wire has to be
1602 * disabled in the local APIC.
1603 */
1604 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1605 init_8259A(1);
1606 if (timer_over_8254 > 0)
1607 enable_8259A_irq(0);
1608
1609 pin1 = find_isa_irq_pin(0, mp_INT);
1610 apic1 = find_isa_irq_apic(0, mp_INT);
1611 pin2 = ioapic_i8259.pin;
1612 apic2 = ioapic_i8259.apic;
1613
1614 apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
1615 vector, apic1, pin1, apic2, pin2);
1616
1617 if (pin1 != -1) {
1618 /*
1619 * Ok, does IRQ0 through the IOAPIC work?
1620 */
1621 unmask_IO_APIC_irq(0);
1622 if (!no_timer_check && timer_irq_works()) {
1623 nmi_watchdog_default();
1624 if (nmi_watchdog == NMI_IO_APIC) {
1625 disable_8259A_irq(0);
1626 setup_nmi();
1627 enable_8259A_irq(0);
1628 }
1629 if (disable_timer_pin_1 > 0)
1630 clear_IO_APIC_pin(0, pin1);
1631 return;
1632 }
1633 clear_IO_APIC_pin(apic1, pin1);
1634 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not "
1635 "connected to IO-APIC\n");
1636 }
1637
1638 apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) "
1639 "through the 8259A ... ");
1640 if (pin2 != -1) {
1641 apic_printk(APIC_VERBOSE,"\n..... (found apic %d pin %d) ...",
1642 apic2, pin2);
1643 /*
1644 * legacy devices should be connected to IO APIC #0
1645 */
1646 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
1647 if (timer_irq_works()) {
1648 apic_printk(APIC_VERBOSE," works.\n");
1649 nmi_watchdog_default();
1650 if (nmi_watchdog == NMI_IO_APIC) {
1651 setup_nmi();
1652 }
1653 return;
1654 }
1655 /*
1656 * Cleanup, just in case ...
1657 */
1658 clear_IO_APIC_pin(apic2, pin2);
1659 }
1660 apic_printk(APIC_VERBOSE," failed.\n");
1661
1662 if (nmi_watchdog == NMI_IO_APIC) {
1663 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1664 nmi_watchdog = 0;
1665 }
1666
1667 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1668
1669 disable_8259A_irq(0);
1670 irq_desc[0].chip = &lapic_irq_type;
1671 apic_write(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
1672 enable_8259A_irq(0);
1673
1674 if (timer_irq_works()) {
1675 apic_printk(APIC_VERBOSE," works.\n");
1676 return;
1677 }
1678 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
1679 apic_printk(APIC_VERBOSE," failed.\n");
1680
1681 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1682
1683 init_8259A(0);
1684 make_8259A_irq(0);
1685 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1686
1687 unlock_ExtINT_logic();
1688
1689 if (timer_irq_works()) {
1690 apic_printk(APIC_VERBOSE," works.\n");
1691 return;
1692 }
1693 apic_printk(APIC_VERBOSE," failed :(.\n");
1694 panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1695 }
1696
1697 static int __init notimercheck(char *s)
1698 {
1699 no_timer_check = 1;
1700 return 1;
1701 }
1702 __setup("no_timer_check", notimercheck);
1703
1704 /*
1705 *
1706 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
1707 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1708 * Linux doesn't really care, as it's not actually used
1709 * for any interrupt handling anyway.
1710 */
1711 #define PIC_IRQS (1<<2)
1712
1713 void __init setup_IO_APIC(void)
1714 {
1715 enable_IO_APIC();
1716
1717 if (acpi_ioapic)
1718 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
1719 else
1720 io_apic_irqs = ~PIC_IRQS;
1721
1722 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
1723
1724 sync_Arb_IDs();
1725 setup_IO_APIC_irqs();
1726 init_IO_APIC_traps();
1727 check_timer();
1728 if (!acpi_ioapic)
1729 print_IO_APIC();
1730 }
1731
1732 struct sysfs_ioapic_data {
1733 struct sys_device dev;
1734 struct IO_APIC_route_entry entry[0];
1735 };
1736 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1737
1738 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1739 {
1740 struct IO_APIC_route_entry *entry;
1741 struct sysfs_ioapic_data *data;
1742 int i;
1743
1744 data = container_of(dev, struct sysfs_ioapic_data, dev);
1745 entry = data->entry;
1746 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
1747 *entry = ioapic_read_entry(dev->id, i);
1748
1749 return 0;
1750 }
1751
1752 static int ioapic_resume(struct sys_device *dev)
1753 {
1754 struct IO_APIC_route_entry *entry;
1755 struct sysfs_ioapic_data *data;
1756 unsigned long flags;
1757 union IO_APIC_reg_00 reg_00;
1758 int i;
1759
1760 data = container_of(dev, struct sysfs_ioapic_data, dev);
1761 entry = data->entry;
1762
1763 spin_lock_irqsave(&ioapic_lock, flags);
1764 reg_00.raw = io_apic_read(dev->id, 0);
1765 if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
1766 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
1767 io_apic_write(dev->id, 0, reg_00.raw);
1768 }
1769 spin_unlock_irqrestore(&ioapic_lock, flags);
1770 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
1771 ioapic_write_entry(dev->id, i, entry[i]);
1772
1773 return 0;
1774 }
1775
1776 static struct sysdev_class ioapic_sysdev_class = {
1777 set_kset_name("ioapic"),
1778 .suspend = ioapic_suspend,
1779 .resume = ioapic_resume,
1780 };
1781
1782 static int __init ioapic_init_sysfs(void)
1783 {
1784 struct sys_device * dev;
1785 int i, size, error = 0;
1786
1787 error = sysdev_class_register(&ioapic_sysdev_class);
1788 if (error)
1789 return error;
1790
1791 for (i = 0; i < nr_ioapics; i++ ) {
1792 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
1793 * sizeof(struct IO_APIC_route_entry);
1794 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
1795 if (!mp_ioapic_data[i]) {
1796 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1797 continue;
1798 }
1799 memset(mp_ioapic_data[i], 0, size);
1800 dev = &mp_ioapic_data[i]->dev;
1801 dev->id = i;
1802 dev->cls = &ioapic_sysdev_class;
1803 error = sysdev_register(dev);
1804 if (error) {
1805 kfree(mp_ioapic_data[i]);
1806 mp_ioapic_data[i] = NULL;
1807 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1808 continue;
1809 }
1810 }
1811
1812 return 0;
1813 }
1814
1815 device_initcall(ioapic_init_sysfs);
1816
1817 /*
1818 * Dynamic irq allocate and deallocation
1819 */
1820 int create_irq(void)
1821 {
1822 /* Allocate an unused irq */
1823 int irq;
1824 int new;
1825 int vector = 0;
1826 unsigned long flags;
1827 cpumask_t mask;
1828
1829 irq = -ENOSPC;
1830 spin_lock_irqsave(&vector_lock, flags);
1831 for (new = (NR_IRQS - 1); new >= 0; new--) {
1832 if (platform_legacy_irq(new))
1833 continue;
1834 if (irq_vector[new] != 0)
1835 continue;
1836 vector = __assign_irq_vector(new, TARGET_CPUS, &mask);
1837 if (likely(vector > 0))
1838 irq = new;
1839 break;
1840 }
1841 spin_unlock_irqrestore(&vector_lock, flags);
1842
1843 if (irq >= 0) {
1844 dynamic_irq_init(irq);
1845 }
1846 return irq;
1847 }
1848
1849 void destroy_irq(unsigned int irq)
1850 {
1851 unsigned long flags;
1852
1853 dynamic_irq_cleanup(irq);
1854
1855 spin_lock_irqsave(&vector_lock, flags);
1856 __clear_irq_vector(irq);
1857 spin_unlock_irqrestore(&vector_lock, flags);
1858 }
1859
1860 /*
1861 * MSI mesage composition
1862 */
1863 #ifdef CONFIG_PCI_MSI
1864 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
1865 {
1866 int vector;
1867 unsigned dest;
1868 cpumask_t tmp;
1869
1870 vector = assign_irq_vector(irq, TARGET_CPUS, &tmp);
1871 if (vector >= 0) {
1872 dest = cpu_mask_to_apicid(tmp);
1873
1874 msg->address_hi = MSI_ADDR_BASE_HI;
1875 msg->address_lo =
1876 MSI_ADDR_BASE_LO |
1877 ((INT_DEST_MODE == 0) ?
1878 MSI_ADDR_DEST_MODE_PHYSICAL:
1879 MSI_ADDR_DEST_MODE_LOGICAL) |
1880 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1881 MSI_ADDR_REDIRECTION_CPU:
1882 MSI_ADDR_REDIRECTION_LOWPRI) |
1883 MSI_ADDR_DEST_ID(dest);
1884
1885 msg->data =
1886 MSI_DATA_TRIGGER_EDGE |
1887 MSI_DATA_LEVEL_ASSERT |
1888 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1889 MSI_DATA_DELIVERY_FIXED:
1890 MSI_DATA_DELIVERY_LOWPRI) |
1891 MSI_DATA_VECTOR(vector);
1892 }
1893 return vector;
1894 }
1895
1896 #ifdef CONFIG_SMP
1897 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
1898 {
1899 struct msi_msg msg;
1900 unsigned int dest;
1901 cpumask_t tmp;
1902 int vector;
1903
1904 cpus_and(tmp, mask, cpu_online_map);
1905 if (cpus_empty(tmp))
1906 tmp = TARGET_CPUS;
1907
1908 cpus_and(mask, tmp, CPU_MASK_ALL);
1909
1910 vector = assign_irq_vector(irq, mask, &tmp);
1911 if (vector < 0)
1912 return;
1913
1914 dest = cpu_mask_to_apicid(tmp);
1915
1916 read_msi_msg(irq, &msg);
1917
1918 msg.data &= ~MSI_DATA_VECTOR_MASK;
1919 msg.data |= MSI_DATA_VECTOR(vector);
1920 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
1921 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
1922
1923 write_msi_msg(irq, &msg);
1924 set_native_irq_info(irq, mask);
1925 }
1926 #endif /* CONFIG_SMP */
1927
1928 /*
1929 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
1930 * which implement the MSI or MSI-X Capability Structure.
1931 */
1932 static struct irq_chip msi_chip = {
1933 .name = "PCI-MSI",
1934 .unmask = unmask_msi_irq,
1935 .mask = mask_msi_irq,
1936 .ack = ack_apic_edge,
1937 #ifdef CONFIG_SMP
1938 .set_affinity = set_msi_irq_affinity,
1939 #endif
1940 .retrigger = ioapic_retrigger_irq,
1941 };
1942
1943 int arch_setup_msi_irq(unsigned int irq, struct pci_dev *dev)
1944 {
1945 struct msi_msg msg;
1946 int ret;
1947 ret = msi_compose_msg(dev, irq, &msg);
1948 if (ret < 0)
1949 return ret;
1950
1951 write_msi_msg(irq, &msg);
1952
1953 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
1954
1955 return 0;
1956 }
1957
1958 void arch_teardown_msi_irq(unsigned int irq)
1959 {
1960 return;
1961 }
1962
1963 #endif /* CONFIG_PCI_MSI */
1964
1965 /*
1966 * Hypertransport interrupt support
1967 */
1968 #ifdef CONFIG_HT_IRQ
1969
1970 #ifdef CONFIG_SMP
1971
1972 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
1973 {
1974 struct ht_irq_msg msg;
1975 fetch_ht_irq_msg(irq, &msg);
1976
1977 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
1978 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
1979
1980 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
1981 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
1982
1983 write_ht_irq_msg(irq, &msg);
1984 }
1985
1986 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
1987 {
1988 unsigned int dest;
1989 cpumask_t tmp;
1990 int vector;
1991
1992 cpus_and(tmp, mask, cpu_online_map);
1993 if (cpus_empty(tmp))
1994 tmp = TARGET_CPUS;
1995
1996 cpus_and(mask, tmp, CPU_MASK_ALL);
1997
1998 vector = assign_irq_vector(irq, mask, &tmp);
1999 if (vector < 0)
2000 return;
2001
2002 dest = cpu_mask_to_apicid(tmp);
2003
2004 target_ht_irq(irq, dest, vector);
2005 set_native_irq_info(irq, mask);
2006 }
2007 #endif
2008
2009 static struct irq_chip ht_irq_chip = {
2010 .name = "PCI-HT",
2011 .mask = mask_ht_irq,
2012 .unmask = unmask_ht_irq,
2013 .ack = ack_apic_edge,
2014 #ifdef CONFIG_SMP
2015 .set_affinity = set_ht_irq_affinity,
2016 #endif
2017 .retrigger = ioapic_retrigger_irq,
2018 };
2019
2020 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2021 {
2022 int vector;
2023 cpumask_t tmp;
2024
2025 vector = assign_irq_vector(irq, TARGET_CPUS, &tmp);
2026 if (vector >= 0) {
2027 struct ht_irq_msg msg;
2028 unsigned dest;
2029
2030 dest = cpu_mask_to_apicid(tmp);
2031
2032 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
2033
2034 msg.address_lo =
2035 HT_IRQ_LOW_BASE |
2036 HT_IRQ_LOW_DEST_ID(dest) |
2037 HT_IRQ_LOW_VECTOR(vector) |
2038 ((INT_DEST_MODE == 0) ?
2039 HT_IRQ_LOW_DM_PHYSICAL :
2040 HT_IRQ_LOW_DM_LOGICAL) |
2041 HT_IRQ_LOW_RQEOI_EDGE |
2042 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2043 HT_IRQ_LOW_MT_FIXED :
2044 HT_IRQ_LOW_MT_ARBITRATED) |
2045 HT_IRQ_LOW_IRQ_MASKED;
2046
2047 write_ht_irq_msg(irq, &msg);
2048
2049 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2050 handle_edge_irq, "edge");
2051 }
2052 return vector;
2053 }
2054 #endif /* CONFIG_HT_IRQ */
2055
2056 /* --------------------------------------------------------------------------
2057 ACPI-based IOAPIC Configuration
2058 -------------------------------------------------------------------------- */
2059
2060 #ifdef CONFIG_ACPI
2061
2062 #define IO_APIC_MAX_ID 0xFE
2063
2064 int __init io_apic_get_redir_entries (int ioapic)
2065 {
2066 union IO_APIC_reg_01 reg_01;
2067 unsigned long flags;
2068
2069 spin_lock_irqsave(&ioapic_lock, flags);
2070 reg_01.raw = io_apic_read(ioapic, 1);
2071 spin_unlock_irqrestore(&ioapic_lock, flags);
2072
2073 return reg_01.bits.entries;
2074 }
2075
2076
2077 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
2078 {
2079 struct IO_APIC_route_entry entry;
2080 unsigned long flags;
2081 int vector;
2082 cpumask_t mask;
2083
2084 if (!IO_APIC_IRQ(irq)) {
2085 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2086 ioapic);
2087 return -EINVAL;
2088 }
2089
2090 /*
2091 * IRQs < 16 are already in the irq_2_pin[] map
2092 */
2093 if (irq >= 16)
2094 add_pin_to_irq(irq, ioapic, pin);
2095
2096
2097 vector = assign_irq_vector(irq, TARGET_CPUS, &mask);
2098 if (vector < 0)
2099 return vector;
2100
2101 /*
2102 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2103 * Note that we mask (disable) IRQs now -- these get enabled when the
2104 * corresponding device driver registers for this IRQ.
2105 */
2106
2107 memset(&entry,0,sizeof(entry));
2108
2109 entry.delivery_mode = INT_DELIVERY_MODE;
2110 entry.dest_mode = INT_DEST_MODE;
2111 entry.dest.logical.logical_dest = cpu_mask_to_apicid(mask);
2112 entry.trigger = triggering;
2113 entry.polarity = polarity;
2114 entry.mask = 1; /* Disabled (masked) */
2115 entry.vector = vector & 0xff;
2116
2117 apic_printk(APIC_VERBOSE,KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry (%d-%d -> 0x%x -> "
2118 "IRQ %d Mode:%i Active:%i)\n", ioapic,
2119 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2120 triggering, polarity);
2121
2122 ioapic_register_intr(irq, entry.vector, triggering);
2123
2124 if (!ioapic && (irq < 16))
2125 disable_8259A_irq(irq);
2126
2127 ioapic_write_entry(ioapic, pin, entry);
2128
2129 spin_lock_irqsave(&ioapic_lock, flags);
2130 set_native_irq_info(irq, TARGET_CPUS);
2131 spin_unlock_irqrestore(&ioapic_lock, flags);
2132
2133 return 0;
2134 }
2135
2136 #endif /* CONFIG_ACPI */
2137
2138
2139 /*
2140 * This function currently is only a helper for the i386 smp boot process where
2141 * we need to reprogram the ioredtbls to cater for the cpus which have come online
2142 * so mask in all cases should simply be TARGET_CPUS
2143 */
2144 #ifdef CONFIG_SMP
2145 void __init setup_ioapic_dest(void)
2146 {
2147 int pin, ioapic, irq, irq_entry;
2148
2149 if (skip_ioapic_setup == 1)
2150 return;
2151
2152 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
2153 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
2154 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2155 if (irq_entry == -1)
2156 continue;
2157 irq = pin_2_irq(irq_entry, ioapic, pin);
2158 set_ioapic_affinity_irq(irq, TARGET_CPUS);
2159 }
2160
2161 }
2162 }
2163 #endif
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