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netxen: defer firmware handshake
[linux-2.6/verdex.git] / drivers / net / netxen / netxen_nic.h
blob7e208b31a27eb3bb2048fdb5f4d0bb7d6d3d8851
1 /*
2 * Copyright (C) 2003 - 2009 NetXen, Inc.
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
18 * MA 02111-1307, USA.
19 *
20 * The full GNU General Public License is included in this distribution
21 * in the file called LICENSE.
22 *
23 * Contact Information:
24 * info@netxen.com
25 * NetXen Inc,
26 * 18922 Forge Drive
27 * Cupertino, CA 95014-0701
28 *
29 */
30
31 #ifndef _NETXEN_NIC_H_
32 #define _NETXEN_NIC_H_
33
34 #include <linux/module.h>
35 #include <linux/kernel.h>
36 #include <linux/types.h>
37 #include <linux/ioport.h>
38 #include <linux/pci.h>
39 #include <linux/netdevice.h>
40 #include <linux/etherdevice.h>
41 #include <linux/ip.h>
42 #include <linux/in.h>
43 #include <linux/tcp.h>
44 #include <linux/skbuff.h>
45
46 #include <linux/ethtool.h>
47 #include <linux/mii.h>
48 #include <linux/timer.h>
49
50 #include <linux/vmalloc.h>
51
52 #include <asm/io.h>
53 #include <asm/byteorder.h>
54
55 #include "netxen_nic_hw.h"
56
57 #define _NETXEN_NIC_LINUX_MAJOR 4
58 #define _NETXEN_NIC_LINUX_MINOR 0
59 #define _NETXEN_NIC_LINUX_SUBVERSION 30
60 #define NETXEN_NIC_LINUX_VERSIONID "4.0.30"
61
62 #define NETXEN_VERSION_CODE(a, b, c) (((a) << 16) + ((b) << 8) + (c))
63
64 #define NETXEN_NUM_FLASH_SECTORS (64)
65 #define NETXEN_FLASH_SECTOR_SIZE (64 * 1024)
66 #define NETXEN_FLASH_TOTAL_SIZE (NETXEN_NUM_FLASH_SECTORS \
67 * NETXEN_FLASH_SECTOR_SIZE)
68
69 #define PHAN_VENDOR_ID 0x4040
70
71 #define RCV_DESC_RINGSIZE(rds_ring) \
72 (sizeof(struct rcv_desc) * (rds_ring)->num_desc)
73 #define RCV_BUFF_RINGSIZE(rds_ring) \
74 (sizeof(struct netxen_rx_buffer) * rds_ring->num_desc)
75 #define STATUS_DESC_RINGSIZE(sds_ring) \
76 (sizeof(struct status_desc) * (sds_ring)->num_desc)
77 #define TX_BUFF_RINGSIZE(tx_ring) \
78 (sizeof(struct netxen_cmd_buffer) * tx_ring->num_desc)
79 #define TX_DESC_RINGSIZE(tx_ring) \
80 (sizeof(struct cmd_desc_type0) * tx_ring->num_desc)
81
82 #define find_diff_among(a,b,range) ((a)<(b)?((b)-(a)):((b)+(range)-(a)))
83
84 #define NETXEN_RCV_PRODUCER_OFFSET 0
85 #define NETXEN_RCV_PEG_DB_ID 2
86 #define NETXEN_HOST_DUMMY_DMA_SIZE 1024
87 #define FLASH_SUCCESS 0
88
89 #define ADDR_IN_WINDOW1(off) \
90 ((off > NETXEN_CRB_PCIX_HOST2) && (off < NETXEN_CRB_MAX)) ? 1 : 0
91
92 /*
93 * normalize a 64MB crb address to 32MB PCI window
94 * To use NETXEN_CRB_NORMALIZE, window _must_ be set to 1
95 */
96 #define NETXEN_CRB_NORMAL(reg) \
97 ((reg) - NETXEN_CRB_PCIX_HOST2 + NETXEN_CRB_PCIX_HOST)
98
99 #define NETXEN_CRB_NORMALIZE(adapter, reg) \
100 pci_base_offset(adapter, NETXEN_CRB_NORMAL(reg))
101
102 #define DB_NORMALIZE(adapter, off) \
103 (adapter->ahw.db_base + (off))
104
105 #define NX_P2_C0 0x24
106 #define NX_P2_C1 0x25
107 #define NX_P3_A0 0x30
108 #define NX_P3_A2 0x30
109 #define NX_P3_B0 0x40
110 #define NX_P3_B1 0x41
111 #define NX_P3_B2 0x42
112
113 #define NX_IS_REVISION_P2(REVISION) (REVISION <= NX_P2_C1)
114 #define NX_IS_REVISION_P3(REVISION) (REVISION >= NX_P3_A0)
115
116 #define FIRST_PAGE_GROUP_START 0
117 #define FIRST_PAGE_GROUP_END 0x100000
118
119 #define SECOND_PAGE_GROUP_START 0x6000000
120 #define SECOND_PAGE_GROUP_END 0x68BC000
121
122 #define THIRD_PAGE_GROUP_START 0x70E4000
123 #define THIRD_PAGE_GROUP_END 0x8000000
124
125 #define FIRST_PAGE_GROUP_SIZE FIRST_PAGE_GROUP_END - FIRST_PAGE_GROUP_START
126 #define SECOND_PAGE_GROUP_SIZE SECOND_PAGE_GROUP_END - SECOND_PAGE_GROUP_START
127 #define THIRD_PAGE_GROUP_SIZE THIRD_PAGE_GROUP_END - THIRD_PAGE_GROUP_START
128
129 #define P2_MAX_MTU (8000)
130 #define P3_MAX_MTU (9600)
131 #define NX_ETHERMTU 1500
132 #define NX_MAX_ETHERHDR 32 /* This contains some padding */
133
134 #define NX_RX_NORMAL_BUF_MAX_LEN (NX_MAX_ETHERHDR + NX_ETHERMTU)
135 #define NX_P2_RX_JUMBO_BUF_MAX_LEN (NX_MAX_ETHERHDR + P2_MAX_MTU)
136 #define NX_P3_RX_JUMBO_BUF_MAX_LEN (NX_MAX_ETHERHDR + P3_MAX_MTU)
137 #define NX_CT_DEFAULT_RX_BUF_LEN 2048
138
139 #define MAX_RX_BUFFER_LENGTH 1760
140 #define MAX_RX_JUMBO_BUFFER_LENGTH 8062
141 #define MAX_RX_LRO_BUFFER_LENGTH (8062)
142 #define RX_DMA_MAP_LEN (MAX_RX_BUFFER_LENGTH - 2)
143 #define RX_JUMBO_DMA_MAP_LEN \
144 (MAX_RX_JUMBO_BUFFER_LENGTH - 2)
145 #define RX_LRO_DMA_MAP_LEN (MAX_RX_LRO_BUFFER_LENGTH - 2)
146
147 /*
148 * Maximum number of ring contexts
149 */
150 #define MAX_RING_CTX 1
151
152 /* Opcodes to be used with the commands */
153 #define TX_ETHER_PKT 0x01
154 #define TX_TCP_PKT 0x02
155 #define TX_UDP_PKT 0x03
156 #define TX_IP_PKT 0x04
157 #define TX_TCP_LSO 0x05
158 #define TX_TCP_LSO6 0x06
159 #define TX_IPSEC 0x07
160 #define TX_IPSEC_CMD 0x0a
161 #define TX_TCPV6_PKT 0x0b
162 #define TX_UDPV6_PKT 0x0c
163
164 /* The following opcodes are for internal consumption. */
165 #define NETXEN_CONTROL_OP 0x10
166 #define PEGNET_REQUEST 0x11
167
168 #define MAX_NUM_CARDS 4
169
170 #define MAX_BUFFERS_PER_CMD 32
171
172 /*
173 * Following are the states of the Phantom. Phantom will set them and
174 * Host will read to check if the fields are correct.
175 */
176 #define PHAN_INITIALIZE_START 0xff00
177 #define PHAN_INITIALIZE_FAILED 0xffff
178 #define PHAN_INITIALIZE_COMPLETE 0xff01
179
180 /* Host writes the following to notify that it has done the init-handshake */
181 #define PHAN_INITIALIZE_ACK 0xf00f
182
183 #define NUM_RCV_DESC_RINGS 3
184 #define NUM_STS_DESC_RINGS 4
185
186 #define RCV_RING_NORMAL 0
187 #define RCV_RING_JUMBO 1
188 #define RCV_RING_LRO 2
189
190 #define MAX_CMD_DESCRIPTORS 4096
191 #define MAX_RCV_DESCRIPTORS 16384
192 #define MAX_CMD_DESCRIPTORS_HOST 1024
193 #define MAX_RCV_DESCRIPTORS_1G 2048
194 #define MAX_RCV_DESCRIPTORS_10G 4096
195 #define MAX_JUMBO_RCV_DESCRIPTORS 1024
196 #define MAX_LRO_RCV_DESCRIPTORS 8
197 #define NETXEN_CTX_SIGNATURE 0xdee0
198 #define NETXEN_RCV_PRODUCER(ringid) (ringid)
199
200 #define PHAN_PEG_RCV_INITIALIZED 0xff01
201 #define PHAN_PEG_RCV_START_INITIALIZE 0xff00
202
203 #define get_next_index(index, length) \
204 (((index) + 1) & ((length) - 1))
205
206 #define get_index_range(index,length,count) \
207 (((index) + (count)) & ((length) - 1))
208
209 #define MPORT_SINGLE_FUNCTION_MODE 0x1111
210 #define MPORT_MULTI_FUNCTION_MODE 0x2222
211
212 #include "netxen_nic_phan_reg.h"
213
214 /*
215 * NetXen host-peg signal message structure
216 *
217 * Bit 0-1 : peg_id => 0x2 for tx and 01 for rx
218 * Bit 2 : priv_id => must be 1
219 * Bit 3-17 : count => for doorbell
220 * Bit 18-27 : ctx_id => Context id
221 * Bit 28-31 : opcode
222 */
223
224 typedef u32 netxen_ctx_msg;
225
226 #define netxen_set_msg_peg_id(config_word, val) \
227 ((config_word) &= ~3, (config_word) |= val & 3)
228 #define netxen_set_msg_privid(config_word) \
229 ((config_word) |= 1 << 2)
230 #define netxen_set_msg_count(config_word, val) \
231 ((config_word) &= ~(0x7fff<<3), (config_word) |= (val & 0x7fff) << 3)
232 #define netxen_set_msg_ctxid(config_word, val) \
233 ((config_word) &= ~(0x3ff<<18), (config_word) |= (val & 0x3ff) << 18)
234 #define netxen_set_msg_opcode(config_word, val) \
235 ((config_word) &= ~(0xf<<28), (config_word) |= (val & 0xf) << 28)
236
237 struct netxen_rcv_context {
238 __le64 rcv_ring_addr;
239 __le32 rcv_ring_size;
240 __le32 rsrvd;
241 };
242
243 struct netxen_ring_ctx {
244
245 /* one command ring */
246 __le64 cmd_consumer_offset;
247 __le64 cmd_ring_addr;
248 __le32 cmd_ring_size;
249 __le32 rsrvd;
250
251 /* three receive rings */
252 struct netxen_rcv_context rcv_ctx[3];
253
254 /* one status ring */
255 __le64 sts_ring_addr;
256 __le32 sts_ring_size;
257
258 __le32 ctx_id;
259 } __attribute__ ((aligned(64)));
260
261 /*
262 * Following data structures describe the descriptors that will be used.
263 * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when
264 * we are doing LSO (above the 1500 size packet) only.
265 */
266
267 /*
268 * The size of reference handle been changed to 16 bits to pass the MSS fields
269 * for the LSO packet
270 */
271
272 #define FLAGS_CHECKSUM_ENABLED 0x01
273 #define FLAGS_LSO_ENABLED 0x02
274 #define FLAGS_IPSEC_SA_ADD 0x04
275 #define FLAGS_IPSEC_SA_DELETE 0x08
276 #define FLAGS_VLAN_TAGGED 0x10
277
278 #define netxen_set_cmd_desc_port(cmd_desc, var) \
279 ((cmd_desc)->port_ctxid |= ((var) & 0x0F))
280 #define netxen_set_cmd_desc_ctxid(cmd_desc, var) \
281 ((cmd_desc)->port_ctxid |= ((var) << 4 & 0xF0))
282
283 #define netxen_set_tx_port(_desc, _port) \
284 (_desc)->port_ctxid = ((_port) & 0xf) | (((_port) << 4) & 0xf0)
285
286 #define netxen_set_tx_flags_opcode(_desc, _flags, _opcode) \
287 (_desc)->flags_opcode = \
288 cpu_to_le16(((_flags) & 0x7f) | (((_opcode) & 0x3f) << 7))
289
290 #define netxen_set_tx_frags_len(_desc, _frags, _len) \
291 (_desc)->num_of_buffers_total_length = \
292 cpu_to_le32(((_frags) & 0xff) | (((_len) & 0xffffff) << 8))
293
294 struct cmd_desc_type0 {
295 u8 tcp_hdr_offset; /* For LSO only */
296 u8 ip_hdr_offset; /* For LSO only */
297 /* Bit pattern: 0-6 flags, 7-12 opcode, 13-15 unused */
298 __le16 flags_opcode;
299 /* Bit pattern: 0-7 total number of segments,
300 8-31 Total size of the packet */
301 __le32 num_of_buffers_total_length;
302 union {
303 struct {
304 __le32 addr_low_part2;
305 __le32 addr_high_part2;
306 };
307 __le64 addr_buffer2;
308 };
309
310 __le16 reference_handle; /* changed to u16 to add mss */
311 __le16 mss; /* passed by NDIS_PACKET for LSO */
312 /* Bit pattern 0-3 port, 0-3 ctx id */
313 u8 port_ctxid;
314 u8 total_hdr_length; /* LSO only : MAC+IP+TCP Hdr size */
315 __le16 conn_id; /* IPSec offoad only */
316
317 union {
318 struct {
319 __le32 addr_low_part3;
320 __le32 addr_high_part3;
321 };
322 __le64 addr_buffer3;
323 };
324 union {
325 struct {
326 __le32 addr_low_part1;
327 __le32 addr_high_part1;
328 };
329 __le64 addr_buffer1;
330 };
331
332 __le16 buffer_length[4];
333
334 union {
335 struct {
336 __le32 addr_low_part4;
337 __le32 addr_high_part4;
338 };
339 __le64 addr_buffer4;
340 };
341
342 __le64 unused;
343
344 } __attribute__ ((aligned(64)));
345
346 /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */
347 struct rcv_desc {
348 __le16 reference_handle;
349 __le16 reserved;
350 __le32 buffer_length; /* allocated buffer length (usually 2K) */
351 __le64 addr_buffer;
352 };
353
354 /* opcode field in status_desc */
355 #define NETXEN_NIC_RXPKT_DESC 0x04
356 #define NETXEN_OLD_RXPKT_DESC 0x3f
357
358 /* for status field in status_desc */
359 #define STATUS_NEED_CKSUM (1)
360 #define STATUS_CKSUM_OK (2)
361
362 /* owner bits of status_desc */
363 #define STATUS_OWNER_HOST (0x1ULL << 56)
364 #define STATUS_OWNER_PHANTOM (0x2ULL << 56)
365
366 /* Note: sizeof(status_desc) should always be a mutliple of 2 */
367
368 #define netxen_get_sts_port(sts_data) \
369 ((sts_data) & 0x0F)
370 #define netxen_get_sts_status(sts_data) \
371 (((sts_data) >> 4) & 0x0F)
372 #define netxen_get_sts_type(sts_data) \
373 (((sts_data) >> 8) & 0x0F)
374 #define netxen_get_sts_totallength(sts_data) \
375 (((sts_data) >> 12) & 0xFFFF)
376 #define netxen_get_sts_refhandle(sts_data) \
377 (((sts_data) >> 28) & 0xFFFF)
378 #define netxen_get_sts_prot(sts_data) \
379 (((sts_data) >> 44) & 0x0F)
380 #define netxen_get_sts_pkt_offset(sts_data) \
381 (((sts_data) >> 48) & 0x1F)
382 #define netxen_get_sts_opcode(sts_data) \
383 (((sts_data) >> 58) & 0x03F)
384
385 struct status_desc {
386 /* Bit pattern: 0-3 port, 4-7 status, 8-11 type, 12-27 total_length
387 28-43 reference_handle, 44-47 protocol, 48-52 pkt_offset
388 53-55 desc_cnt, 56-57 owner, 58-63 opcode
389 */
390 __le64 status_desc_data;
391 union {
392 struct {
393 __le32 hash_value;
394 u8 hash_type;
395 u8 msg_type;
396 u8 unused;
397 union {
398 /* Bit pattern: 0-6 lro_count indicates frag
399 * sequence, 7 last_frag indicates last frag
400 */
401 u8 lro;
402
403 /* chained buffers */
404 u8 nr_frags;
405 };
406 };
407 struct {
408 __le16 frag_handles[4];
409 };
410 };
411 } __attribute__ ((aligned(16)));
412
413 /* The version of the main data structure */
414 #define NETXEN_BDINFO_VERSION 1
415
416 /* Magic number to let user know flash is programmed */
417 #define NETXEN_BDINFO_MAGIC 0x12345678
418
419 /* Max number of Gig ports on a Phantom board */
420 #define NETXEN_MAX_PORTS 4
421
422 #define NETXEN_BRDTYPE_P1_BD 0x0000
423 #define NETXEN_BRDTYPE_P1_SB 0x0001
424 #define NETXEN_BRDTYPE_P1_SMAX 0x0002
425 #define NETXEN_BRDTYPE_P1_SOCK 0x0003
426
427 #define NETXEN_BRDTYPE_P2_SOCK_31 0x0008
428 #define NETXEN_BRDTYPE_P2_SOCK_35 0x0009
429 #define NETXEN_BRDTYPE_P2_SB35_4G 0x000a
430 #define NETXEN_BRDTYPE_P2_SB31_10G 0x000b
431 #define NETXEN_BRDTYPE_P2_SB31_2G 0x000c
432
433 #define NETXEN_BRDTYPE_P2_SB31_10G_IMEZ 0x000d
434 #define NETXEN_BRDTYPE_P2_SB31_10G_HMEZ 0x000e
435 #define NETXEN_BRDTYPE_P2_SB31_10G_CX4 0x000f
436
437 #define NETXEN_BRDTYPE_P3_REF_QG 0x0021
438 #define NETXEN_BRDTYPE_P3_HMEZ 0x0022
439 #define NETXEN_BRDTYPE_P3_10G_CX4_LP 0x0023
440 #define NETXEN_BRDTYPE_P3_4_GB 0x0024
441 #define NETXEN_BRDTYPE_P3_IMEZ 0x0025
442 #define NETXEN_BRDTYPE_P3_10G_SFP_PLUS 0x0026
443 #define NETXEN_BRDTYPE_P3_10000_BASE_T 0x0027
444 #define NETXEN_BRDTYPE_P3_XG_LOM 0x0028
445 #define NETXEN_BRDTYPE_P3_4_GB_MM 0x0029
446 #define NETXEN_BRDTYPE_P3_10G_SFP_CT 0x002a
447 #define NETXEN_BRDTYPE_P3_10G_SFP_QT 0x002b
448 #define NETXEN_BRDTYPE_P3_10G_CX4 0x0031
449 #define NETXEN_BRDTYPE_P3_10G_XFP 0x0032
450 #define NETXEN_BRDTYPE_P3_10G_TP 0x0080
451
452 struct netxen_board_info {
453 u32 header_version;
454
455 u32 board_mfg;
456 u32 board_type;
457 u32 board_num;
458 u32 chip_id;
459 u32 chip_minor;
460 u32 chip_major;
461 u32 chip_pkg;
462 u32 chip_lot;
463
464 u32 port_mask; /* available niu ports */
465 u32 peg_mask; /* available pegs */
466 u32 icache_ok; /* can we run with icache? */
467 u32 dcache_ok; /* can we run with dcache? */
468 u32 casper_ok;
469
470 u32 mac_addr_lo_0;
471 u32 mac_addr_lo_1;
472 u32 mac_addr_lo_2;
473 u32 mac_addr_lo_3;
474
475 /* MN-related config */
476 u32 mn_sync_mode; /* enable/ sync shift cclk/ sync shift mclk */
477 u32 mn_sync_shift_cclk;
478 u32 mn_sync_shift_mclk;
479 u32 mn_wb_en;
480 u32 mn_crystal_freq; /* in MHz */
481 u32 mn_speed; /* in MHz */
482 u32 mn_org;
483 u32 mn_depth;
484 u32 mn_ranks_0; /* ranks per slot */
485 u32 mn_ranks_1; /* ranks per slot */
486 u32 mn_rd_latency_0;
487 u32 mn_rd_latency_1;
488 u32 mn_rd_latency_2;
489 u32 mn_rd_latency_3;
490 u32 mn_rd_latency_4;
491 u32 mn_rd_latency_5;
492 u32 mn_rd_latency_6;
493 u32 mn_rd_latency_7;
494 u32 mn_rd_latency_8;
495 u32 mn_dll_val[18];
496 u32 mn_mode_reg; /* MIU DDR Mode Register */
497 u32 mn_ext_mode_reg; /* MIU DDR Extended Mode Register */
498 u32 mn_timing_0; /* MIU Memory Control Timing Rgister */
499 u32 mn_timing_1; /* MIU Extended Memory Ctrl Timing Register */
500 u32 mn_timing_2; /* MIU Extended Memory Ctrl Timing2 Register */
501
502 /* SN-related config */
503 u32 sn_sync_mode; /* enable/ sync shift cclk / sync shift mclk */
504 u32 sn_pt_mode; /* pass through mode */
505 u32 sn_ecc_en;
506 u32 sn_wb_en;
507 u32 sn_crystal_freq;
508 u32 sn_speed;
509 u32 sn_org;
510 u32 sn_depth;
511 u32 sn_dll_tap;
512 u32 sn_rd_latency;
513
514 u32 mac_addr_hi_0;
515 u32 mac_addr_hi_1;
516 u32 mac_addr_hi_2;
517 u32 mac_addr_hi_3;
518
519 u32 magic; /* indicates flash has been initialized */
520
521 u32 mn_rdimm;
522 u32 mn_dll_override;
523
524 };
525
526 #define FLASH_NUM_PORTS (4)
527
528 struct netxen_flash_mac_addr {
529 u32 flash_addr[32];
530 };
531
532 struct netxen_user_old_info {
533 u8 flash_md5[16];
534 u8 crbinit_md5[16];
535 u8 brdcfg_md5[16];
536 /* bootloader */
537 u32 bootld_version;
538 u32 bootld_size;
539 u8 bootld_md5[16];
540 /* image */
541 u32 image_version;
542 u32 image_size;
543 u8 image_md5[16];
544 /* primary image status */
545 u32 primary_status;
546 u32 secondary_present;
547
548 /* MAC address , 4 ports */
549 struct netxen_flash_mac_addr mac_addr[FLASH_NUM_PORTS];
550 };
551 #define FLASH_NUM_MAC_PER_PORT 32
552 struct netxen_user_info {
553 u8 flash_md5[16 * 64];
554 /* bootloader */
555 u32 bootld_version;
556 u32 bootld_size;
557 /* image */
558 u32 image_version;
559 u32 image_size;
560 /* primary image status */
561 u32 primary_status;
562 u32 secondary_present;
563
564 /* MAC address , 4 ports, 32 address per port */
565 u64 mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT];
566 u32 sub_sys_id;
567 u8 serial_num[32];
568
569 /* Any user defined data */
570 };
571
572 /*
573 * Flash Layout - new format.
574 */
575 struct netxen_new_user_info {
576 u8 flash_md5[16 * 64];
577 /* bootloader */
578 u32 bootld_version;
579 u32 bootld_size;
580 /* image */
581 u32 image_version;
582 u32 image_size;
583 /* primary image status */
584 u32 primary_status;
585 u32 secondary_present;
586
587 /* MAC address , 4 ports, 32 address per port */
588 u64 mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT];
589 u32 sub_sys_id;
590 u8 serial_num[32];
591
592 /* Any user defined data */
593 };
594
595 #define SECONDARY_IMAGE_PRESENT 0xb3b4b5b6
596 #define SECONDARY_IMAGE_ABSENT 0xffffffff
597 #define PRIMARY_IMAGE_GOOD 0x5a5a5a5a
598 #define PRIMARY_IMAGE_BAD 0xffffffff
599
600 /* Flash memory map */
601 #define NETXEN_CRBINIT_START 0 /* crbinit section */
602 #define NETXEN_BRDCFG_START 0x4000 /* board config */
603 #define NETXEN_INITCODE_START 0x6000 /* pegtune code */
604 #define NETXEN_BOOTLD_START 0x10000 /* bootld */
605 #define NETXEN_IMAGE_START 0x43000 /* compressed image */
606 #define NETXEN_SECONDARY_START 0x200000 /* backup images */
607 #define NETXEN_PXE_START 0x3E0000 /* PXE boot rom */
608 #define NETXEN_USER_START 0x3E8000 /* Firmare info */
609 #define NETXEN_FIXED_START 0x3F0000 /* backup of crbinit */
610
611 #define NX_FW_VERSION_OFFSET (NETXEN_USER_START+0x408)
612 #define NX_FW_SIZE_OFFSET (NETXEN_USER_START+0x40c)
613 #define NX_BIOS_VERSION_OFFSET (NETXEN_USER_START+0x83c)
614 #define NX_FW_MAGIC_OFFSET (NETXEN_BRDCFG_START+0x128)
615 #define NX_FW_MIN_SIZE (0x3fffff)
616 #define NX_P2_MN_ROMIMAGE 0
617 #define NX_P3_CT_ROMIMAGE 1
618 #define NX_P3_MN_ROMIMAGE 2
619
620 #define NETXEN_USER_START_OLD NETXEN_PXE_START /* for backward compatibility */
621
622 #define NETXEN_FLASH_START (NETXEN_CRBINIT_START)
623 #define NETXEN_INIT_SECTOR (0)
624 #define NETXEN_PRIMARY_START (NETXEN_BOOTLD_START)
625 #define NETXEN_FLASH_CRBINIT_SIZE (0x4000)
626 #define NETXEN_FLASH_BRDCFG_SIZE (sizeof(struct netxen_board_info))
627 #define NETXEN_FLASH_USER_SIZE (sizeof(struct netxen_user_info)/sizeof(u32))
628 #define NETXEN_FLASH_SECONDARY_SIZE (NETXEN_USER_START-NETXEN_SECONDARY_START)
629 #define NETXEN_NUM_PRIMARY_SECTORS (0x20)
630 #define NETXEN_NUM_CONFIG_SECTORS (1)
631 extern char netxen_nic_driver_name[];
632
633 /* Number of status descriptors to handle per interrupt */
634 #define MAX_STATUS_HANDLE (64)
635
636 /*
637 * netxen_skb_frag{} is to contain mapping info for each SG list. This
638 * has to be freed when DMA is complete. This is part of netxen_tx_buffer{}.
639 */
640 struct netxen_skb_frag {
641 u64 dma;
642 u64 length;
643 };
644
645 #define _netxen_set_bits(config_word, start, bits, val) {\
646 unsigned long long __tmask = (((1ULL << (bits)) - 1) << (start));\
647 unsigned long long __tvalue = (val); \
648 (config_word) &= ~__tmask; \
649 (config_word) |= (((__tvalue) << (start)) & __tmask); \
650 }
651
652 #define _netxen_clear_bits(config_word, start, bits) {\
653 unsigned long long __tmask = (((1ULL << (bits)) - 1) << (start)); \
654 (config_word) &= ~__tmask; \
655 }
656
657 /* Following defines are for the state of the buffers */
658 #define NETXEN_BUFFER_FREE 0
659 #define NETXEN_BUFFER_BUSY 1
660
661 /*
662 * There will be one netxen_buffer per skb packet. These will be
663 * used to save the dma info for pci_unmap_page()
664 */
665 struct netxen_cmd_buffer {
666 struct sk_buff *skb;
667 struct netxen_skb_frag frag_array[MAX_BUFFERS_PER_CMD + 1];
668 u32 frag_count;
669 };
670
671 /* In rx_buffer, we do not need multiple fragments as is a single buffer */
672 struct netxen_rx_buffer {
673 struct list_head list;
674 struct sk_buff *skb;
675 u64 dma;
676 u16 ref_handle;
677 u16 state;
678 };
679
680 /* Board types */
681 #define NETXEN_NIC_GBE 0x01
682 #define NETXEN_NIC_XGBE 0x02
683
684 /*
685 * One hardware_context{} per adapter
686 * contains interrupt info as well shared hardware info.
687 */
688 struct netxen_hardware_context {
689 void __iomem *pci_base0;
690 void __iomem *pci_base1;
691 void __iomem *pci_base2;
692 void __iomem *db_base;
693 unsigned long db_len;
694 unsigned long pci_len0;
695
696 int qdr_sn_window;
697 int ddr_mn_window;
698 unsigned long mn_win_crb;
699 unsigned long ms_win_crb;
700
701 u8 cut_through;
702 u8 revision_id;
703 u8 pci_func;
704 u8 linkup;
705 u16 port_type;
706 u16 board_type;
707 };
708
709 #define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */
710 #define ETHERNET_FCS_SIZE 4
711
712 struct netxen_adapter_stats {
713 u64 xmitcalled;
714 u64 xmitfinished;
715 u64 rxdropped;
716 u64 txdropped;
717 u64 csummed;
718 u64 no_rcv;
719 u64 rxbytes;
720 u64 txbytes;
721 };
722
723 /*
724 * Rcv Descriptor Context. One such per Rcv Descriptor. There may
725 * be one Rcv Descriptor for normal packets, one for jumbo and may be others.
726 */
727 struct nx_host_rds_ring {
728 u32 producer;
729 u32 crb_rcv_producer;
730 u32 num_desc;
731 u32 dma_size;
732 u32 skb_size;
733 u32 flags;
734 struct rcv_desc *desc_head;
735 struct netxen_rx_buffer *rx_buf_arr;
736 struct list_head free_list;
737 spinlock_t lock;
738 dma_addr_t phys_addr;
739 };
740
741 struct nx_host_sds_ring {
742 u32 consumer;
743 u32 crb_sts_consumer;
744 u32 crb_intr_mask;
745 u32 num_desc;
746
747 struct status_desc *desc_head;
748 struct netxen_adapter *adapter;
749 struct napi_struct napi;
750 struct list_head free_list[NUM_RCV_DESC_RINGS];
751
752 int irq;
753
754 dma_addr_t phys_addr;
755 char name[IFNAMSIZ+4];
756 };
757
758 struct nx_host_tx_ring {
759 u32 producer;
760 __le32 *hw_consumer;
761 u32 sw_consumer;
762 u32 crb_cmd_producer;
763 u32 crb_cmd_consumer;
764 u32 num_desc;
765
766 struct netxen_cmd_buffer *cmd_buf_arr;
767 struct cmd_desc_type0 *desc_head;
768 dma_addr_t phys_addr;
769 };
770
771 /*
772 * Receive context. There is one such structure per instance of the
773 * receive processing. Any state information that is relevant to
774 * the receive, and is must be in this structure. The global data may be
775 * present elsewhere.
776 */
777 struct netxen_recv_context {
778 u32 state;
779 u16 context_id;
780 u16 virt_port;
781
782 struct nx_host_rds_ring rds_rings[NUM_RCV_DESC_RINGS];
783 struct nx_host_sds_ring sds_rings[NUM_STS_DESC_RINGS];
784 };
785
786 /* New HW context creation */
787
788 #define NX_OS_CRB_RETRY_COUNT 4000
789 #define NX_CDRP_SIGNATURE_MAKE(pcifn, version) \
790 (((pcifn) & 0xff) | (((version) & 0xff) << 8) | (0xcafe << 16))
791
792 #define NX_CDRP_CLEAR 0x00000000
793 #define NX_CDRP_CMD_BIT 0x80000000
794
795 /*
796 * All responses must have the NX_CDRP_CMD_BIT cleared
797 * in the crb NX_CDRP_CRB_OFFSET.
798 */
799 #define NX_CDRP_FORM_RSP(rsp) (rsp)
800 #define NX_CDRP_IS_RSP(rsp) (((rsp) & NX_CDRP_CMD_BIT) == 0)
801
802 #define NX_CDRP_RSP_OK 0x00000001
803 #define NX_CDRP_RSP_FAIL 0x00000002
804 #define NX_CDRP_RSP_TIMEOUT 0x00000003
805
806 /*
807 * All commands must have the NX_CDRP_CMD_BIT set in
808 * the crb NX_CDRP_CRB_OFFSET.
809 */
810 #define NX_CDRP_FORM_CMD(cmd) (NX_CDRP_CMD_BIT | (cmd))
811 #define NX_CDRP_IS_CMD(cmd) (((cmd) & NX_CDRP_CMD_BIT) != 0)
812
813 #define NX_CDRP_CMD_SUBMIT_CAPABILITIES 0x00000001
814 #define NX_CDRP_CMD_READ_MAX_RDS_PER_CTX 0x00000002
815 #define NX_CDRP_CMD_READ_MAX_SDS_PER_CTX 0x00000003
816 #define NX_CDRP_CMD_READ_MAX_RULES_PER_CTX 0x00000004
817 #define NX_CDRP_CMD_READ_MAX_RX_CTX 0x00000005
818 #define NX_CDRP_CMD_READ_MAX_TX_CTX 0x00000006
819 #define NX_CDRP_CMD_CREATE_RX_CTX 0x00000007
820 #define NX_CDRP_CMD_DESTROY_RX_CTX 0x00000008
821 #define NX_CDRP_CMD_CREATE_TX_CTX 0x00000009
822 #define NX_CDRP_CMD_DESTROY_TX_CTX 0x0000000a
823 #define NX_CDRP_CMD_SETUP_STATISTICS 0x0000000e
824 #define NX_CDRP_CMD_GET_STATISTICS 0x0000000f
825 #define NX_CDRP_CMD_DELETE_STATISTICS 0x00000010
826 #define NX_CDRP_CMD_SET_MTU 0x00000012
827 #define NX_CDRP_CMD_MAX 0x00000013
828
829 #define NX_RCODE_SUCCESS 0
830 #define NX_RCODE_NO_HOST_MEM 1
831 #define NX_RCODE_NO_HOST_RESOURCE 2
832 #define NX_RCODE_NO_CARD_CRB 3
833 #define NX_RCODE_NO_CARD_MEM 4
834 #define NX_RCODE_NO_CARD_RESOURCE 5
835 #define NX_RCODE_INVALID_ARGS 6
836 #define NX_RCODE_INVALID_ACTION 7
837 #define NX_RCODE_INVALID_STATE 8
838 #define NX_RCODE_NOT_SUPPORTED 9
839 #define NX_RCODE_NOT_PERMITTED 10
840 #define NX_RCODE_NOT_READY 11
841 #define NX_RCODE_DOES_NOT_EXIST 12
842 #define NX_RCODE_ALREADY_EXISTS 13
843 #define NX_RCODE_BAD_SIGNATURE 14
844 #define NX_RCODE_CMD_NOT_IMPL 15
845 #define NX_RCODE_CMD_INVALID 16
846 #define NX_RCODE_TIMEOUT 17
847 #define NX_RCODE_CMD_FAILED 18
848 #define NX_RCODE_MAX_EXCEEDED 19
849 #define NX_RCODE_MAX 20
850
851 #define NX_DESTROY_CTX_RESET 0
852 #define NX_DESTROY_CTX_D3_RESET 1
853 #define NX_DESTROY_CTX_MAX 2
854
855 /*
856 * Capabilities
857 */
858 #define NX_CAP_BIT(class, bit) (1 << bit)
859 #define NX_CAP0_LEGACY_CONTEXT NX_CAP_BIT(0, 0)
860 #define NX_CAP0_MULTI_CONTEXT NX_CAP_BIT(0, 1)
861 #define NX_CAP0_LEGACY_MN NX_CAP_BIT(0, 2)
862 #define NX_CAP0_LEGACY_MS NX_CAP_BIT(0, 3)
863 #define NX_CAP0_CUT_THROUGH NX_CAP_BIT(0, 4)
864 #define NX_CAP0_LRO NX_CAP_BIT(0, 5)
865 #define NX_CAP0_LSO NX_CAP_BIT(0, 6)
866 #define NX_CAP0_JUMBO_CONTIGUOUS NX_CAP_BIT(0, 7)
867 #define NX_CAP0_LRO_CONTIGUOUS NX_CAP_BIT(0, 8)
868
869 /*
870 * Context state
871 */
872 #define NX_HOST_CTX_STATE_FREED 0
873 #define NX_HOST_CTX_STATE_ALLOCATED 1
874 #define NX_HOST_CTX_STATE_ACTIVE 2
875 #define NX_HOST_CTX_STATE_DISABLED 3
876 #define NX_HOST_CTX_STATE_QUIESCED 4
877 #define NX_HOST_CTX_STATE_MAX 5
878
879 /*
880 * Rx context
881 */
882
883 typedef struct {
884 __le64 host_phys_addr; /* Ring base addr */
885 __le32 ring_size; /* Ring entries */
886 __le16 msi_index;
887 __le16 rsvd; /* Padding */
888 } nx_hostrq_sds_ring_t;
889
890 typedef struct {
891 __le64 host_phys_addr; /* Ring base addr */
892 __le64 buff_size; /* Packet buffer size */
893 __le32 ring_size; /* Ring entries */
894 __le32 ring_kind; /* Class of ring */
895 } nx_hostrq_rds_ring_t;
896
897 typedef struct {
898 __le64 host_rsp_dma_addr; /* Response dma'd here */
899 __le32 capabilities[4]; /* Flag bit vector */
900 __le32 host_int_crb_mode; /* Interrupt crb usage */
901 __le32 host_rds_crb_mode; /* RDS crb usage */
902 /* These ring offsets are relative to data[0] below */
903 __le32 rds_ring_offset; /* Offset to RDS config */
904 __le32 sds_ring_offset; /* Offset to SDS config */
905 __le16 num_rds_rings; /* Count of RDS rings */
906 __le16 num_sds_rings; /* Count of SDS rings */
907 __le16 rsvd1; /* Padding */
908 __le16 rsvd2; /* Padding */
909 u8 reserved[128]; /* reserve space for future expansion*/
910 /* MUST BE 64-bit aligned.
911 The following is packed:
912 - N hostrq_rds_rings
913 - N hostrq_sds_rings */
914 char data[0];
915 } nx_hostrq_rx_ctx_t;
916
917 typedef struct {
918 __le32 host_producer_crb; /* Crb to use */
919 __le32 rsvd1; /* Padding */
920 } nx_cardrsp_rds_ring_t;
921
922 typedef struct {
923 __le32 host_consumer_crb; /* Crb to use */
924 __le32 interrupt_crb; /* Crb to use */
925 } nx_cardrsp_sds_ring_t;
926
927 typedef struct {
928 /* These ring offsets are relative to data[0] below */
929 __le32 rds_ring_offset; /* Offset to RDS config */
930 __le32 sds_ring_offset; /* Offset to SDS config */
931 __le32 host_ctx_state; /* Starting State */
932 __le32 num_fn_per_port; /* How many PCI fn share the port */
933 __le16 num_rds_rings; /* Count of RDS rings */
934 __le16 num_sds_rings; /* Count of SDS rings */
935 __le16 context_id; /* Handle for context */
936 u8 phys_port; /* Physical id of port */
937 u8 virt_port; /* Virtual/Logical id of port */
938 u8 reserved[128]; /* save space for future expansion */
939 /* MUST BE 64-bit aligned.
940 The following is packed:
941 - N cardrsp_rds_rings
942 - N cardrs_sds_rings */
943 char data[0];
944 } nx_cardrsp_rx_ctx_t;
945
946 #define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \
947 (sizeof(HOSTRQ_RX) + \
948 (rds_rings)*(sizeof(nx_hostrq_rds_ring_t)) + \
949 (sds_rings)*(sizeof(nx_hostrq_sds_ring_t)))
950
951 #define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \
952 (sizeof(CARDRSP_RX) + \
953 (rds_rings)*(sizeof(nx_cardrsp_rds_ring_t)) + \
954 (sds_rings)*(sizeof(nx_cardrsp_sds_ring_t)))
955
956 /*
957 * Tx context
958 */
959
960 typedef struct {
961 __le64 host_phys_addr; /* Ring base addr */
962 __le32 ring_size; /* Ring entries */
963 __le32 rsvd; /* Padding */
964 } nx_hostrq_cds_ring_t;
965
966 typedef struct {
967 __le64 host_rsp_dma_addr; /* Response dma'd here */
968 __le64 cmd_cons_dma_addr; /* */
969 __le64 dummy_dma_addr; /* */
970 __le32 capabilities[4]; /* Flag bit vector */
971 __le32 host_int_crb_mode; /* Interrupt crb usage */
972 __le32 rsvd1; /* Padding */
973 __le16 rsvd2; /* Padding */
974 __le16 interrupt_ctl;
975 __le16 msi_index;
976 __le16 rsvd3; /* Padding */
977 nx_hostrq_cds_ring_t cds_ring; /* Desc of cds ring */
978 u8 reserved[128]; /* future expansion */
979 } nx_hostrq_tx_ctx_t;
980
981 typedef struct {
982 __le32 host_producer_crb; /* Crb to use */
983 __le32 interrupt_crb; /* Crb to use */
984 } nx_cardrsp_cds_ring_t;
985
986 typedef struct {
987 __le32 host_ctx_state; /* Starting state */
988 __le16 context_id; /* Handle for context */
989 u8 phys_port; /* Physical id of port */
990 u8 virt_port; /* Virtual/Logical id of port */
991 nx_cardrsp_cds_ring_t cds_ring; /* Card cds settings */
992 u8 reserved[128]; /* future expansion */
993 } nx_cardrsp_tx_ctx_t;
994
995 #define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX))
996 #define SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX))
997
998 /* CRB */
999
1000 #define NX_HOST_RDS_CRB_MODE_UNIQUE 0
1001 #define NX_HOST_RDS_CRB_MODE_SHARED 1
1002 #define NX_HOST_RDS_CRB_MODE_CUSTOM 2
1003 #define NX_HOST_RDS_CRB_MODE_MAX 3
1004
1005 #define NX_HOST_INT_CRB_MODE_UNIQUE 0
1006 #define NX_HOST_INT_CRB_MODE_SHARED 1
1007 #define NX_HOST_INT_CRB_MODE_NORX 2
1008 #define NX_HOST_INT_CRB_MODE_NOTX 3
1009 #define NX_HOST_INT_CRB_MODE_NORXTX 4
1010
1011
1012 /* MAC */
1013
1014 #define MC_COUNT_P2 16
1015 #define MC_COUNT_P3 38
1016
1017 #define NETXEN_MAC_NOOP 0
1018 #define NETXEN_MAC_ADD 1
1019 #define NETXEN_MAC_DEL 2
1020
1021 typedef struct nx_mac_list_s {
1022 struct nx_mac_list_s *next;
1023 uint8_t mac_addr[MAX_ADDR_LEN];
1024 } nx_mac_list_t;
1025
1026 /*
1027 * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is
1028 * adjusted based on configured MTU.
1029 */
1030 #define NETXEN_DEFAULT_INTR_COALESCE_RX_TIME_US 3
1031 #define NETXEN_DEFAULT_INTR_COALESCE_RX_PACKETS 256
1032 #define NETXEN_DEFAULT_INTR_COALESCE_TX_PACKETS 64
1033 #define NETXEN_DEFAULT_INTR_COALESCE_TX_TIME_US 4
1034
1035 #define NETXEN_NIC_INTR_DEFAULT 0x04
1036
1037 typedef union {
1038 struct {
1039 uint16_t rx_packets;
1040 uint16_t rx_time_us;
1041 uint16_t tx_packets;
1042 uint16_t tx_time_us;
1043 } data;
1044 uint64_t word;
1045 } nx_nic_intr_coalesce_data_t;
1046
1047 typedef struct {
1048 uint16_t stats_time_us;
1049 uint16_t rate_sample_time;
1050 uint16_t flags;
1051 uint16_t rsvd_1;
1052 uint32_t low_threshold;
1053 uint32_t high_threshold;
1054 nx_nic_intr_coalesce_data_t normal;
1055 nx_nic_intr_coalesce_data_t low;
1056 nx_nic_intr_coalesce_data_t high;
1057 nx_nic_intr_coalesce_data_t irq;
1058 } nx_nic_intr_coalesce_t;
1059
1060 #define NX_HOST_REQUEST 0x13
1061 #define NX_NIC_REQUEST 0x14
1062
1063 #define NX_MAC_EVENT 0x1
1064
1065 /*
1066 * Driver --> Firmware
1067 */
1068 #define NX_NIC_H2C_OPCODE_START 0
1069 #define NX_NIC_H2C_OPCODE_CONFIG_RSS 1
1070 #define NX_NIC_H2C_OPCODE_CONFIG_RSS_TBL 2
1071 #define NX_NIC_H2C_OPCODE_CONFIG_INTR_COALESCE 3
1072 #define NX_NIC_H2C_OPCODE_CONFIG_LED 4
1073 #define NX_NIC_H2C_OPCODE_CONFIG_PROMISCUOUS 5
1074 #define NX_NIC_H2C_OPCODE_CONFIG_L2_MAC 6
1075 #define NX_NIC_H2C_OPCODE_LRO_REQUEST 7
1076 #define NX_NIC_H2C_OPCODE_GET_SNMP_STATS 8
1077 #define NX_NIC_H2C_OPCODE_PROXY_START_REQUEST 9
1078 #define NX_NIC_H2C_OPCODE_PROXY_STOP_REQUEST 10
1079 #define NX_NIC_H2C_OPCODE_PROXY_SET_MTU 11
1080 #define NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE 12
1081 #define NX_NIC_H2C_OPCODE_GET_FINGER_PRINT_REQUEST 13
1082 #define NX_NIC_H2C_OPCODE_INSTALL_LICENSE_REQUEST 14
1083 #define NX_NIC_H2C_OPCODE_GET_LICENSE_CAPABILITY_REQUEST 15
1084 #define NX_NIC_H2C_OPCODE_GET_NET_STATS 16
1085 #define NX_NIC_H2C_OPCODE_PROXY_UPDATE_P2V 17
1086 #define NX_NIC_H2C_OPCODE_CONFIG_IPADDR 18
1087 #define NX_NIC_H2C_OPCODE_CONFIG_LOOPBACK 19
1088 #define NX_NIC_H2C_OPCODE_PROXY_STOP_DONE 20
1089 #define NX_NIC_H2C_OPCODE_GET_LINKEVENT 21
1090 #define NX_NIC_C2C_OPCODE 22
1091 #define NX_NIC_H2C_OPCODE_LAST 23
1092
1093 /*
1094 * Firmware --> Driver
1095 */
1096
1097 #define NX_NIC_C2H_OPCODE_START 128
1098 #define NX_NIC_C2H_OPCODE_CONFIG_RSS_RESPONSE 129
1099 #define NX_NIC_C2H_OPCODE_CONFIG_RSS_TBL_RESPONSE 130
1100 #define NX_NIC_C2H_OPCODE_CONFIG_MAC_RESPONSE 131
1101 #define NX_NIC_C2H_OPCODE_CONFIG_PROMISCUOUS_RESPONSE 132
1102 #define NX_NIC_C2H_OPCODE_CONFIG_L2_MAC_RESPONSE 133
1103 #define NX_NIC_C2H_OPCODE_LRO_DELETE_RESPONSE 134
1104 #define NX_NIC_C2H_OPCODE_LRO_ADD_FAILURE_RESPONSE 135
1105 #define NX_NIC_C2H_OPCODE_GET_SNMP_STATS 136
1106 #define NX_NIC_C2H_OPCODE_GET_FINGER_PRINT_REPLY 137
1107 #define NX_NIC_C2H_OPCODE_INSTALL_LICENSE_REPLY 138
1108 #define NX_NIC_C2H_OPCODE_GET_LICENSE_CAPABILITIES_REPLY 139
1109 #define NX_NIC_C2H_OPCODE_GET_NET_STATS_RESPONSE 140
1110 #define NX_NIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE 141
1111 #define NX_NIC_C2H_OPCODE_LAST 142
1112
1113 #define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */
1114 #define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */
1115 #define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */
1116
1117 typedef struct {
1118 __le64 qhdr;
1119 __le64 req_hdr;
1120 __le64 words[6];
1121 } nx_nic_req_t;
1122
1123 typedef struct {
1124 u8 op;
1125 u8 tag;
1126 u8 mac_addr[6];
1127 } nx_mac_req_t;
1128
1129 #define MAX_PENDING_DESC_BLOCK_SIZE 64
1130
1131 #define NETXEN_NIC_MSI_ENABLED 0x02
1132 #define NETXEN_NIC_MSIX_ENABLED 0x04
1133 #define NETXEN_IS_MSI_FAMILY(adapter) \
1134 ((adapter)->flags & (NETXEN_NIC_MSI_ENABLED | NETXEN_NIC_MSIX_ENABLED))
1135
1136 #define MSIX_ENTRIES_PER_ADAPTER NUM_STS_DESC_RINGS
1137 #define NETXEN_MSIX_TBL_SPACE 8192
1138 #define NETXEN_PCI_REG_MSIX_TBL 0x44
1139
1140 #define NETXEN_DB_MAPSIZE_BYTES 0x1000
1141
1142 #define NETXEN_NETDEV_WEIGHT 128
1143 #define NETXEN_ADAPTER_UP_MAGIC 777
1144 #define NETXEN_NIC_PEG_TUNE 0
1145
1146 struct netxen_dummy_dma {
1147 void *addr;
1148 dma_addr_t phys_addr;
1149 };
1150
1151 struct netxen_adapter {
1152 struct netxen_hardware_context ahw;
1153
1154 struct net_device *netdev;
1155 struct pci_dev *pdev;
1156 nx_mac_list_t *mac_list;
1157
1158 u32 curr_window;
1159 u32 crb_win;
1160 rwlock_t adapter_lock;
1161
1162 spinlock_t tx_clean_lock;
1163
1164 u32 num_txd;
1165 u32 num_rxd;
1166 u32 num_jumbo_rxd;
1167 u32 num_lro_rxd;
1168
1169 u8 max_rds_rings;
1170 u8 max_sds_rings;
1171 u8 driver_mismatch;
1172 u8 msix_supported;
1173 u8 rx_csum;
1174 u8 pci_using_dac;
1175 u8 portnum;
1176 u8 physical_port;
1177
1178 u8 mc_enabled;
1179 u8 max_mc_count;
1180 u16 tx_context_id;
1181 u16 mtu;
1182 u16 is_up;
1183 u16 link_speed;
1184 u16 link_duplex;
1185 u16 link_autoneg;
1186 u16 resv1;
1187
1188 u32 resv2;
1189 u32 flags;
1190 u32 irq;
1191 u32 temp;
1192 u32 fw_major;
1193 u32 fw_version;
1194
1195 struct netxen_adapter_stats stats;
1196
1197 struct netxen_recv_context recv_ctx;
1198 struct nx_host_tx_ring tx_ring;
1199
1200 /* Context interface shared between card and host */
1201 struct netxen_ring_ctx *ctx_desc;
1202 dma_addr_t ctx_desc_phys_addr;
1203 int (*enable_phy_interrupts) (struct netxen_adapter *);
1204 int (*disable_phy_interrupts) (struct netxen_adapter *);
1205 int (*macaddr_set) (struct netxen_adapter *, netxen_ethernet_macaddr_t);
1206 int (*set_mtu) (struct netxen_adapter *, int);
1207 int (*set_promisc) (struct netxen_adapter *, u32);
1208 int (*phy_read) (struct netxen_adapter *, long reg, u32 *);
1209 int (*phy_write) (struct netxen_adapter *, long reg, u32 val);
1210 int (*init_port) (struct netxen_adapter *, int);
1211 int (*stop_port) (struct netxen_adapter *);
1212
1213 int (*hw_read_wx)(struct netxen_adapter *, ulong, void *, int);
1214 int (*hw_write_wx)(struct netxen_adapter *, ulong, void *, int);
1215 int (*pci_mem_read)(struct netxen_adapter *, u64, void *, int);
1216 int (*pci_mem_write)(struct netxen_adapter *, u64, void *, int);
1217 int (*pci_write_immediate)(struct netxen_adapter *, u64, u32);
1218 u32 (*pci_read_immediate)(struct netxen_adapter *, u64);
1219 void (*pci_write_normalize)(struct netxen_adapter *, u64, u32);
1220 u32 (*pci_read_normalize)(struct netxen_adapter *, u64);
1221 unsigned long (*pci_set_window)(struct netxen_adapter *,
1222 unsigned long long);
1223
1224 struct netxen_legacy_intr_set legacy_intr;
1225
1226 struct msix_entry msix_entries[MSIX_ENTRIES_PER_ADAPTER];
1227
1228 struct netxen_dummy_dma dummy_dma;
1229
1230 struct work_struct watchdog_task;
1231 struct timer_list watchdog_timer;
1232 struct work_struct tx_timeout_task;
1233
1234 struct net_device_stats net_stats;
1235
1236 nx_nic_intr_coalesce_t coal;
1237 };
1238
1239 /*
1240 * NetXen dma watchdog control structure
1241 *
1242 * Bit 0 : enabled => R/O: 1 watchdog active, 0 inactive
1243 * Bit 1 : disable_request => 1 req disable dma watchdog
1244 * Bit 2 : enable_request => 1 req enable dma watchdog
1245 * Bit 3-31 : unused
1246 */
1247
1248 #define netxen_set_dma_watchdog_disable_req(config_word) \
1249 _netxen_set_bits(config_word, 1, 1, 1)
1250 #define netxen_set_dma_watchdog_enable_req(config_word) \
1251 _netxen_set_bits(config_word, 2, 1, 1)
1252 #define netxen_get_dma_watchdog_enabled(config_word) \
1253 ((config_word) & 0x1)
1254 #define netxen_get_dma_watchdog_disabled(config_word) \
1255 (((config_word) >> 1) & 0x1)
1256
1257 /* Max number of xmit producer threads that can run simultaneously */
1258 #define MAX_XMIT_PRODUCERS 16
1259
1260 #define PCI_OFFSET_FIRST_RANGE(adapter, off) \
1261 ((adapter)->ahw.pci_base0 + (off))
1262 #define PCI_OFFSET_SECOND_RANGE(adapter, off) \
1263 ((adapter)->ahw.pci_base1 + (off) - SECOND_PAGE_GROUP_START)
1264 #define PCI_OFFSET_THIRD_RANGE(adapter, off) \
1265 ((adapter)->ahw.pci_base2 + (off) - THIRD_PAGE_GROUP_START)
1266
1267 static inline void __iomem *pci_base_offset(struct netxen_adapter *adapter,
1268 unsigned long off)
1269 {
1270 if ((off < FIRST_PAGE_GROUP_END) && (off >= FIRST_PAGE_GROUP_START)) {
1271 return (adapter->ahw.pci_base0 + off);
1272 } else if ((off < SECOND_PAGE_GROUP_END) &&
1273 (off >= SECOND_PAGE_GROUP_START)) {
1274 return (adapter->ahw.pci_base1 + off - SECOND_PAGE_GROUP_START);
1275 } else if ((off < THIRD_PAGE_GROUP_END) &&
1276 (off >= THIRD_PAGE_GROUP_START)) {
1277 return (adapter->ahw.pci_base2 + off - THIRD_PAGE_GROUP_START);
1278 }
1279 return NULL;
1280 }
1281
1282 static inline void __iomem *pci_base(struct netxen_adapter *adapter,
1283 unsigned long off)
1284 {
1285 if ((off < FIRST_PAGE_GROUP_END) && (off >= FIRST_PAGE_GROUP_START)) {
1286 return adapter->ahw.pci_base0;
1287 } else if ((off < SECOND_PAGE_GROUP_END) &&
1288 (off >= SECOND_PAGE_GROUP_START)) {
1289 return adapter->ahw.pci_base1;
1290 } else if ((off < THIRD_PAGE_GROUP_END) &&
1291 (off >= THIRD_PAGE_GROUP_START)) {
1292 return adapter->ahw.pci_base2;
1293 }
1294 return NULL;
1295 }
1296
1297 int netxen_niu_xgbe_enable_phy_interrupts(struct netxen_adapter *adapter);
1298 int netxen_niu_gbe_enable_phy_interrupts(struct netxen_adapter *adapter);
1299 int netxen_niu_xgbe_disable_phy_interrupts(struct netxen_adapter *adapter);
1300 int netxen_niu_gbe_disable_phy_interrupts(struct netxen_adapter *adapter);
1301 int netxen_niu_gbe_phy_read(struct netxen_adapter *adapter, long reg,
1302 __u32 * readval);
1303 int netxen_niu_gbe_phy_write(struct netxen_adapter *adapter,
1304 long reg, __u32 val);
1305
1306 /* Functions available from netxen_nic_hw.c */
1307 int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu);
1308 int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu);
1309 void netxen_nic_reg_write(struct netxen_adapter *adapter, u64 off, u32 val);
1310 int netxen_nic_reg_read(struct netxen_adapter *adapter, u64 off);
1311 void netxen_nic_write_w0(struct netxen_adapter *adapter, u32 index, u32 value);
1312 void netxen_nic_read_w0(struct netxen_adapter *adapter, u32 index, u32 *value);
1313 void netxen_nic_write_w1(struct netxen_adapter *adapter, u32 index, u32 value);
1314 void netxen_nic_read_w1(struct netxen_adapter *adapter, u32 index, u32 *value);
1315
1316 int netxen_nic_get_board_info(struct netxen_adapter *adapter);
1317 void netxen_nic_get_firmware_info(struct netxen_adapter *adapter);
1318 int netxen_nic_wol_supported(struct netxen_adapter *adapter);
1319
1320 int netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter,
1321 ulong off, void *data, int len);
1322 int netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter,
1323 ulong off, void *data, int len);
1324 int netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter,
1325 u64 off, void *data, int size);
1326 int netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter,
1327 u64 off, void *data, int size);
1328 int netxen_nic_pci_write_immediate_128M(struct netxen_adapter *adapter,
1329 u64 off, u32 data);
1330 u32 netxen_nic_pci_read_immediate_128M(struct netxen_adapter *adapter, u64 off);
1331 void netxen_nic_pci_write_normalize_128M(struct netxen_adapter *adapter,
1332 u64 off, u32 data);
1333 u32 netxen_nic_pci_read_normalize_128M(struct netxen_adapter *adapter, u64 off);
1334 unsigned long netxen_nic_pci_set_window_128M(struct netxen_adapter *adapter,
1335 unsigned long long addr);
1336 void netxen_nic_pci_change_crbwindow_128M(struct netxen_adapter *adapter,
1337 u32 wndw);
1338
1339 int netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter,
1340 ulong off, void *data, int len);
1341 int netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter,
1342 ulong off, void *data, int len);
1343 int netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
1344 u64 off, void *data, int size);
1345 int netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter,
1346 u64 off, void *data, int size);
1347 void netxen_crb_writelit_adapter(struct netxen_adapter *adapter,
1348 unsigned long off, int data);
1349 int netxen_nic_pci_write_immediate_2M(struct netxen_adapter *adapter,
1350 u64 off, u32 data);
1351 u32 netxen_nic_pci_read_immediate_2M(struct netxen_adapter *adapter, u64 off);
1352 void netxen_nic_pci_write_normalize_2M(struct netxen_adapter *adapter,
1353 u64 off, u32 data);
1354 u32 netxen_nic_pci_read_normalize_2M(struct netxen_adapter *adapter, u64 off);
1355 unsigned long netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
1356 unsigned long long addr);
1357
1358 /* Functions from netxen_nic_init.c */
1359 void netxen_free_adapter_offload(struct netxen_adapter *adapter);
1360 int netxen_initialize_adapter_offload(struct netxen_adapter *adapter);
1361 int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val);
1362 int netxen_load_firmware(struct netxen_adapter *adapter);
1363 int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose);
1364
1365 int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp);
1366 int netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
1367 u8 *bytes, size_t size);
1368 int netxen_rom_fast_write_words(struct netxen_adapter *adapter, int addr,
1369 u8 *bytes, size_t size);
1370 int netxen_flash_unlock(struct netxen_adapter *adapter);
1371 int netxen_backup_crbinit(struct netxen_adapter *adapter);
1372 int netxen_flash_erase_secondary(struct netxen_adapter *adapter);
1373 int netxen_flash_erase_primary(struct netxen_adapter *adapter);
1374 void netxen_halt_pegs(struct netxen_adapter *adapter);
1375
1376 int netxen_rom_se(struct netxen_adapter *adapter, int addr);
1377
1378 int netxen_alloc_sw_resources(struct netxen_adapter *adapter);
1379 void netxen_free_sw_resources(struct netxen_adapter *adapter);
1380
1381 int netxen_alloc_hw_resources(struct netxen_adapter *adapter);
1382 void netxen_free_hw_resources(struct netxen_adapter *adapter);
1383
1384 void netxen_release_rx_buffers(struct netxen_adapter *adapter);
1385 void netxen_release_tx_buffers(struct netxen_adapter *adapter);
1386
1387 void netxen_initialize_adapter_ops(struct netxen_adapter *adapter);
1388 int netxen_init_firmware(struct netxen_adapter *adapter);
1389 void netxen_nic_clear_stats(struct netxen_adapter *adapter);
1390 void netxen_watchdog_task(struct work_struct *work);
1391 void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ringid,
1392 struct nx_host_rds_ring *rds_ring);
1393 int netxen_process_cmd_ring(struct netxen_adapter *adapter);
1394 int netxen_process_rcv_ring(struct nx_host_sds_ring *sds_ring, int max);
1395 void netxen_p2_nic_set_multi(struct net_device *netdev);
1396 void netxen_p3_nic_set_multi(struct net_device *netdev);
1397 void netxen_p3_free_mac_list(struct netxen_adapter *adapter);
1398 int netxen_p3_nic_set_promisc(struct netxen_adapter *adapter, u32);
1399 int netxen_config_intr_coalesce(struct netxen_adapter *adapter);
1400 int netxen_config_rss(struct netxen_adapter *adapter, int enable);
1401
1402 int nx_fw_cmd_set_mtu(struct netxen_adapter *adapter, int mtu);
1403 int netxen_nic_change_mtu(struct net_device *netdev, int new_mtu);
1404
1405 int netxen_nic_set_mac(struct net_device *netdev, void *p);
1406 struct net_device_stats *netxen_nic_get_stats(struct net_device *netdev);
1407
1408 void netxen_nic_update_cmd_producer(struct netxen_adapter *adapter,
1409 struct nx_host_tx_ring *tx_ring, uint32_t crb_producer);
1410
1411 /*
1412 * NetXen Board information
1413 */
1414
1415 #define NETXEN_MAX_SHORT_NAME 32
1416 struct netxen_brdinfo {
1417 int brdtype; /* type of board */
1418 long ports; /* max no of physical ports */
1419 char short_name[NETXEN_MAX_SHORT_NAME];
1420 };
1421
1422 static const struct netxen_brdinfo netxen_boards[] = {
1423 {NETXEN_BRDTYPE_P2_SB31_10G_CX4, 1, "XGb CX4"},
1424 {NETXEN_BRDTYPE_P2_SB31_10G_HMEZ, 1, "XGb HMEZ"},
1425 {NETXEN_BRDTYPE_P2_SB31_10G_IMEZ, 2, "XGb IMEZ"},
1426 {NETXEN_BRDTYPE_P2_SB31_10G, 1, "XGb XFP"},
1427 {NETXEN_BRDTYPE_P2_SB35_4G, 4, "Quad Gb"},
1428 {NETXEN_BRDTYPE_P2_SB31_2G, 2, "Dual Gb"},
1429 {NETXEN_BRDTYPE_P3_REF_QG, 4, "Reference Quad Gig "},
1430 {NETXEN_BRDTYPE_P3_HMEZ, 2, "Dual XGb HMEZ"},
1431 {NETXEN_BRDTYPE_P3_10G_CX4_LP, 2, "Dual XGb CX4 LP"},
1432 {NETXEN_BRDTYPE_P3_4_GB, 4, "Quad Gig LP"},
1433 {NETXEN_BRDTYPE_P3_IMEZ, 2, "Dual XGb IMEZ"},
1434 {NETXEN_BRDTYPE_P3_10G_SFP_PLUS, 2, "Dual XGb SFP+ LP"},
1435 {NETXEN_BRDTYPE_P3_10000_BASE_T, 1, "XGB 10G BaseT LP"},
1436 {NETXEN_BRDTYPE_P3_XG_LOM, 2, "Dual XGb LOM"},
1437 {NETXEN_BRDTYPE_P3_4_GB_MM, 4, "NX3031 Gigabit Ethernet"},
1438 {NETXEN_BRDTYPE_P3_10G_SFP_CT, 2, "NX3031 10 Gigabit Ethernet"},
1439 {NETXEN_BRDTYPE_P3_10G_SFP_QT, 2, "Quanta Dual XGb SFP+"},
1440 {NETXEN_BRDTYPE_P3_10G_CX4, 2, "Reference Dual CX4 Option"},
1441 {NETXEN_BRDTYPE_P3_10G_XFP, 1, "Reference Single XFP Option"}
1442 };
1443
1444 #define NUM_SUPPORTED_BOARDS ARRAY_SIZE(netxen_boards)
1445
1446 static inline void get_brd_name_by_type(u32 type, char *name)
1447 {
1448 int i, found = 0;
1449 for (i = 0; i < NUM_SUPPORTED_BOARDS; ++i) {
1450 if (netxen_boards[i].brdtype == type) {
1451 strcpy(name, netxen_boards[i].short_name);
1452 found = 1;
1453 break;
1454 }
1455
1456 }
1457 if (!found)
1458 name = "Unknown";
1459 }
1460
1461 static inline int
1462 dma_watchdog_shutdown_request(struct netxen_adapter *adapter)
1463 {
1464 u32 ctrl;
1465
1466 /* check if already inactive */
1467 if (adapter->hw_read_wx(adapter,
1468 NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), &ctrl, 4))
1469 printk(KERN_ERR "failed to read dma watchdog status\n");
1470
1471 if (netxen_get_dma_watchdog_enabled(ctrl) == 0)
1472 return 1;
1473
1474 /* Send the disable request */
1475 netxen_set_dma_watchdog_disable_req(ctrl);
1476 netxen_crb_writelit_adapter(adapter,
1477 NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), ctrl);
1478
1479 return 0;
1480 }
1481
1482 static inline int
1483 dma_watchdog_shutdown_poll_result(struct netxen_adapter *adapter)
1484 {
1485 u32 ctrl;
1486
1487 if (adapter->hw_read_wx(adapter,
1488 NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), &ctrl, 4))
1489 printk(KERN_ERR "failed to read dma watchdog status\n");
1490
1491 return (netxen_get_dma_watchdog_enabled(ctrl) == 0);
1492 }
1493
1494 static inline int
1495 dma_watchdog_wakeup(struct netxen_adapter *adapter)
1496 {
1497 u32 ctrl;
1498
1499 if (adapter->hw_read_wx(adapter,
1500 NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), &ctrl, 4))
1501 printk(KERN_ERR "failed to read dma watchdog status\n");
1502
1503 if (netxen_get_dma_watchdog_enabled(ctrl))
1504 return 1;
1505
1506 /* send the wakeup request */
1507 netxen_set_dma_watchdog_enable_req(ctrl);
1508
1509 netxen_crb_writelit_adapter(adapter,
1510 NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), ctrl);
1511
1512 return 0;
1513 }
1514
1515
1516 int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 *mac);
1517 int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, __le64 *mac);
1518 extern void netxen_change_ringparam(struct netxen_adapter *adapter);
1519 extern int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr,
1520 int *valp);
1521
1522 extern struct ethtool_ops netxen_nic_ethtool_ops;
1523
1524 #endif /* __NETXEN_NIC_H_ */
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