arch/mips/alchemy/common/power.c

   1 /*
   2  * BRIEF MODULE DESCRIPTION
   3  *      Au1xx0 Power Management routines.
   4  *
   5  * Copyright 2001, 2008 MontaVista Software Inc.
   6  * Author: MontaVista Software, Inc. <source@mvista.com>
   7  *
   8  *  Some of the routines are right out of init/main.c, whose
   9  *  copyrights apply here.
  10  *
  11  *  This program is free software; you can redistribute  it and/or modify it
  12  *  under  the terms of  the GNU General  Public License as published by the
  13  *  Free Software Foundation;  either version 2 of the  License, or (at your
  14  *  option) any later version.
  15  *
  16  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  17  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  18  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  19  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  20  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  21  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  22  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  23  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  24  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  25  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26  *
  27  *  You should have received a copy of the  GNU General Public License along
  28  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  29  *  675 Mass Ave, Cambridge, MA 02139, USA.
  30  */
  31
  32 #include <linux/init.h>
  33 #include <linux/pm.h>
  34 #include <linux/sysctl.h>
  35 #include <linux/jiffies.h>
  36
  37 #include <asm/uaccess.h>
  38 #include <asm/mach-au1x00/au1000.h>
  39
  40 #ifdef CONFIG_PM
  41
  42 #define DEBUG 1
  43 #ifdef  DEBUG
  44 #define DPRINTK(fmt, args...)   printk(KERN_DEBUG "%s: " fmt, __func__, ## args)
  45 #else
  46 #define DPRINTK(fmt, args...)
  47 #endif
  48
  49 extern unsigned long save_local_and_disable(int controller);
  50 extern void restore_local_and_enable(int controller, unsigned long mask);
  51
  52 static DEFINE_SPINLOCK(pm_lock);
  53
  54 /*
  55  * We need to save/restore a bunch of core registers that are
  56  * either volatile or reset to some state across a processor sleep.
  57  * If reading a register doesn't provide a proper result for a
  58  * later restore, we have to provide a function for loading that
  59  * register and save a copy.
  60  *
  61  * We only have to save/restore registers that aren't otherwise
  62  * done as part of a driver pm_* function.
  63  */
  64 static unsigned int sleep_uart0_inten;
  65 static unsigned int sleep_uart0_fifoctl;
  66 static unsigned int sleep_uart0_linectl;
  67 static unsigned int sleep_uart0_clkdiv;
  68 static unsigned int sleep_uart0_enable;
  69 static unsigned int sleep_usb[2];
  70 static unsigned int sleep_sys_clocks[5];
  71 static unsigned int sleep_sys_pinfunc;
  72 static unsigned int sleep_static_memctlr[4][3];
  73
  74 /*
  75  * Define this to cause the value you write to /proc/sys/pm/sleep to
  76  * set the TOY timer for the amount of time you want to sleep.
  77  * This is done mainly for testing, but may be useful in other cases.
  78  * The value is number of 32KHz ticks to sleep.
  79  */
  80 #define SLEEP_TEST_TIMEOUT 1
  81 #ifdef  SLEEP_TEST_TIMEOUT
  82 static int sleep_ticks;
  83 static void wakeup_counter0_set(int ticks)
  84 {
  85         au_writel(au_readl(SYS_TOYREAD) + ticks, SYS_TOYMATCH2);
  86         au_sync();
  87 }
  88 #endif
  89
  90 static void save_core_regs(void)
  91 {
  92         extern void save_au1xxx_intctl(void);
  93         extern void pm_eth0_shutdown(void);
  94
  95         /*
  96          * Do the serial ports.....these really should be a pm_*
  97          * registered function by the driver......but of course the
  98          * standard serial driver doesn't understand our Au1xxx
  99          * unique registers.
 100          */
 101         sleep_uart0_inten = au_readl(UART0_ADDR + UART_IER);
 102         sleep_uart0_fifoctl = au_readl(UART0_ADDR + UART_FCR);
 103         sleep_uart0_linectl = au_readl(UART0_ADDR + UART_LCR);
 104         sleep_uart0_clkdiv = au_readl(UART0_ADDR + UART_CLK);
 105         sleep_uart0_enable = au_readl(UART0_ADDR + UART_MOD_CNTRL);
 106         au_sync();
 107
 108 #ifndef CONFIG_SOC_AU1200
 109         /* Shutdown USB host/device. */
 110         sleep_usb[0] = au_readl(USB_HOST_CONFIG);
 111
 112         /* There appears to be some undocumented reset register.... */
 113         au_writel(0, 0xb0100004);
 114         au_sync();
 115         au_writel(0, USB_HOST_CONFIG);
 116         au_sync();
 117
 118         sleep_usb[1] = au_readl(USBD_ENABLE);
 119         au_writel(0, USBD_ENABLE);
 120         au_sync();
 121
 122 #else   /* AU1200 */
 123
 124         /* enable access to OTG mmio so we can save OTG CAP/MUX.
 125          * FIXME: write an OTG driver and move this stuff there!
 126          */
 127         au_writel(au_readl(USB_MSR_BASE + 4) | (1 << 6), USB_MSR_BASE + 4);
 128         au_sync();
 129         sleep_usb[0] = au_readl(0xb4020020);    /* OTG_CAP */
 130         sleep_usb[1] = au_readl(0xb4020024);    /* OTG_MUX */
 131 #endif
 132
 133         /* Save interrupt controller state. */
 134         save_au1xxx_intctl();
 135
 136         /* Clocks and PLLs. */
 137         sleep_sys_clocks[0] = au_readl(SYS_FREQCTRL0);
 138         sleep_sys_clocks[1] = au_readl(SYS_FREQCTRL1);
 139         sleep_sys_clocks[2] = au_readl(SYS_CLKSRC);
 140         sleep_sys_clocks[3] = au_readl(SYS_CPUPLL);
 141         sleep_sys_clocks[4] = au_readl(SYS_AUXPLL);
 142
 143         /* pin mux config */
 144         sleep_sys_pinfunc = au_readl(SYS_PINFUNC);
 145
 146         /* Save the static memory controller configuration. */
 147         sleep_static_memctlr[0][0] = au_readl(MEM_STCFG0);
 148         sleep_static_memctlr[0][1] = au_readl(MEM_STTIME0);
 149         sleep_static_memctlr[0][2] = au_readl(MEM_STADDR0);
 150         sleep_static_memctlr[1][0] = au_readl(MEM_STCFG1);
 151         sleep_static_memctlr[1][1] = au_readl(MEM_STTIME1);
 152         sleep_static_memctlr[1][2] = au_readl(MEM_STADDR1);
 153         sleep_static_memctlr[2][0] = au_readl(MEM_STCFG2);
 154         sleep_static_memctlr[2][1] = au_readl(MEM_STTIME2);
 155         sleep_static_memctlr[2][2] = au_readl(MEM_STADDR2);
 156         sleep_static_memctlr[3][0] = au_readl(MEM_STCFG3);
 157         sleep_static_memctlr[3][1] = au_readl(MEM_STTIME3);
 158         sleep_static_memctlr[3][2] = au_readl(MEM_STADDR3);
 159 }
 160
 161 static void restore_core_regs(void)
 162 {
 163         /* restore clock configuration.  Writing CPUPLL last will
 164          * stall a bit and stabilize other clocks (unless this is
 165          * one of those Au1000 with a write-only PLL, where we dont
 166          * have a valid value)
 167          */
 168         au_writel(sleep_sys_clocks[0], SYS_FREQCTRL0);
 169         au_writel(sleep_sys_clocks[1], SYS_FREQCTRL1);
 170         au_writel(sleep_sys_clocks[2], SYS_CLKSRC);
 171         au_writel(sleep_sys_clocks[4], SYS_AUXPLL);
 172         if (!au1xxx_cpu_has_pll_wo())
 173                 au_writel(sleep_sys_clocks[3], SYS_CPUPLL);
 174         au_sync();
 175
 176         au_writel(sleep_sys_pinfunc, SYS_PINFUNC);
 177         au_sync();
 178
 179 #ifndef CONFIG_SOC_AU1200
 180         au_writel(sleep_usb[0], USB_HOST_CONFIG);
 181         au_writel(sleep_usb[1], USBD_ENABLE);
 182         au_sync();
 183 #else
 184         /* enable accces to OTG memory */
 185         au_writel(au_readl(USB_MSR_BASE + 4) | (1 << 6), USB_MSR_BASE + 4);
 186         au_sync();
 187
 188         /* restore OTG caps and port mux. */
 189         au_writel(sleep_usb[0], 0xb4020020 + 0);        /* OTG_CAP */
 190         au_sync();
 191         au_writel(sleep_usb[1], 0xb4020020 + 4);        /* OTG_MUX */
 192         au_sync();
 193 #endif
 194
 195         /* Restore the static memory controller configuration. */
 196         au_writel(sleep_static_memctlr[0][0], MEM_STCFG0);
 197         au_writel(sleep_static_memctlr[0][1], MEM_STTIME0);
 198         au_writel(sleep_static_memctlr[0][2], MEM_STADDR0);
 199         au_writel(sleep_static_memctlr[1][0], MEM_STCFG1);
 200         au_writel(sleep_static_memctlr[1][1], MEM_STTIME1);
 201         au_writel(sleep_static_memctlr[1][2], MEM_STADDR1);
 202         au_writel(sleep_static_memctlr[2][0], MEM_STCFG2);
 203         au_writel(sleep_static_memctlr[2][1], MEM_STTIME2);
 204         au_writel(sleep_static_memctlr[2][2], MEM_STADDR2);
 205         au_writel(sleep_static_memctlr[3][0], MEM_STCFG3);
 206         au_writel(sleep_static_memctlr[3][1], MEM_STTIME3);
 207         au_writel(sleep_static_memctlr[3][2], MEM_STADDR3);
 208
 209         /*
 210          * Enable the UART if it was enabled before sleep.
 211          * I guess I should define module control bits........
 212          */
 213         if (sleep_uart0_enable & 0x02) {
 214                 au_writel(0, UART0_ADDR + UART_MOD_CNTRL); au_sync();
 215                 au_writel(1, UART0_ADDR + UART_MOD_CNTRL); au_sync();
 216                 au_writel(3, UART0_ADDR + UART_MOD_CNTRL); au_sync();
 217                 au_writel(sleep_uart0_inten, UART0_ADDR + UART_IER); au_sync();
 218                 au_writel(sleep_uart0_fifoctl, UART0_ADDR + UART_FCR); au_sync();
 219                 au_writel(sleep_uart0_linectl, UART0_ADDR + UART_LCR); au_sync();
 220                 au_writel(sleep_uart0_clkdiv, UART0_ADDR + UART_CLK); au_sync();
 221         }
 222
 223         restore_au1xxx_intctl();
 224 }
 225
 226 unsigned long suspend_mode;
 227
 228 void wakeup_from_suspend(void)
 229 {
 230         suspend_mode = 0;
 231 }
 232
 233 void au_sleep(void)
 234 {
 235         save_core_regs();
 236         au1xxx_save_and_sleep();
 237         restore_core_regs();
 238 }
 239
 240 static int pm_do_sleep(ctl_table *ctl, int write, struct file *file,
 241                        void __user *buffer, size_t *len, loff_t *ppos)
 242 {
 243         unsigned long wakeup, flags;
 244         int ret;
 245 #ifdef SLEEP_TEST_TIMEOUT
 246 #define TMPBUFLEN2 16
 247         char buf[TMPBUFLEN2], *p;
 248 #endif
 249
 250         spin_lock_irqsave(&pm_lock, flags);
 251
 252         if (!write) {
 253                 *len = 0;
 254                 ret = 0;
 255                 goto out_unlock;
 256         };
 257
 258 #ifdef SLEEP_TEST_TIMEOUT
 259         if (*len > TMPBUFLEN2 - 1) {
 260                 ret = -EFAULT;
 261                 goto out_unlock;
 262         }
 263         if (copy_from_user(buf, buffer, *len)) {
 264                 return -EFAULT;
 265                 goto out_unlock;
 266         }
 267         buf[*len] = 0;
 268         p = buf;
 269         sleep_ticks = simple_strtoul(p, &p, 0);
 270         wakeup_counter0_set(sleep_ticks);
 271 #endif
 272
 273         /**
 274          ** The code below is all system dependent and we should probably
 275          ** have a function call out of here to set this up.  You need
 276          ** to configure the GPIO or timer interrupts that will bring
 277          ** you out of sleep.
 278          ** For testing, the TOY counter wakeup is useful.
 279          **/
 280 #if 0
 281         au_writel(au_readl(SYS_PINSTATERD) & ~(1 << 11), SYS_PINSTATERD);
 282
 283         /* GPIO 6 can cause a wake up event */
 284         wakeup = au_readl(SYS_WAKEMSK);
 285         wakeup &= ~(1 << 8);    /* turn off match20 wakeup */
 286         wakeup |= 1 << 6;       /* turn on  GPIO  6 wakeup */
 287 #else
 288         /* For testing, allow match20 to wake us up. */
 289         wakeup = 1 << 8;        /* turn on match20 wakeup   */
 290         wakeup = 0;
 291 #endif
 292         au_writel(1, SYS_WAKESRC);      /* clear cause */
 293         au_sync();
 294         au_writel(wakeup, SYS_WAKEMSK);
 295         au_sync();
 296
 297         au_sleep();
 298         ret = 0;
 299
 300 out_unlock:
 301         spin_unlock_irqrestore(&pm_lock, flags);
 302         return ret;
 303 }
 304
 305 #if !defined(CONFIG_SOC_AU1200) && !defined(CONFIG_SOC_AU1550)
 306
 307 /*
 308  * This is right out of init/main.c
 309  */
 310
 311 /*
 312  * This is the number of bits of precision for the loops_per_jiffy.
 313  * Each bit takes on average 1.5/HZ seconds.  This (like the original)
 314  * is a little better than 1%.
 315  */
 316 #define LPS_PREC 8
 317
 318 static void au1000_calibrate_delay(void)
 319 {
 320         unsigned long ticks, loopbit;
 321         int lps_precision = LPS_PREC;
 322
 323         loops_per_jiffy = 1 << 12;
 324
 325         while (loops_per_jiffy <<= 1) {
 326                 /* Wait for "start of" clock tick */
 327                 ticks = jiffies;
 328                 while (ticks == jiffies)
 329                         /* nothing */ ;
 330                 /* Go ... */
 331                 ticks = jiffies;
 332                 __delay(loops_per_jiffy);
 333                 ticks = jiffies - ticks;
 334                 if (ticks)
 335                         break;
 336         }
 337
 338         /*
 339          * Do a binary approximation to get loops_per_jiffy set to be equal
 340          * one clock (up to lps_precision bits)
 341          */
 342         loops_per_jiffy >>= 1;
 343         loopbit = loops_per_jiffy;
 344         while (lps_precision-- && (loopbit >>= 1)) {
 345                 loops_per_jiffy |= loopbit;
 346                 ticks = jiffies;
 347                 while (ticks == jiffies);
 348                 ticks = jiffies;
 349                 __delay(loops_per_jiffy);
 350                 if (jiffies != ticks)   /* longer than 1 tick */
 351                         loops_per_jiffy &= ~loopbit;
 352         }
 353 }
 354
 355 static int pm_do_freq(ctl_table *ctl, int write, struct file *file,
 356                       void __user *buffer, size_t *len, loff_t *ppos)
 357 {
 358         int retval = 0, i;
 359         unsigned long val, pll;
 360 #define TMPBUFLEN 64
 361 #define MAX_CPU_FREQ 396
 362         char buf[TMPBUFLEN], *p;
 363         unsigned long flags, intc0_mask, intc1_mask;
 364         unsigned long old_baud_base, old_cpu_freq, old_clk, old_refresh;
 365         unsigned long new_baud_base, new_cpu_freq, new_clk, new_refresh;
 366         unsigned long baud_rate;
 367
 368         spin_lock_irqsave(&pm_lock, flags);
 369         if (!write)
 370                 *len = 0;
 371         else {
 372                 /* Parse the new frequency */
 373                 if (*len > TMPBUFLEN - 1) {
 374                         spin_unlock_irqrestore(&pm_lock, flags);
 375                         return -EFAULT;
 376                 }
 377                 if (copy_from_user(buf, buffer, *len)) {
 378                         spin_unlock_irqrestore(&pm_lock, flags);
 379                         return -EFAULT;
 380                 }
 381                 buf[*len] = 0;
 382                 p = buf;
 383                 val = simple_strtoul(p, &p, 0);
 384                 if (val > MAX_CPU_FREQ) {
 385                         spin_unlock_irqrestore(&pm_lock, flags);
 386                         return -EFAULT;
 387                 }
 388
 389                 pll = val / 12;
 390                 if ((pll > 33) || (pll < 7)) {  /* 396 MHz max, 84 MHz min */
 391                         /* Revisit this for higher speed CPUs */
 392                         spin_unlock_irqrestore(&pm_lock, flags);
 393                         return -EFAULT;
 394                 }
 395
 396                 old_baud_base = get_au1x00_uart_baud_base();
 397                 old_cpu_freq = get_au1x00_speed();
 398
 399                 new_cpu_freq = pll * 12 * 1000000;
 400                 new_baud_base = (new_cpu_freq / (2 * ((int)(au_readl(SYS_POWERCTRL)
 401                                                             & 0x03) + 2) * 16));
 402                 set_au1x00_speed(new_cpu_freq);
 403                 set_au1x00_uart_baud_base(new_baud_base);
 404
 405                 old_refresh = au_readl(MEM_SDREFCFG) & 0x1ffffff;
 406                 new_refresh = ((old_refresh * new_cpu_freq) / old_cpu_freq) |
 407                               (au_readl(MEM_SDREFCFG) & ~0x1ffffff);
 408
 409                 au_writel(pll, SYS_CPUPLL);
 410                 au_sync_delay(1);
 411                 au_writel(new_refresh, MEM_SDREFCFG);
 412                 au_sync_delay(1);
 413
 414                 for (i = 0; i < 4; i++)
 415                         if (au_readl(UART_BASE + UART_MOD_CNTRL +
 416                                      i * 0x00100000) == 3) {
 417                                 old_clk = au_readl(UART_BASE + UART_CLK +
 418                                                    i * 0x00100000);
 419                                 baud_rate = old_baud_base / old_clk;
 420                                 /*
 421                                  * We won't get an exact baud rate and the error
 422                                  * could be significant enough that our new
 423                                  * calculation will result in a clock that will
 424                                  * give us a baud rate that's too far off from
 425                                  * what we really want.
 426                                  */
 427                                 if (baud_rate > 100000)
 428                                         baud_rate = 115200;
 429                                 else if (baud_rate > 50000)
 430                                         baud_rate = 57600;
 431                                 else if (baud_rate > 30000)
 432                                         baud_rate = 38400;
 433                                 else if (baud_rate > 17000)
 434                                         baud_rate = 19200;
 435                                 else
 436                                         baud_rate = 9600;
 437                                 new_clk = new_baud_base / baud_rate;
 438                                 au_writel(new_clk, UART_BASE + UART_CLK +
 439                                           i * 0x00100000);
 440                                 au_sync_delay(10);
 441                         }
 442         }
 443
 444         /*
 445          * We don't want _any_ interrupts other than match20. Otherwise our
 446          * au1000_calibrate_delay() calculation will be off, potentially a lot.
 447          */
 448         intc0_mask = save_local_and_disable(0);
 449         intc1_mask = save_local_and_disable(1);
 450         val = 1 << (AU1000_TOY_MATCH2_INT - AU1000_INTC0_INT_BASE);
 451         au_writel(val, IC0_MASKSET);    /* unmask */
 452         au_writel(val, IC0_WAKESET);    /* enable wake-from-sleep */
 453         au_sync();
 454         spin_unlock_irqrestore(&pm_lock, flags);
 455         au1000_calibrate_delay();
 456         restore_local_and_enable(0, intc0_mask);
 457         restore_local_and_enable(1, intc1_mask);
 458
 459         return retval;
 460 }
 461 #endif
 462
 463 static struct ctl_table pm_table[] = {
 464         {
 465                 .ctl_name       = CTL_UNNUMBERED,
 466                 .procname       = "sleep",
 467                 .data           = NULL,
 468                 .maxlen         = 0,
 469                 .mode           = 0600,
 470                 .proc_handler   = &pm_do_sleep
 471         },
 472 #if !defined(CONFIG_SOC_AU1200) && !defined(CONFIG_SOC_AU1550)
 473         {
 474                 .ctl_name       = CTL_UNNUMBERED,
 475                 .procname       = "freq",
 476                 .data           = NULL,
 477                 .maxlen         = 0,
 478                 .mode           = 0600,
 479                 .proc_handler   = &pm_do_freq
 480         },
 481 #endif
 482         {}
 483 };
 484
 485 static struct ctl_table pm_dir_table[] = {
 486         {
 487                 .ctl_name       = CTL_UNNUMBERED,
 488                 .procname       = "pm",
 489                 .mode           = 0555,
 490                 .child          = pm_table
 491         },
 492         {}
 493 };
 494
 495 /*
 496  * Initialize power interface
 497  */
 498 static int __init pm_init(void)
 499 {
 500         /* init TOY to tick at 1Hz. No need to wait for access bits
 501          * since there's plenty of time between here and the first
 502          * suspend cycle.
 503          */
 504         if (au_readl(SYS_TOYTRIM) != 32767) {
 505                 au_writel(32767, SYS_TOYTRIM);
 506                 au_sync();
 507         }
 508
 509         register_sysctl_table(pm_dir_table);
 510         return 0;
 511 }
 512
 513 __initcall(pm_init);
 514
 515 #endif  /* CONFIG_PM */