2 * Sonics Silicon Backplane
5 * Copyright 2005, Broadcom Corporation
6 * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
8 * Licensed under the GNU/GPL. See COPYING for details.
11 #include "ssb_private.h"
13 #include <linux/delay.h>
15 #include <linux/ssb/ssb.h>
16 #include <linux/ssb/ssb_regs.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/pci.h>
20 #include <pcmcia/cs_types.h>
21 #include <pcmcia/cs.h>
22 #include <pcmcia/cistpl.h>
23 #include <pcmcia/ds.h>
26 MODULE_DESCRIPTION("Sonics Silicon Backplane driver");
27 MODULE_LICENSE("GPL");
30 /* Temporary list of yet-to-be-attached buses */
31 static LIST_HEAD(attach_queue
);
32 /* List if running buses */
33 static LIST_HEAD(buses
);
34 /* Software ID counter */
35 static unsigned int next_busnumber
;
36 /* buses_mutes locks the two buslists and the next_busnumber.
37 * Don't lock this directly, but use ssb_buses_[un]lock() below. */
38 static DEFINE_MUTEX(buses_mutex
);
40 /* There are differences in the codeflow, if the bus is
41 * initialized from early boot, as various needed services
42 * are not available early. This is a mechanism to delay
43 * these initializations to after early boot has finished.
44 * It's also used to avoid mutex locking, as that's not
45 * available and needed early. */
46 static bool ssb_is_early_boot
= 1;
48 static void ssb_buses_lock(void);
49 static void ssb_buses_unlock(void);
52 #ifdef CONFIG_SSB_PCIHOST
53 struct ssb_bus
*ssb_pci_dev_to_bus(struct pci_dev
*pdev
)
58 list_for_each_entry(bus
, &buses
, list
) {
59 if (bus
->bustype
== SSB_BUSTYPE_PCI
&&
60 bus
->host_pci
== pdev
)
69 #endif /* CONFIG_SSB_PCIHOST */
71 static struct ssb_device
*ssb_device_get(struct ssb_device
*dev
)
78 static void ssb_device_put(struct ssb_device
*dev
)
84 static int ssb_bus_resume(struct ssb_bus
*bus
)
88 ssb_pci_xtal(bus
, SSB_GPIO_XTAL
| SSB_GPIO_PLL
, 1);
89 err
= ssb_pcmcia_init(bus
);
91 /* No need to disable XTAL, as we don't have one on PCMCIA. */
94 ssb_chipco_resume(&bus
->chipco
);
99 static int ssb_device_resume(struct device
*dev
)
101 struct ssb_device
*ssb_dev
= dev_to_ssb_dev(dev
);
102 struct ssb_driver
*ssb_drv
;
107 if (bus
->suspend_cnt
== bus
->nr_devices
) {
108 err
= ssb_bus_resume(bus
);
114 ssb_drv
= drv_to_ssb_drv(dev
->driver
);
115 if (ssb_drv
&& ssb_drv
->resume
)
116 err
= ssb_drv
->resume(ssb_dev
);
124 static void ssb_bus_suspend(struct ssb_bus
*bus
, pm_message_t state
)
126 ssb_chipco_suspend(&bus
->chipco
, state
);
127 ssb_pci_xtal(bus
, SSB_GPIO_XTAL
| SSB_GPIO_PLL
, 0);
129 /* Reset HW state information in memory, so that HW is
130 * completely reinitialized on resume. */
131 bus
->mapped_device
= NULL
;
132 #ifdef CONFIG_SSB_DRIVER_PCICORE
133 bus
->pcicore
.setup_done
= 0;
135 #ifdef CONFIG_SSB_DEBUG
140 static int ssb_device_suspend(struct device
*dev
, pm_message_t state
)
142 struct ssb_device
*ssb_dev
= dev_to_ssb_dev(dev
);
143 struct ssb_driver
*ssb_drv
;
148 ssb_drv
= drv_to_ssb_drv(dev
->driver
);
149 if (ssb_drv
&& ssb_drv
->suspend
)
150 err
= ssb_drv
->suspend(ssb_dev
, state
);
157 if (bus
->suspend_cnt
== bus
->nr_devices
) {
158 /* All devices suspended. Shutdown the bus. */
159 ssb_bus_suspend(bus
, state
);
166 #ifdef CONFIG_SSB_PCIHOST
167 int ssb_devices_freeze(struct ssb_bus
*bus
)
169 struct ssb_device
*dev
;
170 struct ssb_driver
*drv
;
173 pm_message_t state
= PMSG_FREEZE
;
175 /* First check that we are capable to freeze all devices. */
176 for (i
= 0; i
< bus
->nr_devices
; i
++) {
177 dev
= &(bus
->devices
[i
]);
180 !device_is_registered(dev
->dev
))
182 drv
= drv_to_ssb_drv(dev
->dev
->driver
);
186 /* Nope, can't suspend this one. */
190 /* Now suspend all devices */
191 for (i
= 0; i
< bus
->nr_devices
; i
++) {
192 dev
= &(bus
->devices
[i
]);
195 !device_is_registered(dev
->dev
))
197 drv
= drv_to_ssb_drv(dev
->dev
->driver
);
200 err
= drv
->suspend(dev
, state
);
202 ssb_printk(KERN_ERR PFX
"Failed to freeze device %s\n",
210 for (i
--; i
>= 0; i
--) {
211 dev
= &(bus
->devices
[i
]);
214 !device_is_registered(dev
->dev
))
216 drv
= drv_to_ssb_drv(dev
->dev
->driver
);
225 int ssb_devices_thaw(struct ssb_bus
*bus
)
227 struct ssb_device
*dev
;
228 struct ssb_driver
*drv
;
232 for (i
= 0; i
< bus
->nr_devices
; i
++) {
233 dev
= &(bus
->devices
[i
]);
236 !device_is_registered(dev
->dev
))
238 drv
= drv_to_ssb_drv(dev
->dev
->driver
);
241 if (SSB_WARN_ON(!drv
->resume
))
243 err
= drv
->resume(dev
);
245 ssb_printk(KERN_ERR PFX
"Failed to thaw device %s\n",
252 #endif /* CONFIG_SSB_PCIHOST */
254 static void ssb_device_shutdown(struct device
*dev
)
256 struct ssb_device
*ssb_dev
= dev_to_ssb_dev(dev
);
257 struct ssb_driver
*ssb_drv
;
261 ssb_drv
= drv_to_ssb_drv(dev
->driver
);
262 if (ssb_drv
&& ssb_drv
->shutdown
)
263 ssb_drv
->shutdown(ssb_dev
);
266 static int ssb_device_remove(struct device
*dev
)
268 struct ssb_device
*ssb_dev
= dev_to_ssb_dev(dev
);
269 struct ssb_driver
*ssb_drv
= drv_to_ssb_drv(dev
->driver
);
271 if (ssb_drv
&& ssb_drv
->remove
)
272 ssb_drv
->remove(ssb_dev
);
273 ssb_device_put(ssb_dev
);
278 static int ssb_device_probe(struct device
*dev
)
280 struct ssb_device
*ssb_dev
= dev_to_ssb_dev(dev
);
281 struct ssb_driver
*ssb_drv
= drv_to_ssb_drv(dev
->driver
);
284 ssb_device_get(ssb_dev
);
285 if (ssb_drv
&& ssb_drv
->probe
)
286 err
= ssb_drv
->probe(ssb_dev
, &ssb_dev
->id
);
288 ssb_device_put(ssb_dev
);
293 static int ssb_match_devid(const struct ssb_device_id
*tabid
,
294 const struct ssb_device_id
*devid
)
296 if ((tabid
->vendor
!= devid
->vendor
) &&
297 tabid
->vendor
!= SSB_ANY_VENDOR
)
299 if ((tabid
->coreid
!= devid
->coreid
) &&
300 tabid
->coreid
!= SSB_ANY_ID
)
302 if ((tabid
->revision
!= devid
->revision
) &&
303 tabid
->revision
!= SSB_ANY_REV
)
308 static int ssb_bus_match(struct device
*dev
, struct device_driver
*drv
)
310 struct ssb_device
*ssb_dev
= dev_to_ssb_dev(dev
);
311 struct ssb_driver
*ssb_drv
= drv_to_ssb_drv(drv
);
312 const struct ssb_device_id
*id
;
314 for (id
= ssb_drv
->id_table
;
315 id
->vendor
|| id
->coreid
|| id
->revision
;
317 if (ssb_match_devid(id
, &ssb_dev
->id
))
318 return 1; /* found */
324 static int ssb_device_uevent(struct device
*dev
, struct kobj_uevent_env
*env
)
326 struct ssb_device
*ssb_dev
= dev_to_ssb_dev(dev
);
331 return add_uevent_var(env
,
332 "MODALIAS=ssb:v%04Xid%04Xrev%02X",
333 ssb_dev
->id
.vendor
, ssb_dev
->id
.coreid
,
334 ssb_dev
->id
.revision
);
337 static struct bus_type ssb_bustype
= {
339 .match
= ssb_bus_match
,
340 .probe
= ssb_device_probe
,
341 .remove
= ssb_device_remove
,
342 .shutdown
= ssb_device_shutdown
,
343 .suspend
= ssb_device_suspend
,
344 .resume
= ssb_device_resume
,
345 .uevent
= ssb_device_uevent
,
348 static void ssb_buses_lock(void)
350 /* See the comment at the ssb_is_early_boot definition */
351 if (!ssb_is_early_boot
)
352 mutex_lock(&buses_mutex
);
355 static void ssb_buses_unlock(void)
357 /* See the comment at the ssb_is_early_boot definition */
358 if (!ssb_is_early_boot
)
359 mutex_unlock(&buses_mutex
);
362 static void ssb_devices_unregister(struct ssb_bus
*bus
)
364 struct ssb_device
*sdev
;
367 for (i
= bus
->nr_devices
- 1; i
>= 0; i
--) {
368 sdev
= &(bus
->devices
[i
]);
370 device_unregister(sdev
->dev
);
374 void ssb_bus_unregister(struct ssb_bus
*bus
)
377 ssb_devices_unregister(bus
);
378 list_del(&bus
->list
);
381 /* ssb_pcmcia_exit(bus); */
385 EXPORT_SYMBOL(ssb_bus_unregister
);
387 static void ssb_release_dev(struct device
*dev
)
389 struct __ssb_dev_wrapper
*devwrap
;
391 devwrap
= container_of(dev
, struct __ssb_dev_wrapper
, dev
);
395 static int ssb_devices_register(struct ssb_bus
*bus
)
397 struct ssb_device
*sdev
;
399 struct __ssb_dev_wrapper
*devwrap
;
403 for (i
= 0; i
< bus
->nr_devices
; i
++) {
404 sdev
= &(bus
->devices
[i
]);
406 /* We don't register SSB-system devices to the kernel,
407 * as the drivers for them are built into SSB. */
408 switch (sdev
->id
.coreid
) {
409 case SSB_DEV_CHIPCOMMON
:
414 case SSB_DEV_MIPS_3302
:
419 devwrap
= kzalloc(sizeof(*devwrap
), GFP_KERNEL
);
421 ssb_printk(KERN_ERR PFX
422 "Could not allocate device\n");
427 devwrap
->sdev
= sdev
;
429 dev
->release
= ssb_release_dev
;
430 dev
->bus
= &ssb_bustype
;
431 snprintf(dev
->bus_id
, sizeof(dev
->bus_id
),
432 "ssb%u:%d", bus
->busnumber
, dev_idx
);
434 switch (bus
->bustype
) {
435 case SSB_BUSTYPE_PCI
:
436 #ifdef CONFIG_SSB_PCIHOST
437 sdev
->irq
= bus
->host_pci
->irq
;
438 dev
->parent
= &bus
->host_pci
->dev
;
441 case SSB_BUSTYPE_PCMCIA
:
442 #ifdef CONFIG_SSB_PCMCIAHOST
443 sdev
->irq
= bus
->host_pcmcia
->irq
.AssignedIRQ
;
444 dev
->parent
= &bus
->host_pcmcia
->dev
;
447 case SSB_BUSTYPE_SSB
:
452 err
= device_register(dev
);
454 ssb_printk(KERN_ERR PFX
455 "Could not register %s\n",
457 /* Set dev to NULL to not unregister
458 * dev on error unwinding. */
468 /* Unwind the already registered devices. */
469 ssb_devices_unregister(bus
);
473 /* Needs ssb_buses_lock() */
474 static int ssb_attach_queued_buses(void)
476 struct ssb_bus
*bus
, *n
;
478 int drop_them_all
= 0;
480 list_for_each_entry_safe(bus
, n
, &attach_queue
, list
) {
482 list_del(&bus
->list
);
485 /* Can't init the PCIcore in ssb_bus_register(), as that
486 * is too early in boot for embedded systems
487 * (no udelay() available). So do it here in attach stage.
489 err
= ssb_bus_powerup(bus
, 0);
492 ssb_pcicore_init(&bus
->pcicore
);
493 ssb_bus_may_powerdown(bus
);
495 err
= ssb_devices_register(bus
);
499 list_del(&bus
->list
);
502 list_move_tail(&bus
->list
, &buses
);
508 static u16
ssb_ssb_read16(struct ssb_device
*dev
, u16 offset
)
510 struct ssb_bus
*bus
= dev
->bus
;
512 offset
+= dev
->core_index
* SSB_CORE_SIZE
;
513 return readw(bus
->mmio
+ offset
);
516 static u32
ssb_ssb_read32(struct ssb_device
*dev
, u16 offset
)
518 struct ssb_bus
*bus
= dev
->bus
;
520 offset
+= dev
->core_index
* SSB_CORE_SIZE
;
521 return readl(bus
->mmio
+ offset
);
524 static void ssb_ssb_write16(struct ssb_device
*dev
, u16 offset
, u16 value
)
526 struct ssb_bus
*bus
= dev
->bus
;
528 offset
+= dev
->core_index
* SSB_CORE_SIZE
;
529 writew(value
, bus
->mmio
+ offset
);
532 static void ssb_ssb_write32(struct ssb_device
*dev
, u16 offset
, u32 value
)
534 struct ssb_bus
*bus
= dev
->bus
;
536 offset
+= dev
->core_index
* SSB_CORE_SIZE
;
537 writel(value
, bus
->mmio
+ offset
);
540 /* Ops for the plain SSB bus without a host-device (no PCI or PCMCIA). */
541 static const struct ssb_bus_ops ssb_ssb_ops
= {
542 .read16
= ssb_ssb_read16
,
543 .read32
= ssb_ssb_read32
,
544 .write16
= ssb_ssb_write16
,
545 .write32
= ssb_ssb_write32
,
548 static int ssb_fetch_invariants(struct ssb_bus
*bus
,
549 ssb_invariants_func_t get_invariants
)
551 struct ssb_init_invariants iv
;
554 memset(&iv
, 0, sizeof(iv
));
555 err
= get_invariants(bus
, &iv
);
558 memcpy(&bus
->boardinfo
, &iv
.boardinfo
, sizeof(iv
.boardinfo
));
559 memcpy(&bus
->sprom
, &iv
.sprom
, sizeof(iv
.sprom
));
564 static int ssb_bus_register(struct ssb_bus
*bus
,
565 ssb_invariants_func_t get_invariants
,
566 unsigned long baseaddr
)
570 spin_lock_init(&bus
->bar_lock
);
571 INIT_LIST_HEAD(&bus
->list
);
572 #ifdef CONFIG_SSB_EMBEDDED
573 spin_lock_init(&bus
->gpio_lock
);
576 /* Powerup the bus */
577 err
= ssb_pci_xtal(bus
, SSB_GPIO_XTAL
| SSB_GPIO_PLL
, 1);
581 bus
->busnumber
= next_busnumber
;
582 /* Scan for devices (cores) */
583 err
= ssb_bus_scan(bus
, baseaddr
);
585 goto err_disable_xtal
;
587 /* Init PCI-host device (if any) */
588 err
= ssb_pci_init(bus
);
591 /* Init PCMCIA-host device (if any) */
592 err
= ssb_pcmcia_init(bus
);
596 /* Initialize basic system devices (if available) */
597 err
= ssb_bus_powerup(bus
, 0);
599 goto err_pcmcia_exit
;
600 ssb_chipcommon_init(&bus
->chipco
);
601 ssb_mipscore_init(&bus
->mipscore
);
602 err
= ssb_fetch_invariants(bus
, get_invariants
);
604 ssb_bus_may_powerdown(bus
);
605 goto err_pcmcia_exit
;
607 ssb_bus_may_powerdown(bus
);
609 /* Queue it for attach.
610 * See the comment at the ssb_is_early_boot definition. */
611 list_add_tail(&bus
->list
, &attach_queue
);
612 if (!ssb_is_early_boot
) {
613 /* This is not early boot, so we must attach the bus now */
614 err
= ssb_attach_queued_buses();
625 list_del(&bus
->list
);
627 /* ssb_pcmcia_exit(bus); */
634 ssb_pci_xtal(bus
, SSB_GPIO_XTAL
| SSB_GPIO_PLL
, 0);
638 #ifdef CONFIG_SSB_PCIHOST
639 int ssb_bus_pcibus_register(struct ssb_bus
*bus
,
640 struct pci_dev
*host_pci
)
644 bus
->bustype
= SSB_BUSTYPE_PCI
;
645 bus
->host_pci
= host_pci
;
646 bus
->ops
= &ssb_pci_ops
;
648 err
= ssb_bus_register(bus
, ssb_pci_get_invariants
, 0);
650 ssb_printk(KERN_INFO PFX
"Sonics Silicon Backplane found on "
651 "PCI device %s\n", host_pci
->dev
.bus_id
);
656 EXPORT_SYMBOL(ssb_bus_pcibus_register
);
657 #endif /* CONFIG_SSB_PCIHOST */
659 #ifdef CONFIG_SSB_PCMCIAHOST
660 int ssb_bus_pcmciabus_register(struct ssb_bus
*bus
,
661 struct pcmcia_device
*pcmcia_dev
,
662 unsigned long baseaddr
)
666 bus
->bustype
= SSB_BUSTYPE_PCMCIA
;
667 bus
->host_pcmcia
= pcmcia_dev
;
668 bus
->ops
= &ssb_pcmcia_ops
;
670 err
= ssb_bus_register(bus
, ssb_pcmcia_get_invariants
, baseaddr
);
672 ssb_printk(KERN_INFO PFX
"Sonics Silicon Backplane found on "
673 "PCMCIA device %s\n", pcmcia_dev
->devname
);
678 EXPORT_SYMBOL(ssb_bus_pcmciabus_register
);
679 #endif /* CONFIG_SSB_PCMCIAHOST */
681 int ssb_bus_ssbbus_register(struct ssb_bus
*bus
,
682 unsigned long baseaddr
,
683 ssb_invariants_func_t get_invariants
)
687 bus
->bustype
= SSB_BUSTYPE_SSB
;
688 bus
->ops
= &ssb_ssb_ops
;
690 err
= ssb_bus_register(bus
, get_invariants
, baseaddr
);
692 ssb_printk(KERN_INFO PFX
"Sonics Silicon Backplane found at "
693 "address 0x%08lX\n", baseaddr
);
699 int __ssb_driver_register(struct ssb_driver
*drv
, struct module
*owner
)
701 drv
->drv
.name
= drv
->name
;
702 drv
->drv
.bus
= &ssb_bustype
;
703 drv
->drv
.owner
= owner
;
705 return driver_register(&drv
->drv
);
707 EXPORT_SYMBOL(__ssb_driver_register
);
709 void ssb_driver_unregister(struct ssb_driver
*drv
)
711 driver_unregister(&drv
->drv
);
713 EXPORT_SYMBOL(ssb_driver_unregister
);
715 void ssb_set_devtypedata(struct ssb_device
*dev
, void *data
)
717 struct ssb_bus
*bus
= dev
->bus
;
718 struct ssb_device
*ent
;
721 for (i
= 0; i
< bus
->nr_devices
; i
++) {
722 ent
= &(bus
->devices
[i
]);
723 if (ent
->id
.vendor
!= dev
->id
.vendor
)
725 if (ent
->id
.coreid
!= dev
->id
.coreid
)
728 ent
->devtypedata
= data
;
731 EXPORT_SYMBOL(ssb_set_devtypedata
);
733 static u32
clkfactor_f6_resolve(u32 v
)
735 /* map the magic values */
737 case SSB_CHIPCO_CLK_F6_2
:
739 case SSB_CHIPCO_CLK_F6_3
:
741 case SSB_CHIPCO_CLK_F6_4
:
743 case SSB_CHIPCO_CLK_F6_5
:
745 case SSB_CHIPCO_CLK_F6_6
:
747 case SSB_CHIPCO_CLK_F6_7
:
753 /* Calculate the speed the backplane would run at a given set of clockcontrol values */
754 u32
ssb_calc_clock_rate(u32 plltype
, u32 n
, u32 m
)
756 u32 n1
, n2
, clock
, m1
, m2
, m3
, mc
;
758 n1
= (n
& SSB_CHIPCO_CLK_N1
);
759 n2
= ((n
& SSB_CHIPCO_CLK_N2
) >> SSB_CHIPCO_CLK_N2_SHIFT
);
762 case SSB_PLLTYPE_6
: /* 100/200 or 120/240 only */
763 if (m
& SSB_CHIPCO_CLK_T6_MMASK
)
764 return SSB_CHIPCO_CLK_T6_M0
;
765 return SSB_CHIPCO_CLK_T6_M1
;
766 case SSB_PLLTYPE_1
: /* 48Mhz base, 3 dividers */
767 case SSB_PLLTYPE_3
: /* 25Mhz, 2 dividers */
768 case SSB_PLLTYPE_4
: /* 48Mhz, 4 dividers */
769 case SSB_PLLTYPE_7
: /* 25Mhz, 4 dividers */
770 n1
= clkfactor_f6_resolve(n1
);
771 n2
+= SSB_CHIPCO_CLK_F5_BIAS
;
773 case SSB_PLLTYPE_2
: /* 48Mhz, 4 dividers */
774 n1
+= SSB_CHIPCO_CLK_T2_BIAS
;
775 n2
+= SSB_CHIPCO_CLK_T2_BIAS
;
776 SSB_WARN_ON(!((n1
>= 2) && (n1
<= 7)));
777 SSB_WARN_ON(!((n2
>= 5) && (n2
<= 23)));
779 case SSB_PLLTYPE_5
: /* 25Mhz, 4 dividers */
786 case SSB_PLLTYPE_3
: /* 25Mhz, 2 dividers */
787 case SSB_PLLTYPE_7
: /* 25Mhz, 4 dividers */
788 clock
= SSB_CHIPCO_CLK_BASE2
* n1
* n2
;
791 clock
= SSB_CHIPCO_CLK_BASE1
* n1
* n2
;
796 m1
= (m
& SSB_CHIPCO_CLK_M1
);
797 m2
= ((m
& SSB_CHIPCO_CLK_M2
) >> SSB_CHIPCO_CLK_M2_SHIFT
);
798 m3
= ((m
& SSB_CHIPCO_CLK_M3
) >> SSB_CHIPCO_CLK_M3_SHIFT
);
799 mc
= ((m
& SSB_CHIPCO_CLK_MC
) >> SSB_CHIPCO_CLK_MC_SHIFT
);
802 case SSB_PLLTYPE_1
: /* 48Mhz base, 3 dividers */
803 case SSB_PLLTYPE_3
: /* 25Mhz, 2 dividers */
804 case SSB_PLLTYPE_4
: /* 48Mhz, 4 dividers */
805 case SSB_PLLTYPE_7
: /* 25Mhz, 4 dividers */
806 m1
= clkfactor_f6_resolve(m1
);
807 if ((plltype
== SSB_PLLTYPE_1
) ||
808 (plltype
== SSB_PLLTYPE_3
))
809 m2
+= SSB_CHIPCO_CLK_F5_BIAS
;
811 m2
= clkfactor_f6_resolve(m2
);
812 m3
= clkfactor_f6_resolve(m3
);
815 case SSB_CHIPCO_CLK_MC_BYPASS
:
817 case SSB_CHIPCO_CLK_MC_M1
:
819 case SSB_CHIPCO_CLK_MC_M1M2
:
820 return (clock
/ (m1
* m2
));
821 case SSB_CHIPCO_CLK_MC_M1M2M3
:
822 return (clock
/ (m1
* m2
* m3
));
823 case SSB_CHIPCO_CLK_MC_M1M3
:
824 return (clock
/ (m1
* m3
));
828 m1
+= SSB_CHIPCO_CLK_T2_BIAS
;
829 m2
+= SSB_CHIPCO_CLK_T2M2_BIAS
;
830 m3
+= SSB_CHIPCO_CLK_T2_BIAS
;
831 SSB_WARN_ON(!((m1
>= 2) && (m1
<= 7)));
832 SSB_WARN_ON(!((m2
>= 3) && (m2
<= 10)));
833 SSB_WARN_ON(!((m3
>= 2) && (m3
<= 7)));
835 if (!(mc
& SSB_CHIPCO_CLK_T2MC_M1BYP
))
837 if (!(mc
& SSB_CHIPCO_CLK_T2MC_M2BYP
))
839 if (!(mc
& SSB_CHIPCO_CLK_T2MC_M3BYP
))
848 /* Get the current speed the backplane is running at */
849 u32
ssb_clockspeed(struct ssb_bus
*bus
)
853 u32 clkctl_n
, clkctl_m
;
855 if (ssb_extif_available(&bus
->extif
))
856 ssb_extif_get_clockcontrol(&bus
->extif
, &plltype
,
857 &clkctl_n
, &clkctl_m
);
858 else if (bus
->chipco
.dev
)
859 ssb_chipco_get_clockcontrol(&bus
->chipco
, &plltype
,
860 &clkctl_n
, &clkctl_m
);
864 if (bus
->chip_id
== 0x5365) {
867 rate
= ssb_calc_clock_rate(plltype
, clkctl_n
, clkctl_m
);
868 if (plltype
== SSB_PLLTYPE_3
) /* 25Mhz, 2 dividers */
874 EXPORT_SYMBOL(ssb_clockspeed
);
876 static u32
ssb_tmslow_reject_bitmask(struct ssb_device
*dev
)
878 u32 rev
= ssb_read32(dev
, SSB_IDLOW
) & SSB_IDLOW_SSBREV
;
880 /* The REJECT bit changed position in TMSLOW between
881 * Backplane revisions. */
883 case SSB_IDLOW_SSBREV_22
:
884 return SSB_TMSLOW_REJECT_22
;
885 case SSB_IDLOW_SSBREV_23
:
886 return SSB_TMSLOW_REJECT_23
;
887 case SSB_IDLOW_SSBREV_24
: /* TODO - find the proper REJECT bits */
888 case SSB_IDLOW_SSBREV_25
: /* same here */
889 case SSB_IDLOW_SSBREV_26
: /* same here */
890 case SSB_IDLOW_SSBREV_27
: /* same here */
891 return SSB_TMSLOW_REJECT_23
; /* this is a guess */
893 printk(KERN_INFO
"ssb: Backplane Revision 0x%.8X\n", rev
);
896 return (SSB_TMSLOW_REJECT_22
| SSB_TMSLOW_REJECT_23
);
899 int ssb_device_is_enabled(struct ssb_device
*dev
)
904 reject
= ssb_tmslow_reject_bitmask(dev
);
905 val
= ssb_read32(dev
, SSB_TMSLOW
);
906 val
&= SSB_TMSLOW_CLOCK
| SSB_TMSLOW_RESET
| reject
;
908 return (val
== SSB_TMSLOW_CLOCK
);
910 EXPORT_SYMBOL(ssb_device_is_enabled
);
912 static void ssb_flush_tmslow(struct ssb_device
*dev
)
914 /* Make _really_ sure the device has finished the TMSLOW
915 * register write transaction, as we risk running into
916 * a machine check exception otherwise.
917 * Do this by reading the register back to commit the
918 * PCI write and delay an additional usec for the device
919 * to react to the change. */
920 ssb_read32(dev
, SSB_TMSLOW
);
924 void ssb_device_enable(struct ssb_device
*dev
, u32 core_specific_flags
)
928 ssb_device_disable(dev
, core_specific_flags
);
929 ssb_write32(dev
, SSB_TMSLOW
,
930 SSB_TMSLOW_RESET
| SSB_TMSLOW_CLOCK
|
931 SSB_TMSLOW_FGC
| core_specific_flags
);
932 ssb_flush_tmslow(dev
);
934 /* Clear SERR if set. This is a hw bug workaround. */
935 if (ssb_read32(dev
, SSB_TMSHIGH
) & SSB_TMSHIGH_SERR
)
936 ssb_write32(dev
, SSB_TMSHIGH
, 0);
938 val
= ssb_read32(dev
, SSB_IMSTATE
);
939 if (val
& (SSB_IMSTATE_IBE
| SSB_IMSTATE_TO
)) {
940 val
&= ~(SSB_IMSTATE_IBE
| SSB_IMSTATE_TO
);
941 ssb_write32(dev
, SSB_IMSTATE
, val
);
944 ssb_write32(dev
, SSB_TMSLOW
,
945 SSB_TMSLOW_CLOCK
| SSB_TMSLOW_FGC
|
946 core_specific_flags
);
947 ssb_flush_tmslow(dev
);
949 ssb_write32(dev
, SSB_TMSLOW
, SSB_TMSLOW_CLOCK
|
950 core_specific_flags
);
951 ssb_flush_tmslow(dev
);
953 EXPORT_SYMBOL(ssb_device_enable
);
955 /* Wait for a bit in a register to get set or unset.
956 * timeout is in units of ten-microseconds */
957 static int ssb_wait_bit(struct ssb_device
*dev
, u16 reg
, u32 bitmask
,
958 int timeout
, int set
)
963 for (i
= 0; i
< timeout
; i
++) {
964 val
= ssb_read32(dev
, reg
);
969 if (!(val
& bitmask
))
974 printk(KERN_ERR PFX
"Timeout waiting for bitmask %08X on "
975 "register %04X to %s.\n",
976 bitmask
, reg
, (set
? "set" : "clear"));
981 void ssb_device_disable(struct ssb_device
*dev
, u32 core_specific_flags
)
985 if (ssb_read32(dev
, SSB_TMSLOW
) & SSB_TMSLOW_RESET
)
988 reject
= ssb_tmslow_reject_bitmask(dev
);
989 ssb_write32(dev
, SSB_TMSLOW
, reject
| SSB_TMSLOW_CLOCK
);
990 ssb_wait_bit(dev
, SSB_TMSLOW
, reject
, 1000, 1);
991 ssb_wait_bit(dev
, SSB_TMSHIGH
, SSB_TMSHIGH_BUSY
, 1000, 0);
992 ssb_write32(dev
, SSB_TMSLOW
,
993 SSB_TMSLOW_FGC
| SSB_TMSLOW_CLOCK
|
994 reject
| SSB_TMSLOW_RESET
|
995 core_specific_flags
);
996 ssb_flush_tmslow(dev
);
998 ssb_write32(dev
, SSB_TMSLOW
,
999 reject
| SSB_TMSLOW_RESET
|
1000 core_specific_flags
);
1001 ssb_flush_tmslow(dev
);
1003 EXPORT_SYMBOL(ssb_device_disable
);
1005 u32
ssb_dma_translation(struct ssb_device
*dev
)
1007 switch (dev
->bus
->bustype
) {
1008 case SSB_BUSTYPE_SSB
:
1010 case SSB_BUSTYPE_PCI
:
1011 case SSB_BUSTYPE_PCMCIA
:
1016 EXPORT_SYMBOL(ssb_dma_translation
);
1018 int ssb_dma_set_mask(struct ssb_device
*ssb_dev
, u64 mask
)
1020 struct device
*dev
= ssb_dev
->dev
;
1022 #ifdef CONFIG_SSB_PCIHOST
1023 if (ssb_dev
->bus
->bustype
== SSB_BUSTYPE_PCI
&&
1024 !dma_supported(dev
, mask
))
1027 dev
->coherent_dma_mask
= mask
;
1028 dev
->dma_mask
= &dev
->coherent_dma_mask
;
1032 EXPORT_SYMBOL(ssb_dma_set_mask
);
1034 int ssb_bus_may_powerdown(struct ssb_bus
*bus
)
1036 struct ssb_chipcommon
*cc
;
1039 /* On buses where more than one core may be working
1040 * at a time, we must not powerdown stuff if there are
1041 * still cores that may want to run. */
1042 if (bus
->bustype
== SSB_BUSTYPE_SSB
)
1046 ssb_chipco_set_clockmode(cc
, SSB_CLKMODE_SLOW
);
1047 err
= ssb_pci_xtal(bus
, SSB_GPIO_XTAL
| SSB_GPIO_PLL
, 0);
1051 #ifdef CONFIG_SSB_DEBUG
1052 bus
->powered_up
= 0;
1056 ssb_printk(KERN_ERR PFX
"Bus powerdown failed\n");
1059 EXPORT_SYMBOL(ssb_bus_may_powerdown
);
1061 int ssb_bus_powerup(struct ssb_bus
*bus
, bool dynamic_pctl
)
1063 struct ssb_chipcommon
*cc
;
1065 enum ssb_clkmode mode
;
1067 err
= ssb_pci_xtal(bus
, SSB_GPIO_XTAL
| SSB_GPIO_PLL
, 1);
1071 mode
= dynamic_pctl
? SSB_CLKMODE_DYNAMIC
: SSB_CLKMODE_FAST
;
1072 ssb_chipco_set_clockmode(cc
, mode
);
1074 #ifdef CONFIG_SSB_DEBUG
1075 bus
->powered_up
= 1;
1079 ssb_printk(KERN_ERR PFX
"Bus powerup failed\n");
1082 EXPORT_SYMBOL(ssb_bus_powerup
);
1084 u32
ssb_admatch_base(u32 adm
)
1088 switch (adm
& SSB_ADM_TYPE
) {
1090 base
= (adm
& SSB_ADM_BASE0
);
1093 SSB_WARN_ON(adm
& SSB_ADM_NEG
); /* unsupported */
1094 base
= (adm
& SSB_ADM_BASE1
);
1097 SSB_WARN_ON(adm
& SSB_ADM_NEG
); /* unsupported */
1098 base
= (adm
& SSB_ADM_BASE2
);
1106 EXPORT_SYMBOL(ssb_admatch_base
);
1108 u32
ssb_admatch_size(u32 adm
)
1112 switch (adm
& SSB_ADM_TYPE
) {
1114 size
= ((adm
& SSB_ADM_SZ0
) >> SSB_ADM_SZ0_SHIFT
);
1117 SSB_WARN_ON(adm
& SSB_ADM_NEG
); /* unsupported */
1118 size
= ((adm
& SSB_ADM_SZ1
) >> SSB_ADM_SZ1_SHIFT
);
1121 SSB_WARN_ON(adm
& SSB_ADM_NEG
); /* unsupported */
1122 size
= ((adm
& SSB_ADM_SZ2
) >> SSB_ADM_SZ2_SHIFT
);
1127 size
= (1 << (size
+ 1));
1131 EXPORT_SYMBOL(ssb_admatch_size
);
1133 static int __init
ssb_modinit(void)
1137 /* See the comment at the ssb_is_early_boot definition */
1138 ssb_is_early_boot
= 0;
1139 err
= bus_register(&ssb_bustype
);
1143 /* Maybe we already registered some buses at early boot.
1144 * Check for this and attach them
1147 err
= ssb_attach_queued_buses();
1150 bus_unregister(&ssb_bustype
);
1152 err
= b43_pci_ssb_bridge_init();
1154 ssb_printk(KERN_ERR
"Broadcom 43xx PCI-SSB-bridge "
1155 "initialization failed");
1156 /* don't fail SSB init because of this */
1162 /* ssb must be initialized after PCI but before the ssb drivers.
1163 * That means we must use some initcall between subsys_initcall
1164 * and device_initcall. */
1165 fs_initcall(ssb_modinit
);
1167 static void __exit
ssb_modexit(void)
1169 b43_pci_ssb_bridge_exit();
1170 bus_unregister(&ssb_bustype
);
1172 module_exit(ssb_modexit
)