drivers/net/netxen/netxen_nic_hw.h

   1 /*
   2  * Copyright (C) 2003 - 2006 NetXen, Inc.
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License
   7  * as published by the Free Software Foundation; either version 2
   8  * of the License, or (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  18  * MA  02111-1307, USA.
  19  *
  20  * The full GNU General Public License is included in this distribution
  21  * in the file called LICENSE.
  22  *
  23  * Contact Information:
  24  *    info@netxen.com
  25  * NetXen,
  26  * 3965 Freedom Circle, Fourth floor,
  27  * Santa Clara, CA 95054
  28  *
  29  *
  30  * Structures, enums, and macros for the MAC
  31  *
  32  */
  33
  34 #ifndef __NETXEN_NIC_HW_H_
  35 #define __NETXEN_NIC_HW_H_
  36
  37 #include "netxen_nic_hdr.h"
  38
  39 /* Hardware memory size of 128 meg */
  40 #define NETXEN_MEMADDR_MAX (128 * 1024 * 1024)
  41
  42 #ifndef readq
  43 static inline u64 readq(void __iomem * addr)
  44 {
  45         return readl(addr) | (((u64) readl(addr + 4)) << 32LL);
  46 }
  47 #endif
  48
  49 #ifndef writeq
  50 static inline void writeq(u64 val, void __iomem * addr)
  51 {
  52         writel(((u32) (val)), (addr));
  53         writel(((u32) (val >> 32)), (addr + 4));
  54 }
  55 #endif
  56
  57 static inline void netxen_nic_hw_block_write64(u64 __iomem * data_ptr,
  58                                                u64 __iomem * addr,
  59                                                int num_words)
  60 {
  61         int num;
  62         for (num = 0; num < num_words; num++) {
  63                 writeq(readq((void __iomem *)data_ptr), addr);
  64                 addr++;
  65                 data_ptr++;
  66         }
  67 }
  68
  69 static inline void netxen_nic_hw_block_read64(u64 __iomem * data_ptr,
  70                                               u64 __iomem * addr, int num_words)
  71 {
  72         int num;
  73         for (num = 0; num < num_words; num++) {
  74                 writeq(readq((void __iomem *)addr), data_ptr);
  75                 addr++;
  76                 data_ptr++;
  77         }
  78
  79 }
  80
  81 struct netxen_adapter;
  82
  83 #define NETXEN_PCI_MAPSIZE_BYTES  (NETXEN_PCI_MAPSIZE << 20)
  84
  85 struct netxen_port;
  86 void netxen_nic_set_link_parameters(struct netxen_adapter *adapter);
  87 void netxen_nic_flash_print(struct netxen_adapter *adapter);
  88
  89 typedef u8 netxen_ethernet_macaddr_t[6];
  90
  91 /* Nibble or Byte mode for phy interface (GbE mode only) */
  92 typedef enum {
  93         NETXEN_NIU_10_100_MB = 0,
  94         NETXEN_NIU_1000_MB
  95 } netxen_niu_gbe_ifmode_t;
  96
  97 #define _netxen_crb_get_bit(var, bit)  ((var >> bit) & 0x1)
  98
  99 /*
 100  * NIU GB MAC Config Register 0 (applies to GB0, GB1, GB2, GB3)
 101  *
 102  *      Bit 0 : enable_tx => 1:enable frame xmit, 0:disable
 103  *      Bit 1 : tx_synced => R/O: xmit enable synched to xmit stream
 104  *      Bit 2 : enable_rx => 1:enable frame recv, 0:disable
 105  *      Bit 3 : rx_synced => R/O: recv enable synched to recv stream
 106  *      Bit 4 : tx_flowctl => 1:enable pause frame generation, 0:disable
 107  *      Bit 5 : rx_flowctl => 1:act on recv'd pause frames, 0:ignore
 108  *      Bit 8 : loopback => 1:loop MAC xmits to MAC recvs, 0:normal
 109  *      Bit 16: tx_reset_pb => 1:reset frame xmit protocol blk, 0:no-op
 110  *      Bit 17: rx_reset_pb => 1:reset frame recv protocol blk, 0:no-op
 111  *      Bit 18: tx_reset_mac => 1:reset data/ctl multiplexer blk, 0:no-op
 112  *      Bit 19: rx_reset_mac => 1:reset ctl frames & timers blk, 0:no-op
 113  *      Bit 31: soft_reset => 1:reset the MAC and the SERDES, 0:no-op
 114  */
 115
 116 #define netxen_gb_enable_tx(config_word)        \
 117         ((config_word) |= 1 << 0)
 118 #define netxen_gb_enable_rx(config_word)        \
 119         ((config_word) |= 1 << 2)
 120 #define netxen_gb_tx_flowctl(config_word)       \
 121         ((config_word) |= 1 << 4)
 122 #define netxen_gb_rx_flowctl(config_word)       \
 123         ((config_word) |= 1 << 5)
 124 #define netxen_gb_tx_reset_pb(config_word)      \
 125         ((config_word) |= 1 << 16)
 126 #define netxen_gb_rx_reset_pb(config_word)      \
 127         ((config_word) |= 1 << 17)
 128 #define netxen_gb_tx_reset_mac(config_word)     \
 129         ((config_word) |= 1 << 18)
 130 #define netxen_gb_rx_reset_mac(config_word)     \
 131         ((config_word) |= 1 << 19)
 132 #define netxen_gb_soft_reset(config_word)       \
 133         ((config_word) |= 1 << 31)
 134
 135 #define netxen_gb_unset_tx_flowctl(config_word) \
 136         ((config_word) &= ~(1 << 4))
 137 #define netxen_gb_unset_rx_flowctl(config_word) \
 138         ((config_word) &= ~(1 << 5))
 139
 140 #define netxen_gb_get_tx_synced(config_word)    \
 141                 _netxen_crb_get_bit((config_word), 1)
 142 #define netxen_gb_get_rx_synced(config_word)    \
 143                 _netxen_crb_get_bit((config_word), 3)
 144 #define netxen_gb_get_tx_flowctl(config_word)   \
 145                 _netxen_crb_get_bit((config_word), 4)
 146 #define netxen_gb_get_rx_flowctl(config_word)   \
 147                 _netxen_crb_get_bit((config_word), 5)
 148 #define netxen_gb_get_soft_reset(config_word)   \
 149                 _netxen_crb_get_bit((config_word), 31)
 150
 151 /*
 152  * NIU GB MAC Config Register 1 (applies to GB0, GB1, GB2, GB3)
 153  *
 154  *      Bit 0       : duplex => 1:full duplex mode, 0:half duplex
 155  *      Bit 1       : crc_enable => 1:append CRC to xmit frames, 0:dont append
 156  *      Bit 2       : padshort => 1:pad short frames and add CRC, 0:dont pad
 157  *      Bit 4       : checklength => 1:check framelen with actual,0:dont check
 158  *      Bit 5       : hugeframes => 1:allow oversize xmit frames, 0:dont allow
 159  *      Bits 8-9    : intfmode => 01:nibble (10/100), 10:byte (1000)
 160  *      Bits 12-15  : preamblelen => preamble field length in bytes, default 7
 161  */
 162
 163 #define netxen_gb_set_duplex(config_word)       \
 164                 ((config_word) |= 1 << 0)
 165 #define netxen_gb_set_crc_enable(config_word)   \
 166                 ((config_word) |= 1 << 1)
 167 #define netxen_gb_set_padshort(config_word)     \
 168                 ((config_word) |= 1 << 2)
 169 #define netxen_gb_set_checklength(config_word)  \
 170                 ((config_word) |= 1 << 4)
 171 #define netxen_gb_set_hugeframes(config_word)   \
 172                 ((config_word) |= 1 << 5)
 173 #define netxen_gb_set_preamblelen(config_word, val)     \
 174                 ((config_word) |= ((val) << 12) & 0xF000)
 175 #define netxen_gb_set_intfmode(config_word, val)                \
 176                 ((config_word) |= ((val) << 8) & 0x300)
 177
 178 #define netxen_gb_get_stationaddress_low(config_word) ((config_word) >> 16)
 179
 180 #define netxen_gb_set_mii_mgmt_clockselect(config_word, val)    \
 181                 ((config_word) |= ((val) & 0x07))
 182 #define netxen_gb_mii_mgmt_reset(config_word)   \
 183                 ((config_word) |= 1 << 31)
 184 #define netxen_gb_mii_mgmt_unset(config_word)   \
 185                 ((config_word) &= ~(1 << 31))
 186
 187 /*
 188  * NIU GB MII Mgmt Command Register (applies to GB0, GB1, GB2, GB3)
 189  * Bit 0 : read_cycle => 1:perform single read cycle, 0:no-op
 190  * Bit 1 : scan_cycle => 1:perform continuous read cycles, 0:no-op
 191  */
 192
 193 #define netxen_gb_mii_mgmt_set_read_cycle(config_word)  \
 194                 ((config_word) |= 1 << 0)
 195 #define netxen_gb_mii_mgmt_reg_addr(config_word, val)   \
 196                 ((config_word) |= ((val) & 0x1F))
 197 #define netxen_gb_mii_mgmt_phy_addr(config_word, val)   \
 198                 ((config_word) |= (((val) & 0x1F) << 8))
 199
 200 /*
 201  * NIU GB MII Mgmt Indicators Register (applies to GB0, GB1, GB2, GB3)
 202  * Read-only register.
 203  * Bit 0 : busy => 1:performing an MII mgmt cycle, 0:idle
 204  * Bit 1 : scanning => 1:scan operation in progress, 0:idle
 205  * Bit 2 : notvalid => :mgmt result data not yet valid, 0:idle
 206  */
 207 #define netxen_get_gb_mii_mgmt_busy(config_word)        \
 208                 _netxen_crb_get_bit(config_word, 0)
 209 #define netxen_get_gb_mii_mgmt_scanning(config_word)    \
 210                 _netxen_crb_get_bit(config_word, 1)
 211 #define netxen_get_gb_mii_mgmt_notvalid(config_word)    \
 212                 _netxen_crb_get_bit(config_word, 2)
 213 /*
 214  * NIU XG Pause Ctl Register
 215  *
 216  *      Bit 0       : xg0_mask => 1:disable tx pause frames
 217  *      Bit 1       : xg0_request => 1:request single pause frame
 218  *      Bit 2       : xg0_on_off => 1:request is pause on, 0:off
 219  *      Bit 3       : xg1_mask => 1:disable tx pause frames
 220  *      Bit 4       : xg1_request => 1:request single pause frame
 221  *      Bit 5       : xg1_on_off => 1:request is pause on, 0:off
 222  */
 223
 224 #define netxen_xg_set_xg0_mask(config_word)    \
 225         ((config_word) |= 1 << 0)
 226 #define netxen_xg_set_xg1_mask(config_word)    \
 227         ((config_word) |= 1 << 3)
 228
 229 #define netxen_xg_get_xg0_mask(config_word)    \
 230         _netxen_crb_get_bit((config_word), 0)
 231 #define netxen_xg_get_xg1_mask(config_word)    \
 232         _netxen_crb_get_bit((config_word), 3)
 233
 234 #define netxen_xg_unset_xg0_mask(config_word)  \
 235         ((config_word) &= ~(1 << 0))
 236 #define netxen_xg_unset_xg1_mask(config_word)  \
 237         ((config_word) &= ~(1 << 3))
 238
 239 /*
 240  * NIU XG Pause Ctl Register
 241  *
 242  *      Bit 0       : xg0_mask => 1:disable tx pause frames
 243  *      Bit 1       : xg0_request => 1:request single pause frame
 244  *      Bit 2       : xg0_on_off => 1:request is pause on, 0:off
 245  *      Bit 3       : xg1_mask => 1:disable tx pause frames
 246  *      Bit 4       : xg1_request => 1:request single pause frame
 247  *      Bit 5       : xg1_on_off => 1:request is pause on, 0:off
 248  */
 249 #define netxen_gb_set_gb0_mask(config_word)    \
 250         ((config_word) |= 1 << 0)
 251 #define netxen_gb_set_gb1_mask(config_word)    \
 252         ((config_word) |= 1 << 2)
 253 #define netxen_gb_set_gb2_mask(config_word)    \
 254         ((config_word) |= 1 << 4)
 255 #define netxen_gb_set_gb3_mask(config_word)    \
 256         ((config_word) |= 1 << 6)
 257
 258 #define netxen_gb_get_gb0_mask(config_word)    \
 259         _netxen_crb_get_bit((config_word), 0)
 260 #define netxen_gb_get_gb1_mask(config_word)    \
 261         _netxen_crb_get_bit((config_word), 2)
 262 #define netxen_gb_get_gb2_mask(config_word)    \
 263         _netxen_crb_get_bit((config_word), 4)
 264 #define netxen_gb_get_gb3_mask(config_word)    \
 265         _netxen_crb_get_bit((config_word), 6)
 266
 267 #define netxen_gb_unset_gb0_mask(config_word)  \
 268         ((config_word) &= ~(1 << 0))
 269 #define netxen_gb_unset_gb1_mask(config_word)  \
 270         ((config_word) &= ~(1 << 2))
 271 #define netxen_gb_unset_gb2_mask(config_word)  \
 272         ((config_word) &= ~(1 << 4))
 273 #define netxen_gb_unset_gb3_mask(config_word)  \
 274         ((config_word) &= ~(1 << 6))
 275
 276
 277 /*
 278  * PHY-Specific MII control/status registers.
 279  */
 280 typedef enum {
 281         NETXEN_NIU_GB_MII_MGMT_ADDR_CONTROL = 0,
 282         NETXEN_NIU_GB_MII_MGMT_ADDR_STATUS = 1,
 283         NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_ID_0 = 2,
 284         NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_ID_1 = 3,
 285         NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG = 4,
 286         NETXEN_NIU_GB_MII_MGMT_ADDR_LNKPART = 5,
 287         NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG_MORE = 6,
 288         NETXEN_NIU_GB_MII_MGMT_ADDR_NEXTPAGE_XMIT = 7,
 289         NETXEN_NIU_GB_MII_MGMT_ADDR_LNKPART_NEXTPAGE = 8,
 290         NETXEN_NIU_GB_MII_MGMT_ADDR_1000BT_CONTROL = 9,
 291         NETXEN_NIU_GB_MII_MGMT_ADDR_1000BT_STATUS = 10,
 292         NETXEN_NIU_GB_MII_MGMT_ADDR_EXTENDED_STATUS = 15,
 293         NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_CONTROL = 16,
 294         NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS = 17,
 295         NETXEN_NIU_GB_MII_MGMT_ADDR_INT_ENABLE = 18,
 296         NETXEN_NIU_GB_MII_MGMT_ADDR_INT_STATUS = 19,
 297         NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_CONTROL_MORE = 20,
 298         NETXEN_NIU_GB_MII_MGMT_ADDR_RECV_ERROR_COUNT = 21,
 299         NETXEN_NIU_GB_MII_MGMT_ADDR_LED_CONTROL = 24,
 300         NETXEN_NIU_GB_MII_MGMT_ADDR_LED_OVERRIDE = 25,
 301         NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_CONTROL_MORE_YET = 26,
 302         NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS_MORE = 27
 303 } netxen_niu_phy_register_t;
 304
 305 /*
 306  * PHY-Specific Status Register (reg 17).
 307  *
 308  * Bit 0      : jabber => 1:jabber detected, 0:not
 309  * Bit 1      : polarity => 1:polarity reversed, 0:normal
 310  * Bit 2      : recvpause => 1:receive pause enabled, 0:disabled
 311  * Bit 3      : xmitpause => 1:transmit pause enabled, 0:disabled
 312  * Bit 4      : energydetect => 1:sleep, 0:active
 313  * Bit 5      : downshift => 1:downshift, 0:no downshift
 314  * Bit 6      : crossover => 1:MDIX (crossover), 0:MDI (no crossover)
 315  * Bits 7-9   : cablelen => not valid in 10Mb/s mode
 316  *                      0:<50m, 1:50-80m, 2:80-110m, 3:110-140m, 4:>140m
 317  * Bit 10     : link => 1:link up, 0:link down
 318  * Bit 11     : resolved => 1:speed and duplex resolved, 0:not yet
 319  * Bit 12     : pagercvd => 1:page received, 0:page not received
 320  * Bit 13     : duplex => 1:full duplex, 0:half duplex
 321  * Bits 14-15 : speed => 0:10Mb/s, 1:100Mb/s, 2:1000Mb/s, 3:rsvd
 322  */
 323
 324 #define netxen_get_phy_cablelen(config_word) (((config_word) >> 7) & 0x07)
 325 #define netxen_get_phy_speed(config_word) (((config_word) >> 14) & 0x03)
 326
 327 #define netxen_set_phy_speed(config_word, val)  \
 328                 ((config_word) |= ((val & 0x03) << 14))
 329 #define netxen_set_phy_duplex(config_word)      \
 330                 ((config_word) |= 1 << 13)
 331 #define netxen_clear_phy_duplex(config_word)    \
 332                 ((config_word) &= ~(1 << 13))
 333
 334 #define netxen_get_phy_jabber(config_word)      \
 335                 _netxen_crb_get_bit(config_word, 0)
 336 #define netxen_get_phy_polarity(config_word)    \
 337                 _netxen_crb_get_bit(config_word, 1)
 338 #define netxen_get_phy_recvpause(config_word)   \
 339                 _netxen_crb_get_bit(config_word, 2)
 340 #define netxen_get_phy_xmitpause(config_word)   \
 341                 _netxen_crb_get_bit(config_word, 3)
 342 #define netxen_get_phy_energydetect(config_word) \
 343                 _netxen_crb_get_bit(config_word, 4)
 344 #define netxen_get_phy_downshift(config_word)   \
 345                 _netxen_crb_get_bit(config_word, 5)
 346 #define netxen_get_phy_crossover(config_word)   \
 347                 _netxen_crb_get_bit(config_word, 6)
 348 #define netxen_get_phy_link(config_word)        \
 349                 _netxen_crb_get_bit(config_word, 10)
 350 #define netxen_get_phy_resolved(config_word)    \
 351                 _netxen_crb_get_bit(config_word, 11)
 352 #define netxen_get_phy_pagercvd(config_word)    \
 353                 _netxen_crb_get_bit(config_word, 12)
 354 #define netxen_get_phy_duplex(config_word)      \
 355                 _netxen_crb_get_bit(config_word, 13)
 356
 357 /*
 358  * Interrupt Register definition
 359  * This definition applies to registers 18 and 19 (int enable and int status).
 360  * Bit 0 : jabber
 361  * Bit 1 : polarity_changed
 362  * Bit 4 : energy_detect
 363  * Bit 5 : downshift
 364  * Bit 6 : mdi_xover_changed
 365  * Bit 7 : fifo_over_underflow
 366  * Bit 8 : false_carrier
 367  * Bit 9 : symbol_error
 368  * Bit 10: link_status_changed
 369  * Bit 11: autoneg_completed
 370  * Bit 12: page_received
 371  * Bit 13: duplex_changed
 372  * Bit 14: speed_changed
 373  * Bit 15: autoneg_error
 374  */
 375
 376 #define netxen_get_phy_int_jabber(config_word)  \
 377                 _netxen_crb_get_bit(config_word, 0)
 378 #define netxen_get_phy_int_polarity_changed(config_word)        \
 379                 _netxen_crb_get_bit(config_word, 1)
 380 #define netxen_get_phy_int_energy_detect(config_word)   \
 381                 _netxen_crb_get_bit(config_word, 4)
 382 #define netxen_get_phy_int_downshift(config_word)       \
 383                 _netxen_crb_get_bit(config_word, 5)
 384 #define netxen_get_phy_int_mdi_xover_changed(config_word)       \
 385                 _netxen_crb_get_bit(config_word, 6)
 386 #define netxen_get_phy_int_fifo_over_underflow(config_word)     \
 387                 _netxen_crb_get_bit(config_word, 7)
 388 #define netxen_get_phy_int_false_carrier(config_word)   \
 389                 _netxen_crb_get_bit(config_word, 8)
 390 #define netxen_get_phy_int_symbol_error(config_word)    \
 391                 _netxen_crb_get_bit(config_word, 9)
 392 #define netxen_get_phy_int_link_status_changed(config_word)     \
 393                 _netxen_crb_get_bit(config_word, 10)
 394 #define netxen_get_phy_int_autoneg_completed(config_word)       \
 395                 _netxen_crb_get_bit(config_word, 11)
 396 #define netxen_get_phy_int_page_received(config_word)   \
 397                 _netxen_crb_get_bit(config_word, 12)
 398 #define netxen_get_phy_int_duplex_changed(config_word)  \
 399                 _netxen_crb_get_bit(config_word, 13)
 400 #define netxen_get_phy_int_speed_changed(config_word)   \
 401                 _netxen_crb_get_bit(config_word, 14)
 402 #define netxen_get_phy_int_autoneg_error(config_word)   \
 403                 _netxen_crb_get_bit(config_word, 15)
 404
 405 #define netxen_set_phy_int_link_status_changed(config_word)     \
 406                 ((config_word) |= 1 << 10)
 407 #define netxen_set_phy_int_autoneg_completed(config_word)       \
 408                 ((config_word) |= 1 << 11)
 409 #define netxen_set_phy_int_speed_changed(config_word)   \
 410                 ((config_word) |= 1 << 14)
 411
 412 /*
 413  * NIU Mode Register.
 414  * Bit 0 : enable FibreChannel
 415  * Bit 1 : enable 10/100/1000 Ethernet
 416  * Bit 2 : enable 10Gb Ethernet
 417  */
 418
 419 #define netxen_get_niu_enable_ge(config_word)   \
 420                 _netxen_crb_get_bit(config_word, 1)
 421
 422 #define NETXEN_NIU_NON_PROMISC_MODE     0
 423 #define NETXEN_NIU_PROMISC_MODE         1
 424 #define NETXEN_NIU_ALLMULTI_MODE        2
 425
 426 /*
 427  * NIU GB Drop CRC Register
 428  *
 429  * Bit 0 : drop_gb0 => 1:drop pkts with bad CRCs, 0:pass them on
 430  * Bit 1 : drop_gb1 => 1:drop pkts with bad CRCs, 0:pass them on
 431  * Bit 2 : drop_gb2 => 1:drop pkts with bad CRCs, 0:pass them on
 432  * Bit 3 : drop_gb3 => 1:drop pkts with bad CRCs, 0:pass them on
 433  */
 434
 435 #define netxen_set_gb_drop_gb0(config_word)     \
 436                 ((config_word) |= 1 << 0)
 437 #define netxen_set_gb_drop_gb1(config_word)     \
 438                 ((config_word) |= 1 << 1)
 439 #define netxen_set_gb_drop_gb2(config_word)     \
 440                 ((config_word) |= 1 << 2)
 441 #define netxen_set_gb_drop_gb3(config_word)     \
 442                 ((config_word) |= 1 << 3)
 443
 444 #define netxen_clear_gb_drop_gb0(config_word)   \
 445                 ((config_word) &= ~(1 << 0))
 446 #define netxen_clear_gb_drop_gb1(config_word)   \
 447                 ((config_word) &= ~(1 << 1))
 448 #define netxen_clear_gb_drop_gb2(config_word)   \
 449                 ((config_word) &= ~(1 << 2))
 450 #define netxen_clear_gb_drop_gb3(config_word)   \
 451                 ((config_word) &= ~(1 << 3))
 452
 453 /*
 454  * NIU XG MAC Config Register
 455  *
 456  * Bit 0 : tx_enable => 1:enable frame xmit, 0:disable
 457  * Bit 2 : rx_enable => 1:enable frame recv, 0:disable
 458  * Bit 4 : soft_reset => 1:reset the MAC , 0:no-op
 459  * Bit 27: xaui_framer_reset
 460  * Bit 28: xaui_rx_reset
 461  * Bit 29: xaui_tx_reset
 462  * Bit 30: xg_ingress_afifo_reset
 463  * Bit 31: xg_egress_afifo_reset
 464  */
 465
 466 #define netxen_xg_soft_reset(config_word)       \
 467                 ((config_word) |= 1 << 4)
 468
 469 /* Set promiscuous mode for a GbE interface */
 470 int netxen_niu_set_promiscuous_mode(struct netxen_adapter *adapter,
 471                                     u32 mode);
 472 int netxen_niu_xg_set_promiscuous_mode(struct netxen_adapter *adapter,
 473                                        u32 mode);
 474
 475 /* set the MAC address for a given MAC */
 476 int netxen_niu_macaddr_set(struct netxen_adapter *adapter,
 477                            netxen_ethernet_macaddr_t addr);
 478
 479 /* XG version */
 480 int netxen_niu_xg_macaddr_set(struct netxen_adapter *adapter,
 481                               netxen_ethernet_macaddr_t addr);
 482
 483 /* Generic enable for GbE ports. Will detect the speed of the link. */
 484 int netxen_niu_gbe_init_port(struct netxen_adapter *adapter, int port);
 485
 486 int netxen_niu_xg_init_port(struct netxen_adapter *adapter, int port);
 487
 488 /* Disable a GbE interface */
 489 int netxen_niu_disable_gbe_port(struct netxen_adapter *adapter);
 490
 491 int netxen_niu_disable_xg_port(struct netxen_adapter *adapter);
 492
 493 typedef struct {
 494         unsigned valid;
 495         unsigned start_128M;
 496         unsigned end_128M;
 497         unsigned start_2M;
 498 } crb_128M_2M_sub_block_map_t;
 499
 500 typedef struct {
 501         crb_128M_2M_sub_block_map_t sub_block[16];
 502 } crb_128M_2M_block_map_t;
 503
 504 #endif                          /* __NETXEN_NIC_HW_H_ */