2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23 Abstract: rt61pci device specific routines.
24 Supported chipsets: RT2561, RT2561s, RT2661.
27 #include <linux/crc-itu-t.h>
28 #include <linux/delay.h>
29 #include <linux/etherdevice.h>
30 #include <linux/init.h>
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/pci.h>
34 #include <linux/eeprom_93cx6.h>
37 #include "rt2x00pci.h"
42 * BBP and RF register require indirect register access,
43 * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
44 * These indirect registers work with busy bits,
45 * and we will try maximal REGISTER_BUSY_COUNT times to access
46 * the register while taking a REGISTER_BUSY_DELAY us delay
47 * between each attampt. When the busy bit is still set at that time,
48 * the access attempt is considered to have failed,
49 * and we will print an error.
51 static u32
rt61pci_bbp_check(struct rt2x00_dev
*rt2x00dev
)
56 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
57 rt2x00pci_register_read(rt2x00dev
, PHY_CSR3
, ®
);
58 if (!rt2x00_get_field32(reg
, PHY_CSR3_BUSY
))
60 udelay(REGISTER_BUSY_DELAY
);
66 static void rt61pci_bbp_write(struct rt2x00_dev
*rt2x00dev
,
67 const unsigned int word
, const u8 value
)
72 * Wait until the BBP becomes ready.
74 reg
= rt61pci_bbp_check(rt2x00dev
);
75 if (rt2x00_get_field32(reg
, PHY_CSR3_BUSY
)) {
76 ERROR(rt2x00dev
, "PHY_CSR3 register busy. Write failed.\n");
81 * Write the data into the BBP.
84 rt2x00_set_field32(®
, PHY_CSR3_VALUE
, value
);
85 rt2x00_set_field32(®
, PHY_CSR3_REGNUM
, word
);
86 rt2x00_set_field32(®
, PHY_CSR3_BUSY
, 1);
87 rt2x00_set_field32(®
, PHY_CSR3_READ_CONTROL
, 0);
89 rt2x00pci_register_write(rt2x00dev
, PHY_CSR3
, reg
);
92 static void rt61pci_bbp_read(struct rt2x00_dev
*rt2x00dev
,
93 const unsigned int word
, u8
*value
)
98 * Wait until the BBP becomes ready.
100 reg
= rt61pci_bbp_check(rt2x00dev
);
101 if (rt2x00_get_field32(reg
, PHY_CSR3_BUSY
)) {
102 ERROR(rt2x00dev
, "PHY_CSR3 register busy. Read failed.\n");
107 * Write the request into the BBP.
110 rt2x00_set_field32(®
, PHY_CSR3_REGNUM
, word
);
111 rt2x00_set_field32(®
, PHY_CSR3_BUSY
, 1);
112 rt2x00_set_field32(®
, PHY_CSR3_READ_CONTROL
, 1);
114 rt2x00pci_register_write(rt2x00dev
, PHY_CSR3
, reg
);
117 * Wait until the BBP becomes ready.
119 reg
= rt61pci_bbp_check(rt2x00dev
);
120 if (rt2x00_get_field32(reg
, PHY_CSR3_BUSY
)) {
121 ERROR(rt2x00dev
, "PHY_CSR3 register busy. Read failed.\n");
126 *value
= rt2x00_get_field32(reg
, PHY_CSR3_VALUE
);
129 static void rt61pci_rf_write(struct rt2x00_dev
*rt2x00dev
,
130 const unsigned int word
, const u32 value
)
138 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
139 rt2x00pci_register_read(rt2x00dev
, PHY_CSR4
, ®
);
140 if (!rt2x00_get_field32(reg
, PHY_CSR4_BUSY
))
142 udelay(REGISTER_BUSY_DELAY
);
145 ERROR(rt2x00dev
, "PHY_CSR4 register busy. Write failed.\n");
150 rt2x00_set_field32(®
, PHY_CSR4_VALUE
, value
);
151 rt2x00_set_field32(®
, PHY_CSR4_NUMBER_OF_BITS
, 21);
152 rt2x00_set_field32(®
, PHY_CSR4_IF_SELECT
, 0);
153 rt2x00_set_field32(®
, PHY_CSR4_BUSY
, 1);
155 rt2x00pci_register_write(rt2x00dev
, PHY_CSR4
, reg
);
156 rt2x00_rf_write(rt2x00dev
, word
, value
);
159 #ifdef CONFIG_RT61PCI_LEDS
161 * This function is only called from rt61pci_led_brightness()
162 * make gcc happy by placing this function inside the
163 * same ifdef statement as the caller.
165 static void rt61pci_mcu_request(struct rt2x00_dev
*rt2x00dev
,
166 const u8 command
, const u8 token
,
167 const u8 arg0
, const u8 arg1
)
171 rt2x00pci_register_read(rt2x00dev
, H2M_MAILBOX_CSR
, ®
);
173 if (rt2x00_get_field32(reg
, H2M_MAILBOX_CSR_OWNER
)) {
174 ERROR(rt2x00dev
, "mcu request error. "
175 "Request 0x%02x failed for token 0x%02x.\n",
180 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_OWNER
, 1);
181 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_CMD_TOKEN
, token
);
182 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_ARG0
, arg0
);
183 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_ARG1
, arg1
);
184 rt2x00pci_register_write(rt2x00dev
, H2M_MAILBOX_CSR
, reg
);
186 rt2x00pci_register_read(rt2x00dev
, HOST_CMD_CSR
, ®
);
187 rt2x00_set_field32(®
, HOST_CMD_CSR_HOST_COMMAND
, command
);
188 rt2x00_set_field32(®
, HOST_CMD_CSR_INTERRUPT_MCU
, 1);
189 rt2x00pci_register_write(rt2x00dev
, HOST_CMD_CSR
, reg
);
191 #endif /* CONFIG_RT61PCI_LEDS */
193 static void rt61pci_eepromregister_read(struct eeprom_93cx6
*eeprom
)
195 struct rt2x00_dev
*rt2x00dev
= eeprom
->data
;
198 rt2x00pci_register_read(rt2x00dev
, E2PROM_CSR
, ®
);
200 eeprom
->reg_data_in
= !!rt2x00_get_field32(reg
, E2PROM_CSR_DATA_IN
);
201 eeprom
->reg_data_out
= !!rt2x00_get_field32(reg
, E2PROM_CSR_DATA_OUT
);
202 eeprom
->reg_data_clock
=
203 !!rt2x00_get_field32(reg
, E2PROM_CSR_DATA_CLOCK
);
204 eeprom
->reg_chip_select
=
205 !!rt2x00_get_field32(reg
, E2PROM_CSR_CHIP_SELECT
);
208 static void rt61pci_eepromregister_write(struct eeprom_93cx6
*eeprom
)
210 struct rt2x00_dev
*rt2x00dev
= eeprom
->data
;
213 rt2x00_set_field32(®
, E2PROM_CSR_DATA_IN
, !!eeprom
->reg_data_in
);
214 rt2x00_set_field32(®
, E2PROM_CSR_DATA_OUT
, !!eeprom
->reg_data_out
);
215 rt2x00_set_field32(®
, E2PROM_CSR_DATA_CLOCK
,
216 !!eeprom
->reg_data_clock
);
217 rt2x00_set_field32(®
, E2PROM_CSR_CHIP_SELECT
,
218 !!eeprom
->reg_chip_select
);
220 rt2x00pci_register_write(rt2x00dev
, E2PROM_CSR
, reg
);
223 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
224 #define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
226 static void rt61pci_read_csr(struct rt2x00_dev
*rt2x00dev
,
227 const unsigned int word
, u32
*data
)
229 rt2x00pci_register_read(rt2x00dev
, CSR_OFFSET(word
), data
);
232 static void rt61pci_write_csr(struct rt2x00_dev
*rt2x00dev
,
233 const unsigned int word
, u32 data
)
235 rt2x00pci_register_write(rt2x00dev
, CSR_OFFSET(word
), data
);
238 static const struct rt2x00debug rt61pci_rt2x00debug
= {
239 .owner
= THIS_MODULE
,
241 .read
= rt61pci_read_csr
,
242 .write
= rt61pci_write_csr
,
243 .word_size
= sizeof(u32
),
244 .word_count
= CSR_REG_SIZE
/ sizeof(u32
),
247 .read
= rt2x00_eeprom_read
,
248 .write
= rt2x00_eeprom_write
,
249 .word_size
= sizeof(u16
),
250 .word_count
= EEPROM_SIZE
/ sizeof(u16
),
253 .read
= rt61pci_bbp_read
,
254 .write
= rt61pci_bbp_write
,
255 .word_size
= sizeof(u8
),
256 .word_count
= BBP_SIZE
/ sizeof(u8
),
259 .read
= rt2x00_rf_read
,
260 .write
= rt61pci_rf_write
,
261 .word_size
= sizeof(u32
),
262 .word_count
= RF_SIZE
/ sizeof(u32
),
265 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
267 #ifdef CONFIG_RT61PCI_RFKILL
268 static int rt61pci_rfkill_poll(struct rt2x00_dev
*rt2x00dev
)
272 rt2x00pci_register_read(rt2x00dev
, MAC_CSR13
, ®
);
273 return rt2x00_get_field32(reg
, MAC_CSR13_BIT5
);
276 #define rt61pci_rfkill_poll NULL
277 #endif /* CONFIG_RT61PCI_RFKILL */
279 #ifdef CONFIG_RT61PCI_LEDS
280 static void rt61pci_brightness_set(struct led_classdev
*led_cdev
,
281 enum led_brightness brightness
)
283 struct rt2x00_led
*led
=
284 container_of(led_cdev
, struct rt2x00_led
, led_dev
);
285 unsigned int enabled
= brightness
!= LED_OFF
;
286 unsigned int a_mode
=
287 (enabled
&& led
->rt2x00dev
->curr_band
== IEEE80211_BAND_5GHZ
);
288 unsigned int bg_mode
=
289 (enabled
&& led
->rt2x00dev
->curr_band
== IEEE80211_BAND_2GHZ
);
291 if (led
->type
== LED_TYPE_RADIO
) {
292 rt2x00_set_field16(&led
->rt2x00dev
->led_mcu_reg
,
293 MCU_LEDCS_RADIO_STATUS
, enabled
);
295 rt61pci_mcu_request(led
->rt2x00dev
, MCU_LED
, 0xff,
296 (led
->rt2x00dev
->led_mcu_reg
& 0xff),
297 ((led
->rt2x00dev
->led_mcu_reg
>> 8)));
298 } else if (led
->type
== LED_TYPE_ASSOC
) {
299 rt2x00_set_field16(&led
->rt2x00dev
->led_mcu_reg
,
300 MCU_LEDCS_LINK_BG_STATUS
, bg_mode
);
301 rt2x00_set_field16(&led
->rt2x00dev
->led_mcu_reg
,
302 MCU_LEDCS_LINK_A_STATUS
, a_mode
);
304 rt61pci_mcu_request(led
->rt2x00dev
, MCU_LED
, 0xff,
305 (led
->rt2x00dev
->led_mcu_reg
& 0xff),
306 ((led
->rt2x00dev
->led_mcu_reg
>> 8)));
307 } else if (led
->type
== LED_TYPE_QUALITY
) {
309 * The brightness is divided into 6 levels (0 - 5),
310 * this means we need to convert the brightness
311 * argument into the matching level within that range.
313 rt61pci_mcu_request(led
->rt2x00dev
, MCU_LED_STRENGTH
, 0xff,
314 brightness
/ (LED_FULL
/ 6), 0);
318 static int rt61pci_blink_set(struct led_classdev
*led_cdev
,
319 unsigned long *delay_on
,
320 unsigned long *delay_off
)
322 struct rt2x00_led
*led
=
323 container_of(led_cdev
, struct rt2x00_led
, led_dev
);
326 rt2x00pci_register_read(led
->rt2x00dev
, MAC_CSR14
, ®
);
327 rt2x00_set_field32(®
, MAC_CSR14_ON_PERIOD
, *delay_on
);
328 rt2x00_set_field32(®
, MAC_CSR14_OFF_PERIOD
, *delay_off
);
329 rt2x00pci_register_write(led
->rt2x00dev
, MAC_CSR14
, reg
);
334 static void rt61pci_init_led(struct rt2x00_dev
*rt2x00dev
,
335 struct rt2x00_led
*led
,
338 led
->rt2x00dev
= rt2x00dev
;
340 led
->led_dev
.brightness_set
= rt61pci_brightness_set
;
341 led
->led_dev
.blink_set
= rt61pci_blink_set
;
342 led
->flags
= LED_INITIALIZED
;
344 #endif /* CONFIG_RT61PCI_LEDS */
347 * Configuration handlers.
349 static void rt61pci_config_filter(struct rt2x00_dev
*rt2x00dev
,
350 const unsigned int filter_flags
)
355 * Start configuration steps.
356 * Note that the version error will always be dropped
357 * and broadcast frames will always be accepted since
358 * there is no filter for it at this time.
360 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR0
, ®
);
361 rt2x00_set_field32(®
, TXRX_CSR0_DROP_CRC
,
362 !(filter_flags
& FIF_FCSFAIL
));
363 rt2x00_set_field32(®
, TXRX_CSR0_DROP_PHYSICAL
,
364 !(filter_flags
& FIF_PLCPFAIL
));
365 rt2x00_set_field32(®
, TXRX_CSR0_DROP_CONTROL
,
366 !(filter_flags
& FIF_CONTROL
));
367 rt2x00_set_field32(®
, TXRX_CSR0_DROP_NOT_TO_ME
,
368 !(filter_flags
& FIF_PROMISC_IN_BSS
));
369 rt2x00_set_field32(®
, TXRX_CSR0_DROP_TO_DS
,
370 !(filter_flags
& FIF_PROMISC_IN_BSS
) &&
371 !rt2x00dev
->intf_ap_count
);
372 rt2x00_set_field32(®
, TXRX_CSR0_DROP_VERSION_ERROR
, 1);
373 rt2x00_set_field32(®
, TXRX_CSR0_DROP_MULTICAST
,
374 !(filter_flags
& FIF_ALLMULTI
));
375 rt2x00_set_field32(®
, TXRX_CSR0_DROP_BROADCAST
, 0);
376 rt2x00_set_field32(®
, TXRX_CSR0_DROP_ACK_CTS
,
377 !(filter_flags
& FIF_CONTROL
));
378 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR0
, reg
);
381 static void rt61pci_config_intf(struct rt2x00_dev
*rt2x00dev
,
382 struct rt2x00_intf
*intf
,
383 struct rt2x00intf_conf
*conf
,
384 const unsigned int flags
)
386 unsigned int beacon_base
;
389 if (flags
& CONFIG_UPDATE_TYPE
) {
391 * Clear current synchronisation setup.
392 * For the Beacon base registers we only need to clear
393 * the first byte since that byte contains the VALID and OWNER
394 * bits which (when set to 0) will invalidate the entire beacon.
396 beacon_base
= HW_BEACON_OFFSET(intf
->beacon
->entry_idx
);
397 rt2x00pci_register_write(rt2x00dev
, beacon_base
, 0);
400 * Enable synchronisation.
402 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR9
, ®
);
403 rt2x00_set_field32(®
, TXRX_CSR9_TSF_TICKING
, 1);
404 rt2x00_set_field32(®
, TXRX_CSR9_TSF_SYNC
, conf
->sync
);
405 rt2x00_set_field32(®
, TXRX_CSR9_TBTT_ENABLE
, 1);
406 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR9
, reg
);
409 if (flags
& CONFIG_UPDATE_MAC
) {
410 reg
= le32_to_cpu(conf
->mac
[1]);
411 rt2x00_set_field32(®
, MAC_CSR3_UNICAST_TO_ME_MASK
, 0xff);
412 conf
->mac
[1] = cpu_to_le32(reg
);
414 rt2x00pci_register_multiwrite(rt2x00dev
, MAC_CSR2
,
415 conf
->mac
, sizeof(conf
->mac
));
418 if (flags
& CONFIG_UPDATE_BSSID
) {
419 reg
= le32_to_cpu(conf
->bssid
[1]);
420 rt2x00_set_field32(®
, MAC_CSR5_BSS_ID_MASK
, 3);
421 conf
->bssid
[1] = cpu_to_le32(reg
);
423 rt2x00pci_register_multiwrite(rt2x00dev
, MAC_CSR4
,
424 conf
->bssid
, sizeof(conf
->bssid
));
428 static void rt61pci_config_erp(struct rt2x00_dev
*rt2x00dev
,
429 struct rt2x00lib_erp
*erp
)
433 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR0
, ®
);
434 rt2x00_set_field32(®
, TXRX_CSR0_RX_ACK_TIMEOUT
, erp
->ack_timeout
);
435 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR0
, reg
);
437 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR4
, ®
);
438 rt2x00_set_field32(®
, TXRX_CSR4_AUTORESPOND_PREAMBLE
,
439 !!erp
->short_preamble
);
440 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR4
, reg
);
443 static void rt61pci_config_phymode(struct rt2x00_dev
*rt2x00dev
,
444 const int basic_rate_mask
)
446 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR5
, basic_rate_mask
);
449 static void rt61pci_config_channel(struct rt2x00_dev
*rt2x00dev
,
450 struct rf_channel
*rf
, const int txpower
)
456 rt2x00_set_field32(&rf
->rf3
, RF3_TXPOWER
, TXPOWER_TO_DEV(txpower
));
457 rt2x00_set_field32(&rf
->rf4
, RF4_FREQ_OFFSET
, rt2x00dev
->freq_offset
);
459 smart
= !(rt2x00_rf(&rt2x00dev
->chip
, RF5225
) ||
460 rt2x00_rf(&rt2x00dev
->chip
, RF2527
));
462 rt61pci_bbp_read(rt2x00dev
, 3, &r3
);
463 rt2x00_set_field8(&r3
, BBP_R3_SMART_MODE
, smart
);
464 rt61pci_bbp_write(rt2x00dev
, 3, r3
);
467 if (txpower
> MAX_TXPOWER
&& txpower
<= (MAX_TXPOWER
+ r94
))
468 r94
+= txpower
- MAX_TXPOWER
;
469 else if (txpower
< MIN_TXPOWER
&& txpower
>= (MIN_TXPOWER
- r94
))
471 rt61pci_bbp_write(rt2x00dev
, 94, r94
);
473 rt61pci_rf_write(rt2x00dev
, 1, rf
->rf1
);
474 rt61pci_rf_write(rt2x00dev
, 2, rf
->rf2
);
475 rt61pci_rf_write(rt2x00dev
, 3, rf
->rf3
& ~0x00000004);
476 rt61pci_rf_write(rt2x00dev
, 4, rf
->rf4
);
480 rt61pci_rf_write(rt2x00dev
, 1, rf
->rf1
);
481 rt61pci_rf_write(rt2x00dev
, 2, rf
->rf2
);
482 rt61pci_rf_write(rt2x00dev
, 3, rf
->rf3
| 0x00000004);
483 rt61pci_rf_write(rt2x00dev
, 4, rf
->rf4
);
487 rt61pci_rf_write(rt2x00dev
, 1, rf
->rf1
);
488 rt61pci_rf_write(rt2x00dev
, 2, rf
->rf2
);
489 rt61pci_rf_write(rt2x00dev
, 3, rf
->rf3
& ~0x00000004);
490 rt61pci_rf_write(rt2x00dev
, 4, rf
->rf4
);
495 static void rt61pci_config_txpower(struct rt2x00_dev
*rt2x00dev
,
498 struct rf_channel rf
;
500 rt2x00_rf_read(rt2x00dev
, 1, &rf
.rf1
);
501 rt2x00_rf_read(rt2x00dev
, 2, &rf
.rf2
);
502 rt2x00_rf_read(rt2x00dev
, 3, &rf
.rf3
);
503 rt2x00_rf_read(rt2x00dev
, 4, &rf
.rf4
);
505 rt61pci_config_channel(rt2x00dev
, &rf
, txpower
);
508 static void rt61pci_config_antenna_5x(struct rt2x00_dev
*rt2x00dev
,
509 struct antenna_setup
*ant
)
515 rt61pci_bbp_read(rt2x00dev
, 3, &r3
);
516 rt61pci_bbp_read(rt2x00dev
, 4, &r4
);
517 rt61pci_bbp_read(rt2x00dev
, 77, &r77
);
519 rt2x00_set_field8(&r3
, BBP_R3_SMART_MODE
,
520 rt2x00_rf(&rt2x00dev
->chip
, RF5325
));
523 * Configure the RX antenna.
526 case ANTENNA_HW_DIVERSITY
:
527 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA_CONTROL
, 2);
528 rt2x00_set_field8(&r4
, BBP_R4_RX_FRAME_END
,
529 (rt2x00dev
->curr_band
!= IEEE80211_BAND_5GHZ
));
532 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA_CONTROL
, 1);
533 rt2x00_set_field8(&r4
, BBP_R4_RX_FRAME_END
, 0);
534 if (rt2x00dev
->curr_band
== IEEE80211_BAND_5GHZ
)
535 rt2x00_set_field8(&r77
, BBP_R77_RX_ANTENNA
, 0);
537 rt2x00_set_field8(&r77
, BBP_R77_RX_ANTENNA
, 3);
541 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA_CONTROL
, 1);
542 rt2x00_set_field8(&r4
, BBP_R4_RX_FRAME_END
, 0);
543 if (rt2x00dev
->curr_band
== IEEE80211_BAND_5GHZ
)
544 rt2x00_set_field8(&r77
, BBP_R77_RX_ANTENNA
, 3);
546 rt2x00_set_field8(&r77
, BBP_R77_RX_ANTENNA
, 0);
550 rt61pci_bbp_write(rt2x00dev
, 77, r77
);
551 rt61pci_bbp_write(rt2x00dev
, 3, r3
);
552 rt61pci_bbp_write(rt2x00dev
, 4, r4
);
555 static void rt61pci_config_antenna_2x(struct rt2x00_dev
*rt2x00dev
,
556 struct antenna_setup
*ant
)
562 rt61pci_bbp_read(rt2x00dev
, 3, &r3
);
563 rt61pci_bbp_read(rt2x00dev
, 4, &r4
);
564 rt61pci_bbp_read(rt2x00dev
, 77, &r77
);
566 rt2x00_set_field8(&r3
, BBP_R3_SMART_MODE
,
567 rt2x00_rf(&rt2x00dev
->chip
, RF2529
));
568 rt2x00_set_field8(&r4
, BBP_R4_RX_FRAME_END
,
569 !test_bit(CONFIG_FRAME_TYPE
, &rt2x00dev
->flags
));
572 * Configure the RX antenna.
575 case ANTENNA_HW_DIVERSITY
:
576 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA_CONTROL
, 2);
579 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA_CONTROL
, 1);
580 rt2x00_set_field8(&r77
, BBP_R77_RX_ANTENNA
, 3);
584 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA_CONTROL
, 1);
585 rt2x00_set_field8(&r77
, BBP_R77_RX_ANTENNA
, 0);
589 rt61pci_bbp_write(rt2x00dev
, 77, r77
);
590 rt61pci_bbp_write(rt2x00dev
, 3, r3
);
591 rt61pci_bbp_write(rt2x00dev
, 4, r4
);
594 static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev
*rt2x00dev
,
595 const int p1
, const int p2
)
599 rt2x00pci_register_read(rt2x00dev
, MAC_CSR13
, ®
);
601 rt2x00_set_field32(®
, MAC_CSR13_BIT4
, p1
);
602 rt2x00_set_field32(®
, MAC_CSR13_BIT12
, 0);
604 rt2x00_set_field32(®
, MAC_CSR13_BIT3
, !p2
);
605 rt2x00_set_field32(®
, MAC_CSR13_BIT11
, 0);
607 rt2x00pci_register_write(rt2x00dev
, MAC_CSR13
, reg
);
610 static void rt61pci_config_antenna_2529(struct rt2x00_dev
*rt2x00dev
,
611 struct antenna_setup
*ant
)
617 rt61pci_bbp_read(rt2x00dev
, 3, &r3
);
618 rt61pci_bbp_read(rt2x00dev
, 4, &r4
);
619 rt61pci_bbp_read(rt2x00dev
, 77, &r77
);
622 * Configure the RX antenna.
626 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA_CONTROL
, 1);
627 rt2x00_set_field8(&r77
, BBP_R77_RX_ANTENNA
, 0);
628 rt61pci_config_antenna_2529_rx(rt2x00dev
, 0, 0);
630 case ANTENNA_HW_DIVERSITY
:
632 * FIXME: Antenna selection for the rf 2529 is very confusing
633 * in the legacy driver. Just default to antenna B until the
634 * legacy code can be properly translated into rt2x00 code.
638 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA_CONTROL
, 1);
639 rt2x00_set_field8(&r77
, BBP_R77_RX_ANTENNA
, 3);
640 rt61pci_config_antenna_2529_rx(rt2x00dev
, 1, 1);
644 rt61pci_bbp_write(rt2x00dev
, 77, r77
);
645 rt61pci_bbp_write(rt2x00dev
, 3, r3
);
646 rt61pci_bbp_write(rt2x00dev
, 4, r4
);
652 * value[0] -> non-LNA
658 static const struct antenna_sel antenna_sel_a
[] = {
659 { 96, { 0x58, 0x78 } },
660 { 104, { 0x38, 0x48 } },
661 { 75, { 0xfe, 0x80 } },
662 { 86, { 0xfe, 0x80 } },
663 { 88, { 0xfe, 0x80 } },
664 { 35, { 0x60, 0x60 } },
665 { 97, { 0x58, 0x58 } },
666 { 98, { 0x58, 0x58 } },
669 static const struct antenna_sel antenna_sel_bg
[] = {
670 { 96, { 0x48, 0x68 } },
671 { 104, { 0x2c, 0x3c } },
672 { 75, { 0xfe, 0x80 } },
673 { 86, { 0xfe, 0x80 } },
674 { 88, { 0xfe, 0x80 } },
675 { 35, { 0x50, 0x50 } },
676 { 97, { 0x48, 0x48 } },
677 { 98, { 0x48, 0x48 } },
680 static void rt61pci_config_antenna(struct rt2x00_dev
*rt2x00dev
,
681 struct antenna_setup
*ant
)
683 const struct antenna_sel
*sel
;
689 * We should never come here because rt2x00lib is supposed
690 * to catch this and send us the correct antenna explicitely.
692 BUG_ON(ant
->rx
== ANTENNA_SW_DIVERSITY
||
693 ant
->tx
== ANTENNA_SW_DIVERSITY
);
695 if (rt2x00dev
->curr_band
== IEEE80211_BAND_5GHZ
) {
697 lna
= test_bit(CONFIG_EXTERNAL_LNA_A
, &rt2x00dev
->flags
);
699 sel
= antenna_sel_bg
;
700 lna
= test_bit(CONFIG_EXTERNAL_LNA_BG
, &rt2x00dev
->flags
);
703 for (i
= 0; i
< ARRAY_SIZE(antenna_sel_a
); i
++)
704 rt61pci_bbp_write(rt2x00dev
, sel
[i
].word
, sel
[i
].value
[lna
]);
706 rt2x00pci_register_read(rt2x00dev
, PHY_CSR0
, ®
);
708 rt2x00_set_field32(®
, PHY_CSR0_PA_PE_BG
,
709 rt2x00dev
->curr_band
== IEEE80211_BAND_2GHZ
);
710 rt2x00_set_field32(®
, PHY_CSR0_PA_PE_A
,
711 rt2x00dev
->curr_band
== IEEE80211_BAND_5GHZ
);
713 rt2x00pci_register_write(rt2x00dev
, PHY_CSR0
, reg
);
715 if (rt2x00_rf(&rt2x00dev
->chip
, RF5225
) ||
716 rt2x00_rf(&rt2x00dev
->chip
, RF5325
))
717 rt61pci_config_antenna_5x(rt2x00dev
, ant
);
718 else if (rt2x00_rf(&rt2x00dev
->chip
, RF2527
))
719 rt61pci_config_antenna_2x(rt2x00dev
, ant
);
720 else if (rt2x00_rf(&rt2x00dev
->chip
, RF2529
)) {
721 if (test_bit(CONFIG_DOUBLE_ANTENNA
, &rt2x00dev
->flags
))
722 rt61pci_config_antenna_2x(rt2x00dev
, ant
);
724 rt61pci_config_antenna_2529(rt2x00dev
, ant
);
728 static void rt61pci_config_duration(struct rt2x00_dev
*rt2x00dev
,
729 struct rt2x00lib_conf
*libconf
)
733 rt2x00pci_register_read(rt2x00dev
, MAC_CSR9
, ®
);
734 rt2x00_set_field32(®
, MAC_CSR9_SLOT_TIME
, libconf
->slot_time
);
735 rt2x00pci_register_write(rt2x00dev
, MAC_CSR9
, reg
);
737 rt2x00pci_register_read(rt2x00dev
, MAC_CSR8
, ®
);
738 rt2x00_set_field32(®
, MAC_CSR8_SIFS
, libconf
->sifs
);
739 rt2x00_set_field32(®
, MAC_CSR8_SIFS_AFTER_RX_OFDM
, 3);
740 rt2x00_set_field32(®
, MAC_CSR8_EIFS
, libconf
->eifs
);
741 rt2x00pci_register_write(rt2x00dev
, MAC_CSR8
, reg
);
743 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR0
, ®
);
744 rt2x00_set_field32(®
, TXRX_CSR0_TSF_OFFSET
, IEEE80211_HEADER
);
745 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR0
, reg
);
747 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR4
, ®
);
748 rt2x00_set_field32(®
, TXRX_CSR4_AUTORESPOND_ENABLE
, 1);
749 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR4
, reg
);
751 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR9
, ®
);
752 rt2x00_set_field32(®
, TXRX_CSR9_BEACON_INTERVAL
,
753 libconf
->conf
->beacon_int
* 16);
754 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR9
, reg
);
757 static void rt61pci_config(struct rt2x00_dev
*rt2x00dev
,
758 struct rt2x00lib_conf
*libconf
,
759 const unsigned int flags
)
761 if (flags
& CONFIG_UPDATE_PHYMODE
)
762 rt61pci_config_phymode(rt2x00dev
, libconf
->basic_rates
);
763 if (flags
& CONFIG_UPDATE_CHANNEL
)
764 rt61pci_config_channel(rt2x00dev
, &libconf
->rf
,
765 libconf
->conf
->power_level
);
766 if ((flags
& CONFIG_UPDATE_TXPOWER
) && !(flags
& CONFIG_UPDATE_CHANNEL
))
767 rt61pci_config_txpower(rt2x00dev
, libconf
->conf
->power_level
);
768 if (flags
& CONFIG_UPDATE_ANTENNA
)
769 rt61pci_config_antenna(rt2x00dev
, &libconf
->ant
);
770 if (flags
& (CONFIG_UPDATE_SLOT_TIME
| CONFIG_UPDATE_BEACON_INT
))
771 rt61pci_config_duration(rt2x00dev
, libconf
);
777 static void rt61pci_link_stats(struct rt2x00_dev
*rt2x00dev
,
778 struct link_qual
*qual
)
783 * Update FCS error count from register.
785 rt2x00pci_register_read(rt2x00dev
, STA_CSR0
, ®
);
786 qual
->rx_failed
= rt2x00_get_field32(reg
, STA_CSR0_FCS_ERROR
);
789 * Update False CCA count from register.
791 rt2x00pci_register_read(rt2x00dev
, STA_CSR1
, ®
);
792 qual
->false_cca
= rt2x00_get_field32(reg
, STA_CSR1_FALSE_CCA_ERROR
);
795 static void rt61pci_reset_tuner(struct rt2x00_dev
*rt2x00dev
)
797 rt61pci_bbp_write(rt2x00dev
, 17, 0x20);
798 rt2x00dev
->link
.vgc_level
= 0x20;
801 static void rt61pci_link_tuner(struct rt2x00_dev
*rt2x00dev
)
803 int rssi
= rt2x00_get_link_rssi(&rt2x00dev
->link
);
808 rt61pci_bbp_read(rt2x00dev
, 17, &r17
);
811 * Determine r17 bounds.
813 if (rt2x00dev
->rx_status
.band
== IEEE80211_BAND_5GHZ
) {
816 if (test_bit(CONFIG_EXTERNAL_LNA_A
, &rt2x00dev
->flags
)) {
823 if (test_bit(CONFIG_EXTERNAL_LNA_BG
, &rt2x00dev
->flags
)) {
830 * If we are not associated, we should go straight to the
831 * dynamic CCA tuning.
833 if (!rt2x00dev
->intf_associated
)
834 goto dynamic_cca_tune
;
837 * Special big-R17 for very short distance
841 rt61pci_bbp_write(rt2x00dev
, 17, 0x60);
846 * Special big-R17 for short distance
850 rt61pci_bbp_write(rt2x00dev
, 17, up_bound
);
855 * Special big-R17 for middle-short distance
859 if (r17
!= low_bound
)
860 rt61pci_bbp_write(rt2x00dev
, 17, low_bound
);
865 * Special mid-R17 for middle distance
869 if (r17
!= low_bound
)
870 rt61pci_bbp_write(rt2x00dev
, 17, low_bound
);
875 * Special case: Change up_bound based on the rssi.
876 * Lower up_bound when rssi is weaker then -74 dBm.
878 up_bound
-= 2 * (-74 - rssi
);
879 if (low_bound
> up_bound
)
880 up_bound
= low_bound
;
882 if (r17
> up_bound
) {
883 rt61pci_bbp_write(rt2x00dev
, 17, up_bound
);
890 * r17 does not yet exceed upper limit, continue and base
891 * the r17 tuning on the false CCA count.
893 if (rt2x00dev
->link
.qual
.false_cca
> 512 && r17
< up_bound
) {
894 if (++r17
> up_bound
)
896 rt61pci_bbp_write(rt2x00dev
, 17, r17
);
897 } else if (rt2x00dev
->link
.qual
.false_cca
< 100 && r17
> low_bound
) {
898 if (--r17
< low_bound
)
900 rt61pci_bbp_write(rt2x00dev
, 17, r17
);
907 static char *rt61pci_get_firmware_name(struct rt2x00_dev
*rt2x00dev
)
911 switch (rt2x00dev
->chip
.rt
) {
913 fw_name
= FIRMWARE_RT2561
;
916 fw_name
= FIRMWARE_RT2561s
;
919 fw_name
= FIRMWARE_RT2661
;
929 static u16
rt61pci_get_firmware_crc(const void *data
, const size_t len
)
934 * Use the crc itu-t algorithm.
935 * The last 2 bytes in the firmware array are the crc checksum itself,
936 * this means that we should never pass those 2 bytes to the crc
939 crc
= crc_itu_t(0, data
, len
- 2);
940 crc
= crc_itu_t_byte(crc
, 0);
941 crc
= crc_itu_t_byte(crc
, 0);
946 static int rt61pci_load_firmware(struct rt2x00_dev
*rt2x00dev
, const void *data
,
953 * Wait for stable hardware.
955 for (i
= 0; i
< 100; i
++) {
956 rt2x00pci_register_read(rt2x00dev
, MAC_CSR0
, ®
);
963 ERROR(rt2x00dev
, "Unstable hardware.\n");
968 * Prepare MCU and mailbox for firmware loading.
971 rt2x00_set_field32(®
, MCU_CNTL_CSR_RESET
, 1);
972 rt2x00pci_register_write(rt2x00dev
, MCU_CNTL_CSR
, reg
);
973 rt2x00pci_register_write(rt2x00dev
, M2H_CMD_DONE_CSR
, 0xffffffff);
974 rt2x00pci_register_write(rt2x00dev
, H2M_MAILBOX_CSR
, 0);
975 rt2x00pci_register_write(rt2x00dev
, HOST_CMD_CSR
, 0);
978 * Write firmware to device.
981 rt2x00_set_field32(®
, MCU_CNTL_CSR_RESET
, 1);
982 rt2x00_set_field32(®
, MCU_CNTL_CSR_SELECT_BANK
, 1);
983 rt2x00pci_register_write(rt2x00dev
, MCU_CNTL_CSR
, reg
);
985 rt2x00pci_register_multiwrite(rt2x00dev
, FIRMWARE_IMAGE_BASE
,
988 rt2x00_set_field32(®
, MCU_CNTL_CSR_SELECT_BANK
, 0);
989 rt2x00pci_register_write(rt2x00dev
, MCU_CNTL_CSR
, reg
);
991 rt2x00_set_field32(®
, MCU_CNTL_CSR_RESET
, 0);
992 rt2x00pci_register_write(rt2x00dev
, MCU_CNTL_CSR
, reg
);
994 for (i
= 0; i
< 100; i
++) {
995 rt2x00pci_register_read(rt2x00dev
, MCU_CNTL_CSR
, ®
);
996 if (rt2x00_get_field32(reg
, MCU_CNTL_CSR_READY
))
1002 ERROR(rt2x00dev
, "MCU Control register not ready.\n");
1007 * Reset MAC and BBP registers.
1010 rt2x00_set_field32(®
, MAC_CSR1_SOFT_RESET
, 1);
1011 rt2x00_set_field32(®
, MAC_CSR1_BBP_RESET
, 1);
1012 rt2x00pci_register_write(rt2x00dev
, MAC_CSR1
, reg
);
1014 rt2x00pci_register_read(rt2x00dev
, MAC_CSR1
, ®
);
1015 rt2x00_set_field32(®
, MAC_CSR1_SOFT_RESET
, 0);
1016 rt2x00_set_field32(®
, MAC_CSR1_BBP_RESET
, 0);
1017 rt2x00pci_register_write(rt2x00dev
, MAC_CSR1
, reg
);
1019 rt2x00pci_register_read(rt2x00dev
, MAC_CSR1
, ®
);
1020 rt2x00_set_field32(®
, MAC_CSR1_HOST_READY
, 1);
1021 rt2x00pci_register_write(rt2x00dev
, MAC_CSR1
, reg
);
1027 * Initialization functions.
1029 static void rt61pci_init_rxentry(struct rt2x00_dev
*rt2x00dev
,
1030 struct queue_entry
*entry
)
1032 struct queue_entry_priv_pci
*entry_priv
= entry
->priv_data
;
1033 struct skb_frame_desc
*skbdesc
= get_skb_frame_desc(entry
->skb
);
1036 rt2x00_desc_read(entry_priv
->desc
, 5, &word
);
1037 rt2x00_set_field32(&word
, RXD_W5_BUFFER_PHYSICAL_ADDRESS
,
1039 rt2x00_desc_write(entry_priv
->desc
, 5, word
);
1041 rt2x00_desc_read(entry_priv
->desc
, 0, &word
);
1042 rt2x00_set_field32(&word
, RXD_W0_OWNER_NIC
, 1);
1043 rt2x00_desc_write(entry_priv
->desc
, 0, word
);
1046 static void rt61pci_init_txentry(struct rt2x00_dev
*rt2x00dev
,
1047 struct queue_entry
*entry
)
1049 struct queue_entry_priv_pci
*entry_priv
= entry
->priv_data
;
1052 rt2x00_desc_read(entry_priv
->desc
, 0, &word
);
1053 rt2x00_set_field32(&word
, TXD_W0_VALID
, 0);
1054 rt2x00_set_field32(&word
, TXD_W0_OWNER_NIC
, 0);
1055 rt2x00_desc_write(entry_priv
->desc
, 0, word
);
1058 static int rt61pci_init_queues(struct rt2x00_dev
*rt2x00dev
)
1060 struct queue_entry_priv_pci
*entry_priv
;
1064 * Initialize registers.
1066 rt2x00pci_register_read(rt2x00dev
, TX_RING_CSR0
, ®
);
1067 rt2x00_set_field32(®
, TX_RING_CSR0_AC0_RING_SIZE
,
1068 rt2x00dev
->tx
[0].limit
);
1069 rt2x00_set_field32(®
, TX_RING_CSR0_AC1_RING_SIZE
,
1070 rt2x00dev
->tx
[1].limit
);
1071 rt2x00_set_field32(®
, TX_RING_CSR0_AC2_RING_SIZE
,
1072 rt2x00dev
->tx
[2].limit
);
1073 rt2x00_set_field32(®
, TX_RING_CSR0_AC3_RING_SIZE
,
1074 rt2x00dev
->tx
[3].limit
);
1075 rt2x00pci_register_write(rt2x00dev
, TX_RING_CSR0
, reg
);
1077 rt2x00pci_register_read(rt2x00dev
, TX_RING_CSR1
, ®
);
1078 rt2x00_set_field32(®
, TX_RING_CSR1_TXD_SIZE
,
1079 rt2x00dev
->tx
[0].desc_size
/ 4);
1080 rt2x00pci_register_write(rt2x00dev
, TX_RING_CSR1
, reg
);
1082 entry_priv
= rt2x00dev
->tx
[0].entries
[0].priv_data
;
1083 rt2x00pci_register_read(rt2x00dev
, AC0_BASE_CSR
, ®
);
1084 rt2x00_set_field32(®
, AC0_BASE_CSR_RING_REGISTER
,
1085 entry_priv
->desc_dma
);
1086 rt2x00pci_register_write(rt2x00dev
, AC0_BASE_CSR
, reg
);
1088 entry_priv
= rt2x00dev
->tx
[1].entries
[0].priv_data
;
1089 rt2x00pci_register_read(rt2x00dev
, AC1_BASE_CSR
, ®
);
1090 rt2x00_set_field32(®
, AC1_BASE_CSR_RING_REGISTER
,
1091 entry_priv
->desc_dma
);
1092 rt2x00pci_register_write(rt2x00dev
, AC1_BASE_CSR
, reg
);
1094 entry_priv
= rt2x00dev
->tx
[2].entries
[0].priv_data
;
1095 rt2x00pci_register_read(rt2x00dev
, AC2_BASE_CSR
, ®
);
1096 rt2x00_set_field32(®
, AC2_BASE_CSR_RING_REGISTER
,
1097 entry_priv
->desc_dma
);
1098 rt2x00pci_register_write(rt2x00dev
, AC2_BASE_CSR
, reg
);
1100 entry_priv
= rt2x00dev
->tx
[3].entries
[0].priv_data
;
1101 rt2x00pci_register_read(rt2x00dev
, AC3_BASE_CSR
, ®
);
1102 rt2x00_set_field32(®
, AC3_BASE_CSR_RING_REGISTER
,
1103 entry_priv
->desc_dma
);
1104 rt2x00pci_register_write(rt2x00dev
, AC3_BASE_CSR
, reg
);
1106 rt2x00pci_register_read(rt2x00dev
, RX_RING_CSR
, ®
);
1107 rt2x00_set_field32(®
, RX_RING_CSR_RING_SIZE
, rt2x00dev
->rx
->limit
);
1108 rt2x00_set_field32(®
, RX_RING_CSR_RXD_SIZE
,
1109 rt2x00dev
->rx
->desc_size
/ 4);
1110 rt2x00_set_field32(®
, RX_RING_CSR_RXD_WRITEBACK_SIZE
, 4);
1111 rt2x00pci_register_write(rt2x00dev
, RX_RING_CSR
, reg
);
1113 entry_priv
= rt2x00dev
->rx
->entries
[0].priv_data
;
1114 rt2x00pci_register_read(rt2x00dev
, RX_BASE_CSR
, ®
);
1115 rt2x00_set_field32(®
, RX_BASE_CSR_RING_REGISTER
,
1116 entry_priv
->desc_dma
);
1117 rt2x00pci_register_write(rt2x00dev
, RX_BASE_CSR
, reg
);
1119 rt2x00pci_register_read(rt2x00dev
, TX_DMA_DST_CSR
, ®
);
1120 rt2x00_set_field32(®
, TX_DMA_DST_CSR_DEST_AC0
, 2);
1121 rt2x00_set_field32(®
, TX_DMA_DST_CSR_DEST_AC1
, 2);
1122 rt2x00_set_field32(®
, TX_DMA_DST_CSR_DEST_AC2
, 2);
1123 rt2x00_set_field32(®
, TX_DMA_DST_CSR_DEST_AC3
, 2);
1124 rt2x00pci_register_write(rt2x00dev
, TX_DMA_DST_CSR
, reg
);
1126 rt2x00pci_register_read(rt2x00dev
, LOAD_TX_RING_CSR
, ®
);
1127 rt2x00_set_field32(®
, LOAD_TX_RING_CSR_LOAD_TXD_AC0
, 1);
1128 rt2x00_set_field32(®
, LOAD_TX_RING_CSR_LOAD_TXD_AC1
, 1);
1129 rt2x00_set_field32(®
, LOAD_TX_RING_CSR_LOAD_TXD_AC2
, 1);
1130 rt2x00_set_field32(®
, LOAD_TX_RING_CSR_LOAD_TXD_AC3
, 1);
1131 rt2x00pci_register_write(rt2x00dev
, LOAD_TX_RING_CSR
, reg
);
1133 rt2x00pci_register_read(rt2x00dev
, RX_CNTL_CSR
, ®
);
1134 rt2x00_set_field32(®
, RX_CNTL_CSR_LOAD_RXD
, 1);
1135 rt2x00pci_register_write(rt2x00dev
, RX_CNTL_CSR
, reg
);
1140 static int rt61pci_init_registers(struct rt2x00_dev
*rt2x00dev
)
1144 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR0
, ®
);
1145 rt2x00_set_field32(®
, TXRX_CSR0_AUTO_TX_SEQ
, 1);
1146 rt2x00_set_field32(®
, TXRX_CSR0_DISABLE_RX
, 0);
1147 rt2x00_set_field32(®
, TXRX_CSR0_TX_WITHOUT_WAITING
, 0);
1148 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR0
, reg
);
1150 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR1
, ®
);
1151 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID0
, 47); /* CCK Signal */
1152 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID0_VALID
, 1);
1153 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID1
, 30); /* Rssi */
1154 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID1_VALID
, 1);
1155 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID2
, 42); /* OFDM Rate */
1156 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID2_VALID
, 1);
1157 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID3
, 30); /* Rssi */
1158 rt2x00_set_field32(®
, TXRX_CSR1_BBP_ID3_VALID
, 1);
1159 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR1
, reg
);
1162 * CCK TXD BBP registers
1164 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR2
, ®
);
1165 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID0
, 13);
1166 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID0_VALID
, 1);
1167 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID1
, 12);
1168 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID1_VALID
, 1);
1169 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID2
, 11);
1170 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID2_VALID
, 1);
1171 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID3
, 10);
1172 rt2x00_set_field32(®
, TXRX_CSR2_BBP_ID3_VALID
, 1);
1173 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR2
, reg
);
1176 * OFDM TXD BBP registers
1178 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR3
, ®
);
1179 rt2x00_set_field32(®
, TXRX_CSR3_BBP_ID0
, 7);
1180 rt2x00_set_field32(®
, TXRX_CSR3_BBP_ID0_VALID
, 1);
1181 rt2x00_set_field32(®
, TXRX_CSR3_BBP_ID1
, 6);
1182 rt2x00_set_field32(®
, TXRX_CSR3_BBP_ID1_VALID
, 1);
1183 rt2x00_set_field32(®
, TXRX_CSR3_BBP_ID2
, 5);
1184 rt2x00_set_field32(®
, TXRX_CSR3_BBP_ID2_VALID
, 1);
1185 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR3
, reg
);
1187 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR7
, ®
);
1188 rt2x00_set_field32(®
, TXRX_CSR7_ACK_CTS_6MBS
, 59);
1189 rt2x00_set_field32(®
, TXRX_CSR7_ACK_CTS_9MBS
, 53);
1190 rt2x00_set_field32(®
, TXRX_CSR7_ACK_CTS_12MBS
, 49);
1191 rt2x00_set_field32(®
, TXRX_CSR7_ACK_CTS_18MBS
, 46);
1192 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR7
, reg
);
1194 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR8
, ®
);
1195 rt2x00_set_field32(®
, TXRX_CSR8_ACK_CTS_24MBS
, 44);
1196 rt2x00_set_field32(®
, TXRX_CSR8_ACK_CTS_36MBS
, 42);
1197 rt2x00_set_field32(®
, TXRX_CSR8_ACK_CTS_48MBS
, 42);
1198 rt2x00_set_field32(®
, TXRX_CSR8_ACK_CTS_54MBS
, 42);
1199 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR8
, reg
);
1201 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR9
, ®
);
1202 rt2x00_set_field32(®
, TXRX_CSR9_BEACON_INTERVAL
, 0);
1203 rt2x00_set_field32(®
, TXRX_CSR9_TSF_TICKING
, 0);
1204 rt2x00_set_field32(®
, TXRX_CSR9_TSF_SYNC
, 0);
1205 rt2x00_set_field32(®
, TXRX_CSR9_TBTT_ENABLE
, 0);
1206 rt2x00_set_field32(®
, TXRX_CSR9_BEACON_GEN
, 0);
1207 rt2x00_set_field32(®
, TXRX_CSR9_TIMESTAMP_COMPENSATE
, 0);
1208 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR9
, reg
);
1210 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR15
, 0x0000000f);
1212 rt2x00pci_register_write(rt2x00dev
, MAC_CSR6
, 0x00000fff);
1214 rt2x00pci_register_read(rt2x00dev
, MAC_CSR9
, ®
);
1215 rt2x00_set_field32(®
, MAC_CSR9_CW_SELECT
, 0);
1216 rt2x00pci_register_write(rt2x00dev
, MAC_CSR9
, reg
);
1218 rt2x00pci_register_write(rt2x00dev
, MAC_CSR10
, 0x0000071c);
1220 if (rt2x00dev
->ops
->lib
->set_device_state(rt2x00dev
, STATE_AWAKE
))
1223 rt2x00pci_register_write(rt2x00dev
, MAC_CSR13
, 0x0000e000);
1226 * Invalidate all Shared Keys (SEC_CSR0),
1227 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1229 rt2x00pci_register_write(rt2x00dev
, SEC_CSR0
, 0x00000000);
1230 rt2x00pci_register_write(rt2x00dev
, SEC_CSR1
, 0x00000000);
1231 rt2x00pci_register_write(rt2x00dev
, SEC_CSR5
, 0x00000000);
1233 rt2x00pci_register_write(rt2x00dev
, PHY_CSR1
, 0x000023b0);
1234 rt2x00pci_register_write(rt2x00dev
, PHY_CSR5
, 0x060a100c);
1235 rt2x00pci_register_write(rt2x00dev
, PHY_CSR6
, 0x00080606);
1236 rt2x00pci_register_write(rt2x00dev
, PHY_CSR7
, 0x00000a08);
1238 rt2x00pci_register_write(rt2x00dev
, PCI_CFG_CSR
, 0x28ca4404);
1240 rt2x00pci_register_write(rt2x00dev
, TEST_MODE_CSR
, 0x00000200);
1242 rt2x00pci_register_write(rt2x00dev
, M2H_CMD_DONE_CSR
, 0xffffffff);
1244 rt2x00pci_register_read(rt2x00dev
, AC_TXOP_CSR0
, ®
);
1245 rt2x00_set_field32(®
, AC_TXOP_CSR0_AC0_TX_OP
, 0);
1246 rt2x00_set_field32(®
, AC_TXOP_CSR0_AC1_TX_OP
, 0);
1247 rt2x00pci_register_write(rt2x00dev
, AC_TXOP_CSR0
, reg
);
1249 rt2x00pci_register_read(rt2x00dev
, AC_TXOP_CSR1
, ®
);
1250 rt2x00_set_field32(®
, AC_TXOP_CSR1_AC2_TX_OP
, 192);
1251 rt2x00_set_field32(®
, AC_TXOP_CSR1_AC3_TX_OP
, 48);
1252 rt2x00pci_register_write(rt2x00dev
, AC_TXOP_CSR1
, reg
);
1256 * For the Beacon base registers we only need to clear
1257 * the first byte since that byte contains the VALID and OWNER
1258 * bits which (when set to 0) will invalidate the entire beacon.
1260 rt2x00pci_register_write(rt2x00dev
, HW_BEACON_BASE0
, 0);
1261 rt2x00pci_register_write(rt2x00dev
, HW_BEACON_BASE1
, 0);
1262 rt2x00pci_register_write(rt2x00dev
, HW_BEACON_BASE2
, 0);
1263 rt2x00pci_register_write(rt2x00dev
, HW_BEACON_BASE3
, 0);
1266 * We must clear the error counters.
1267 * These registers are cleared on read,
1268 * so we may pass a useless variable to store the value.
1270 rt2x00pci_register_read(rt2x00dev
, STA_CSR0
, ®
);
1271 rt2x00pci_register_read(rt2x00dev
, STA_CSR1
, ®
);
1272 rt2x00pci_register_read(rt2x00dev
, STA_CSR2
, ®
);
1275 * Reset MAC and BBP registers.
1277 rt2x00pci_register_read(rt2x00dev
, MAC_CSR1
, ®
);
1278 rt2x00_set_field32(®
, MAC_CSR1_SOFT_RESET
, 1);
1279 rt2x00_set_field32(®
, MAC_CSR1_BBP_RESET
, 1);
1280 rt2x00pci_register_write(rt2x00dev
, MAC_CSR1
, reg
);
1282 rt2x00pci_register_read(rt2x00dev
, MAC_CSR1
, ®
);
1283 rt2x00_set_field32(®
, MAC_CSR1_SOFT_RESET
, 0);
1284 rt2x00_set_field32(®
, MAC_CSR1_BBP_RESET
, 0);
1285 rt2x00pci_register_write(rt2x00dev
, MAC_CSR1
, reg
);
1287 rt2x00pci_register_read(rt2x00dev
, MAC_CSR1
, ®
);
1288 rt2x00_set_field32(®
, MAC_CSR1_HOST_READY
, 1);
1289 rt2x00pci_register_write(rt2x00dev
, MAC_CSR1
, reg
);
1294 static int rt61pci_wait_bbp_ready(struct rt2x00_dev
*rt2x00dev
)
1299 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
1300 rt61pci_bbp_read(rt2x00dev
, 0, &value
);
1301 if ((value
!= 0xff) && (value
!= 0x00))
1303 udelay(REGISTER_BUSY_DELAY
);
1306 ERROR(rt2x00dev
, "BBP register access failed, aborting.\n");
1310 static int rt61pci_init_bbp(struct rt2x00_dev
*rt2x00dev
)
1317 if (unlikely(rt61pci_wait_bbp_ready(rt2x00dev
)))
1320 rt61pci_bbp_write(rt2x00dev
, 3, 0x00);
1321 rt61pci_bbp_write(rt2x00dev
, 15, 0x30);
1322 rt61pci_bbp_write(rt2x00dev
, 21, 0xc8);
1323 rt61pci_bbp_write(rt2x00dev
, 22, 0x38);
1324 rt61pci_bbp_write(rt2x00dev
, 23, 0x06);
1325 rt61pci_bbp_write(rt2x00dev
, 24, 0xfe);
1326 rt61pci_bbp_write(rt2x00dev
, 25, 0x0a);
1327 rt61pci_bbp_write(rt2x00dev
, 26, 0x0d);
1328 rt61pci_bbp_write(rt2x00dev
, 34, 0x12);
1329 rt61pci_bbp_write(rt2x00dev
, 37, 0x07);
1330 rt61pci_bbp_write(rt2x00dev
, 39, 0xf8);
1331 rt61pci_bbp_write(rt2x00dev
, 41, 0x60);
1332 rt61pci_bbp_write(rt2x00dev
, 53, 0x10);
1333 rt61pci_bbp_write(rt2x00dev
, 54, 0x18);
1334 rt61pci_bbp_write(rt2x00dev
, 60, 0x10);
1335 rt61pci_bbp_write(rt2x00dev
, 61, 0x04);
1336 rt61pci_bbp_write(rt2x00dev
, 62, 0x04);
1337 rt61pci_bbp_write(rt2x00dev
, 75, 0xfe);
1338 rt61pci_bbp_write(rt2x00dev
, 86, 0xfe);
1339 rt61pci_bbp_write(rt2x00dev
, 88, 0xfe);
1340 rt61pci_bbp_write(rt2x00dev
, 90, 0x0f);
1341 rt61pci_bbp_write(rt2x00dev
, 99, 0x00);
1342 rt61pci_bbp_write(rt2x00dev
, 102, 0x16);
1343 rt61pci_bbp_write(rt2x00dev
, 107, 0x04);
1345 for (i
= 0; i
< EEPROM_BBP_SIZE
; i
++) {
1346 rt2x00_eeprom_read(rt2x00dev
, EEPROM_BBP_START
+ i
, &eeprom
);
1348 if (eeprom
!= 0xffff && eeprom
!= 0x0000) {
1349 reg_id
= rt2x00_get_field16(eeprom
, EEPROM_BBP_REG_ID
);
1350 value
= rt2x00_get_field16(eeprom
, EEPROM_BBP_VALUE
);
1351 rt61pci_bbp_write(rt2x00dev
, reg_id
, value
);
1359 * Device state switch handlers.
1361 static void rt61pci_toggle_rx(struct rt2x00_dev
*rt2x00dev
,
1362 enum dev_state state
)
1366 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR0
, ®
);
1367 rt2x00_set_field32(®
, TXRX_CSR0_DISABLE_RX
,
1368 (state
== STATE_RADIO_RX_OFF
) ||
1369 (state
== STATE_RADIO_RX_OFF_LINK
));
1370 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR0
, reg
);
1373 static void rt61pci_toggle_irq(struct rt2x00_dev
*rt2x00dev
,
1374 enum dev_state state
)
1376 int mask
= (state
== STATE_RADIO_IRQ_OFF
);
1380 * When interrupts are being enabled, the interrupt registers
1381 * should clear the register to assure a clean state.
1383 if (state
== STATE_RADIO_IRQ_ON
) {
1384 rt2x00pci_register_read(rt2x00dev
, INT_SOURCE_CSR
, ®
);
1385 rt2x00pci_register_write(rt2x00dev
, INT_SOURCE_CSR
, reg
);
1387 rt2x00pci_register_read(rt2x00dev
, MCU_INT_SOURCE_CSR
, ®
);
1388 rt2x00pci_register_write(rt2x00dev
, MCU_INT_SOURCE_CSR
, reg
);
1392 * Only toggle the interrupts bits we are going to use.
1393 * Non-checked interrupt bits are disabled by default.
1395 rt2x00pci_register_read(rt2x00dev
, INT_MASK_CSR
, ®
);
1396 rt2x00_set_field32(®
, INT_MASK_CSR_TXDONE
, mask
);
1397 rt2x00_set_field32(®
, INT_MASK_CSR_RXDONE
, mask
);
1398 rt2x00_set_field32(®
, INT_MASK_CSR_ENABLE_MITIGATION
, mask
);
1399 rt2x00_set_field32(®
, INT_MASK_CSR_MITIGATION_PERIOD
, 0xff);
1400 rt2x00pci_register_write(rt2x00dev
, INT_MASK_CSR
, reg
);
1402 rt2x00pci_register_read(rt2x00dev
, MCU_INT_MASK_CSR
, ®
);
1403 rt2x00_set_field32(®
, MCU_INT_MASK_CSR_0
, mask
);
1404 rt2x00_set_field32(®
, MCU_INT_MASK_CSR_1
, mask
);
1405 rt2x00_set_field32(®
, MCU_INT_MASK_CSR_2
, mask
);
1406 rt2x00_set_field32(®
, MCU_INT_MASK_CSR_3
, mask
);
1407 rt2x00_set_field32(®
, MCU_INT_MASK_CSR_4
, mask
);
1408 rt2x00_set_field32(®
, MCU_INT_MASK_CSR_5
, mask
);
1409 rt2x00_set_field32(®
, MCU_INT_MASK_CSR_6
, mask
);
1410 rt2x00_set_field32(®
, MCU_INT_MASK_CSR_7
, mask
);
1411 rt2x00pci_register_write(rt2x00dev
, MCU_INT_MASK_CSR
, reg
);
1414 static int rt61pci_enable_radio(struct rt2x00_dev
*rt2x00dev
)
1419 * Initialize all registers.
1421 if (unlikely(rt61pci_init_queues(rt2x00dev
) ||
1422 rt61pci_init_registers(rt2x00dev
) ||
1423 rt61pci_init_bbp(rt2x00dev
)))
1429 rt2x00pci_register_read(rt2x00dev
, RX_CNTL_CSR
, ®
);
1430 rt2x00_set_field32(®
, RX_CNTL_CSR_ENABLE_RX_DMA
, 1);
1431 rt2x00pci_register_write(rt2x00dev
, RX_CNTL_CSR
, reg
);
1436 static void rt61pci_disable_radio(struct rt2x00_dev
*rt2x00dev
)
1440 rt2x00pci_register_write(rt2x00dev
, MAC_CSR10
, 0x00001818);
1443 * Disable synchronisation.
1445 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR9
, 0);
1450 rt2x00pci_register_read(rt2x00dev
, TX_CNTL_CSR
, ®
);
1451 rt2x00_set_field32(®
, TX_CNTL_CSR_ABORT_TX_AC0
, 1);
1452 rt2x00_set_field32(®
, TX_CNTL_CSR_ABORT_TX_AC1
, 1);
1453 rt2x00_set_field32(®
, TX_CNTL_CSR_ABORT_TX_AC2
, 1);
1454 rt2x00_set_field32(®
, TX_CNTL_CSR_ABORT_TX_AC3
, 1);
1455 rt2x00pci_register_write(rt2x00dev
, TX_CNTL_CSR
, reg
);
1458 static int rt61pci_set_state(struct rt2x00_dev
*rt2x00dev
, enum dev_state state
)
1464 put_to_sleep
= (state
!= STATE_AWAKE
);
1466 rt2x00pci_register_read(rt2x00dev
, MAC_CSR12
, ®
);
1467 rt2x00_set_field32(®
, MAC_CSR12_FORCE_WAKEUP
, !put_to_sleep
);
1468 rt2x00_set_field32(®
, MAC_CSR12_PUT_TO_SLEEP
, put_to_sleep
);
1469 rt2x00pci_register_write(rt2x00dev
, MAC_CSR12
, reg
);
1472 * Device is not guaranteed to be in the requested state yet.
1473 * We must wait until the register indicates that the
1474 * device has entered the correct state.
1476 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
1477 rt2x00pci_register_read(rt2x00dev
, MAC_CSR12
, ®
);
1478 state
= rt2x00_get_field32(reg
, MAC_CSR12_BBP_CURRENT_STATE
);
1479 if (state
== !put_to_sleep
)
1487 static int rt61pci_set_device_state(struct rt2x00_dev
*rt2x00dev
,
1488 enum dev_state state
)
1493 case STATE_RADIO_ON
:
1494 retval
= rt61pci_enable_radio(rt2x00dev
);
1496 case STATE_RADIO_OFF
:
1497 rt61pci_disable_radio(rt2x00dev
);
1499 case STATE_RADIO_RX_ON
:
1500 case STATE_RADIO_RX_ON_LINK
:
1501 case STATE_RADIO_RX_OFF
:
1502 case STATE_RADIO_RX_OFF_LINK
:
1503 rt61pci_toggle_rx(rt2x00dev
, state
);
1505 case STATE_RADIO_IRQ_ON
:
1506 case STATE_RADIO_IRQ_OFF
:
1507 rt61pci_toggle_irq(rt2x00dev
, state
);
1509 case STATE_DEEP_SLEEP
:
1513 retval
= rt61pci_set_state(rt2x00dev
, state
);
1520 if (unlikely(retval
))
1521 ERROR(rt2x00dev
, "Device failed to enter state %d (%d).\n",
1528 * TX descriptor initialization
1530 static void rt61pci_write_tx_desc(struct rt2x00_dev
*rt2x00dev
,
1531 struct sk_buff
*skb
,
1532 struct txentry_desc
*txdesc
)
1534 struct skb_frame_desc
*skbdesc
= get_skb_frame_desc(skb
);
1535 __le32
*txd
= skbdesc
->desc
;
1539 * Start writing the descriptor words.
1541 rt2x00_desc_read(txd
, 1, &word
);
1542 rt2x00_set_field32(&word
, TXD_W1_HOST_Q_ID
, txdesc
->queue
);
1543 rt2x00_set_field32(&word
, TXD_W1_AIFSN
, txdesc
->aifs
);
1544 rt2x00_set_field32(&word
, TXD_W1_CWMIN
, txdesc
->cw_min
);
1545 rt2x00_set_field32(&word
, TXD_W1_CWMAX
, txdesc
->cw_max
);
1546 rt2x00_set_field32(&word
, TXD_W1_IV_OFFSET
, IEEE80211_HEADER
);
1547 rt2x00_set_field32(&word
, TXD_W1_HW_SEQUENCE
, 1);
1548 rt2x00_set_field32(&word
, TXD_W1_BUFFER_COUNT
, 1);
1549 rt2x00_desc_write(txd
, 1, word
);
1551 rt2x00_desc_read(txd
, 2, &word
);
1552 rt2x00_set_field32(&word
, TXD_W2_PLCP_SIGNAL
, txdesc
->signal
);
1553 rt2x00_set_field32(&word
, TXD_W2_PLCP_SERVICE
, txdesc
->service
);
1554 rt2x00_set_field32(&word
, TXD_W2_PLCP_LENGTH_LOW
, txdesc
->length_low
);
1555 rt2x00_set_field32(&word
, TXD_W2_PLCP_LENGTH_HIGH
, txdesc
->length_high
);
1556 rt2x00_desc_write(txd
, 2, word
);
1558 rt2x00_desc_read(txd
, 5, &word
);
1559 rt2x00_set_field32(&word
, TXD_W5_PID_TYPE
, skbdesc
->entry
->queue
->qid
);
1560 rt2x00_set_field32(&word
, TXD_W5_PID_SUBTYPE
,
1561 skbdesc
->entry
->entry_idx
);
1562 rt2x00_set_field32(&word
, TXD_W5_TX_POWER
,
1563 TXPOWER_TO_DEV(rt2x00dev
->tx_power
));
1564 rt2x00_set_field32(&word
, TXD_W5_WAITING_DMA_DONE_INT
, 1);
1565 rt2x00_desc_write(txd
, 5, word
);
1567 rt2x00_desc_read(txd
, 6, &word
);
1568 rt2x00_set_field32(&word
, TXD_W6_BUFFER_PHYSICAL_ADDRESS
,
1570 rt2x00_desc_write(txd
, 6, word
);
1572 if (skbdesc
->desc_len
> TXINFO_SIZE
) {
1573 rt2x00_desc_read(txd
, 11, &word
);
1574 rt2x00_set_field32(&word
, TXD_W11_BUFFER_LENGTH0
, skb
->len
);
1575 rt2x00_desc_write(txd
, 11, word
);
1578 rt2x00_desc_read(txd
, 0, &word
);
1579 rt2x00_set_field32(&word
, TXD_W0_OWNER_NIC
, 1);
1580 rt2x00_set_field32(&word
, TXD_W0_VALID
, 1);
1581 rt2x00_set_field32(&word
, TXD_W0_MORE_FRAG
,
1582 test_bit(ENTRY_TXD_MORE_FRAG
, &txdesc
->flags
));
1583 rt2x00_set_field32(&word
, TXD_W0_ACK
,
1584 test_bit(ENTRY_TXD_ACK
, &txdesc
->flags
));
1585 rt2x00_set_field32(&word
, TXD_W0_TIMESTAMP
,
1586 test_bit(ENTRY_TXD_REQ_TIMESTAMP
, &txdesc
->flags
));
1587 rt2x00_set_field32(&word
, TXD_W0_OFDM
,
1588 test_bit(ENTRY_TXD_OFDM_RATE
, &txdesc
->flags
));
1589 rt2x00_set_field32(&word
, TXD_W0_IFS
, txdesc
->ifs
);
1590 rt2x00_set_field32(&word
, TXD_W0_RETRY_MODE
,
1591 test_bit(ENTRY_TXD_RETRY_MODE
, &txdesc
->flags
));
1592 rt2x00_set_field32(&word
, TXD_W0_TKIP_MIC
, 0);
1593 rt2x00_set_field32(&word
, TXD_W0_DATABYTE_COUNT
, skb
->len
);
1594 rt2x00_set_field32(&word
, TXD_W0_BURST
,
1595 test_bit(ENTRY_TXD_BURST
, &txdesc
->flags
));
1596 rt2x00_set_field32(&word
, TXD_W0_CIPHER_ALG
, CIPHER_NONE
);
1597 rt2x00_desc_write(txd
, 0, word
);
1601 * TX data initialization
1603 static void rt61pci_write_beacon(struct queue_entry
*entry
)
1605 struct rt2x00_dev
*rt2x00dev
= entry
->queue
->rt2x00dev
;
1606 struct skb_frame_desc
*skbdesc
= get_skb_frame_desc(entry
->skb
);
1607 unsigned int beacon_base
;
1611 * Disable beaconing while we are reloading the beacon data,
1612 * otherwise we might be sending out invalid data.
1614 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR9
, ®
);
1615 rt2x00_set_field32(®
, TXRX_CSR9_TSF_TICKING
, 0);
1616 rt2x00_set_field32(®
, TXRX_CSR9_TBTT_ENABLE
, 0);
1617 rt2x00_set_field32(®
, TXRX_CSR9_BEACON_GEN
, 0);
1618 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR9
, reg
);
1621 * Write entire beacon with descriptor to register.
1623 beacon_base
= HW_BEACON_OFFSET(entry
->entry_idx
);
1624 rt2x00pci_register_multiwrite(rt2x00dev
,
1626 skbdesc
->desc
, skbdesc
->desc_len
);
1627 rt2x00pci_register_multiwrite(rt2x00dev
,
1628 beacon_base
+ skbdesc
->desc_len
,
1629 entry
->skb
->data
, entry
->skb
->len
);
1632 * Clean up beacon skb.
1634 dev_kfree_skb_any(entry
->skb
);
1638 static void rt61pci_kick_tx_queue(struct rt2x00_dev
*rt2x00dev
,
1639 const enum data_queue_qid queue
)
1643 if (queue
== QID_BEACON
) {
1645 * For Wi-Fi faily generated beacons between participating
1646 * stations. Set TBTT phase adaptive adjustment step to 8us.
1648 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR10
, 0x00001008);
1650 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR9
, ®
);
1651 if (!rt2x00_get_field32(reg
, TXRX_CSR9_BEACON_GEN
)) {
1652 rt2x00_set_field32(®
, TXRX_CSR9_TSF_TICKING
, 1);
1653 rt2x00_set_field32(®
, TXRX_CSR9_TBTT_ENABLE
, 1);
1654 rt2x00_set_field32(®
, TXRX_CSR9_BEACON_GEN
, 1);
1655 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR9
, reg
);
1660 rt2x00pci_register_read(rt2x00dev
, TX_CNTL_CSR
, ®
);
1661 rt2x00_set_field32(®
, TX_CNTL_CSR_KICK_TX_AC0
, (queue
== QID_AC_BE
));
1662 rt2x00_set_field32(®
, TX_CNTL_CSR_KICK_TX_AC1
, (queue
== QID_AC_BK
));
1663 rt2x00_set_field32(®
, TX_CNTL_CSR_KICK_TX_AC2
, (queue
== QID_AC_VI
));
1664 rt2x00_set_field32(®
, TX_CNTL_CSR_KICK_TX_AC3
, (queue
== QID_AC_VO
));
1665 rt2x00pci_register_write(rt2x00dev
, TX_CNTL_CSR
, reg
);
1669 * RX control handlers
1671 static int rt61pci_agc_to_rssi(struct rt2x00_dev
*rt2x00dev
, int rxd_w1
)
1677 lna
= rt2x00_get_field32(rxd_w1
, RXD_W1_RSSI_LNA
);
1692 if (rt2x00dev
->rx_status
.band
== IEEE80211_BAND_5GHZ
) {
1693 if (test_bit(CONFIG_EXTERNAL_LNA_A
, &rt2x00dev
->flags
))
1696 if (lna
== 3 || lna
== 2)
1699 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_OFFSET_A
, &eeprom
);
1700 offset
-= rt2x00_get_field16(eeprom
, EEPROM_RSSI_OFFSET_A_1
);
1702 if (test_bit(CONFIG_EXTERNAL_LNA_BG
, &rt2x00dev
->flags
))
1705 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_OFFSET_BG
, &eeprom
);
1706 offset
-= rt2x00_get_field16(eeprom
, EEPROM_RSSI_OFFSET_BG_1
);
1709 return rt2x00_get_field32(rxd_w1
, RXD_W1_RSSI_AGC
) * 2 - offset
;
1712 static void rt61pci_fill_rxdone(struct queue_entry
*entry
,
1713 struct rxdone_entry_desc
*rxdesc
)
1715 struct queue_entry_priv_pci
*entry_priv
= entry
->priv_data
;
1719 rt2x00_desc_read(entry_priv
->desc
, 0, &word0
);
1720 rt2x00_desc_read(entry_priv
->desc
, 1, &word1
);
1722 if (rt2x00_get_field32(word0
, RXD_W0_CRC_ERROR
))
1723 rxdesc
->flags
|= RX_FLAG_FAILED_FCS_CRC
;
1726 * Obtain the status about this packet.
1727 * When frame was received with an OFDM bitrate,
1728 * the signal is the PLCP value. If it was received with
1729 * a CCK bitrate the signal is the rate in 100kbit/s.
1731 rxdesc
->signal
= rt2x00_get_field32(word1
, RXD_W1_SIGNAL
);
1732 rxdesc
->rssi
= rt61pci_agc_to_rssi(entry
->queue
->rt2x00dev
, word1
);
1733 rxdesc
->size
= rt2x00_get_field32(word0
, RXD_W0_DATABYTE_COUNT
);
1735 if (rt2x00_get_field32(word0
, RXD_W0_OFDM
))
1736 rxdesc
->dev_flags
|= RXDONE_SIGNAL_PLCP
;
1737 if (rt2x00_get_field32(word0
, RXD_W0_MY_BSS
))
1738 rxdesc
->dev_flags
|= RXDONE_MY_BSS
;
1742 * Interrupt functions.
1744 static void rt61pci_txdone(struct rt2x00_dev
*rt2x00dev
)
1746 struct data_queue
*queue
;
1747 struct queue_entry
*entry
;
1748 struct queue_entry
*entry_done
;
1749 struct queue_entry_priv_pci
*entry_priv
;
1750 struct txdone_entry_desc txdesc
;
1758 * During each loop we will compare the freshly read
1759 * STA_CSR4 register value with the value read from
1760 * the previous loop. If the 2 values are equal then
1761 * we should stop processing because the chance it
1762 * quite big that the device has been unplugged and
1763 * we risk going into an endless loop.
1768 rt2x00pci_register_read(rt2x00dev
, STA_CSR4
, ®
);
1769 if (!rt2x00_get_field32(reg
, STA_CSR4_VALID
))
1777 * Skip this entry when it contains an invalid
1778 * queue identication number.
1780 type
= rt2x00_get_field32(reg
, STA_CSR4_PID_TYPE
);
1781 queue
= rt2x00queue_get_queue(rt2x00dev
, type
);
1782 if (unlikely(!queue
))
1786 * Skip this entry when it contains an invalid
1789 index
= rt2x00_get_field32(reg
, STA_CSR4_PID_SUBTYPE
);
1790 if (unlikely(index
>= queue
->limit
))
1793 entry
= &queue
->entries
[index
];
1794 entry_priv
= entry
->priv_data
;
1795 rt2x00_desc_read(entry_priv
->desc
, 0, &word
);
1797 if (rt2x00_get_field32(word
, TXD_W0_OWNER_NIC
) ||
1798 !rt2x00_get_field32(word
, TXD_W0_VALID
))
1801 entry_done
= rt2x00queue_get_entry(queue
, Q_INDEX_DONE
);
1802 while (entry
!= entry_done
) {
1804 * Just report any entries we missed as failed.
1807 "TX status report missed for entry %d\n",
1808 entry_done
->entry_idx
);
1811 __set_bit(TXDONE_UNKNOWN
, &txdesc
.flags
);
1814 rt2x00lib_txdone(entry_done
, &txdesc
);
1815 entry_done
= rt2x00queue_get_entry(queue
, Q_INDEX_DONE
);
1819 * Obtain the status about this packet.
1822 switch (rt2x00_get_field32(reg
, STA_CSR4_TX_RESULT
)) {
1823 case 0: /* Success, maybe with retry */
1824 __set_bit(TXDONE_SUCCESS
, &txdesc
.flags
);
1826 case 6: /* Failure, excessive retries */
1827 __set_bit(TXDONE_EXCESSIVE_RETRY
, &txdesc
.flags
);
1828 /* Don't break, this is a failed frame! */
1829 default: /* Failure */
1830 __set_bit(TXDONE_FAILURE
, &txdesc
.flags
);
1832 txdesc
.retry
= rt2x00_get_field32(reg
, STA_CSR4_RETRY_COUNT
);
1834 rt2x00lib_txdone(entry
, &txdesc
);
1838 static irqreturn_t
rt61pci_interrupt(int irq
, void *dev_instance
)
1840 struct rt2x00_dev
*rt2x00dev
= dev_instance
;
1845 * Get the interrupt sources & saved to local variable.
1846 * Write register value back to clear pending interrupts.
1848 rt2x00pci_register_read(rt2x00dev
, MCU_INT_SOURCE_CSR
, ®_mcu
);
1849 rt2x00pci_register_write(rt2x00dev
, MCU_INT_SOURCE_CSR
, reg_mcu
);
1851 rt2x00pci_register_read(rt2x00dev
, INT_SOURCE_CSR
, ®
);
1852 rt2x00pci_register_write(rt2x00dev
, INT_SOURCE_CSR
, reg
);
1854 if (!reg
&& !reg_mcu
)
1857 if (!test_bit(DEVICE_ENABLED_RADIO
, &rt2x00dev
->flags
))
1861 * Handle interrupts, walk through all bits
1862 * and run the tasks, the bits are checked in order of
1867 * 1 - Rx ring done interrupt.
1869 if (rt2x00_get_field32(reg
, INT_SOURCE_CSR_RXDONE
))
1870 rt2x00pci_rxdone(rt2x00dev
);
1873 * 2 - Tx ring done interrupt.
1875 if (rt2x00_get_field32(reg
, INT_SOURCE_CSR_TXDONE
))
1876 rt61pci_txdone(rt2x00dev
);
1879 * 3 - Handle MCU command done.
1882 rt2x00pci_register_write(rt2x00dev
,
1883 M2H_CMD_DONE_CSR
, 0xffffffff);
1889 * Device probe functions.
1891 static int rt61pci_validate_eeprom(struct rt2x00_dev
*rt2x00dev
)
1893 struct eeprom_93cx6 eeprom
;
1899 rt2x00pci_register_read(rt2x00dev
, E2PROM_CSR
, ®
);
1901 eeprom
.data
= rt2x00dev
;
1902 eeprom
.register_read
= rt61pci_eepromregister_read
;
1903 eeprom
.register_write
= rt61pci_eepromregister_write
;
1904 eeprom
.width
= rt2x00_get_field32(reg
, E2PROM_CSR_TYPE_93C46
) ?
1905 PCI_EEPROM_WIDTH_93C46
: PCI_EEPROM_WIDTH_93C66
;
1906 eeprom
.reg_data_in
= 0;
1907 eeprom
.reg_data_out
= 0;
1908 eeprom
.reg_data_clock
= 0;
1909 eeprom
.reg_chip_select
= 0;
1911 eeprom_93cx6_multiread(&eeprom
, EEPROM_BASE
, rt2x00dev
->eeprom
,
1912 EEPROM_SIZE
/ sizeof(u16
));
1915 * Start validation of the data that has been read.
1917 mac
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_MAC_ADDR_0
);
1918 if (!is_valid_ether_addr(mac
)) {
1919 DECLARE_MAC_BUF(macbuf
);
1921 random_ether_addr(mac
);
1922 EEPROM(rt2x00dev
, "MAC: %s\n", print_mac(macbuf
, mac
));
1925 rt2x00_eeprom_read(rt2x00dev
, EEPROM_ANTENNA
, &word
);
1926 if (word
== 0xffff) {
1927 rt2x00_set_field16(&word
, EEPROM_ANTENNA_NUM
, 2);
1928 rt2x00_set_field16(&word
, EEPROM_ANTENNA_TX_DEFAULT
,
1930 rt2x00_set_field16(&word
, EEPROM_ANTENNA_RX_DEFAULT
,
1932 rt2x00_set_field16(&word
, EEPROM_ANTENNA_FRAME_TYPE
, 0);
1933 rt2x00_set_field16(&word
, EEPROM_ANTENNA_DYN_TXAGC
, 0);
1934 rt2x00_set_field16(&word
, EEPROM_ANTENNA_HARDWARE_RADIO
, 0);
1935 rt2x00_set_field16(&word
, EEPROM_ANTENNA_RF_TYPE
, RF5225
);
1936 rt2x00_eeprom_write(rt2x00dev
, EEPROM_ANTENNA
, word
);
1937 EEPROM(rt2x00dev
, "Antenna: 0x%04x\n", word
);
1940 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC
, &word
);
1941 if (word
== 0xffff) {
1942 rt2x00_set_field16(&word
, EEPROM_NIC_ENABLE_DIVERSITY
, 0);
1943 rt2x00_set_field16(&word
, EEPROM_NIC_TX_DIVERSITY
, 0);
1944 rt2x00_set_field16(&word
, EEPROM_NIC_TX_RX_FIXED
, 0);
1945 rt2x00_set_field16(&word
, EEPROM_NIC_EXTERNAL_LNA_BG
, 0);
1946 rt2x00_set_field16(&word
, EEPROM_NIC_CARDBUS_ACCEL
, 0);
1947 rt2x00_set_field16(&word
, EEPROM_NIC_EXTERNAL_LNA_A
, 0);
1948 rt2x00_eeprom_write(rt2x00dev
, EEPROM_NIC
, word
);
1949 EEPROM(rt2x00dev
, "NIC: 0x%04x\n", word
);
1952 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LED
, &word
);
1953 if (word
== 0xffff) {
1954 rt2x00_set_field16(&word
, EEPROM_LED_LED_MODE
,
1956 rt2x00_eeprom_write(rt2x00dev
, EEPROM_LED
, word
);
1957 EEPROM(rt2x00dev
, "Led: 0x%04x\n", word
);
1960 rt2x00_eeprom_read(rt2x00dev
, EEPROM_FREQ
, &word
);
1961 if (word
== 0xffff) {
1962 rt2x00_set_field16(&word
, EEPROM_FREQ_OFFSET
, 0);
1963 rt2x00_set_field16(&word
, EEPROM_FREQ_SEQ
, 0);
1964 rt2x00_eeprom_write(rt2x00dev
, EEPROM_FREQ
, word
);
1965 EEPROM(rt2x00dev
, "Freq: 0x%04x\n", word
);
1968 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_OFFSET_BG
, &word
);
1969 if (word
== 0xffff) {
1970 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_BG_1
, 0);
1971 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_BG_2
, 0);
1972 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_OFFSET_BG
, word
);
1973 EEPROM(rt2x00dev
, "RSSI OFFSET BG: 0x%04x\n", word
);
1975 value
= rt2x00_get_field16(word
, EEPROM_RSSI_OFFSET_BG_1
);
1976 if (value
< -10 || value
> 10)
1977 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_BG_1
, 0);
1978 value
= rt2x00_get_field16(word
, EEPROM_RSSI_OFFSET_BG_2
);
1979 if (value
< -10 || value
> 10)
1980 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_BG_2
, 0);
1981 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_OFFSET_BG
, word
);
1984 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_OFFSET_A
, &word
);
1985 if (word
== 0xffff) {
1986 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_A_1
, 0);
1987 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_A_2
, 0);
1988 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_OFFSET_A
, word
);
1989 EEPROM(rt2x00dev
, "RSSI OFFSET A: 0x%04x\n", word
);
1991 value
= rt2x00_get_field16(word
, EEPROM_RSSI_OFFSET_A_1
);
1992 if (value
< -10 || value
> 10)
1993 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_A_1
, 0);
1994 value
= rt2x00_get_field16(word
, EEPROM_RSSI_OFFSET_A_2
);
1995 if (value
< -10 || value
> 10)
1996 rt2x00_set_field16(&word
, EEPROM_RSSI_OFFSET_A_2
, 0);
1997 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_OFFSET_A
, word
);
2003 static int rt61pci_init_eeprom(struct rt2x00_dev
*rt2x00dev
)
2011 * Read EEPROM word for configuration.
2013 rt2x00_eeprom_read(rt2x00dev
, EEPROM_ANTENNA
, &eeprom
);
2016 * Identify RF chipset.
2017 * To determine the RT chip we have to read the
2018 * PCI header of the device.
2020 pci_read_config_word(to_pci_dev(rt2x00dev
->dev
),
2021 PCI_CONFIG_HEADER_DEVICE
, &device
);
2022 value
= rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_RF_TYPE
);
2023 rt2x00pci_register_read(rt2x00dev
, MAC_CSR0
, ®
);
2024 rt2x00_set_chip(rt2x00dev
, device
, value
, reg
);
2026 if (!rt2x00_rf(&rt2x00dev
->chip
, RF5225
) &&
2027 !rt2x00_rf(&rt2x00dev
->chip
, RF5325
) &&
2028 !rt2x00_rf(&rt2x00dev
->chip
, RF2527
) &&
2029 !rt2x00_rf(&rt2x00dev
->chip
, RF2529
)) {
2030 ERROR(rt2x00dev
, "Invalid RF chipset detected.\n");
2035 * Determine number of antenna's.
2037 if (rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_NUM
) == 2)
2038 __set_bit(CONFIG_DOUBLE_ANTENNA
, &rt2x00dev
->flags
);
2041 * Identify default antenna configuration.
2043 rt2x00dev
->default_ant
.tx
=
2044 rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_TX_DEFAULT
);
2045 rt2x00dev
->default_ant
.rx
=
2046 rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_RX_DEFAULT
);
2049 * Read the Frame type.
2051 if (rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_FRAME_TYPE
))
2052 __set_bit(CONFIG_FRAME_TYPE
, &rt2x00dev
->flags
);
2055 * Detect if this device has an hardware controlled radio.
2057 #ifdef CONFIG_RT61PCI_RFKILL
2058 if (rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_HARDWARE_RADIO
))
2059 __set_bit(CONFIG_SUPPORT_HW_BUTTON
, &rt2x00dev
->flags
);
2060 #endif /* CONFIG_RT61PCI_RFKILL */
2063 * Read frequency offset and RF programming sequence.
2065 rt2x00_eeprom_read(rt2x00dev
, EEPROM_FREQ
, &eeprom
);
2066 if (rt2x00_get_field16(eeprom
, EEPROM_FREQ_SEQ
))
2067 __set_bit(CONFIG_RF_SEQUENCE
, &rt2x00dev
->flags
);
2069 rt2x00dev
->freq_offset
= rt2x00_get_field16(eeprom
, EEPROM_FREQ_OFFSET
);
2072 * Read external LNA informations.
2074 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC
, &eeprom
);
2076 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_EXTERNAL_LNA_A
))
2077 __set_bit(CONFIG_EXTERNAL_LNA_A
, &rt2x00dev
->flags
);
2078 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_EXTERNAL_LNA_BG
))
2079 __set_bit(CONFIG_EXTERNAL_LNA_BG
, &rt2x00dev
->flags
);
2082 * When working with a RF2529 chip without double antenna
2083 * the antenna settings should be gathered from the NIC
2086 if (rt2x00_rf(&rt2x00dev
->chip
, RF2529
) &&
2087 !test_bit(CONFIG_DOUBLE_ANTENNA
, &rt2x00dev
->flags
)) {
2088 switch (rt2x00_get_field16(eeprom
, EEPROM_NIC_TX_RX_FIXED
)) {
2090 rt2x00dev
->default_ant
.tx
= ANTENNA_B
;
2091 rt2x00dev
->default_ant
.rx
= ANTENNA_A
;
2094 rt2x00dev
->default_ant
.tx
= ANTENNA_B
;
2095 rt2x00dev
->default_ant
.rx
= ANTENNA_B
;
2098 rt2x00dev
->default_ant
.tx
= ANTENNA_A
;
2099 rt2x00dev
->default_ant
.rx
= ANTENNA_A
;
2102 rt2x00dev
->default_ant
.tx
= ANTENNA_A
;
2103 rt2x00dev
->default_ant
.rx
= ANTENNA_B
;
2107 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_TX_DIVERSITY
))
2108 rt2x00dev
->default_ant
.tx
= ANTENNA_SW_DIVERSITY
;
2109 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_ENABLE_DIVERSITY
))
2110 rt2x00dev
->default_ant
.rx
= ANTENNA_SW_DIVERSITY
;
2114 * Store led settings, for correct led behaviour.
2115 * If the eeprom value is invalid,
2116 * switch to default led mode.
2118 #ifdef CONFIG_RT61PCI_LEDS
2119 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LED
, &eeprom
);
2120 value
= rt2x00_get_field16(eeprom
, EEPROM_LED_LED_MODE
);
2122 rt61pci_init_led(rt2x00dev
, &rt2x00dev
->led_radio
, LED_TYPE_RADIO
);
2123 rt61pci_init_led(rt2x00dev
, &rt2x00dev
->led_assoc
, LED_TYPE_ASSOC
);
2124 if (value
== LED_MODE_SIGNAL_STRENGTH
)
2125 rt61pci_init_led(rt2x00dev
, &rt2x00dev
->led_qual
,
2128 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_LED_MODE
, value
);
2129 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_GPIO_0
,
2130 rt2x00_get_field16(eeprom
,
2131 EEPROM_LED_POLARITY_GPIO_0
));
2132 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_GPIO_1
,
2133 rt2x00_get_field16(eeprom
,
2134 EEPROM_LED_POLARITY_GPIO_1
));
2135 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_GPIO_2
,
2136 rt2x00_get_field16(eeprom
,
2137 EEPROM_LED_POLARITY_GPIO_2
));
2138 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_GPIO_3
,
2139 rt2x00_get_field16(eeprom
,
2140 EEPROM_LED_POLARITY_GPIO_3
));
2141 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_GPIO_4
,
2142 rt2x00_get_field16(eeprom
,
2143 EEPROM_LED_POLARITY_GPIO_4
));
2144 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_ACT
,
2145 rt2x00_get_field16(eeprom
, EEPROM_LED_POLARITY_ACT
));
2146 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_READY_BG
,
2147 rt2x00_get_field16(eeprom
,
2148 EEPROM_LED_POLARITY_RDY_G
));
2149 rt2x00_set_field16(&rt2x00dev
->led_mcu_reg
, MCU_LEDCS_POLARITY_READY_A
,
2150 rt2x00_get_field16(eeprom
,
2151 EEPROM_LED_POLARITY_RDY_A
));
2152 #endif /* CONFIG_RT61PCI_LEDS */
2158 * RF value list for RF5225 & RF5325
2159 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence disabled
2161 static const struct rf_channel rf_vals_noseq
[] = {
2162 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2163 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2164 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2165 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2166 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2167 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2168 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2169 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2170 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2171 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2172 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2173 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2174 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2175 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2177 /* 802.11 UNI / HyperLan 2 */
2178 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2179 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2180 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2181 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2182 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2183 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2184 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2185 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2187 /* 802.11 HyperLan 2 */
2188 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2189 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2190 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2191 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2192 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2193 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2194 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2195 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2196 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2197 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2200 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2201 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2202 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2203 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2204 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2205 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2207 /* MMAC(Japan)J52 ch 34,38,42,46 */
2208 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2209 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2210 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2211 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2215 * RF value list for RF5225 & RF5325
2216 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence enabled
2218 static const struct rf_channel rf_vals_seq
[] = {
2219 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2220 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2221 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2222 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2223 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2224 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2225 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2226 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2227 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2228 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2229 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2230 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2231 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2232 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2234 /* 802.11 UNI / HyperLan 2 */
2235 { 36, 0x00002cd4, 0x0004481a, 0x00098455, 0x000c0a03 },
2236 { 40, 0x00002cd0, 0x00044682, 0x00098455, 0x000c0a03 },
2237 { 44, 0x00002cd0, 0x00044686, 0x00098455, 0x000c0a1b },
2238 { 48, 0x00002cd0, 0x0004468e, 0x00098655, 0x000c0a0b },
2239 { 52, 0x00002cd0, 0x00044692, 0x00098855, 0x000c0a23 },
2240 { 56, 0x00002cd0, 0x0004469a, 0x00098c55, 0x000c0a13 },
2241 { 60, 0x00002cd0, 0x000446a2, 0x00098e55, 0x000c0a03 },
2242 { 64, 0x00002cd0, 0x000446a6, 0x00099255, 0x000c0a1b },
2244 /* 802.11 HyperLan 2 */
2245 { 100, 0x00002cd4, 0x0004489a, 0x000b9855, 0x000c0a03 },
2246 { 104, 0x00002cd4, 0x000448a2, 0x000b9855, 0x000c0a03 },
2247 { 108, 0x00002cd4, 0x000448aa, 0x000b9855, 0x000c0a03 },
2248 { 112, 0x00002cd4, 0x000448b2, 0x000b9a55, 0x000c0a03 },
2249 { 116, 0x00002cd4, 0x000448ba, 0x000b9a55, 0x000c0a03 },
2250 { 120, 0x00002cd0, 0x00044702, 0x000b9a55, 0x000c0a03 },
2251 { 124, 0x00002cd0, 0x00044706, 0x000b9a55, 0x000c0a1b },
2252 { 128, 0x00002cd0, 0x0004470e, 0x000b9c55, 0x000c0a0b },
2253 { 132, 0x00002cd0, 0x00044712, 0x000b9c55, 0x000c0a23 },
2254 { 136, 0x00002cd0, 0x0004471a, 0x000b9e55, 0x000c0a13 },
2257 { 140, 0x00002cd0, 0x00044722, 0x000b9e55, 0x000c0a03 },
2258 { 149, 0x00002cd0, 0x0004472e, 0x000ba255, 0x000c0a1b },
2259 { 153, 0x00002cd0, 0x00044736, 0x000ba255, 0x000c0a0b },
2260 { 157, 0x00002cd4, 0x0004490a, 0x000ba255, 0x000c0a17 },
2261 { 161, 0x00002cd4, 0x00044912, 0x000ba255, 0x000c0a17 },
2262 { 165, 0x00002cd4, 0x0004491a, 0x000ba255, 0x000c0a17 },
2264 /* MMAC(Japan)J52 ch 34,38,42,46 */
2265 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000c0a0b },
2266 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000c0a13 },
2267 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000c0a1b },
2268 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000c0a23 },
2271 static void rt61pci_probe_hw_mode(struct rt2x00_dev
*rt2x00dev
)
2273 struct hw_mode_spec
*spec
= &rt2x00dev
->spec
;
2278 * Initialize all hw fields.
2280 rt2x00dev
->hw
->flags
=
2281 IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE
|
2282 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING
|
2283 IEEE80211_HW_SIGNAL_DBM
;
2284 rt2x00dev
->hw
->extra_tx_headroom
= 0;
2286 SET_IEEE80211_DEV(rt2x00dev
->hw
, rt2x00dev
->dev
);
2287 SET_IEEE80211_PERM_ADDR(rt2x00dev
->hw
,
2288 rt2x00_eeprom_addr(rt2x00dev
,
2289 EEPROM_MAC_ADDR_0
));
2292 * Convert tx_power array in eeprom.
2294 txpower
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_G_START
);
2295 for (i
= 0; i
< 14; i
++)
2296 txpower
[i
] = TXPOWER_FROM_DEV(txpower
[i
]);
2299 * Initialize hw_mode information.
2301 spec
->supported_bands
= SUPPORT_BAND_2GHZ
;
2302 spec
->supported_rates
= SUPPORT_RATE_CCK
| SUPPORT_RATE_OFDM
;
2303 spec
->tx_power_a
= NULL
;
2304 spec
->tx_power_bg
= txpower
;
2305 spec
->tx_power_default
= DEFAULT_TXPOWER
;
2307 if (!test_bit(CONFIG_RF_SEQUENCE
, &rt2x00dev
->flags
)) {
2308 spec
->num_channels
= 14;
2309 spec
->channels
= rf_vals_noseq
;
2311 spec
->num_channels
= 14;
2312 spec
->channels
= rf_vals_seq
;
2315 if (rt2x00_rf(&rt2x00dev
->chip
, RF5225
) ||
2316 rt2x00_rf(&rt2x00dev
->chip
, RF5325
)) {
2317 spec
->supported_bands
|= SUPPORT_BAND_5GHZ
;
2318 spec
->num_channels
= ARRAY_SIZE(rf_vals_seq
);
2320 txpower
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_A_START
);
2321 for (i
= 0; i
< 14; i
++)
2322 txpower
[i
] = TXPOWER_FROM_DEV(txpower
[i
]);
2324 spec
->tx_power_a
= txpower
;
2328 static int rt61pci_probe_hw(struct rt2x00_dev
*rt2x00dev
)
2333 * Allocate eeprom data.
2335 retval
= rt61pci_validate_eeprom(rt2x00dev
);
2339 retval
= rt61pci_init_eeprom(rt2x00dev
);
2344 * Initialize hw specifications.
2346 rt61pci_probe_hw_mode(rt2x00dev
);
2349 * This device requires firmware and DMA mapped skbs.
2351 __set_bit(DRIVER_REQUIRE_FIRMWARE
, &rt2x00dev
->flags
);
2352 __set_bit(DRIVER_REQUIRE_DMA
, &rt2x00dev
->flags
);
2355 * Set the rssi offset.
2357 rt2x00dev
->rssi_offset
= DEFAULT_RSSI_OFFSET
;
2363 * IEEE80211 stack callback functions.
2365 static int rt61pci_set_retry_limit(struct ieee80211_hw
*hw
,
2366 u32 short_retry
, u32 long_retry
)
2368 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
2371 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR4
, ®
);
2372 rt2x00_set_field32(®
, TXRX_CSR4_LONG_RETRY_LIMIT
, long_retry
);
2373 rt2x00_set_field32(®
, TXRX_CSR4_SHORT_RETRY_LIMIT
, short_retry
);
2374 rt2x00pci_register_write(rt2x00dev
, TXRX_CSR4
, reg
);
2379 static u64
rt61pci_get_tsf(struct ieee80211_hw
*hw
)
2381 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
2385 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR13
, ®
);
2386 tsf
= (u64
) rt2x00_get_field32(reg
, TXRX_CSR13_HIGH_TSFTIMER
) << 32;
2387 rt2x00pci_register_read(rt2x00dev
, TXRX_CSR12
, ®
);
2388 tsf
|= rt2x00_get_field32(reg
, TXRX_CSR12_LOW_TSFTIMER
);
2393 static const struct ieee80211_ops rt61pci_mac80211_ops
= {
2395 .start
= rt2x00mac_start
,
2396 .stop
= rt2x00mac_stop
,
2397 .add_interface
= rt2x00mac_add_interface
,
2398 .remove_interface
= rt2x00mac_remove_interface
,
2399 .config
= rt2x00mac_config
,
2400 .config_interface
= rt2x00mac_config_interface
,
2401 .configure_filter
= rt2x00mac_configure_filter
,
2402 .get_stats
= rt2x00mac_get_stats
,
2403 .set_retry_limit
= rt61pci_set_retry_limit
,
2404 .bss_info_changed
= rt2x00mac_bss_info_changed
,
2405 .conf_tx
= rt2x00mac_conf_tx
,
2406 .get_tx_stats
= rt2x00mac_get_tx_stats
,
2407 .get_tsf
= rt61pci_get_tsf
,
2410 static const struct rt2x00lib_ops rt61pci_rt2x00_ops
= {
2411 .irq_handler
= rt61pci_interrupt
,
2412 .probe_hw
= rt61pci_probe_hw
,
2413 .get_firmware_name
= rt61pci_get_firmware_name
,
2414 .get_firmware_crc
= rt61pci_get_firmware_crc
,
2415 .load_firmware
= rt61pci_load_firmware
,
2416 .initialize
= rt2x00pci_initialize
,
2417 .uninitialize
= rt2x00pci_uninitialize
,
2418 .init_rxentry
= rt61pci_init_rxentry
,
2419 .init_txentry
= rt61pci_init_txentry
,
2420 .set_device_state
= rt61pci_set_device_state
,
2421 .rfkill_poll
= rt61pci_rfkill_poll
,
2422 .link_stats
= rt61pci_link_stats
,
2423 .reset_tuner
= rt61pci_reset_tuner
,
2424 .link_tuner
= rt61pci_link_tuner
,
2425 .write_tx_desc
= rt61pci_write_tx_desc
,
2426 .write_tx_data
= rt2x00pci_write_tx_data
,
2427 .write_beacon
= rt61pci_write_beacon
,
2428 .kick_tx_queue
= rt61pci_kick_tx_queue
,
2429 .fill_rxdone
= rt61pci_fill_rxdone
,
2430 .config_filter
= rt61pci_config_filter
,
2431 .config_intf
= rt61pci_config_intf
,
2432 .config_erp
= rt61pci_config_erp
,
2433 .config
= rt61pci_config
,
2436 static const struct data_queue_desc rt61pci_queue_rx
= {
2437 .entry_num
= RX_ENTRIES
,
2438 .data_size
= DATA_FRAME_SIZE
,
2439 .desc_size
= RXD_DESC_SIZE
,
2440 .priv_size
= sizeof(struct queue_entry_priv_pci
),
2443 static const struct data_queue_desc rt61pci_queue_tx
= {
2444 .entry_num
= TX_ENTRIES
,
2445 .data_size
= DATA_FRAME_SIZE
,
2446 .desc_size
= TXD_DESC_SIZE
,
2447 .priv_size
= sizeof(struct queue_entry_priv_pci
),
2450 static const struct data_queue_desc rt61pci_queue_bcn
= {
2451 .entry_num
= 4 * BEACON_ENTRIES
,
2452 .data_size
= 0, /* No DMA required for beacons */
2453 .desc_size
= TXINFO_SIZE
,
2454 .priv_size
= sizeof(struct queue_entry_priv_pci
),
2457 static const struct rt2x00_ops rt61pci_ops
= {
2458 .name
= KBUILD_MODNAME
,
2461 .eeprom_size
= EEPROM_SIZE
,
2463 .tx_queues
= NUM_TX_QUEUES
,
2464 .rx
= &rt61pci_queue_rx
,
2465 .tx
= &rt61pci_queue_tx
,
2466 .bcn
= &rt61pci_queue_bcn
,
2467 .lib
= &rt61pci_rt2x00_ops
,
2468 .hw
= &rt61pci_mac80211_ops
,
2469 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2470 .debugfs
= &rt61pci_rt2x00debug
,
2471 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2475 * RT61pci module information.
2477 static struct pci_device_id rt61pci_device_table
[] = {
2479 { PCI_DEVICE(0x1814, 0x0301), PCI_DEVICE_DATA(&rt61pci_ops
) },
2481 { PCI_DEVICE(0x1814, 0x0302), PCI_DEVICE_DATA(&rt61pci_ops
) },
2483 { PCI_DEVICE(0x1814, 0x0401), PCI_DEVICE_DATA(&rt61pci_ops
) },
2487 MODULE_AUTHOR(DRV_PROJECT
);
2488 MODULE_VERSION(DRV_VERSION
);
2489 MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver.");
2490 MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 "
2491 "PCI & PCMCIA chipset based cards");
2492 MODULE_DEVICE_TABLE(pci
, rt61pci_device_table
);
2493 MODULE_FIRMWARE(FIRMWARE_RT2561
);
2494 MODULE_FIRMWARE(FIRMWARE_RT2561s
);
2495 MODULE_FIRMWARE(FIRMWARE_RT2661
);
2496 MODULE_LICENSE("GPL");
2498 static struct pci_driver rt61pci_driver
= {
2499 .name
= KBUILD_MODNAME
,
2500 .id_table
= rt61pci_device_table
,
2501 .probe
= rt2x00pci_probe
,
2502 .remove
= __devexit_p(rt2x00pci_remove
),
2503 .suspend
= rt2x00pci_suspend
,
2504 .resume
= rt2x00pci_resume
,
2507 static int __init
rt61pci_init(void)
2509 return pci_register_driver(&rt61pci_driver
);
2512 static void __exit
rt61pci_exit(void)
2514 pci_unregister_driver(&rt61pci_driver
);
2517 module_init(rt61pci_init
);
2518 module_exit(rt61pci_exit
);