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Merge master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6
[linux-2.6/verdex.git] / drivers / net / 8139too.c
blob4c2cf7bbd252927c40a018bb8d69b0e3c26b900e
1 /*
2
3 8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux.
4
5 Maintained by Jeff Garzik <jgarzik@pobox.com>
6 Copyright 2000-2002 Jeff Garzik
7
8 Much code comes from Donald Becker's rtl8139.c driver,
9 versions 1.13 and older. This driver was originally based
10 on rtl8139.c version 1.07. Header of rtl8139.c version 1.13:
11
12 -----<snip>-----
13
14 Written 1997-2001 by Donald Becker.
15 This software may be used and distributed according to the
16 terms of the GNU General Public License (GPL), incorporated
17 herein by reference. Drivers based on or derived from this
18 code fall under the GPL and must retain the authorship,
19 copyright and license notice. This file is not a complete
20 program and may only be used when the entire operating
21 system is licensed under the GPL.
22
23 This driver is for boards based on the RTL8129 and RTL8139
24 PCI ethernet chips.
25
26 The author may be reached as becker@scyld.com, or C/O Scyld
27 Computing Corporation 410 Severn Ave., Suite 210 Annapolis
28 MD 21403
29
30 Support and updates available at
31 http://www.scyld.com/network/rtl8139.html
32
33 Twister-tuning table provided by Kinston
34 <shangh@realtek.com.tw>.
35
36 -----<snip>-----
37
38 This software may be used and distributed according to the terms
39 of the GNU General Public License, incorporated herein by reference.
40
41 Contributors:
42
43 Donald Becker - he wrote the original driver, kudos to him!
44 (but please don't e-mail him for support, this isn't his driver)
45
46 Tigran Aivazian - bug fixes, skbuff free cleanup
47
48 Martin Mares - suggestions for PCI cleanup
49
50 David S. Miller - PCI DMA and softnet updates
51
52 Ernst Gill - fixes ported from BSD driver
53
54 Daniel Kobras - identified specific locations of
55 posted MMIO write bugginess
56
57 Gerard Sharp - bug fix, testing and feedback
58
59 David Ford - Rx ring wrap fix
60
61 Dan DeMaggio - swapped RTL8139 cards with me, and allowed me
62 to find and fix a crucial bug on older chipsets.
63
64 Donald Becker/Chris Butterworth/Marcus Westergren -
65 Noticed various Rx packet size-related buglets.
66
67 Santiago Garcia Mantinan - testing and feedback
68
69 Jens David - 2.2.x kernel backports
70
71 Martin Dennett - incredibly helpful insight on undocumented
72 features of the 8139 chips
73
74 Jean-Jacques Michel - bug fix
75
76 Tobias Ringström - Rx interrupt status checking suggestion
77
78 Andrew Morton - Clear blocked signals, avoid
79 buffer overrun setting current->comm.
80
81 Kalle Olavi Niemitalo - Wake-on-LAN ioctls
82
83 Robert Kuebel - Save kernel thread from dying on any signal.
84
85 Submitting bug reports:
86
87 "rtl8139-diag -mmmaaavvveefN" output
88 enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log
89
90 */
91
92 #define DRV_NAME "8139too"
93 #define DRV_VERSION "0.9.27"
94
95
96 #include <linux/config.h>
97 #include <linux/module.h>
98 #include <linux/kernel.h>
99 #include <linux/compiler.h>
100 #include <linux/pci.h>
101 #include <linux/init.h>
102 #include <linux/ioport.h>
103 #include <linux/netdevice.h>
104 #include <linux/etherdevice.h>
105 #include <linux/rtnetlink.h>
106 #include <linux/delay.h>
107 #include <linux/ethtool.h>
108 #include <linux/mii.h>
109 #include <linux/completion.h>
110 #include <linux/crc32.h>
111 #include <asm/io.h>
112 #include <asm/uaccess.h>
113 #include <asm/irq.h>
114
115 #define RTL8139_DRIVER_NAME DRV_NAME " Fast Ethernet driver " DRV_VERSION
116 #define PFX DRV_NAME ": "
117
118 /* Default Message level */
119 #define RTL8139_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
120 NETIF_MSG_PROBE | \
121 NETIF_MSG_LINK)
122
123
124 /* enable PIO instead of MMIO, if CONFIG_8139TOO_PIO is selected */
125 #ifdef CONFIG_8139TOO_PIO
126 #define USE_IO_OPS 1
127 #endif
128
129 /* define to 1, 2 or 3 to enable copious debugging info */
130 #define RTL8139_DEBUG 0
131
132 /* define to 1 to disable lightweight runtime debugging checks */
133 #undef RTL8139_NDEBUG
134
135
136 #if RTL8139_DEBUG
137 /* note: prints function name for you */
138 # define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)
139 #else
140 # define DPRINTK(fmt, args...)
141 #endif
142
143 #ifdef RTL8139_NDEBUG
144 # define assert(expr) do {} while (0)
145 #else
146 # define assert(expr) \
147 if(unlikely(!(expr))) { \
148 printk(KERN_ERR "Assertion failed! %s,%s,%s,line=%d\n", \
149 #expr,__FILE__,__FUNCTION__,__LINE__); \
150 }
151 #endif
152
153
154 /* A few user-configurable values. */
155 /* media options */
156 #define MAX_UNITS 8
157 static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
158 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
159
160 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
161 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
162 static int multicast_filter_limit = 32;
163
164 /* bitmapped message enable number */
165 static int debug = -1;
166
167 /*
168 * Receive ring size
169 * Warning: 64K ring has hardware issues and may lock up.
170 */
171 #if defined(CONFIG_SH_DREAMCAST)
172 #define RX_BUF_IDX 1 /* 16K ring */
173 #else
174 #define RX_BUF_IDX 2 /* 32K ring */
175 #endif
176 #define RX_BUF_LEN (8192 << RX_BUF_IDX)
177 #define RX_BUF_PAD 16
178 #define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */
179
180 #if RX_BUF_LEN == 65536
181 #define RX_BUF_TOT_LEN RX_BUF_LEN
182 #else
183 #define RX_BUF_TOT_LEN (RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)
184 #endif
185
186 /* Number of Tx descriptor registers. */
187 #define NUM_TX_DESC 4
188
189 /* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/
190 #define MAX_ETH_FRAME_SIZE 1536
191
192 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
193 #define TX_BUF_SIZE MAX_ETH_FRAME_SIZE
194 #define TX_BUF_TOT_LEN (TX_BUF_SIZE * NUM_TX_DESC)
195
196 /* PCI Tuning Parameters
197 Threshold is bytes transferred to chip before transmission starts. */
198 #define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */
199
200 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
201 #define RX_FIFO_THRESH 7 /* Rx buffer level before first PCI xfer. */
202 #define RX_DMA_BURST 7 /* Maximum PCI burst, '6' is 1024 */
203 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
204 #define TX_RETRY 8 /* 0-15. retries = 16 + (TX_RETRY * 16) */
205
206 /* Operational parameters that usually are not changed. */
207 /* Time in jiffies before concluding the transmitter is hung. */
208 #define TX_TIMEOUT (6*HZ)
209
210
211 enum {
212 HAS_MII_XCVR = 0x010000,
213 HAS_CHIP_XCVR = 0x020000,
214 HAS_LNK_CHNG = 0x040000,
215 };
216
217 #define RTL_NUM_STATS 4 /* number of ETHTOOL_GSTATS u64's */
218 #define RTL_REGS_VER 1 /* version of reg. data in ETHTOOL_GREGS */
219 #define RTL_MIN_IO_SIZE 0x80
220 #define RTL8139B_IO_SIZE 256
221
222 #define RTL8129_CAPS HAS_MII_XCVR
223 #define RTL8139_CAPS HAS_CHIP_XCVR|HAS_LNK_CHNG
224
225 typedef enum {
226 RTL8139 = 0,
227 RTL8129,
228 } board_t;
229
230
231 /* indexed by board_t, above */
232 static struct {
233 const char *name;
234 u32 hw_flags;
235 } board_info[] __devinitdata = {
236 { "RealTek RTL8139", RTL8139_CAPS },
237 { "RealTek RTL8129", RTL8129_CAPS },
238 };
239
240
241 static struct pci_device_id rtl8139_pci_tbl[] = {
242 {0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
243 {0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
244 {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
245 {0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
246 {0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
247 {0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
248 {0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
249 {0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
250 {0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
251 {0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
252 {0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
253 {0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
254 {0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
255 {0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
256 {0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
257 {0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
258 {0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
259 {0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
260 {0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
261
262 #ifdef CONFIG_SH_SECUREEDGE5410
263 /* Bogus 8139 silicon reports 8129 without external PROM :-( */
264 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
265 #endif
266 #ifdef CONFIG_8139TOO_8129
267 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },
268 #endif
269
270 /* some crazy cards report invalid vendor ids like
271 * 0x0001 here. The other ids are valid and constant,
272 * so we simply don't match on the main vendor id.
273 */
274 {PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 },
275 {PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 },
276 {PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 },
277
278 {0,}
279 };
280 MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl);
281
282 static struct {
283 const char str[ETH_GSTRING_LEN];
284 } ethtool_stats_keys[] = {
285 { "early_rx" },
286 { "tx_buf_mapped" },
287 { "tx_timeouts" },
288 { "rx_lost_in_ring" },
289 };
290
291 /* The rest of these values should never change. */
292
293 /* Symbolic offsets to registers. */
294 enum RTL8139_registers {
295 MAC0 = 0, /* Ethernet hardware address. */
296 MAR0 = 8, /* Multicast filter. */
297 TxStatus0 = 0x10, /* Transmit status (Four 32bit registers). */
298 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
299 RxBuf = 0x30,
300 ChipCmd = 0x37,
301 RxBufPtr = 0x38,
302 RxBufAddr = 0x3A,
303 IntrMask = 0x3C,
304 IntrStatus = 0x3E,
305 TxConfig = 0x40,
306 RxConfig = 0x44,
307 Timer = 0x48, /* A general-purpose counter. */
308 RxMissed = 0x4C, /* 24 bits valid, write clears. */
309 Cfg9346 = 0x50,
310 Config0 = 0x51,
311 Config1 = 0x52,
312 FlashReg = 0x54,
313 MediaStatus = 0x58,
314 Config3 = 0x59,
315 Config4 = 0x5A, /* absent on RTL-8139A */
316 HltClk = 0x5B,
317 MultiIntr = 0x5C,
318 TxSummary = 0x60,
319 BasicModeCtrl = 0x62,
320 BasicModeStatus = 0x64,
321 NWayAdvert = 0x66,
322 NWayLPAR = 0x68,
323 NWayExpansion = 0x6A,
324 /* Undocumented registers, but required for proper operation. */
325 FIFOTMS = 0x70, /* FIFO Control and test. */
326 CSCR = 0x74, /* Chip Status and Configuration Register. */
327 PARA78 = 0x78,
328 PARA7c = 0x7c, /* Magic transceiver parameter register. */
329 Config5 = 0xD8, /* absent on RTL-8139A */
330 };
331
332 enum ClearBitMasks {
333 MultiIntrClear = 0xF000,
334 ChipCmdClear = 0xE2,
335 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
336 };
337
338 enum ChipCmdBits {
339 CmdReset = 0x10,
340 CmdRxEnb = 0x08,
341 CmdTxEnb = 0x04,
342 RxBufEmpty = 0x01,
343 };
344
345 /* Interrupt register bits, using my own meaningful names. */
346 enum IntrStatusBits {
347 PCIErr = 0x8000,
348 PCSTimeout = 0x4000,
349 RxFIFOOver = 0x40,
350 RxUnderrun = 0x20,
351 RxOverflow = 0x10,
352 TxErr = 0x08,
353 TxOK = 0x04,
354 RxErr = 0x02,
355 RxOK = 0x01,
356
357 RxAckBits = RxFIFOOver | RxOverflow | RxOK,
358 };
359
360 enum TxStatusBits {
361 TxHostOwns = 0x2000,
362 TxUnderrun = 0x4000,
363 TxStatOK = 0x8000,
364 TxOutOfWindow = 0x20000000,
365 TxAborted = 0x40000000,
366 TxCarrierLost = 0x80000000,
367 };
368 enum RxStatusBits {
369 RxMulticast = 0x8000,
370 RxPhysical = 0x4000,
371 RxBroadcast = 0x2000,
372 RxBadSymbol = 0x0020,
373 RxRunt = 0x0010,
374 RxTooLong = 0x0008,
375 RxCRCErr = 0x0004,
376 RxBadAlign = 0x0002,
377 RxStatusOK = 0x0001,
378 };
379
380 /* Bits in RxConfig. */
381 enum rx_mode_bits {
382 AcceptErr = 0x20,
383 AcceptRunt = 0x10,
384 AcceptBroadcast = 0x08,
385 AcceptMulticast = 0x04,
386 AcceptMyPhys = 0x02,
387 AcceptAllPhys = 0x01,
388 };
389
390 /* Bits in TxConfig. */
391 enum tx_config_bits {
392
393 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
394 TxIFGShift = 24,
395 TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */
396 TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */
397 TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */
398 TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */
399
400 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
401 TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */
402 TxClearAbt = (1 << 0), /* Clear abort (WO) */
403 TxDMAShift = 8, /* DMA burst value (0-7) is shifted this many bits */
404 TxRetryShift = 4, /* TXRR value (0-15) is shifted this many bits */
405
406 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
407 };
408
409 /* Bits in Config1 */
410 enum Config1Bits {
411 Cfg1_PM_Enable = 0x01,
412 Cfg1_VPD_Enable = 0x02,
413 Cfg1_PIO = 0x04,
414 Cfg1_MMIO = 0x08,
415 LWAKE = 0x10, /* not on 8139, 8139A */
416 Cfg1_Driver_Load = 0x20,
417 Cfg1_LED0 = 0x40,
418 Cfg1_LED1 = 0x80,
419 SLEEP = (1 << 1), /* only on 8139, 8139A */
420 PWRDN = (1 << 0), /* only on 8139, 8139A */
421 };
422
423 /* Bits in Config3 */
424 enum Config3Bits {
425 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */
426 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */
427 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */
428 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */
429 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */
430 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */
431 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */
432 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
433 };
434
435 /* Bits in Config4 */
436 enum Config4Bits {
437 LWPTN = (1 << 2), /* not on 8139, 8139A */
438 };
439
440 /* Bits in Config5 */
441 enum Config5Bits {
442 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */
443 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */
444 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */
445 Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */
446 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */
447 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */
448 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */
449 };
450
451 enum RxConfigBits {
452 /* rx fifo threshold */
453 RxCfgFIFOShift = 13,
454 RxCfgFIFONone = (7 << RxCfgFIFOShift),
455
456 /* Max DMA burst */
457 RxCfgDMAShift = 8,
458 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
459
460 /* rx ring buffer length */
461 RxCfgRcv8K = 0,
462 RxCfgRcv16K = (1 << 11),
463 RxCfgRcv32K = (1 << 12),
464 RxCfgRcv64K = (1 << 11) | (1 << 12),
465
466 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
467 RxNoWrap = (1 << 7),
468 };
469
470 /* Twister tuning parameters from RealTek.
471 Completely undocumented, but required to tune bad links on some boards. */
472 enum CSCRBits {
473 CSCR_LinkOKBit = 0x0400,
474 CSCR_LinkChangeBit = 0x0800,
475 CSCR_LinkStatusBits = 0x0f000,
476 CSCR_LinkDownOffCmd = 0x003c0,
477 CSCR_LinkDownCmd = 0x0f3c0,
478 };
479
480 enum Cfg9346Bits {
481 Cfg9346_Lock = 0x00,
482 Cfg9346_Unlock = 0xC0,
483 };
484
485 typedef enum {
486 CH_8139 = 0,
487 CH_8139_K,
488 CH_8139A,
489 CH_8139A_G,
490 CH_8139B,
491 CH_8130,
492 CH_8139C,
493 CH_8100,
494 CH_8100B_8139D,
495 CH_8101,
496 } chip_t;
497
498 enum chip_flags {
499 HasHltClk = (1 << 0),
500 HasLWake = (1 << 1),
501 };
502
503 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
504 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)
505 #define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1)
506
507 /* directly indexed by chip_t, above */
508 const static struct {
509 const char *name;
510 u32 version; /* from RTL8139C/RTL8139D docs */
511 u32 flags;
512 } rtl_chip_info[] = {
513 { "RTL-8139",
514 HW_REVID(1, 0, 0, 0, 0, 0, 0),
515 HasHltClk,
516 },
517
518 { "RTL-8139 rev K",
519 HW_REVID(1, 1, 0, 0, 0, 0, 0),
520 HasHltClk,
521 },
522
523 { "RTL-8139A",
524 HW_REVID(1, 1, 1, 0, 0, 0, 0),
525 HasHltClk, /* XXX undocumented? */
526 },
527
528 { "RTL-8139A rev G",
529 HW_REVID(1, 1, 1, 0, 0, 1, 0),
530 HasHltClk, /* XXX undocumented? */
531 },
532
533 { "RTL-8139B",
534 HW_REVID(1, 1, 1, 1, 0, 0, 0),
535 HasLWake,
536 },
537
538 { "RTL-8130",
539 HW_REVID(1, 1, 1, 1, 1, 0, 0),
540 HasLWake,
541 },
542
543 { "RTL-8139C",
544 HW_REVID(1, 1, 1, 0, 1, 0, 0),
545 HasLWake,
546 },
547
548 { "RTL-8100",
549 HW_REVID(1, 1, 1, 1, 0, 1, 0),
550 HasLWake,
551 },
552
553 { "RTL-8100B/8139D",
554 HW_REVID(1, 1, 1, 0, 1, 0, 1),
555 HasLWake,
556 },
557
558 { "RTL-8101",
559 HW_REVID(1, 1, 1, 0, 1, 1, 1),
560 HasLWake,
561 },
562 };
563
564 struct rtl_extra_stats {
565 unsigned long early_rx;
566 unsigned long tx_buf_mapped;
567 unsigned long tx_timeouts;
568 unsigned long rx_lost_in_ring;
569 };
570
571 struct rtl8139_private {
572 void __iomem *mmio_addr;
573 int drv_flags;
574 struct pci_dev *pci_dev;
575 u32 msg_enable;
576 struct net_device_stats stats;
577 unsigned char *rx_ring;
578 unsigned int cur_rx; /* Index into the Rx buffer of next Rx pkt. */
579 unsigned int tx_flag;
580 unsigned long cur_tx;
581 unsigned long dirty_tx;
582 unsigned char *tx_buf[NUM_TX_DESC]; /* Tx bounce buffers */
583 unsigned char *tx_bufs; /* Tx bounce buffer region. */
584 dma_addr_t rx_ring_dma;
585 dma_addr_t tx_bufs_dma;
586 signed char phys[4]; /* MII device addresses. */
587 char twistie, twist_row, twist_col; /* Twister tune state. */
588 unsigned int default_port:4; /* Last dev->if_port value. */
589 spinlock_t lock;
590 spinlock_t rx_lock;
591 chip_t chipset;
592 pid_t thr_pid;
593 wait_queue_head_t thr_wait;
594 struct completion thr_exited;
595 u32 rx_config;
596 struct rtl_extra_stats xstats;
597 int time_to_die;
598 struct mii_if_info mii;
599 unsigned int regs_len;
600 unsigned long fifo_copy_timeout;
601 };
602
603 MODULE_AUTHOR ("Jeff Garzik <jgarzik@pobox.com>");
604 MODULE_DESCRIPTION ("RealTek RTL-8139 Fast Ethernet driver");
605 MODULE_LICENSE("GPL");
606 MODULE_VERSION(DRV_VERSION);
607
608 module_param(multicast_filter_limit, int, 0);
609 module_param_array(media, int, NULL, 0);
610 module_param_array(full_duplex, int, NULL, 0);
611 module_param(debug, int, 0);
612 MODULE_PARM_DESC (debug, "8139too bitmapped message enable number");
613 MODULE_PARM_DESC (multicast_filter_limit, "8139too maximum number of filtered multicast addresses");
614 MODULE_PARM_DESC (media, "8139too: Bits 4+9: force full duplex, bit 5: 100Mbps");
615 MODULE_PARM_DESC (full_duplex, "8139too: Force full duplex for board(s) (1)");
616
617 static int read_eeprom (void __iomem *ioaddr, int location, int addr_len);
618 static int rtl8139_open (struct net_device *dev);
619 static int mdio_read (struct net_device *dev, int phy_id, int location);
620 static void mdio_write (struct net_device *dev, int phy_id, int location,
621 int val);
622 static void rtl8139_start_thread(struct net_device *dev);
623 static void rtl8139_tx_timeout (struct net_device *dev);
624 static void rtl8139_init_ring (struct net_device *dev);
625 static int rtl8139_start_xmit (struct sk_buff *skb,
626 struct net_device *dev);
627 static int rtl8139_poll(struct net_device *dev, int *budget);
628 #ifdef CONFIG_NET_POLL_CONTROLLER
629 static void rtl8139_poll_controller(struct net_device *dev);
630 #endif
631 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance,
632 struct pt_regs *regs);
633 static int rtl8139_close (struct net_device *dev);
634 static int netdev_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
635 static struct net_device_stats *rtl8139_get_stats (struct net_device *dev);
636 static void rtl8139_set_rx_mode (struct net_device *dev);
637 static void __set_rx_mode (struct net_device *dev);
638 static void rtl8139_hw_start (struct net_device *dev);
639 static struct ethtool_ops rtl8139_ethtool_ops;
640
641 /* write MMIO register, with flush */
642 /* Flush avoids rtl8139 bug w/ posted MMIO writes */
643 #define RTL_W8_F(reg, val8) do { iowrite8 ((val8), ioaddr + (reg)); ioread8 (ioaddr + (reg)); } while (0)
644 #define RTL_W16_F(reg, val16) do { iowrite16 ((val16), ioaddr + (reg)); ioread16 (ioaddr + (reg)); } while (0)
645 #define RTL_W32_F(reg, val32) do { iowrite32 ((val32), ioaddr + (reg)); ioread32 (ioaddr + (reg)); } while (0)
646
647
648 #define MMIO_FLUSH_AUDIT_COMPLETE 1
649 #if MMIO_FLUSH_AUDIT_COMPLETE
650
651 /* write MMIO register */
652 #define RTL_W8(reg, val8) iowrite8 ((val8), ioaddr + (reg))
653 #define RTL_W16(reg, val16) iowrite16 ((val16), ioaddr + (reg))
654 #define RTL_W32(reg, val32) iowrite32 ((val32), ioaddr + (reg))
655
656 #else
657
658 /* write MMIO register, then flush */
659 #define RTL_W8 RTL_W8_F
660 #define RTL_W16 RTL_W16_F
661 #define RTL_W32 RTL_W32_F
662
663 #endif /* MMIO_FLUSH_AUDIT_COMPLETE */
664
665 /* read MMIO register */
666 #define RTL_R8(reg) ioread8 (ioaddr + (reg))
667 #define RTL_R16(reg) ioread16 (ioaddr + (reg))
668 #define RTL_R32(reg) ((unsigned long) ioread32 (ioaddr + (reg)))
669
670
671 static const u16 rtl8139_intr_mask =
672 PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver |
673 TxErr | TxOK | RxErr | RxOK;
674
675 static const u16 rtl8139_norx_intr_mask =
676 PCIErr | PCSTimeout | RxUnderrun |
677 TxErr | TxOK | RxErr ;
678
679 #if RX_BUF_IDX == 0
680 static const unsigned int rtl8139_rx_config =
681 RxCfgRcv8K | RxNoWrap |
682 (RX_FIFO_THRESH << RxCfgFIFOShift) |
683 (RX_DMA_BURST << RxCfgDMAShift);
684 #elif RX_BUF_IDX == 1
685 static const unsigned int rtl8139_rx_config =
686 RxCfgRcv16K | RxNoWrap |
687 (RX_FIFO_THRESH << RxCfgFIFOShift) |
688 (RX_DMA_BURST << RxCfgDMAShift);
689 #elif RX_BUF_IDX == 2
690 static const unsigned int rtl8139_rx_config =
691 RxCfgRcv32K | RxNoWrap |
692 (RX_FIFO_THRESH << RxCfgFIFOShift) |
693 (RX_DMA_BURST << RxCfgDMAShift);
694 #elif RX_BUF_IDX == 3
695 static const unsigned int rtl8139_rx_config =
696 RxCfgRcv64K |
697 (RX_FIFO_THRESH << RxCfgFIFOShift) |
698 (RX_DMA_BURST << RxCfgDMAShift);
699 #else
700 #error "Invalid configuration for 8139_RXBUF_IDX"
701 #endif
702
703 static const unsigned int rtl8139_tx_config =
704 TxIFG96 | (TX_DMA_BURST << TxDMAShift) | (TX_RETRY << TxRetryShift);
705
706 static void __rtl8139_cleanup_dev (struct net_device *dev)
707 {
708 struct rtl8139_private *tp = netdev_priv(dev);
709 struct pci_dev *pdev;
710
711 assert (dev != NULL);
712 assert (tp->pci_dev != NULL);
713 pdev = tp->pci_dev;
714
715 #ifdef USE_IO_OPS
716 if (tp->mmio_addr)
717 ioport_unmap (tp->mmio_addr);
718 #else
719 if (tp->mmio_addr)
720 pci_iounmap (pdev, tp->mmio_addr);
721 #endif /* USE_IO_OPS */
722
723 /* it's ok to call this even if we have no regions to free */
724 pci_release_regions (pdev);
725
726 free_netdev(dev);
727 pci_set_drvdata (pdev, NULL);
728 }
729
730
731 static void rtl8139_chip_reset (void __iomem *ioaddr)
732 {
733 int i;
734
735 /* Soft reset the chip. */
736 RTL_W8 (ChipCmd, CmdReset);
737
738 /* Check that the chip has finished the reset. */
739 for (i = 1000; i > 0; i--) {
740 barrier();
741 if ((RTL_R8 (ChipCmd) & CmdReset) == 0)
742 break;
743 udelay (10);
744 }
745 }
746
747
748 static int __devinit rtl8139_init_board (struct pci_dev *pdev,
749 struct net_device **dev_out)
750 {
751 void __iomem *ioaddr;
752 struct net_device *dev;
753 struct rtl8139_private *tp;
754 u8 tmp8;
755 int rc, disable_dev_on_err = 0;
756 unsigned int i;
757 unsigned long pio_start, pio_end, pio_flags, pio_len;
758 unsigned long mmio_start, mmio_end, mmio_flags, mmio_len;
759 u32 version;
760
761 assert (pdev != NULL);
762
763 *dev_out = NULL;
764
765 /* dev and priv zeroed in alloc_etherdev */
766 dev = alloc_etherdev (sizeof (*tp));
767 if (dev == NULL) {
768 printk (KERN_ERR PFX "%s: Unable to alloc new net device\n", pci_name(pdev));
769 return -ENOMEM;
770 }
771 SET_MODULE_OWNER(dev);
772 SET_NETDEV_DEV(dev, &pdev->dev);
773
774 tp = netdev_priv(dev);
775 tp->pci_dev = pdev;
776
777 /* enable device (incl. PCI PM wakeup and hotplug setup) */
778 rc = pci_enable_device (pdev);
779 if (rc)
780 goto err_out;
781
782 pio_start = pci_resource_start (pdev, 0);
783 pio_end = pci_resource_end (pdev, 0);
784 pio_flags = pci_resource_flags (pdev, 0);
785 pio_len = pci_resource_len (pdev, 0);
786
787 mmio_start = pci_resource_start (pdev, 1);
788 mmio_end = pci_resource_end (pdev, 1);
789 mmio_flags = pci_resource_flags (pdev, 1);
790 mmio_len = pci_resource_len (pdev, 1);
791
792 /* set this immediately, we need to know before
793 * we talk to the chip directly */
794 DPRINTK("PIO region size == 0x%02X\n", pio_len);
795 DPRINTK("MMIO region size == 0x%02lX\n", mmio_len);
796
797 #ifdef USE_IO_OPS
798 /* make sure PCI base addr 0 is PIO */
799 if (!(pio_flags & IORESOURCE_IO)) {
800 printk (KERN_ERR PFX "%s: region #0 not a PIO resource, aborting\n", pci_name(pdev));
801 rc = -ENODEV;
802 goto err_out;
803 }
804 /* check for weird/broken PCI region reporting */
805 if (pio_len < RTL_MIN_IO_SIZE) {
806 printk (KERN_ERR PFX "%s: Invalid PCI I/O region size(s), aborting\n", pci_name(pdev));
807 rc = -ENODEV;
808 goto err_out;
809 }
810 #else
811 /* make sure PCI base addr 1 is MMIO */
812 if (!(mmio_flags & IORESOURCE_MEM)) {
813 printk (KERN_ERR PFX "%s: region #1 not an MMIO resource, aborting\n", pci_name(pdev));
814 rc = -ENODEV;
815 goto err_out;
816 }
817 if (mmio_len < RTL_MIN_IO_SIZE) {
818 printk (KERN_ERR PFX "%s: Invalid PCI mem region size(s), aborting\n", pci_name(pdev));
819 rc = -ENODEV;
820 goto err_out;
821 }
822 #endif
823
824 rc = pci_request_regions (pdev, "8139too");
825 if (rc)
826 goto err_out;
827 disable_dev_on_err = 1;
828
829 /* enable PCI bus-mastering */
830 pci_set_master (pdev);
831
832 #ifdef USE_IO_OPS
833 ioaddr = ioport_map(pio_start, pio_len);
834 if (!ioaddr) {
835 printk (KERN_ERR PFX "%s: cannot map PIO, aborting\n", pci_name(pdev));
836 rc = -EIO;
837 goto err_out;
838 }
839 dev->base_addr = pio_start;
840 tp->mmio_addr = ioaddr;
841 tp->regs_len = pio_len;
842 #else
843 /* ioremap MMIO region */
844 ioaddr = pci_iomap(pdev, 1, 0);
845 if (ioaddr == NULL) {
846 printk (KERN_ERR PFX "%s: cannot remap MMIO, aborting\n", pci_name(pdev));
847 rc = -EIO;
848 goto err_out;
849 }
850 dev->base_addr = (long) ioaddr;
851 tp->mmio_addr = ioaddr;
852 tp->regs_len = mmio_len;
853 #endif /* USE_IO_OPS */
854
855 /* Bring old chips out of low-power mode. */
856 RTL_W8 (HltClk, 'R');
857
858 /* check for missing/broken hardware */
859 if (RTL_R32 (TxConfig) == 0xFFFFFFFF) {
860 printk (KERN_ERR PFX "%s: Chip not responding, ignoring board\n",
861 pci_name(pdev));
862 rc = -EIO;
863 goto err_out;
864 }
865
866 /* identify chip attached to board */
867 version = RTL_R32 (TxConfig) & HW_REVID_MASK;
868 for (i = 0; i < ARRAY_SIZE (rtl_chip_info); i++)
869 if (version == rtl_chip_info[i].version) {
870 tp->chipset = i;
871 goto match;
872 }
873
874 /* if unknown chip, assume array element #0, original RTL-8139 in this case */
875 printk (KERN_DEBUG PFX "%s: unknown chip version, assuming RTL-8139\n",
876 pci_name(pdev));
877 printk (KERN_DEBUG PFX "%s: TxConfig = 0x%lx\n", pci_name(pdev), RTL_R32 (TxConfig));
878 tp->chipset = 0;
879
880 match:
881 DPRINTK ("chipset id (%d) == index %d, '%s'\n",
882 version, i, rtl_chip_info[i].name);
883
884 if (tp->chipset >= CH_8139B) {
885 u8 new_tmp8 = tmp8 = RTL_R8 (Config1);
886 DPRINTK("PCI PM wakeup\n");
887 if ((rtl_chip_info[tp->chipset].flags & HasLWake) &&
888 (tmp8 & LWAKE))
889 new_tmp8 &= ~LWAKE;
890 new_tmp8 |= Cfg1_PM_Enable;
891 if (new_tmp8 != tmp8) {
892 RTL_W8 (Cfg9346, Cfg9346_Unlock);
893 RTL_W8 (Config1, tmp8);
894 RTL_W8 (Cfg9346, Cfg9346_Lock);
895 }
896 if (rtl_chip_info[tp->chipset].flags & HasLWake) {
897 tmp8 = RTL_R8 (Config4);
898 if (tmp8 & LWPTN) {
899 RTL_W8 (Cfg9346, Cfg9346_Unlock);
900 RTL_W8 (Config4, tmp8 & ~LWPTN);
901 RTL_W8 (Cfg9346, Cfg9346_Lock);
902 }
903 }
904 } else {
905 DPRINTK("Old chip wakeup\n");
906 tmp8 = RTL_R8 (Config1);
907 tmp8 &= ~(SLEEP | PWRDN);
908 RTL_W8 (Config1, tmp8);
909 }
910
911 rtl8139_chip_reset (ioaddr);
912
913 *dev_out = dev;
914 return 0;
915
916 err_out:
917 __rtl8139_cleanup_dev (dev);
918 if (disable_dev_on_err)
919 pci_disable_device (pdev);
920 return rc;
921 }
922
923
924 static int __devinit rtl8139_init_one (struct pci_dev *pdev,
925 const struct pci_device_id *ent)
926 {
927 struct net_device *dev = NULL;
928 struct rtl8139_private *tp;
929 int i, addr_len, option;
930 void __iomem *ioaddr;
931 static int board_idx = -1;
932 u8 pci_rev;
933
934 assert (pdev != NULL);
935 assert (ent != NULL);
936
937 board_idx++;
938
939 /* when we're built into the kernel, the driver version message
940 * is only printed if at least one 8139 board has been found
941 */
942 #ifndef MODULE
943 {
944 static int printed_version;
945 if (!printed_version++)
946 printk (KERN_INFO RTL8139_DRIVER_NAME "\n");
947 }
948 #endif
949
950 pci_read_config_byte(pdev, PCI_REVISION_ID, &pci_rev);
951
952 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
953 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pci_rev >= 0x20) {
954 printk(KERN_INFO PFX "pci dev %s (id %04x:%04x rev %02x) is an enhanced 8139C+ chip\n",
955 pci_name(pdev), pdev->vendor, pdev->device, pci_rev);
956 printk(KERN_INFO PFX "Use the \"8139cp\" driver for improved performance and stability.\n");
957 }
958
959 i = rtl8139_init_board (pdev, &dev);
960 if (i < 0)
961 return i;
962
963 assert (dev != NULL);
964 tp = netdev_priv(dev);
965
966 ioaddr = tp->mmio_addr;
967 assert (ioaddr != NULL);
968
969 addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6;
970 for (i = 0; i < 3; i++)
971 ((u16 *) (dev->dev_addr))[i] =
972 le16_to_cpu (read_eeprom (ioaddr, i + 7, addr_len));
973
974 /* The Rtl8139-specific entries in the device structure. */
975 dev->open = rtl8139_open;
976 dev->hard_start_xmit = rtl8139_start_xmit;
977 dev->poll = rtl8139_poll;
978 dev->weight = 64;
979 dev->stop = rtl8139_close;
980 dev->get_stats = rtl8139_get_stats;
981 dev->set_multicast_list = rtl8139_set_rx_mode;
982 dev->do_ioctl = netdev_ioctl;
983 dev->ethtool_ops = &rtl8139_ethtool_ops;
984 dev->tx_timeout = rtl8139_tx_timeout;
985 dev->watchdog_timeo = TX_TIMEOUT;
986 #ifdef CONFIG_NET_POLL_CONTROLLER
987 dev->poll_controller = rtl8139_poll_controller;
988 #endif
989
990 /* note: the hardware is not capable of sg/csum/highdma, however
991 * through the use of skb_copy_and_csum_dev we enable these
992 * features
993 */
994 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA;
995
996 dev->irq = pdev->irq;
997
998 /* tp zeroed and aligned in alloc_etherdev */
999 tp = netdev_priv(dev);
1000
1001 /* note: tp->chipset set in rtl8139_init_board */
1002 tp->drv_flags = board_info[ent->driver_data].hw_flags;
1003 tp->mmio_addr = ioaddr;
1004 tp->msg_enable =
1005 (debug < 0 ? RTL8139_DEF_MSG_ENABLE : ((1 << debug) - 1));
1006 spin_lock_init (&tp->lock);
1007 spin_lock_init (&tp->rx_lock);
1008 init_waitqueue_head (&tp->thr_wait);
1009 init_completion (&tp->thr_exited);
1010 tp->mii.dev = dev;
1011 tp->mii.mdio_read = mdio_read;
1012 tp->mii.mdio_write = mdio_write;
1013 tp->mii.phy_id_mask = 0x3f;
1014 tp->mii.reg_num_mask = 0x1f;
1015
1016 /* dev is fully set up and ready to use now */
1017 DPRINTK("about to register device named %s (%p)...\n", dev->name, dev);
1018 i = register_netdev (dev);
1019 if (i) goto err_out;
1020
1021 pci_set_drvdata (pdev, dev);
1022
1023 printk (KERN_INFO "%s: %s at 0x%lx, "
1024 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
1025 "IRQ %d\n",
1026 dev->name,
1027 board_info[ent->driver_data].name,
1028 dev->base_addr,
1029 dev->dev_addr[0], dev->dev_addr[1],
1030 dev->dev_addr[2], dev->dev_addr[3],
1031 dev->dev_addr[4], dev->dev_addr[5],
1032 dev->irq);
1033
1034 printk (KERN_DEBUG "%s: Identified 8139 chip type '%s'\n",
1035 dev->name, rtl_chip_info[tp->chipset].name);
1036
1037 /* Find the connected MII xcvrs.
1038 Doing this in open() would allow detecting external xcvrs later, but
1039 takes too much time. */
1040 #ifdef CONFIG_8139TOO_8129
1041 if (tp->drv_flags & HAS_MII_XCVR) {
1042 int phy, phy_idx = 0;
1043 for (phy = 0; phy < 32 && phy_idx < sizeof(tp->phys); phy++) {
1044 int mii_status = mdio_read(dev, phy, 1);
1045 if (mii_status != 0xffff && mii_status != 0x0000) {
1046 u16 advertising = mdio_read(dev, phy, 4);
1047 tp->phys[phy_idx++] = phy;
1048 printk(KERN_INFO "%s: MII transceiver %d status 0x%4.4x "
1049 "advertising %4.4x.\n",
1050 dev->name, phy, mii_status, advertising);
1051 }
1052 }
1053 if (phy_idx == 0) {
1054 printk(KERN_INFO "%s: No MII transceivers found! Assuming SYM "
1055 "transceiver.\n",
1056 dev->name);
1057 tp->phys[0] = 32;
1058 }
1059 } else
1060 #endif
1061 tp->phys[0] = 32;
1062 tp->mii.phy_id = tp->phys[0];
1063
1064 /* The lower four bits are the media type. */
1065 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];
1066 if (option > 0) {
1067 tp->mii.full_duplex = (option & 0x210) ? 1 : 0;
1068 tp->default_port = option & 0xFF;
1069 if (tp->default_port)
1070 tp->mii.force_media = 1;
1071 }
1072 if (board_idx < MAX_UNITS && full_duplex[board_idx] > 0)
1073 tp->mii.full_duplex = full_duplex[board_idx];
1074 if (tp->mii.full_duplex) {
1075 printk(KERN_INFO "%s: Media type forced to Full Duplex.\n", dev->name);
1076 /* Changing the MII-advertised media because might prevent
1077 re-connection. */
1078 tp->mii.force_media = 1;
1079 }
1080 if (tp->default_port) {
1081 printk(KERN_INFO " Forcing %dMbps %s-duplex operation.\n",
1082 (option & 0x20 ? 100 : 10),
1083 (option & 0x10 ? "full" : "half"));
1084 mdio_write(dev, tp->phys[0], 0,
1085 ((option & 0x20) ? 0x2000 : 0) | /* 100Mbps? */
1086 ((option & 0x10) ? 0x0100 : 0)); /* Full duplex? */
1087 }
1088
1089 /* Put the chip into low-power mode. */
1090 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1091 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */
1092
1093 return 0;
1094
1095 err_out:
1096 __rtl8139_cleanup_dev (dev);
1097 pci_disable_device (pdev);
1098 return i;
1099 }
1100
1101
1102 static void __devexit rtl8139_remove_one (struct pci_dev *pdev)
1103 {
1104 struct net_device *dev = pci_get_drvdata (pdev);
1105
1106 assert (dev != NULL);
1107
1108 unregister_netdev (dev);
1109
1110 __rtl8139_cleanup_dev (dev);
1111 pci_disable_device (pdev);
1112 }
1113
1114
1115 /* Serial EEPROM section. */
1116
1117 /* EEPROM_Ctrl bits. */
1118 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1119 #define EE_CS 0x08 /* EEPROM chip select. */
1120 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1121 #define EE_WRITE_0 0x00
1122 #define EE_WRITE_1 0x02
1123 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1124 #define EE_ENB (0x80 | EE_CS)
1125
1126 /* Delay between EEPROM clock transitions.
1127 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1128 */
1129
1130 #define eeprom_delay() RTL_R32(Cfg9346)
1131
1132 /* The EEPROM commands include the alway-set leading bit. */
1133 #define EE_WRITE_CMD (5)
1134 #define EE_READ_CMD (6)
1135 #define EE_ERASE_CMD (7)
1136
1137 static int __devinit read_eeprom (void __iomem *ioaddr, int location, int addr_len)
1138 {
1139 int i;
1140 unsigned retval = 0;
1141 int read_cmd = location | (EE_READ_CMD << addr_len);
1142
1143 RTL_W8 (Cfg9346, EE_ENB & ~EE_CS);
1144 RTL_W8 (Cfg9346, EE_ENB);
1145 eeprom_delay ();
1146
1147 /* Shift the read command bits out. */
1148 for (i = 4 + addr_len; i >= 0; i--) {
1149 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1150 RTL_W8 (Cfg9346, EE_ENB | dataval);
1151 eeprom_delay ();
1152 RTL_W8 (Cfg9346, EE_ENB | dataval | EE_SHIFT_CLK);
1153 eeprom_delay ();
1154 }
1155 RTL_W8 (Cfg9346, EE_ENB);
1156 eeprom_delay ();
1157
1158 for (i = 16; i > 0; i--) {
1159 RTL_W8 (Cfg9346, EE_ENB | EE_SHIFT_CLK);
1160 eeprom_delay ();
1161 retval =
1162 (retval << 1) | ((RTL_R8 (Cfg9346) & EE_DATA_READ) ? 1 :
1163 0);
1164 RTL_W8 (Cfg9346, EE_ENB);
1165 eeprom_delay ();
1166 }
1167
1168 /* Terminate the EEPROM access. */
1169 RTL_W8 (Cfg9346, ~EE_CS);
1170 eeprom_delay ();
1171
1172 return retval;
1173 }
1174
1175 /* MII serial management: mostly bogus for now. */
1176 /* Read and write the MII management registers using software-generated
1177 serial MDIO protocol.
1178 The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
1179 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
1180 "overclocking" issues. */
1181 #define MDIO_DIR 0x80
1182 #define MDIO_DATA_OUT 0x04
1183 #define MDIO_DATA_IN 0x02
1184 #define MDIO_CLK 0x01
1185 #define MDIO_WRITE0 (MDIO_DIR)
1186 #define MDIO_WRITE1 (MDIO_DIR | MDIO_DATA_OUT)
1187
1188 #define mdio_delay() RTL_R8(Config4)
1189
1190
1191 static char mii_2_8139_map[8] = {
1192 BasicModeCtrl,
1193 BasicModeStatus,
1194 0,
1195 0,
1196 NWayAdvert,
1197 NWayLPAR,
1198 NWayExpansion,
1199 0
1200 };
1201
1202
1203 #ifdef CONFIG_8139TOO_8129
1204 /* Syncronize the MII management interface by shifting 32 one bits out. */
1205 static void mdio_sync (void __iomem *ioaddr)
1206 {
1207 int i;
1208
1209 for (i = 32; i >= 0; i--) {
1210 RTL_W8 (Config4, MDIO_WRITE1);
1211 mdio_delay ();
1212 RTL_W8 (Config4, MDIO_WRITE1 | MDIO_CLK);
1213 mdio_delay ();
1214 }
1215 }
1216 #endif
1217
1218 static int mdio_read (struct net_device *dev, int phy_id, int location)
1219 {
1220 struct rtl8139_private *tp = netdev_priv(dev);
1221 int retval = 0;
1222 #ifdef CONFIG_8139TOO_8129
1223 void __iomem *ioaddr = tp->mmio_addr;
1224 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
1225 int i;
1226 #endif
1227
1228 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1229 void __iomem *ioaddr = tp->mmio_addr;
1230 return location < 8 && mii_2_8139_map[location] ?
1231 RTL_R16 (mii_2_8139_map[location]) : 0;
1232 }
1233
1234 #ifdef CONFIG_8139TOO_8129
1235 mdio_sync (ioaddr);
1236 /* Shift the read command bits out. */
1237 for (i = 15; i >= 0; i--) {
1238 int dataval = (mii_cmd & (1 << i)) ? MDIO_DATA_OUT : 0;
1239
1240 RTL_W8 (Config4, MDIO_DIR | dataval);
1241 mdio_delay ();
1242 RTL_W8 (Config4, MDIO_DIR | dataval | MDIO_CLK);
1243 mdio_delay ();
1244 }
1245
1246 /* Read the two transition, 16 data, and wire-idle bits. */
1247 for (i = 19; i > 0; i--) {
1248 RTL_W8 (Config4, 0);
1249 mdio_delay ();
1250 retval = (retval << 1) | ((RTL_R8 (Config4) & MDIO_DATA_IN) ? 1 : 0);
1251 RTL_W8 (Config4, MDIO_CLK);
1252 mdio_delay ();
1253 }
1254 #endif
1255
1256 return (retval >> 1) & 0xffff;
1257 }
1258
1259
1260 static void mdio_write (struct net_device *dev, int phy_id, int location,
1261 int value)
1262 {
1263 struct rtl8139_private *tp = netdev_priv(dev);
1264 #ifdef CONFIG_8139TOO_8129
1265 void __iomem *ioaddr = tp->mmio_addr;
1266 int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location << 18) | value;
1267 int i;
1268 #endif
1269
1270 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1271 void __iomem *ioaddr = tp->mmio_addr;
1272 if (location == 0) {
1273 RTL_W8 (Cfg9346, Cfg9346_Unlock);
1274 RTL_W16 (BasicModeCtrl, value);
1275 RTL_W8 (Cfg9346, Cfg9346_Lock);
1276 } else if (location < 8 && mii_2_8139_map[location])
1277 RTL_W16 (mii_2_8139_map[location], value);
1278 return;
1279 }
1280
1281 #ifdef CONFIG_8139TOO_8129
1282 mdio_sync (ioaddr);
1283
1284 /* Shift the command bits out. */
1285 for (i = 31; i >= 0; i--) {
1286 int dataval =
1287 (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
1288 RTL_W8 (Config4, dataval);
1289 mdio_delay ();
1290 RTL_W8 (Config4, dataval | MDIO_CLK);
1291 mdio_delay ();
1292 }
1293 /* Clear out extra bits. */
1294 for (i = 2; i > 0; i--) {
1295 RTL_W8 (Config4, 0);
1296 mdio_delay ();
1297 RTL_W8 (Config4, MDIO_CLK);
1298 mdio_delay ();
1299 }
1300 #endif
1301 }
1302
1303
1304 static int rtl8139_open (struct net_device *dev)
1305 {
1306 struct rtl8139_private *tp = netdev_priv(dev);
1307 int retval;
1308 void __iomem *ioaddr = tp->mmio_addr;
1309
1310 retval = request_irq (dev->irq, rtl8139_interrupt, SA_SHIRQ, dev->name, dev);
1311 if (retval)
1312 return retval;
1313
1314 tp->tx_bufs = pci_alloc_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
1315 &tp->tx_bufs_dma);
1316 tp->rx_ring = pci_alloc_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
1317 &tp->rx_ring_dma);
1318 if (tp->tx_bufs == NULL || tp->rx_ring == NULL) {
1319 free_irq(dev->irq, dev);
1320
1321 if (tp->tx_bufs)
1322 pci_free_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
1323 tp->tx_bufs, tp->tx_bufs_dma);
1324 if (tp->rx_ring)
1325 pci_free_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
1326 tp->rx_ring, tp->rx_ring_dma);
1327
1328 return -ENOMEM;
1329
1330 }
1331
1332 tp->mii.full_duplex = tp->mii.force_media;
1333 tp->tx_flag = (TX_FIFO_THRESH << 11) & 0x003f0000;
1334
1335 rtl8139_init_ring (dev);
1336 rtl8139_hw_start (dev);
1337 netif_start_queue (dev);
1338
1339 if (netif_msg_ifup(tp))
1340 printk(KERN_DEBUG "%s: rtl8139_open() ioaddr %#lx IRQ %d"
1341 " GP Pins %2.2x %s-duplex.\n",
1342 dev->name, pci_resource_start (tp->pci_dev, 1),
1343 dev->irq, RTL_R8 (MediaStatus),
1344 tp->mii.full_duplex ? "full" : "half");
1345
1346 rtl8139_start_thread(dev);
1347
1348 return 0;
1349 }
1350
1351
1352 static void rtl_check_media (struct net_device *dev, unsigned int init_media)
1353 {
1354 struct rtl8139_private *tp = netdev_priv(dev);
1355
1356 if (tp->phys[0] >= 0) {
1357 mii_check_media(&tp->mii, netif_msg_link(tp), init_media);
1358 }
1359 }
1360
1361 /* Start the hardware at open or resume. */
1362 static void rtl8139_hw_start (struct net_device *dev)
1363 {
1364 struct rtl8139_private *tp = netdev_priv(dev);
1365 void __iomem *ioaddr = tp->mmio_addr;
1366 u32 i;
1367 u8 tmp;
1368
1369 /* Bring old chips out of low-power mode. */
1370 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1371 RTL_W8 (HltClk, 'R');
1372
1373 rtl8139_chip_reset (ioaddr);
1374
1375 /* unlock Config[01234] and BMCR register writes */
1376 RTL_W8_F (Cfg9346, Cfg9346_Unlock);
1377 /* Restore our idea of the MAC address. */
1378 RTL_W32_F (MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0)));
1379 RTL_W32_F (MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4)));
1380
1381 /* Must enable Tx/Rx before setting transfer thresholds! */
1382 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1383
1384 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
1385 RTL_W32 (RxConfig, tp->rx_config);
1386 RTL_W32 (TxConfig, rtl8139_tx_config);
1387
1388 tp->cur_rx = 0;
1389
1390 rtl_check_media (dev, 1);
1391
1392 if (tp->chipset >= CH_8139B) {
1393 /* Disable magic packet scanning, which is enabled
1394 * when PM is enabled in Config1. It can be reenabled
1395 * via ETHTOOL_SWOL if desired. */
1396 RTL_W8 (Config3, RTL_R8 (Config3) & ~Cfg3_Magic);
1397 }
1398
1399 DPRINTK("init buffer addresses\n");
1400
1401 /* Lock Config[01234] and BMCR register writes */
1402 RTL_W8 (Cfg9346, Cfg9346_Lock);
1403
1404 /* init Rx ring buffer DMA address */
1405 RTL_W32_F (RxBuf, tp->rx_ring_dma);
1406
1407 /* init Tx buffer DMA addresses */
1408 for (i = 0; i < NUM_TX_DESC; i++)
1409 RTL_W32_F (TxAddr0 + (i * 4), tp->tx_bufs_dma + (tp->tx_buf[i] - tp->tx_bufs));
1410
1411 RTL_W32 (RxMissed, 0);
1412
1413 rtl8139_set_rx_mode (dev);
1414
1415 /* no early-rx interrupts */
1416 RTL_W16 (MultiIntr, RTL_R16 (MultiIntr) & MultiIntrClear);
1417
1418 /* make sure RxTx has started */
1419 tmp = RTL_R8 (ChipCmd);
1420 if ((!(tmp & CmdRxEnb)) || (!(tmp & CmdTxEnb)))
1421 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1422
1423 /* Enable all known interrupts by setting the interrupt mask. */
1424 RTL_W16 (IntrMask, rtl8139_intr_mask);
1425 }
1426
1427
1428 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1429 static void rtl8139_init_ring (struct net_device *dev)
1430 {
1431 struct rtl8139_private *tp = netdev_priv(dev);
1432 int i;
1433
1434 tp->cur_rx = 0;
1435 tp->cur_tx = 0;
1436 tp->dirty_tx = 0;
1437
1438 for (i = 0; i < NUM_TX_DESC; i++)
1439 tp->tx_buf[i] = &tp->tx_bufs[i * TX_BUF_SIZE];
1440 }
1441
1442
1443 /* This must be global for CONFIG_8139TOO_TUNE_TWISTER case */
1444 static int next_tick = 3 * HZ;
1445
1446 #ifndef CONFIG_8139TOO_TUNE_TWISTER
1447 static inline void rtl8139_tune_twister (struct net_device *dev,
1448 struct rtl8139_private *tp) {}
1449 #else
1450 enum TwisterParamVals {
1451 PARA78_default = 0x78fa8388,
1452 PARA7c_default = 0xcb38de43, /* param[0][3] */
1453 PARA7c_xxx = 0xcb38de43,
1454 };
1455
1456 static const unsigned long param[4][4] = {
1457 {0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43},
1458 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1459 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1460 {0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83}
1461 };
1462
1463 static void rtl8139_tune_twister (struct net_device *dev,
1464 struct rtl8139_private *tp)
1465 {
1466 int linkcase;
1467 void __iomem *ioaddr = tp->mmio_addr;
1468
1469 /* This is a complicated state machine to configure the "twister" for
1470 impedance/echos based on the cable length.
1471 All of this is magic and undocumented.
1472 */
1473 switch (tp->twistie) {
1474 case 1:
1475 if (RTL_R16 (CSCR) & CSCR_LinkOKBit) {
1476 /* We have link beat, let us tune the twister. */
1477 RTL_W16 (CSCR, CSCR_LinkDownOffCmd);
1478 tp->twistie = 2; /* Change to state 2. */
1479 next_tick = HZ / 10;
1480 } else {
1481 /* Just put in some reasonable defaults for when beat returns. */
1482 RTL_W16 (CSCR, CSCR_LinkDownCmd);
1483 RTL_W32 (FIFOTMS, 0x20); /* Turn on cable test mode. */
1484 RTL_W32 (PARA78, PARA78_default);
1485 RTL_W32 (PARA7c, PARA7c_default);
1486 tp->twistie = 0; /* Bail from future actions. */
1487 }
1488 break;
1489 case 2:
1490 /* Read how long it took to hear the echo. */
1491 linkcase = RTL_R16 (CSCR) & CSCR_LinkStatusBits;
1492 if (linkcase == 0x7000)
1493 tp->twist_row = 3;
1494 else if (linkcase == 0x3000)
1495 tp->twist_row = 2;
1496 else if (linkcase == 0x1000)
1497 tp->twist_row = 1;
1498 else
1499 tp->twist_row = 0;
1500 tp->twist_col = 0;
1501 tp->twistie = 3; /* Change to state 2. */
1502 next_tick = HZ / 10;
1503 break;
1504 case 3:
1505 /* Put out four tuning parameters, one per 100msec. */
1506 if (tp->twist_col == 0)
1507 RTL_W16 (FIFOTMS, 0);
1508 RTL_W32 (PARA7c, param[(int) tp->twist_row]
1509 [(int) tp->twist_col]);
1510 next_tick = HZ / 10;
1511 if (++tp->twist_col >= 4) {
1512 /* For short cables we are done.
1513 For long cables (row == 3) check for mistune. */
1514 tp->twistie =
1515 (tp->twist_row == 3) ? 4 : 0;
1516 }
1517 break;
1518 case 4:
1519 /* Special case for long cables: check for mistune. */
1520 if ((RTL_R16 (CSCR) &
1521 CSCR_LinkStatusBits) == 0x7000) {
1522 tp->twistie = 0;
1523 break;
1524 } else {
1525 RTL_W32 (PARA7c, 0xfb38de03);
1526 tp->twistie = 5;
1527 next_tick = HZ / 10;
1528 }
1529 break;
1530 case 5:
1531 /* Retune for shorter cable (column 2). */
1532 RTL_W32 (FIFOTMS, 0x20);
1533 RTL_W32 (PARA78, PARA78_default);
1534 RTL_W32 (PARA7c, PARA7c_default);
1535 RTL_W32 (FIFOTMS, 0x00);
1536 tp->twist_row = 2;
1537 tp->twist_col = 0;
1538 tp->twistie = 3;
1539 next_tick = HZ / 10;
1540 break;
1541
1542 default:
1543 /* do nothing */
1544 break;
1545 }
1546 }
1547 #endif /* CONFIG_8139TOO_TUNE_TWISTER */
1548
1549 static inline void rtl8139_thread_iter (struct net_device *dev,
1550 struct rtl8139_private *tp,
1551 void __iomem *ioaddr)
1552 {
1553 int mii_lpa;
1554
1555 mii_lpa = mdio_read (dev, tp->phys[0], MII_LPA);
1556
1557 if (!tp->mii.force_media && mii_lpa != 0xffff) {
1558 int duplex = (mii_lpa & LPA_100FULL)
1559 || (mii_lpa & 0x01C0) == 0x0040;
1560 if (tp->mii.full_duplex != duplex) {
1561 tp->mii.full_duplex = duplex;
1562
1563 if (mii_lpa) {
1564 printk (KERN_INFO
1565 "%s: Setting %s-duplex based on MII #%d link"
1566 " partner ability of %4.4x.\n",
1567 dev->name,
1568 tp->mii.full_duplex ? "full" : "half",
1569 tp->phys[0], mii_lpa);
1570 } else {
1571 printk(KERN_INFO"%s: media is unconnected, link down, or incompatible connection\n",
1572 dev->name);
1573 }
1574 #if 0
1575 RTL_W8 (Cfg9346, Cfg9346_Unlock);
1576 RTL_W8 (Config1, tp->mii.full_duplex ? 0x60 : 0x20);
1577 RTL_W8 (Cfg9346, Cfg9346_Lock);
1578 #endif
1579 }
1580 }
1581
1582 next_tick = HZ * 60;
1583
1584 rtl8139_tune_twister (dev, tp);
1585
1586 DPRINTK ("%s: Media selection tick, Link partner %4.4x.\n",
1587 dev->name, RTL_R16 (NWayLPAR));
1588 DPRINTK ("%s: Other registers are IntMask %4.4x IntStatus %4.4x\n",
1589 dev->name, RTL_R16 (IntrMask), RTL_R16 (IntrStatus));
1590 DPRINTK ("%s: Chip config %2.2x %2.2x.\n",
1591 dev->name, RTL_R8 (Config0),
1592 RTL_R8 (Config1));
1593 }
1594
1595 static int rtl8139_thread (void *data)
1596 {
1597 struct net_device *dev = data;
1598 struct rtl8139_private *tp = netdev_priv(dev);
1599 unsigned long timeout;
1600
1601 daemonize("%s", dev->name);
1602 allow_signal(SIGTERM);
1603
1604 while (1) {
1605 timeout = next_tick;
1606 do {
1607 timeout = interruptible_sleep_on_timeout (&tp->thr_wait, timeout);
1608 /* make swsusp happy with our thread */
1609 try_to_freeze();
1610 } while (!signal_pending (current) && (timeout > 0));
1611
1612 if (signal_pending (current)) {
1613 flush_signals(current);
1614 }
1615
1616 if (tp->time_to_die)
1617 break;
1618
1619 if (rtnl_lock_interruptible ())
1620 break;
1621 rtl8139_thread_iter (dev, tp, tp->mmio_addr);
1622 rtnl_unlock ();
1623 }
1624
1625 complete_and_exit (&tp->thr_exited, 0);
1626 }
1627
1628 static void rtl8139_start_thread(struct net_device *dev)
1629 {
1630 struct rtl8139_private *tp = netdev_priv(dev);
1631
1632 tp->thr_pid = -1;
1633 tp->twistie = 0;
1634 tp->time_to_die = 0;
1635 if (tp->chipset == CH_8139_K)
1636 tp->twistie = 1;
1637 else if (tp->drv_flags & HAS_LNK_CHNG)
1638 return;
1639
1640 tp->thr_pid = kernel_thread(rtl8139_thread, dev, CLONE_FS|CLONE_FILES);
1641 if (tp->thr_pid < 0) {
1642 printk (KERN_WARNING "%s: unable to start kernel thread\n",
1643 dev->name);
1644 }
1645 }
1646
1647 static inline void rtl8139_tx_clear (struct rtl8139_private *tp)
1648 {
1649 tp->cur_tx = 0;
1650 tp->dirty_tx = 0;
1651
1652 /* XXX account for unsent Tx packets in tp->stats.tx_dropped */
1653 }
1654
1655
1656 static void rtl8139_tx_timeout (struct net_device *dev)
1657 {
1658 struct rtl8139_private *tp = netdev_priv(dev);
1659 void __iomem *ioaddr = tp->mmio_addr;
1660 int i;
1661 u8 tmp8;
1662 unsigned long flags;
1663
1664 printk (KERN_DEBUG "%s: Transmit timeout, status %2.2x %4.4x %4.4x "
1665 "media %2.2x.\n", dev->name, RTL_R8 (ChipCmd),
1666 RTL_R16(IntrStatus), RTL_R16(IntrMask), RTL_R8(MediaStatus));
1667 /* Emit info to figure out what went wrong. */
1668 printk (KERN_DEBUG "%s: Tx queue start entry %ld dirty entry %ld.\n",
1669 dev->name, tp->cur_tx, tp->dirty_tx);
1670 for (i = 0; i < NUM_TX_DESC; i++)
1671 printk (KERN_DEBUG "%s: Tx descriptor %d is %8.8lx.%s\n",
1672 dev->name, i, RTL_R32 (TxStatus0 + (i * 4)),
1673 i == tp->dirty_tx % NUM_TX_DESC ?
1674 " (queue head)" : "");
1675
1676 tp->xstats.tx_timeouts++;
1677
1678 /* disable Tx ASAP, if not already */
1679 tmp8 = RTL_R8 (ChipCmd);
1680 if (tmp8 & CmdTxEnb)
1681 RTL_W8 (ChipCmd, CmdRxEnb);
1682
1683 spin_lock(&tp->rx_lock);
1684 /* Disable interrupts by clearing the interrupt mask. */
1685 RTL_W16 (IntrMask, 0x0000);
1686
1687 /* Stop a shared interrupt from scavenging while we are. */
1688 spin_lock_irqsave (&tp->lock, flags);
1689 rtl8139_tx_clear (tp);
1690 spin_unlock_irqrestore (&tp->lock, flags);
1691
1692 /* ...and finally, reset everything */
1693 if (netif_running(dev)) {
1694 rtl8139_hw_start (dev);
1695 netif_wake_queue (dev);
1696 }
1697 spin_unlock(&tp->rx_lock);
1698 }
1699
1700
1701 static int rtl8139_start_xmit (struct sk_buff *skb, struct net_device *dev)
1702 {
1703 struct rtl8139_private *tp = netdev_priv(dev);
1704 void __iomem *ioaddr = tp->mmio_addr;
1705 unsigned int entry;
1706 unsigned int len = skb->len;
1707
1708 /* Calculate the next Tx descriptor entry. */
1709 entry = tp->cur_tx % NUM_TX_DESC;
1710
1711 /* Note: the chip doesn't have auto-pad! */
1712 if (likely(len < TX_BUF_SIZE)) {
1713 if (len < ETH_ZLEN)
1714 memset(tp->tx_buf[entry], 0, ETH_ZLEN);
1715 skb_copy_and_csum_dev(skb, tp->tx_buf[entry]);
1716 dev_kfree_skb(skb);
1717 } else {
1718 dev_kfree_skb(skb);
1719 tp->stats.tx_dropped++;
1720 return 0;
1721 }
1722
1723 spin_lock_irq(&tp->lock);
1724 RTL_W32_F (TxStatus0 + (entry * sizeof (u32)),
1725 tp->tx_flag | max(len, (unsigned int)ETH_ZLEN));
1726
1727 dev->trans_start = jiffies;
1728
1729 tp->cur_tx++;
1730 wmb();
1731
1732 if ((tp->cur_tx - NUM_TX_DESC) == tp->dirty_tx)
1733 netif_stop_queue (dev);
1734 spin_unlock_irq(&tp->lock);
1735
1736 if (netif_msg_tx_queued(tp))
1737 printk (KERN_DEBUG "%s: Queued Tx packet size %u to slot %d.\n",
1738 dev->name, len, entry);
1739
1740 return 0;
1741 }
1742
1743
1744 static void rtl8139_tx_interrupt (struct net_device *dev,
1745 struct rtl8139_private *tp,
1746 void __iomem *ioaddr)
1747 {
1748 unsigned long dirty_tx, tx_left;
1749
1750 assert (dev != NULL);
1751 assert (ioaddr != NULL);
1752
1753 dirty_tx = tp->dirty_tx;
1754 tx_left = tp->cur_tx - dirty_tx;
1755 while (tx_left > 0) {
1756 int entry = dirty_tx % NUM_TX_DESC;
1757 int txstatus;
1758
1759 txstatus = RTL_R32 (TxStatus0 + (entry * sizeof (u32)));
1760
1761 if (!(txstatus & (TxStatOK | TxUnderrun | TxAborted)))
1762 break; /* It still hasn't been Txed */
1763
1764 /* Note: TxCarrierLost is always asserted at 100mbps. */
1765 if (txstatus & (TxOutOfWindow | TxAborted)) {
1766 /* There was an major error, log it. */
1767 if (netif_msg_tx_err(tp))
1768 printk(KERN_DEBUG "%s: Transmit error, Tx status %8.8x.\n",
1769 dev->name, txstatus);
1770 tp->stats.tx_errors++;
1771 if (txstatus & TxAborted) {
1772 tp->stats.tx_aborted_errors++;
1773 RTL_W32 (TxConfig, TxClearAbt);
1774 RTL_W16 (IntrStatus, TxErr);
1775 wmb();
1776 }
1777 if (txstatus & TxCarrierLost)
1778 tp->stats.tx_carrier_errors++;
1779 if (txstatus & TxOutOfWindow)
1780 tp->stats.tx_window_errors++;
1781 } else {
1782 if (txstatus & TxUnderrun) {
1783 /* Add 64 to the Tx FIFO threshold. */
1784 if (tp->tx_flag < 0x00300000)
1785 tp->tx_flag += 0x00020000;
1786 tp->stats.tx_fifo_errors++;
1787 }
1788 tp->stats.collisions += (txstatus >> 24) & 15;
1789 tp->stats.tx_bytes += txstatus & 0x7ff;
1790 tp->stats.tx_packets++;
1791 }
1792
1793 dirty_tx++;
1794 tx_left--;
1795 }
1796
1797 #ifndef RTL8139_NDEBUG
1798 if (tp->cur_tx - dirty_tx > NUM_TX_DESC) {
1799 printk (KERN_ERR "%s: Out-of-sync dirty pointer, %ld vs. %ld.\n",
1800 dev->name, dirty_tx, tp->cur_tx);
1801 dirty_tx += NUM_TX_DESC;
1802 }
1803 #endif /* RTL8139_NDEBUG */
1804
1805 /* only wake the queue if we did work, and the queue is stopped */
1806 if (tp->dirty_tx != dirty_tx) {
1807 tp->dirty_tx = dirty_tx;
1808 mb();
1809 netif_wake_queue (dev);
1810 }
1811 }
1812
1813
1814 /* TODO: clean this up! Rx reset need not be this intensive */
1815 static void rtl8139_rx_err (u32 rx_status, struct net_device *dev,
1816 struct rtl8139_private *tp, void __iomem *ioaddr)
1817 {
1818 u8 tmp8;
1819 #ifdef CONFIG_8139_OLD_RX_RESET
1820 int tmp_work;
1821 #endif
1822
1823 if (netif_msg_rx_err (tp))
1824 printk(KERN_DEBUG "%s: Ethernet frame had errors, status %8.8x.\n",
1825 dev->name, rx_status);
1826 tp->stats.rx_errors++;
1827 if (!(rx_status & RxStatusOK)) {
1828 if (rx_status & RxTooLong) {
1829 DPRINTK ("%s: Oversized Ethernet frame, status %4.4x!\n",
1830 dev->name, rx_status);
1831 /* A.C.: The chip hangs here. */
1832 }
1833 if (rx_status & (RxBadSymbol | RxBadAlign))
1834 tp->stats.rx_frame_errors++;
1835 if (rx_status & (RxRunt | RxTooLong))
1836 tp->stats.rx_length_errors++;
1837 if (rx_status & RxCRCErr)
1838 tp->stats.rx_crc_errors++;
1839 } else {
1840 tp->xstats.rx_lost_in_ring++;
1841 }
1842
1843 #ifndef CONFIG_8139_OLD_RX_RESET
1844 tmp8 = RTL_R8 (ChipCmd);
1845 RTL_W8 (ChipCmd, tmp8 & ~CmdRxEnb);
1846 RTL_W8 (ChipCmd, tmp8);
1847 RTL_W32 (RxConfig, tp->rx_config);
1848 tp->cur_rx = 0;
1849 #else
1850 /* Reset the receiver, based on RealTek recommendation. (Bug?) */
1851
1852 /* disable receive */
1853 RTL_W8_F (ChipCmd, CmdTxEnb);
1854 tmp_work = 200;
1855 while (--tmp_work > 0) {
1856 udelay(1);
1857 tmp8 = RTL_R8 (ChipCmd);
1858 if (!(tmp8 & CmdRxEnb))
1859 break;
1860 }
1861 if (tmp_work <= 0)
1862 printk (KERN_WARNING PFX "rx stop wait too long\n");
1863 /* restart receive */
1864 tmp_work = 200;
1865 while (--tmp_work > 0) {
1866 RTL_W8_F (ChipCmd, CmdRxEnb | CmdTxEnb);
1867 udelay(1);
1868 tmp8 = RTL_R8 (ChipCmd);
1869 if ((tmp8 & CmdRxEnb) && (tmp8 & CmdTxEnb))
1870 break;
1871 }
1872 if (tmp_work <= 0)
1873 printk (KERN_WARNING PFX "tx/rx enable wait too long\n");
1874
1875 /* and reinitialize all rx related registers */
1876 RTL_W8_F (Cfg9346, Cfg9346_Unlock);
1877 /* Must enable Tx/Rx before setting transfer thresholds! */
1878 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1879
1880 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
1881 RTL_W32 (RxConfig, tp->rx_config);
1882 tp->cur_rx = 0;
1883
1884 DPRINTK("init buffer addresses\n");
1885
1886 /* Lock Config[01234] and BMCR register writes */
1887 RTL_W8 (Cfg9346, Cfg9346_Lock);
1888
1889 /* init Rx ring buffer DMA address */
1890 RTL_W32_F (RxBuf, tp->rx_ring_dma);
1891
1892 /* A.C.: Reset the multicast list. */
1893 __set_rx_mode (dev);
1894 #endif
1895 }
1896
1897 #if RX_BUF_IDX == 3
1898 static __inline__ void wrap_copy(struct sk_buff *skb, const unsigned char *ring,
1899 u32 offset, unsigned int size)
1900 {
1901 u32 left = RX_BUF_LEN - offset;
1902
1903 if (size > left) {
1904 memcpy(skb->data, ring + offset, left);
1905 memcpy(skb->data+left, ring, size - left);
1906 } else
1907 memcpy(skb->data, ring + offset, size);
1908 }
1909 #endif
1910
1911 static void rtl8139_isr_ack(struct rtl8139_private *tp)
1912 {
1913 void __iomem *ioaddr = tp->mmio_addr;
1914 u16 status;
1915
1916 status = RTL_R16 (IntrStatus) & RxAckBits;
1917
1918 /* Clear out errors and receive interrupts */
1919 if (likely(status != 0)) {
1920 if (unlikely(status & (RxFIFOOver | RxOverflow))) {
1921 tp->stats.rx_errors++;
1922 if (status & RxFIFOOver)
1923 tp->stats.rx_fifo_errors++;
1924 }
1925 RTL_W16_F (IntrStatus, RxAckBits);
1926 }
1927 }
1928
1929 static int rtl8139_rx(struct net_device *dev, struct rtl8139_private *tp,
1930 int budget)
1931 {
1932 void __iomem *ioaddr = tp->mmio_addr;
1933 int received = 0;
1934 unsigned char *rx_ring = tp->rx_ring;
1935 unsigned int cur_rx = tp->cur_rx;
1936 unsigned int rx_size = 0;
1937
1938 DPRINTK ("%s: In rtl8139_rx(), current %4.4x BufAddr %4.4x,"
1939 " free to %4.4x, Cmd %2.2x.\n", dev->name, (u16)cur_rx,
1940 RTL_R16 (RxBufAddr),
1941 RTL_R16 (RxBufPtr), RTL_R8 (ChipCmd));
1942
1943 while (netif_running(dev) && received < budget
1944 && (RTL_R8 (ChipCmd) & RxBufEmpty) == 0) {
1945 u32 ring_offset = cur_rx % RX_BUF_LEN;
1946 u32 rx_status;
1947 unsigned int pkt_size;
1948 struct sk_buff *skb;
1949
1950 rmb();
1951
1952 /* read size+status of next frame from DMA ring buffer */
1953 rx_status = le32_to_cpu (*(u32 *) (rx_ring + ring_offset));
1954 rx_size = rx_status >> 16;
1955 pkt_size = rx_size - 4;
1956
1957 if (netif_msg_rx_status(tp))
1958 printk(KERN_DEBUG "%s: rtl8139_rx() status %4.4x, size %4.4x,"
1959 " cur %4.4x.\n", dev->name, rx_status,
1960 rx_size, cur_rx);
1961 #if RTL8139_DEBUG > 2
1962 {
1963 int i;
1964 DPRINTK ("%s: Frame contents ", dev->name);
1965 for (i = 0; i < 70; i++)
1966 printk (" %2.2x",
1967 rx_ring[ring_offset + i]);
1968 printk (".\n");
1969 }
1970 #endif
1971
1972 /* Packet copy from FIFO still in progress.
1973 * Theoretically, this should never happen
1974 * since EarlyRx is disabled.
1975 */
1976 if (unlikely(rx_size == 0xfff0)) {
1977 if (!tp->fifo_copy_timeout)
1978 tp->fifo_copy_timeout = jiffies + 2;
1979 else if (time_after(jiffies, tp->fifo_copy_timeout)) {
1980 DPRINTK ("%s: hung FIFO. Reset.", dev->name);
1981 rx_size = 0;
1982 goto no_early_rx;
1983 }
1984 if (netif_msg_intr(tp)) {
1985 printk(KERN_DEBUG "%s: fifo copy in progress.",
1986 dev->name);
1987 }
1988 tp->xstats.early_rx++;
1989 break;
1990 }
1991
1992 no_early_rx:
1993 tp->fifo_copy_timeout = 0;
1994
1995 /* If Rx err or invalid rx_size/rx_status received
1996 * (which happens if we get lost in the ring),
1997 * Rx process gets reset, so we abort any further
1998 * Rx processing.
1999 */
2000 if (unlikely((rx_size > (MAX_ETH_FRAME_SIZE+4)) ||
2001 (rx_size < 8) ||
2002 (!(rx_status & RxStatusOK)))) {
2003 rtl8139_rx_err (rx_status, dev, tp, ioaddr);
2004 received = -1;
2005 goto out;
2006 }
2007
2008 /* Malloc up new buffer, compatible with net-2e. */
2009 /* Omit the four octet CRC from the length. */
2010
2011 skb = dev_alloc_skb (pkt_size + 2);
2012 if (likely(skb)) {
2013 skb->dev = dev;
2014 skb_reserve (skb, 2); /* 16 byte align the IP fields. */
2015 #if RX_BUF_IDX == 3
2016 wrap_copy(skb, rx_ring, ring_offset+4, pkt_size);
2017 #else
2018 eth_copy_and_sum (skb, &rx_ring[ring_offset + 4], pkt_size, 0);
2019 #endif
2020 skb_put (skb, pkt_size);
2021
2022 skb->protocol = eth_type_trans (skb, dev);
2023
2024 dev->last_rx = jiffies;
2025 tp->stats.rx_bytes += pkt_size;
2026 tp->stats.rx_packets++;
2027
2028 netif_receive_skb (skb);
2029 } else {
2030 if (net_ratelimit())
2031 printk (KERN_WARNING
2032 "%s: Memory squeeze, dropping packet.\n",
2033 dev->name);
2034 tp->stats.rx_dropped++;
2035 }
2036 received++;
2037
2038 cur_rx = (cur_rx + rx_size + 4 + 3) & ~3;
2039 RTL_W16 (RxBufPtr, (u16) (cur_rx - 16));
2040
2041 rtl8139_isr_ack(tp);
2042 }
2043
2044 if (unlikely(!received || rx_size == 0xfff0))
2045 rtl8139_isr_ack(tp);
2046
2047 #if RTL8139_DEBUG > 1
2048 DPRINTK ("%s: Done rtl8139_rx(), current %4.4x BufAddr %4.4x,"
2049 " free to %4.4x, Cmd %2.2x.\n", dev->name, cur_rx,
2050 RTL_R16 (RxBufAddr),
2051 RTL_R16 (RxBufPtr), RTL_R8 (ChipCmd));
2052 #endif
2053
2054 tp->cur_rx = cur_rx;
2055
2056 /*
2057 * The receive buffer should be mostly empty.
2058 * Tell NAPI to reenable the Rx irq.
2059 */
2060 if (tp->fifo_copy_timeout)
2061 received = budget;
2062
2063 out:
2064 return received;
2065 }
2066
2067
2068 static void rtl8139_weird_interrupt (struct net_device *dev,
2069 struct rtl8139_private *tp,
2070 void __iomem *ioaddr,
2071 int status, int link_changed)
2072 {
2073 DPRINTK ("%s: Abnormal interrupt, status %8.8x.\n",
2074 dev->name, status);
2075
2076 assert (dev != NULL);
2077 assert (tp != NULL);
2078 assert (ioaddr != NULL);
2079
2080 /* Update the error count. */
2081 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2082 RTL_W32 (RxMissed, 0);
2083
2084 if ((status & RxUnderrun) && link_changed &&
2085 (tp->drv_flags & HAS_LNK_CHNG)) {
2086 rtl_check_media(dev, 0);
2087 status &= ~RxUnderrun;
2088 }
2089
2090 if (status & (RxUnderrun | RxErr))
2091 tp->stats.rx_errors++;
2092
2093 if (status & PCSTimeout)
2094 tp->stats.rx_length_errors++;
2095 if (status & RxUnderrun)
2096 tp->stats.rx_fifo_errors++;
2097 if (status & PCIErr) {
2098 u16 pci_cmd_status;
2099 pci_read_config_word (tp->pci_dev, PCI_STATUS, &pci_cmd_status);
2100 pci_write_config_word (tp->pci_dev, PCI_STATUS, pci_cmd_status);
2101
2102 printk (KERN_ERR "%s: PCI Bus error %4.4x.\n",
2103 dev->name, pci_cmd_status);
2104 }
2105 }
2106
2107 static int rtl8139_poll(struct net_device *dev, int *budget)
2108 {
2109 struct rtl8139_private *tp = netdev_priv(dev);
2110 void __iomem *ioaddr = tp->mmio_addr;
2111 int orig_budget = min(*budget, dev->quota);
2112 int done = 1;
2113
2114 spin_lock(&tp->rx_lock);
2115 if (likely(RTL_R16(IntrStatus) & RxAckBits)) {
2116 int work_done;
2117
2118 work_done = rtl8139_rx(dev, tp, orig_budget);
2119 if (likely(work_done > 0)) {
2120 *budget -= work_done;
2121 dev->quota -= work_done;
2122 done = (work_done < orig_budget);
2123 }
2124 }
2125
2126 if (done) {
2127 /*
2128 * Order is important since data can get interrupted
2129 * again when we think we are done.
2130 */
2131 local_irq_disable();
2132 RTL_W16_F(IntrMask, rtl8139_intr_mask);
2133 __netif_rx_complete(dev);
2134 local_irq_enable();
2135 }
2136 spin_unlock(&tp->rx_lock);
2137
2138 return !done;
2139 }
2140
2141 /* The interrupt handler does all of the Rx thread work and cleans up
2142 after the Tx thread. */
2143 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance,
2144 struct pt_regs *regs)
2145 {
2146 struct net_device *dev = (struct net_device *) dev_instance;
2147 struct rtl8139_private *tp = netdev_priv(dev);
2148 void __iomem *ioaddr = tp->mmio_addr;
2149 u16 status, ackstat;
2150 int link_changed = 0; /* avoid bogus "uninit" warning */
2151 int handled = 0;
2152
2153 spin_lock (&tp->lock);
2154 status = RTL_R16 (IntrStatus);
2155
2156 /* shared irq? */
2157 if (unlikely((status & rtl8139_intr_mask) == 0))
2158 goto out;
2159
2160 handled = 1;
2161
2162 /* h/w no longer present (hotplug?) or major error, bail */
2163 if (unlikely(status == 0xFFFF))
2164 goto out;
2165
2166 /* close possible race's with dev_close */
2167 if (unlikely(!netif_running(dev))) {
2168 RTL_W16 (IntrMask, 0);
2169 goto out;
2170 }
2171
2172 /* Acknowledge all of the current interrupt sources ASAP, but
2173 an first get an additional status bit from CSCR. */
2174 if (unlikely(status & RxUnderrun))
2175 link_changed = RTL_R16 (CSCR) & CSCR_LinkChangeBit;
2176
2177 ackstat = status & ~(RxAckBits | TxErr);
2178 if (ackstat)
2179 RTL_W16 (IntrStatus, ackstat);
2180
2181 /* Receive packets are processed by poll routine.
2182 If not running start it now. */
2183 if (status & RxAckBits){
2184 if (netif_rx_schedule_prep(dev)) {
2185 RTL_W16_F (IntrMask, rtl8139_norx_intr_mask);
2186 __netif_rx_schedule (dev);
2187 }
2188 }
2189
2190 /* Check uncommon events with one test. */
2191 if (unlikely(status & (PCIErr | PCSTimeout | RxUnderrun | RxErr)))
2192 rtl8139_weird_interrupt (dev, tp, ioaddr,
2193 status, link_changed);
2194
2195 if (status & (TxOK | TxErr)) {
2196 rtl8139_tx_interrupt (dev, tp, ioaddr);
2197 if (status & TxErr)
2198 RTL_W16 (IntrStatus, TxErr);
2199 }
2200 out:
2201 spin_unlock (&tp->lock);
2202
2203 DPRINTK ("%s: exiting interrupt, intr_status=%#4.4x.\n",
2204 dev->name, RTL_R16 (IntrStatus));
2205 return IRQ_RETVAL(handled);
2206 }
2207
2208 #ifdef CONFIG_NET_POLL_CONTROLLER
2209 /*
2210 * Polling receive - used by netconsole and other diagnostic tools
2211 * to allow network i/o with interrupts disabled.
2212 */
2213 static void rtl8139_poll_controller(struct net_device *dev)
2214 {
2215 disable_irq(dev->irq);
2216 rtl8139_interrupt(dev->irq, dev, NULL);
2217 enable_irq(dev->irq);
2218 }
2219 #endif
2220
2221 static int rtl8139_close (struct net_device *dev)
2222 {
2223 struct rtl8139_private *tp = netdev_priv(dev);
2224 void __iomem *ioaddr = tp->mmio_addr;
2225 int ret = 0;
2226 unsigned long flags;
2227
2228 netif_stop_queue (dev);
2229
2230 if (tp->thr_pid >= 0) {
2231 tp->time_to_die = 1;
2232 wmb();
2233 ret = kill_proc (tp->thr_pid, SIGTERM, 1);
2234 if (ret) {
2235 printk (KERN_ERR "%s: unable to signal thread\n", dev->name);
2236 return ret;
2237 }
2238 wait_for_completion (&tp->thr_exited);
2239 }
2240
2241 if (netif_msg_ifdown(tp))
2242 printk(KERN_DEBUG "%s: Shutting down ethercard, status was 0x%4.4x.\n",
2243 dev->name, RTL_R16 (IntrStatus));
2244
2245 spin_lock_irqsave (&tp->lock, flags);
2246
2247 /* Stop the chip's Tx and Rx DMA processes. */
2248 RTL_W8 (ChipCmd, 0);
2249
2250 /* Disable interrupts by clearing the interrupt mask. */
2251 RTL_W16 (IntrMask, 0);
2252
2253 /* Update the error counts. */
2254 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2255 RTL_W32 (RxMissed, 0);
2256
2257 spin_unlock_irqrestore (&tp->lock, flags);
2258
2259 synchronize_irq (dev->irq); /* racy, but that's ok here */
2260 free_irq (dev->irq, dev);
2261
2262 rtl8139_tx_clear (tp);
2263
2264 pci_free_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
2265 tp->rx_ring, tp->rx_ring_dma);
2266 pci_free_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
2267 tp->tx_bufs, tp->tx_bufs_dma);
2268 tp->rx_ring = NULL;
2269 tp->tx_bufs = NULL;
2270
2271 /* Green! Put the chip in low-power mode. */
2272 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2273
2274 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
2275 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */
2276
2277 return 0;
2278 }
2279
2280
2281 /* Get the ethtool Wake-on-LAN settings. Assumes that wol points to
2282 kernel memory, *wol has been initialized as {ETHTOOL_GWOL}, and
2283 other threads or interrupts aren't messing with the 8139. */
2284 static void rtl8139_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2285 {
2286 struct rtl8139_private *np = netdev_priv(dev);
2287 void __iomem *ioaddr = np->mmio_addr;
2288
2289 spin_lock_irq(&np->lock);
2290 if (rtl_chip_info[np->chipset].flags & HasLWake) {
2291 u8 cfg3 = RTL_R8 (Config3);
2292 u8 cfg5 = RTL_R8 (Config5);
2293
2294 wol->supported = WAKE_PHY | WAKE_MAGIC
2295 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST;
2296
2297 wol->wolopts = 0;
2298 if (cfg3 & Cfg3_LinkUp)
2299 wol->wolopts |= WAKE_PHY;
2300 if (cfg3 & Cfg3_Magic)
2301 wol->wolopts |= WAKE_MAGIC;
2302 /* (KON)FIXME: See how netdev_set_wol() handles the
2303 following constants. */
2304 if (cfg5 & Cfg5_UWF)
2305 wol->wolopts |= WAKE_UCAST;
2306 if (cfg5 & Cfg5_MWF)
2307 wol->wolopts |= WAKE_MCAST;
2308 if (cfg5 & Cfg5_BWF)
2309 wol->wolopts |= WAKE_BCAST;
2310 }
2311 spin_unlock_irq(&np->lock);
2312 }
2313
2314
2315 /* Set the ethtool Wake-on-LAN settings. Return 0 or -errno. Assumes
2316 that wol points to kernel memory and other threads or interrupts
2317 aren't messing with the 8139. */
2318 static int rtl8139_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2319 {
2320 struct rtl8139_private *np = netdev_priv(dev);
2321 void __iomem *ioaddr = np->mmio_addr;
2322 u32 support;
2323 u8 cfg3, cfg5;
2324
2325 support = ((rtl_chip_info[np->chipset].flags & HasLWake)
2326 ? (WAKE_PHY | WAKE_MAGIC
2327 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST)
2328 : 0);
2329 if (wol->wolopts & ~support)
2330 return -EINVAL;
2331
2332 spin_lock_irq(&np->lock);
2333 cfg3 = RTL_R8 (Config3) & ~(Cfg3_LinkUp | Cfg3_Magic);
2334 if (wol->wolopts & WAKE_PHY)
2335 cfg3 |= Cfg3_LinkUp;
2336 if (wol->wolopts & WAKE_MAGIC)
2337 cfg3 |= Cfg3_Magic;
2338 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2339 RTL_W8 (Config3, cfg3);
2340 RTL_W8 (Cfg9346, Cfg9346_Lock);
2341
2342 cfg5 = RTL_R8 (Config5) & ~(Cfg5_UWF | Cfg5_MWF | Cfg5_BWF);
2343 /* (KON)FIXME: These are untested. We may have to set the
2344 CRC0, Wakeup0 and LSBCRC0 registers too, but I have no
2345 documentation. */
2346 if (wol->wolopts & WAKE_UCAST)
2347 cfg5 |= Cfg5_UWF;
2348 if (wol->wolopts & WAKE_MCAST)
2349 cfg5 |= Cfg5_MWF;
2350 if (wol->wolopts & WAKE_BCAST)
2351 cfg5 |= Cfg5_BWF;
2352 RTL_W8 (Config5, cfg5); /* need not unlock via Cfg9346 */
2353 spin_unlock_irq(&np->lock);
2354
2355 return 0;
2356 }
2357
2358 static void rtl8139_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2359 {
2360 struct rtl8139_private *np = netdev_priv(dev);
2361 strcpy(info->driver, DRV_NAME);
2362 strcpy(info->version, DRV_VERSION);
2363 strcpy(info->bus_info, pci_name(np->pci_dev));
2364 info->regdump_len = np->regs_len;
2365 }
2366
2367 static int rtl8139_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2368 {
2369 struct rtl8139_private *np = netdev_priv(dev);
2370 spin_lock_irq(&np->lock);
2371 mii_ethtool_gset(&np->mii, cmd);
2372 spin_unlock_irq(&np->lock);
2373 return 0;
2374 }
2375
2376 static int rtl8139_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2377 {
2378 struct rtl8139_private *np = netdev_priv(dev);
2379 int rc;
2380 spin_lock_irq(&np->lock);
2381 rc = mii_ethtool_sset(&np->mii, cmd);
2382 spin_unlock_irq(&np->lock);
2383 return rc;
2384 }
2385
2386 static int rtl8139_nway_reset(struct net_device *dev)
2387 {
2388 struct rtl8139_private *np = netdev_priv(dev);
2389 return mii_nway_restart(&np->mii);
2390 }
2391
2392 static u32 rtl8139_get_link(struct net_device *dev)
2393 {
2394 struct rtl8139_private *np = netdev_priv(dev);
2395 return mii_link_ok(&np->mii);
2396 }
2397
2398 static u32 rtl8139_get_msglevel(struct net_device *dev)
2399 {
2400 struct rtl8139_private *np = netdev_priv(dev);
2401 return np->msg_enable;
2402 }
2403
2404 static void rtl8139_set_msglevel(struct net_device *dev, u32 datum)
2405 {
2406 struct rtl8139_private *np = netdev_priv(dev);
2407 np->msg_enable = datum;
2408 }
2409
2410 /* TODO: we are too slack to do reg dumping for pio, for now */
2411 #ifdef CONFIG_8139TOO_PIO
2412 #define rtl8139_get_regs_len NULL
2413 #define rtl8139_get_regs NULL
2414 #else
2415 static int rtl8139_get_regs_len(struct net_device *dev)
2416 {
2417 struct rtl8139_private *np = netdev_priv(dev);
2418 return np->regs_len;
2419 }
2420
2421 static void rtl8139_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *regbuf)
2422 {
2423 struct rtl8139_private *np = netdev_priv(dev);
2424
2425 regs->version = RTL_REGS_VER;
2426
2427 spin_lock_irq(&np->lock);
2428 memcpy_fromio(regbuf, np->mmio_addr, regs->len);
2429 spin_unlock_irq(&np->lock);
2430 }
2431 #endif /* CONFIG_8139TOO_MMIO */
2432
2433 static int rtl8139_get_stats_count(struct net_device *dev)
2434 {
2435 return RTL_NUM_STATS;
2436 }
2437
2438 static void rtl8139_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data)
2439 {
2440 struct rtl8139_private *np = netdev_priv(dev);
2441
2442 data[0] = np->xstats.early_rx;
2443 data[1] = np->xstats.tx_buf_mapped;
2444 data[2] = np->xstats.tx_timeouts;
2445 data[3] = np->xstats.rx_lost_in_ring;
2446 }
2447
2448 static void rtl8139_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2449 {
2450 memcpy(data, ethtool_stats_keys, sizeof(ethtool_stats_keys));
2451 }
2452
2453 static struct ethtool_ops rtl8139_ethtool_ops = {
2454 .get_drvinfo = rtl8139_get_drvinfo,
2455 .get_settings = rtl8139_get_settings,
2456 .set_settings = rtl8139_set_settings,
2457 .get_regs_len = rtl8139_get_regs_len,
2458 .get_regs = rtl8139_get_regs,
2459 .nway_reset = rtl8139_nway_reset,
2460 .get_link = rtl8139_get_link,
2461 .get_msglevel = rtl8139_get_msglevel,
2462 .set_msglevel = rtl8139_set_msglevel,
2463 .get_wol = rtl8139_get_wol,
2464 .set_wol = rtl8139_set_wol,
2465 .get_strings = rtl8139_get_strings,
2466 .get_stats_count = rtl8139_get_stats_count,
2467 .get_ethtool_stats = rtl8139_get_ethtool_stats,
2468 };
2469
2470 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2471 {
2472 struct rtl8139_private *np = netdev_priv(dev);
2473 int rc;
2474
2475 if (!netif_running(dev))
2476 return -EINVAL;
2477
2478 spin_lock_irq(&np->lock);
2479 rc = generic_mii_ioctl(&np->mii, if_mii(rq), cmd, NULL);
2480 spin_unlock_irq(&np->lock);
2481
2482 return rc;
2483 }
2484
2485
2486 static struct net_device_stats *rtl8139_get_stats (struct net_device *dev)
2487 {
2488 struct rtl8139_private *tp = netdev_priv(dev);
2489 void __iomem *ioaddr = tp->mmio_addr;
2490 unsigned long flags;
2491
2492 if (netif_running(dev)) {
2493 spin_lock_irqsave (&tp->lock, flags);
2494 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2495 RTL_W32 (RxMissed, 0);
2496 spin_unlock_irqrestore (&tp->lock, flags);
2497 }
2498
2499 return &tp->stats;
2500 }
2501
2502 /* Set or clear the multicast filter for this adaptor.
2503 This routine is not state sensitive and need not be SMP locked. */
2504
2505 static void __set_rx_mode (struct net_device *dev)
2506 {
2507 struct rtl8139_private *tp = netdev_priv(dev);
2508 void __iomem *ioaddr = tp->mmio_addr;
2509 u32 mc_filter[2]; /* Multicast hash filter */
2510 int i, rx_mode;
2511 u32 tmp;
2512
2513 DPRINTK ("%s: rtl8139_set_rx_mode(%4.4x) done -- Rx config %8.8lx.\n",
2514 dev->name, dev->flags, RTL_R32 (RxConfig));
2515
2516 /* Note: do not reorder, GCC is clever about common statements. */
2517 if (dev->flags & IFF_PROMISC) {
2518 /* Unconditionally log net taps. */
2519 printk (KERN_NOTICE "%s: Promiscuous mode enabled.\n",
2520 dev->name);
2521 rx_mode =
2522 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
2523 AcceptAllPhys;
2524 mc_filter[1] = mc_filter[0] = 0xffffffff;
2525 } else if ((dev->mc_count > multicast_filter_limit)
2526 || (dev->flags & IFF_ALLMULTI)) {
2527 /* Too many to filter perfectly -- accept all multicasts. */
2528 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
2529 mc_filter[1] = mc_filter[0] = 0xffffffff;
2530 } else {
2531 struct dev_mc_list *mclist;
2532 rx_mode = AcceptBroadcast | AcceptMyPhys;
2533 mc_filter[1] = mc_filter[0] = 0;
2534 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2535 i++, mclist = mclist->next) {
2536 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
2537
2538 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2539 rx_mode |= AcceptMulticast;
2540 }
2541 }
2542
2543 /* We can safely update without stopping the chip. */
2544 tmp = rtl8139_rx_config | rx_mode;
2545 if (tp->rx_config != tmp) {
2546 RTL_W32_F (RxConfig, tmp);
2547 tp->rx_config = tmp;
2548 }
2549 RTL_W32_F (MAR0 + 0, mc_filter[0]);
2550 RTL_W32_F (MAR0 + 4, mc_filter[1]);
2551 }
2552
2553 static void rtl8139_set_rx_mode (struct net_device *dev)
2554 {
2555 unsigned long flags;
2556 struct rtl8139_private *tp = netdev_priv(dev);
2557
2558 spin_lock_irqsave (&tp->lock, flags);
2559 __set_rx_mode(dev);
2560 spin_unlock_irqrestore (&tp->lock, flags);
2561 }
2562
2563 #ifdef CONFIG_PM
2564
2565 static int rtl8139_suspend (struct pci_dev *pdev, pm_message_t state)
2566 {
2567 struct net_device *dev = pci_get_drvdata (pdev);
2568 struct rtl8139_private *tp = netdev_priv(dev);
2569 void __iomem *ioaddr = tp->mmio_addr;
2570 unsigned long flags;
2571
2572 pci_save_state (pdev);
2573
2574 if (!netif_running (dev))
2575 return 0;
2576
2577 netif_device_detach (dev);
2578
2579 spin_lock_irqsave (&tp->lock, flags);
2580
2581 /* Disable interrupts, stop Tx and Rx. */
2582 RTL_W16 (IntrMask, 0);
2583 RTL_W8 (ChipCmd, 0);
2584
2585 /* Update the error counts. */
2586 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2587 RTL_W32 (RxMissed, 0);
2588
2589 spin_unlock_irqrestore (&tp->lock, flags);
2590
2591 pci_set_power_state (pdev, PCI_D3hot);
2592
2593 return 0;
2594 }
2595
2596
2597 static int rtl8139_resume (struct pci_dev *pdev)
2598 {
2599 struct net_device *dev = pci_get_drvdata (pdev);
2600
2601 pci_restore_state (pdev);
2602 if (!netif_running (dev))
2603 return 0;
2604 pci_set_power_state (pdev, PCI_D0);
2605 rtl8139_init_ring (dev);
2606 rtl8139_hw_start (dev);
2607 netif_device_attach (dev);
2608 return 0;
2609 }
2610
2611 #endif /* CONFIG_PM */
2612
2613
2614 static struct pci_driver rtl8139_pci_driver = {
2615 .name = DRV_NAME,
2616 .id_table = rtl8139_pci_tbl,
2617 .probe = rtl8139_init_one,
2618 .remove = __devexit_p(rtl8139_remove_one),
2619 #ifdef CONFIG_PM
2620 .suspend = rtl8139_suspend,
2621 .resume = rtl8139_resume,
2622 #endif /* CONFIG_PM */
2623 };
2624
2625
2626 static int __init rtl8139_init_module (void)
2627 {
2628 /* when we're a module, we always print a version message,
2629 * even if no 8139 board is found.
2630 */
2631 #ifdef MODULE
2632 printk (KERN_INFO RTL8139_DRIVER_NAME "\n");
2633 #endif
2634
2635 return pci_module_init (&rtl8139_pci_driver);
2636 }
2637
2638
2639 static void __exit rtl8139_cleanup_module (void)
2640 {
2641 pci_unregister_driver (&rtl8139_pci_driver);
2642 }
2643
2644
2645 module_init(rtl8139_init_module);
2646 module_exit(rtl8139_cleanup_module);
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