1 /****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2008 Solarflare Communications Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
11 #include <linux/bitops.h>
12 #include <linux/delay.h>
13 #include <linux/pci.h>
14 #include <linux/module.h>
15 #include <linux/seq_file.h>
16 #include <linux/i2c.h>
17 #include <linux/i2c-algo-bit.h>
18 #include <linux/mii.h>
19 #include "net_driver.h"
25 #include "falcon_hwdefs.h"
26 #include "falcon_io.h"
30 #include "workarounds.h"
32 /* Falcon hardware control.
33 * Falcon is the internal codename for the SFC4000 controller that is
34 * present in SFE400X evaluation boards
38 * struct falcon_nic_data - Falcon NIC state
39 * @next_buffer_table: First available buffer table id
40 * @pci_dev2: The secondary PCI device if present
41 * @i2c_data: Operations and state for I2C bit-bashing algorithm
43 struct falcon_nic_data
{
44 unsigned next_buffer_table
;
45 struct pci_dev
*pci_dev2
;
46 struct i2c_algo_bit_data i2c_data
;
49 /**************************************************************************
53 **************************************************************************
56 static int disable_dma_stats
;
58 /* This is set to 16 for a good reason. In summary, if larger than
59 * 16, the descriptor cache holds more than a default socket
60 * buffer's worth of packets (for UDP we can only have at most one
61 * socket buffer's worth outstanding). This combined with the fact
62 * that we only get 1 TX event per descriptor cache means the NIC
65 #define TX_DC_ENTRIES 16
66 #define TX_DC_ENTRIES_ORDER 0
67 #define TX_DC_BASE 0x130000
69 #define RX_DC_ENTRIES 64
70 #define RX_DC_ENTRIES_ORDER 2
71 #define RX_DC_BASE 0x100000
73 static const unsigned int
74 /* "Large" EEPROM device: Atmel AT25640 or similar
75 * 8 KB, 16-bit address, 32 B write block */
76 large_eeprom_type
= ((13 << SPI_DEV_TYPE_SIZE_LBN
)
77 | (2 << SPI_DEV_TYPE_ADDR_LEN_LBN
)
78 | (5 << SPI_DEV_TYPE_BLOCK_SIZE_LBN
)),
79 /* Default flash device: Atmel AT25F1024
80 * 128 KB, 24-bit address, 32 KB erase block, 256 B write block */
81 default_flash_type
= ((17 << SPI_DEV_TYPE_SIZE_LBN
)
82 | (3 << SPI_DEV_TYPE_ADDR_LEN_LBN
)
83 | (0x52 << SPI_DEV_TYPE_ERASE_CMD_LBN
)
84 | (15 << SPI_DEV_TYPE_ERASE_SIZE_LBN
)
85 | (8 << SPI_DEV_TYPE_BLOCK_SIZE_LBN
));
87 /* RX FIFO XOFF watermark
89 * When the amount of the RX FIFO increases used increases past this
90 * watermark send XOFF. Only used if RX flow control is enabled (ethtool -A)
91 * This also has an effect on RX/TX arbitration
93 static int rx_xoff_thresh_bytes
= -1;
94 module_param(rx_xoff_thresh_bytes
, int, 0644);
95 MODULE_PARM_DESC(rx_xoff_thresh_bytes
, "RX fifo XOFF threshold");
97 /* RX FIFO XON watermark
99 * When the amount of the RX FIFO used decreases below this
100 * watermark send XON. Only used if TX flow control is enabled (ethtool -A)
101 * This also has an effect on RX/TX arbitration
103 static int rx_xon_thresh_bytes
= -1;
104 module_param(rx_xon_thresh_bytes
, int, 0644);
105 MODULE_PARM_DESC(rx_xon_thresh_bytes
, "RX fifo XON threshold");
107 /* TX descriptor ring size - min 512 max 4k */
108 #define FALCON_TXD_RING_ORDER TX_DESCQ_SIZE_1K
109 #define FALCON_TXD_RING_SIZE 1024
110 #define FALCON_TXD_RING_MASK (FALCON_TXD_RING_SIZE - 1)
112 /* RX descriptor ring size - min 512 max 4k */
113 #define FALCON_RXD_RING_ORDER RX_DESCQ_SIZE_1K
114 #define FALCON_RXD_RING_SIZE 1024
115 #define FALCON_RXD_RING_MASK (FALCON_RXD_RING_SIZE - 1)
117 /* Event queue size - max 32k */
118 #define FALCON_EVQ_ORDER EVQ_SIZE_4K
119 #define FALCON_EVQ_SIZE 4096
120 #define FALCON_EVQ_MASK (FALCON_EVQ_SIZE - 1)
122 /* Max number of internal errors. After this resets will not be performed */
123 #define FALCON_MAX_INT_ERRORS 4
125 /* We poll for events every FLUSH_INTERVAL ms, and check FLUSH_POLL_COUNT times
127 #define FALCON_FLUSH_INTERVAL 10
128 #define FALCON_FLUSH_POLL_COUNT 100
130 /**************************************************************************
134 **************************************************************************
137 /* DMA address mask */
138 #define FALCON_DMA_MASK DMA_BIT_MASK(46)
140 /* TX DMA length mask (13-bit) */
141 #define FALCON_TX_DMA_MASK (4096 - 1)
143 /* Size and alignment of special buffers (4KB) */
144 #define FALCON_BUF_SIZE 4096
146 /* Dummy SRAM size code */
147 #define SRM_NB_BSZ_ONCHIP_ONLY (-1)
149 /* Be nice if these (or equiv.) were in linux/pci_regs.h, but they're not. */
150 #define PCI_EXP_DEVCAP_PWR_VAL_LBN 18
151 #define PCI_EXP_DEVCAP_PWR_SCL_LBN 26
152 #define PCI_EXP_DEVCTL_PAYLOAD_LBN 5
153 #define PCI_EXP_LNKSTA_LNK_WID 0x3f0
154 #define PCI_EXP_LNKSTA_LNK_WID_LBN 4
156 #define FALCON_IS_DUAL_FUNC(efx) \
157 (falcon_rev(efx) < FALCON_REV_B0)
159 /**************************************************************************
161 * Falcon hardware access
163 **************************************************************************/
165 /* Read the current event from the event queue */
166 static inline efx_qword_t
*falcon_event(struct efx_channel
*channel
,
169 return (((efx_qword_t
*) (channel
->eventq
.addr
)) + index
);
172 /* See if an event is present
174 * We check both the high and low dword of the event for all ones. We
175 * wrote all ones when we cleared the event, and no valid event can
176 * have all ones in either its high or low dwords. This approach is
177 * robust against reordering.
179 * Note that using a single 64-bit comparison is incorrect; even
180 * though the CPU read will be atomic, the DMA write may not be.
182 static inline int falcon_event_present(efx_qword_t
*event
)
184 return (!(EFX_DWORD_IS_ALL_ONES(event
->dword
[0]) |
185 EFX_DWORD_IS_ALL_ONES(event
->dword
[1])));
188 /**************************************************************************
190 * I2C bus - this is a bit-bashing interface using GPIO pins
191 * Note that it uses the output enables to tristate the outputs
192 * SDA is the data pin and SCL is the clock
194 **************************************************************************
196 static void falcon_setsda(void *data
, int state
)
198 struct efx_nic
*efx
= (struct efx_nic
*)data
;
201 falcon_read(efx
, ®
, GPIO_CTL_REG_KER
);
202 EFX_SET_OWORD_FIELD(reg
, GPIO3_OEN
, !state
);
203 falcon_write(efx
, ®
, GPIO_CTL_REG_KER
);
206 static void falcon_setscl(void *data
, int state
)
208 struct efx_nic
*efx
= (struct efx_nic
*)data
;
211 falcon_read(efx
, ®
, GPIO_CTL_REG_KER
);
212 EFX_SET_OWORD_FIELD(reg
, GPIO0_OEN
, !state
);
213 falcon_write(efx
, ®
, GPIO_CTL_REG_KER
);
216 static int falcon_getsda(void *data
)
218 struct efx_nic
*efx
= (struct efx_nic
*)data
;
221 falcon_read(efx
, ®
, GPIO_CTL_REG_KER
);
222 return EFX_OWORD_FIELD(reg
, GPIO3_IN
);
225 static int falcon_getscl(void *data
)
227 struct efx_nic
*efx
= (struct efx_nic
*)data
;
230 falcon_read(efx
, ®
, GPIO_CTL_REG_KER
);
231 return EFX_OWORD_FIELD(reg
, GPIO0_IN
);
234 static struct i2c_algo_bit_data falcon_i2c_bit_operations
= {
235 .setsda
= falcon_setsda
,
236 .setscl
= falcon_setscl
,
237 .getsda
= falcon_getsda
,
238 .getscl
= falcon_getscl
,
240 /* Wait up to 50 ms for slave to let us pull SCL high */
241 .timeout
= DIV_ROUND_UP(HZ
, 20),
244 /**************************************************************************
246 * Falcon special buffer handling
247 * Special buffers are used for event queues and the TX and RX
250 *************************************************************************/
253 * Initialise a Falcon special buffer
255 * This will define a buffer (previously allocated via
256 * falcon_alloc_special_buffer()) in Falcon's buffer table, allowing
257 * it to be used for event queues, descriptor rings etc.
260 falcon_init_special_buffer(struct efx_nic
*efx
,
261 struct efx_special_buffer
*buffer
)
263 efx_qword_t buf_desc
;
268 EFX_BUG_ON_PARANOID(!buffer
->addr
);
270 /* Write buffer descriptors to NIC */
271 for (i
= 0; i
< buffer
->entries
; i
++) {
272 index
= buffer
->index
+ i
;
273 dma_addr
= buffer
->dma_addr
+ (i
* 4096);
274 EFX_LOG(efx
, "mapping special buffer %d at %llx\n",
275 index
, (unsigned long long)dma_addr
);
276 EFX_POPULATE_QWORD_4(buf_desc
,
277 IP_DAT_BUF_SIZE
, IP_DAT_BUF_SIZE_4K
,
279 BUF_ADR_FBUF
, (dma_addr
>> 12),
280 BUF_OWNER_ID_FBUF
, 0);
281 falcon_write_sram(efx
, &buf_desc
, index
);
285 /* Unmaps a buffer from Falcon and clears the buffer table entries */
287 falcon_fini_special_buffer(struct efx_nic
*efx
,
288 struct efx_special_buffer
*buffer
)
290 efx_oword_t buf_tbl_upd
;
291 unsigned int start
= buffer
->index
;
292 unsigned int end
= (buffer
->index
+ buffer
->entries
- 1);
294 if (!buffer
->entries
)
297 EFX_LOG(efx
, "unmapping special buffers %d-%d\n",
298 buffer
->index
, buffer
->index
+ buffer
->entries
- 1);
300 EFX_POPULATE_OWORD_4(buf_tbl_upd
,
304 BUF_CLR_START_ID
, start
);
305 falcon_write(efx
, &buf_tbl_upd
, BUF_TBL_UPD_REG_KER
);
309 * Allocate a new Falcon special buffer
311 * This allocates memory for a new buffer, clears it and allocates a
312 * new buffer ID range. It does not write into Falcon's buffer table.
314 * This call will allocate 4KB buffers, since Falcon can't use 8KB
315 * buffers for event queues and descriptor rings.
317 static int falcon_alloc_special_buffer(struct efx_nic
*efx
,
318 struct efx_special_buffer
*buffer
,
321 struct falcon_nic_data
*nic_data
= efx
->nic_data
;
323 len
= ALIGN(len
, FALCON_BUF_SIZE
);
325 buffer
->addr
= pci_alloc_consistent(efx
->pci_dev
, len
,
330 buffer
->entries
= len
/ FALCON_BUF_SIZE
;
331 BUG_ON(buffer
->dma_addr
& (FALCON_BUF_SIZE
- 1));
333 /* All zeros is a potentially valid event so memset to 0xff */
334 memset(buffer
->addr
, 0xff, len
);
336 /* Select new buffer ID */
337 buffer
->index
= nic_data
->next_buffer_table
;
338 nic_data
->next_buffer_table
+= buffer
->entries
;
340 EFX_LOG(efx
, "allocating special buffers %d-%d at %llx+%x "
341 "(virt %p phys %lx)\n", buffer
->index
,
342 buffer
->index
+ buffer
->entries
- 1,
343 (unsigned long long)buffer
->dma_addr
, len
,
344 buffer
->addr
, virt_to_phys(buffer
->addr
));
349 static void falcon_free_special_buffer(struct efx_nic
*efx
,
350 struct efx_special_buffer
*buffer
)
355 EFX_LOG(efx
, "deallocating special buffers %d-%d at %llx+%x "
356 "(virt %p phys %lx)\n", buffer
->index
,
357 buffer
->index
+ buffer
->entries
- 1,
358 (unsigned long long)buffer
->dma_addr
, buffer
->len
,
359 buffer
->addr
, virt_to_phys(buffer
->addr
));
361 pci_free_consistent(efx
->pci_dev
, buffer
->len
, buffer
->addr
,
367 /**************************************************************************
369 * Falcon generic buffer handling
370 * These buffers are used for interrupt status and MAC stats
372 **************************************************************************/
374 static int falcon_alloc_buffer(struct efx_nic
*efx
,
375 struct efx_buffer
*buffer
, unsigned int len
)
377 buffer
->addr
= pci_alloc_consistent(efx
->pci_dev
, len
,
382 memset(buffer
->addr
, 0, len
);
386 static void falcon_free_buffer(struct efx_nic
*efx
, struct efx_buffer
*buffer
)
389 pci_free_consistent(efx
->pci_dev
, buffer
->len
,
390 buffer
->addr
, buffer
->dma_addr
);
395 /**************************************************************************
399 **************************************************************************/
401 /* Returns a pointer to the specified transmit descriptor in the TX
402 * descriptor queue belonging to the specified channel.
404 static inline efx_qword_t
*falcon_tx_desc(struct efx_tx_queue
*tx_queue
,
407 return (((efx_qword_t
*) (tx_queue
->txd
.addr
)) + index
);
410 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
411 static inline void falcon_notify_tx_desc(struct efx_tx_queue
*tx_queue
)
416 write_ptr
= tx_queue
->write_count
& FALCON_TXD_RING_MASK
;
417 EFX_POPULATE_DWORD_1(reg
, TX_DESC_WPTR_DWORD
, write_ptr
);
418 falcon_writel_page(tx_queue
->efx
, ®
,
419 TX_DESC_UPD_REG_KER_DWORD
, tx_queue
->queue
);
423 /* For each entry inserted into the software descriptor ring, create a
424 * descriptor in the hardware TX descriptor ring (in host memory), and
427 void falcon_push_buffers(struct efx_tx_queue
*tx_queue
)
430 struct efx_tx_buffer
*buffer
;
434 BUG_ON(tx_queue
->write_count
== tx_queue
->insert_count
);
437 write_ptr
= tx_queue
->write_count
& FALCON_TXD_RING_MASK
;
438 buffer
= &tx_queue
->buffer
[write_ptr
];
439 txd
= falcon_tx_desc(tx_queue
, write_ptr
);
440 ++tx_queue
->write_count
;
442 /* Create TX descriptor ring entry */
443 EFX_POPULATE_QWORD_5(*txd
,
445 TX_KER_CONT
, buffer
->continuation
,
446 TX_KER_BYTE_CNT
, buffer
->len
,
447 TX_KER_BUF_REGION
, 0,
448 TX_KER_BUF_ADR
, buffer
->dma_addr
);
449 } while (tx_queue
->write_count
!= tx_queue
->insert_count
);
451 wmb(); /* Ensure descriptors are written before they are fetched */
452 falcon_notify_tx_desc(tx_queue
);
455 /* Allocate hardware resources for a TX queue */
456 int falcon_probe_tx(struct efx_tx_queue
*tx_queue
)
458 struct efx_nic
*efx
= tx_queue
->efx
;
459 return falcon_alloc_special_buffer(efx
, &tx_queue
->txd
,
460 FALCON_TXD_RING_SIZE
*
461 sizeof(efx_qword_t
));
464 void falcon_init_tx(struct efx_tx_queue
*tx_queue
)
466 efx_oword_t tx_desc_ptr
;
467 struct efx_nic
*efx
= tx_queue
->efx
;
469 tx_queue
->flushed
= false;
471 /* Pin TX descriptor ring */
472 falcon_init_special_buffer(efx
, &tx_queue
->txd
);
474 /* Push TX descriptor ring to card */
475 EFX_POPULATE_OWORD_10(tx_desc_ptr
,
479 TX_DESCQ_BUF_BASE_ID
, tx_queue
->txd
.index
,
480 TX_DESCQ_EVQ_ID
, tx_queue
->channel
->channel
,
481 TX_DESCQ_OWNER_ID
, 0,
482 TX_DESCQ_LABEL
, tx_queue
->queue
,
483 TX_DESCQ_SIZE
, FALCON_TXD_RING_ORDER
,
485 TX_NON_IP_DROP_DIS_B0
, 1);
487 if (falcon_rev(efx
) >= FALCON_REV_B0
) {
488 int csum
= tx_queue
->queue
== EFX_TX_QUEUE_OFFLOAD_CSUM
;
489 EFX_SET_OWORD_FIELD(tx_desc_ptr
, TX_IP_CHKSM_DIS_B0
, !csum
);
490 EFX_SET_OWORD_FIELD(tx_desc_ptr
, TX_TCP_CHKSM_DIS_B0
, !csum
);
493 falcon_write_table(efx
, &tx_desc_ptr
, efx
->type
->txd_ptr_tbl_base
,
496 if (falcon_rev(efx
) < FALCON_REV_B0
) {
499 /* Only 128 bits in this register */
500 BUILD_BUG_ON(EFX_TX_QUEUE_COUNT
>= 128);
502 falcon_read(efx
, ®
, TX_CHKSM_CFG_REG_KER_A1
);
503 if (tx_queue
->queue
== EFX_TX_QUEUE_OFFLOAD_CSUM
)
504 clear_bit_le(tx_queue
->queue
, (void *)®
);
506 set_bit_le(tx_queue
->queue
, (void *)®
);
507 falcon_write(efx
, ®
, TX_CHKSM_CFG_REG_KER_A1
);
511 static void falcon_flush_tx_queue(struct efx_tx_queue
*tx_queue
)
513 struct efx_nic
*efx
= tx_queue
->efx
;
514 efx_oword_t tx_flush_descq
;
516 /* Post a flush command */
517 EFX_POPULATE_OWORD_2(tx_flush_descq
,
518 TX_FLUSH_DESCQ_CMD
, 1,
519 TX_FLUSH_DESCQ
, tx_queue
->queue
);
520 falcon_write(efx
, &tx_flush_descq
, TX_FLUSH_DESCQ_REG_KER
);
523 void falcon_fini_tx(struct efx_tx_queue
*tx_queue
)
525 struct efx_nic
*efx
= tx_queue
->efx
;
526 efx_oword_t tx_desc_ptr
;
528 /* The queue should have been flushed */
529 WARN_ON(!tx_queue
->flushed
);
531 /* Remove TX descriptor ring from card */
532 EFX_ZERO_OWORD(tx_desc_ptr
);
533 falcon_write_table(efx
, &tx_desc_ptr
, efx
->type
->txd_ptr_tbl_base
,
536 /* Unpin TX descriptor ring */
537 falcon_fini_special_buffer(efx
, &tx_queue
->txd
);
540 /* Free buffers backing TX queue */
541 void falcon_remove_tx(struct efx_tx_queue
*tx_queue
)
543 falcon_free_special_buffer(tx_queue
->efx
, &tx_queue
->txd
);
546 /**************************************************************************
550 **************************************************************************/
552 /* Returns a pointer to the specified descriptor in the RX descriptor queue */
553 static inline efx_qword_t
*falcon_rx_desc(struct efx_rx_queue
*rx_queue
,
556 return (((efx_qword_t
*) (rx_queue
->rxd
.addr
)) + index
);
559 /* This creates an entry in the RX descriptor queue */
560 static inline void falcon_build_rx_desc(struct efx_rx_queue
*rx_queue
,
563 struct efx_rx_buffer
*rx_buf
;
566 rxd
= falcon_rx_desc(rx_queue
, index
);
567 rx_buf
= efx_rx_buffer(rx_queue
, index
);
568 EFX_POPULATE_QWORD_3(*rxd
,
571 rx_queue
->efx
->type
->rx_buffer_padding
,
572 RX_KER_BUF_REGION
, 0,
573 RX_KER_BUF_ADR
, rx_buf
->dma_addr
);
576 /* This writes to the RX_DESC_WPTR register for the specified receive
579 void falcon_notify_rx_desc(struct efx_rx_queue
*rx_queue
)
584 while (rx_queue
->notified_count
!= rx_queue
->added_count
) {
585 falcon_build_rx_desc(rx_queue
,
586 rx_queue
->notified_count
&
587 FALCON_RXD_RING_MASK
);
588 ++rx_queue
->notified_count
;
592 write_ptr
= rx_queue
->added_count
& FALCON_RXD_RING_MASK
;
593 EFX_POPULATE_DWORD_1(reg
, RX_DESC_WPTR_DWORD
, write_ptr
);
594 falcon_writel_page(rx_queue
->efx
, ®
,
595 RX_DESC_UPD_REG_KER_DWORD
, rx_queue
->queue
);
598 int falcon_probe_rx(struct efx_rx_queue
*rx_queue
)
600 struct efx_nic
*efx
= rx_queue
->efx
;
601 return falcon_alloc_special_buffer(efx
, &rx_queue
->rxd
,
602 FALCON_RXD_RING_SIZE
*
603 sizeof(efx_qword_t
));
606 void falcon_init_rx(struct efx_rx_queue
*rx_queue
)
608 efx_oword_t rx_desc_ptr
;
609 struct efx_nic
*efx
= rx_queue
->efx
;
610 bool is_b0
= falcon_rev(efx
) >= FALCON_REV_B0
;
611 bool iscsi_digest_en
= is_b0
;
613 EFX_LOG(efx
, "RX queue %d ring in special buffers %d-%d\n",
614 rx_queue
->queue
, rx_queue
->rxd
.index
,
615 rx_queue
->rxd
.index
+ rx_queue
->rxd
.entries
- 1);
617 rx_queue
->flushed
= false;
619 /* Pin RX descriptor ring */
620 falcon_init_special_buffer(efx
, &rx_queue
->rxd
);
622 /* Push RX descriptor ring to card */
623 EFX_POPULATE_OWORD_10(rx_desc_ptr
,
624 RX_ISCSI_DDIG_EN
, iscsi_digest_en
,
625 RX_ISCSI_HDIG_EN
, iscsi_digest_en
,
626 RX_DESCQ_BUF_BASE_ID
, rx_queue
->rxd
.index
,
627 RX_DESCQ_EVQ_ID
, rx_queue
->channel
->channel
,
628 RX_DESCQ_OWNER_ID
, 0,
629 RX_DESCQ_LABEL
, rx_queue
->queue
,
630 RX_DESCQ_SIZE
, FALCON_RXD_RING_ORDER
,
631 RX_DESCQ_TYPE
, 0 /* kernel queue */ ,
632 /* For >=B0 this is scatter so disable */
633 RX_DESCQ_JUMBO
, !is_b0
,
635 falcon_write_table(efx
, &rx_desc_ptr
, efx
->type
->rxd_ptr_tbl_base
,
639 static void falcon_flush_rx_queue(struct efx_rx_queue
*rx_queue
)
641 struct efx_nic
*efx
= rx_queue
->efx
;
642 efx_oword_t rx_flush_descq
;
644 /* Post a flush command */
645 EFX_POPULATE_OWORD_2(rx_flush_descq
,
646 RX_FLUSH_DESCQ_CMD
, 1,
647 RX_FLUSH_DESCQ
, rx_queue
->queue
);
648 falcon_write(efx
, &rx_flush_descq
, RX_FLUSH_DESCQ_REG_KER
);
651 void falcon_fini_rx(struct efx_rx_queue
*rx_queue
)
653 efx_oword_t rx_desc_ptr
;
654 struct efx_nic
*efx
= rx_queue
->efx
;
656 /* The queue should already have been flushed */
657 WARN_ON(!rx_queue
->flushed
);
659 /* Remove RX descriptor ring from card */
660 EFX_ZERO_OWORD(rx_desc_ptr
);
661 falcon_write_table(efx
, &rx_desc_ptr
, efx
->type
->rxd_ptr_tbl_base
,
664 /* Unpin RX descriptor ring */
665 falcon_fini_special_buffer(efx
, &rx_queue
->rxd
);
668 /* Free buffers backing RX queue */
669 void falcon_remove_rx(struct efx_rx_queue
*rx_queue
)
671 falcon_free_special_buffer(rx_queue
->efx
, &rx_queue
->rxd
);
674 /**************************************************************************
676 * Falcon event queue processing
677 * Event queues are processed by per-channel tasklets.
679 **************************************************************************/
681 /* Update a channel's event queue's read pointer (RPTR) register
683 * This writes the EVQ_RPTR_REG register for the specified channel's
686 * Note that EVQ_RPTR_REG contains the index of the "last read" event,
687 * whereas channel->eventq_read_ptr contains the index of the "next to
690 void falcon_eventq_read_ack(struct efx_channel
*channel
)
693 struct efx_nic
*efx
= channel
->efx
;
695 EFX_POPULATE_DWORD_1(reg
, EVQ_RPTR_DWORD
, channel
->eventq_read_ptr
);
696 falcon_writel_table(efx
, ®
, efx
->type
->evq_rptr_tbl_base
,
700 /* Use HW to insert a SW defined event */
701 void falcon_generate_event(struct efx_channel
*channel
, efx_qword_t
*event
)
703 efx_oword_t drv_ev_reg
;
705 EFX_POPULATE_OWORD_2(drv_ev_reg
,
706 DRV_EV_QID
, channel
->channel
,
708 EFX_QWORD_FIELD64(*event
, WHOLE_EVENT
));
709 falcon_write(channel
->efx
, &drv_ev_reg
, DRV_EV_REG_KER
);
712 /* Handle a transmit completion event
714 * Falcon batches TX completion events; the message we receive is of
715 * the form "complete all TX events up to this index".
717 static void falcon_handle_tx_event(struct efx_channel
*channel
,
720 unsigned int tx_ev_desc_ptr
;
721 unsigned int tx_ev_q_label
;
722 struct efx_tx_queue
*tx_queue
;
723 struct efx_nic
*efx
= channel
->efx
;
725 if (likely(EFX_QWORD_FIELD(*event
, TX_EV_COMP
))) {
726 /* Transmit completion */
727 tx_ev_desc_ptr
= EFX_QWORD_FIELD(*event
, TX_EV_DESC_PTR
);
728 tx_ev_q_label
= EFX_QWORD_FIELD(*event
, TX_EV_Q_LABEL
);
729 tx_queue
= &efx
->tx_queue
[tx_ev_q_label
];
730 efx_xmit_done(tx_queue
, tx_ev_desc_ptr
);
731 } else if (EFX_QWORD_FIELD(*event
, TX_EV_WQ_FF_FULL
)) {
732 /* Rewrite the FIFO write pointer */
733 tx_ev_q_label
= EFX_QWORD_FIELD(*event
, TX_EV_Q_LABEL
);
734 tx_queue
= &efx
->tx_queue
[tx_ev_q_label
];
736 if (efx_dev_registered(efx
))
737 netif_tx_lock(efx
->net_dev
);
738 falcon_notify_tx_desc(tx_queue
);
739 if (efx_dev_registered(efx
))
740 netif_tx_unlock(efx
->net_dev
);
741 } else if (EFX_QWORD_FIELD(*event
, TX_EV_PKT_ERR
) &&
742 EFX_WORKAROUND_10727(efx
)) {
743 efx_schedule_reset(efx
, RESET_TYPE_TX_DESC_FETCH
);
745 EFX_ERR(efx
, "channel %d unexpected TX event "
746 EFX_QWORD_FMT
"\n", channel
->channel
,
747 EFX_QWORD_VAL(*event
));
751 /* Detect errors included in the rx_evt_pkt_ok bit. */
752 static void falcon_handle_rx_not_ok(struct efx_rx_queue
*rx_queue
,
753 const efx_qword_t
*event
,
757 struct efx_nic
*efx
= rx_queue
->efx
;
758 bool rx_ev_buf_owner_id_err
, rx_ev_ip_hdr_chksum_err
;
759 bool rx_ev_tcp_udp_chksum_err
, rx_ev_eth_crc_err
;
760 bool rx_ev_frm_trunc
, rx_ev_drib_nib
, rx_ev_tobe_disc
;
761 bool rx_ev_other_err
, rx_ev_pause_frm
;
762 bool rx_ev_ip_frag_err
, rx_ev_hdr_type
, rx_ev_mcast_pkt
;
763 unsigned rx_ev_pkt_type
;
765 rx_ev_hdr_type
= EFX_QWORD_FIELD(*event
, RX_EV_HDR_TYPE
);
766 rx_ev_mcast_pkt
= EFX_QWORD_FIELD(*event
, RX_EV_MCAST_PKT
);
767 rx_ev_tobe_disc
= EFX_QWORD_FIELD(*event
, RX_EV_TOBE_DISC
);
768 rx_ev_pkt_type
= EFX_QWORD_FIELD(*event
, RX_EV_PKT_TYPE
);
769 rx_ev_buf_owner_id_err
= EFX_QWORD_FIELD(*event
,
770 RX_EV_BUF_OWNER_ID_ERR
);
771 rx_ev_ip_frag_err
= EFX_QWORD_FIELD(*event
, RX_EV_IF_FRAG_ERR
);
772 rx_ev_ip_hdr_chksum_err
= EFX_QWORD_FIELD(*event
,
773 RX_EV_IP_HDR_CHKSUM_ERR
);
774 rx_ev_tcp_udp_chksum_err
= EFX_QWORD_FIELD(*event
,
775 RX_EV_TCP_UDP_CHKSUM_ERR
);
776 rx_ev_eth_crc_err
= EFX_QWORD_FIELD(*event
, RX_EV_ETH_CRC_ERR
);
777 rx_ev_frm_trunc
= EFX_QWORD_FIELD(*event
, RX_EV_FRM_TRUNC
);
778 rx_ev_drib_nib
= ((falcon_rev(efx
) >= FALCON_REV_B0
) ?
779 0 : EFX_QWORD_FIELD(*event
, RX_EV_DRIB_NIB
));
780 rx_ev_pause_frm
= EFX_QWORD_FIELD(*event
, RX_EV_PAUSE_FRM_ERR
);
782 /* Every error apart from tobe_disc and pause_frm */
783 rx_ev_other_err
= (rx_ev_drib_nib
| rx_ev_tcp_udp_chksum_err
|
784 rx_ev_buf_owner_id_err
| rx_ev_eth_crc_err
|
785 rx_ev_frm_trunc
| rx_ev_ip_hdr_chksum_err
);
787 /* Count errors that are not in MAC stats. Ignore expected
788 * checksum errors during self-test. */
790 ++rx_queue
->channel
->n_rx_frm_trunc
;
791 else if (rx_ev_tobe_disc
)
792 ++rx_queue
->channel
->n_rx_tobe_disc
;
793 else if (!efx
->loopback_selftest
) {
794 if (rx_ev_ip_hdr_chksum_err
)
795 ++rx_queue
->channel
->n_rx_ip_hdr_chksum_err
;
796 else if (rx_ev_tcp_udp_chksum_err
)
797 ++rx_queue
->channel
->n_rx_tcp_udp_chksum_err
;
799 if (rx_ev_ip_frag_err
)
800 ++rx_queue
->channel
->n_rx_ip_frag_err
;
802 /* The frame must be discarded if any of these are true. */
803 *discard
= (rx_ev_eth_crc_err
| rx_ev_frm_trunc
| rx_ev_drib_nib
|
804 rx_ev_tobe_disc
| rx_ev_pause_frm
);
806 /* TOBE_DISC is expected on unicast mismatches; don't print out an
807 * error message. FRM_TRUNC indicates RXDP dropped the packet due
808 * to a FIFO overflow.
810 #ifdef EFX_ENABLE_DEBUG
811 if (rx_ev_other_err
) {
812 EFX_INFO_RL(efx
, " RX queue %d unexpected RX event "
813 EFX_QWORD_FMT
"%s%s%s%s%s%s%s%s\n",
814 rx_queue
->queue
, EFX_QWORD_VAL(*event
),
815 rx_ev_buf_owner_id_err
? " [OWNER_ID_ERR]" : "",
816 rx_ev_ip_hdr_chksum_err
?
817 " [IP_HDR_CHKSUM_ERR]" : "",
818 rx_ev_tcp_udp_chksum_err
?
819 " [TCP_UDP_CHKSUM_ERR]" : "",
820 rx_ev_eth_crc_err
? " [ETH_CRC_ERR]" : "",
821 rx_ev_frm_trunc
? " [FRM_TRUNC]" : "",
822 rx_ev_drib_nib
? " [DRIB_NIB]" : "",
823 rx_ev_tobe_disc
? " [TOBE_DISC]" : "",
824 rx_ev_pause_frm
? " [PAUSE]" : "");
829 /* Handle receive events that are not in-order. */
830 static void falcon_handle_rx_bad_index(struct efx_rx_queue
*rx_queue
,
833 struct efx_nic
*efx
= rx_queue
->efx
;
834 unsigned expected
, dropped
;
836 expected
= rx_queue
->removed_count
& FALCON_RXD_RING_MASK
;
837 dropped
= ((index
+ FALCON_RXD_RING_SIZE
- expected
) &
838 FALCON_RXD_RING_MASK
);
839 EFX_INFO(efx
, "dropped %d events (index=%d expected=%d)\n",
840 dropped
, index
, expected
);
842 efx_schedule_reset(efx
, EFX_WORKAROUND_5676(efx
) ?
843 RESET_TYPE_RX_RECOVERY
: RESET_TYPE_DISABLE
);
846 /* Handle a packet received event
848 * Falcon silicon gives a "discard" flag if it's a unicast packet with the
849 * wrong destination address
850 * Also "is multicast" and "matches multicast filter" flags can be used to
851 * discard non-matching multicast packets.
853 static void falcon_handle_rx_event(struct efx_channel
*channel
,
854 const efx_qword_t
*event
)
856 unsigned int rx_ev_desc_ptr
, rx_ev_byte_cnt
;
857 unsigned int rx_ev_hdr_type
, rx_ev_mcast_pkt
;
858 unsigned expected_ptr
;
859 bool rx_ev_pkt_ok
, discard
= false, checksummed
;
860 struct efx_rx_queue
*rx_queue
;
861 struct efx_nic
*efx
= channel
->efx
;
863 /* Basic packet information */
864 rx_ev_byte_cnt
= EFX_QWORD_FIELD(*event
, RX_EV_BYTE_CNT
);
865 rx_ev_pkt_ok
= EFX_QWORD_FIELD(*event
, RX_EV_PKT_OK
);
866 rx_ev_hdr_type
= EFX_QWORD_FIELD(*event
, RX_EV_HDR_TYPE
);
867 WARN_ON(EFX_QWORD_FIELD(*event
, RX_EV_JUMBO_CONT
));
868 WARN_ON(EFX_QWORD_FIELD(*event
, RX_EV_SOP
) != 1);
869 WARN_ON(EFX_QWORD_FIELD(*event
, RX_EV_Q_LABEL
) != channel
->channel
);
871 rx_queue
= &efx
->rx_queue
[channel
->channel
];
873 rx_ev_desc_ptr
= EFX_QWORD_FIELD(*event
, RX_EV_DESC_PTR
);
874 expected_ptr
= rx_queue
->removed_count
& FALCON_RXD_RING_MASK
;
875 if (unlikely(rx_ev_desc_ptr
!= expected_ptr
))
876 falcon_handle_rx_bad_index(rx_queue
, rx_ev_desc_ptr
);
878 if (likely(rx_ev_pkt_ok
)) {
879 /* If packet is marked as OK and packet type is TCP/IPv4 or
880 * UDP/IPv4, then we can rely on the hardware checksum.
882 checksummed
= RX_EV_HDR_TYPE_HAS_CHECKSUMS(rx_ev_hdr_type
);
884 falcon_handle_rx_not_ok(rx_queue
, event
, &rx_ev_pkt_ok
,
889 /* Detect multicast packets that didn't match the filter */
890 rx_ev_mcast_pkt
= EFX_QWORD_FIELD(*event
, RX_EV_MCAST_PKT
);
891 if (rx_ev_mcast_pkt
) {
892 unsigned int rx_ev_mcast_hash_match
=
893 EFX_QWORD_FIELD(*event
, RX_EV_MCAST_HASH_MATCH
);
895 if (unlikely(!rx_ev_mcast_hash_match
))
899 /* Handle received packet */
900 efx_rx_packet(rx_queue
, rx_ev_desc_ptr
, rx_ev_byte_cnt
,
901 checksummed
, discard
);
904 /* Global events are basically PHY events */
905 static void falcon_handle_global_event(struct efx_channel
*channel
,
908 struct efx_nic
*efx
= channel
->efx
;
909 bool handled
= false;
911 if (EFX_QWORD_FIELD(*event
, G_PHY0_INTR
) ||
912 EFX_QWORD_FIELD(*event
, G_PHY1_INTR
) ||
913 EFX_QWORD_FIELD(*event
, XG_PHY_INTR
) ||
914 EFX_QWORD_FIELD(*event
, XFP_PHY_INTR
)) {
915 efx
->phy_op
->clear_interrupt(efx
);
916 queue_work(efx
->workqueue
, &efx
->phy_work
);
920 if ((falcon_rev(efx
) >= FALCON_REV_B0
) &&
921 EFX_QWORD_FIELD(*event
, XG_MNT_INTR_B0
)) {
922 queue_work(efx
->workqueue
, &efx
->mac_work
);
926 if (EFX_QWORD_FIELD_VER(efx
, *event
, RX_RECOVERY
)) {
927 EFX_ERR(efx
, "channel %d seen global RX_RESET "
928 "event. Resetting.\n", channel
->channel
);
930 atomic_inc(&efx
->rx_reset
);
931 efx_schedule_reset(efx
, EFX_WORKAROUND_6555(efx
) ?
932 RESET_TYPE_RX_RECOVERY
: RESET_TYPE_DISABLE
);
937 EFX_ERR(efx
, "channel %d unknown global event "
938 EFX_QWORD_FMT
"\n", channel
->channel
,
939 EFX_QWORD_VAL(*event
));
942 static void falcon_handle_driver_event(struct efx_channel
*channel
,
945 struct efx_nic
*efx
= channel
->efx
;
946 unsigned int ev_sub_code
;
947 unsigned int ev_sub_data
;
949 ev_sub_code
= EFX_QWORD_FIELD(*event
, DRIVER_EV_SUB_CODE
);
950 ev_sub_data
= EFX_QWORD_FIELD(*event
, DRIVER_EV_SUB_DATA
);
952 switch (ev_sub_code
) {
953 case TX_DESCQ_FLS_DONE_EV_DECODE
:
954 EFX_TRACE(efx
, "channel %d TXQ %d flushed\n",
955 channel
->channel
, ev_sub_data
);
957 case RX_DESCQ_FLS_DONE_EV_DECODE
:
958 EFX_TRACE(efx
, "channel %d RXQ %d flushed\n",
959 channel
->channel
, ev_sub_data
);
961 case EVQ_INIT_DONE_EV_DECODE
:
962 EFX_LOG(efx
, "channel %d EVQ %d initialised\n",
963 channel
->channel
, ev_sub_data
);
965 case SRM_UPD_DONE_EV_DECODE
:
966 EFX_TRACE(efx
, "channel %d SRAM update done\n",
969 case WAKE_UP_EV_DECODE
:
970 EFX_TRACE(efx
, "channel %d RXQ %d wakeup event\n",
971 channel
->channel
, ev_sub_data
);
973 case TIMER_EV_DECODE
:
974 EFX_TRACE(efx
, "channel %d RX queue %d timer expired\n",
975 channel
->channel
, ev_sub_data
);
977 case RX_RECOVERY_EV_DECODE
:
978 EFX_ERR(efx
, "channel %d seen DRIVER RX_RESET event. "
979 "Resetting.\n", channel
->channel
);
980 atomic_inc(&efx
->rx_reset
);
981 efx_schedule_reset(efx
,
982 EFX_WORKAROUND_6555(efx
) ?
983 RESET_TYPE_RX_RECOVERY
:
986 case RX_DSC_ERROR_EV_DECODE
:
987 EFX_ERR(efx
, "RX DMA Q %d reports descriptor fetch error."
988 " RX Q %d is disabled.\n", ev_sub_data
, ev_sub_data
);
989 efx_schedule_reset(efx
, RESET_TYPE_RX_DESC_FETCH
);
991 case TX_DSC_ERROR_EV_DECODE
:
992 EFX_ERR(efx
, "TX DMA Q %d reports descriptor fetch error."
993 " TX Q %d is disabled.\n", ev_sub_data
, ev_sub_data
);
994 efx_schedule_reset(efx
, RESET_TYPE_TX_DESC_FETCH
);
997 EFX_TRACE(efx
, "channel %d unknown driver event code %d "
998 "data %04x\n", channel
->channel
, ev_sub_code
,
1004 int falcon_process_eventq(struct efx_channel
*channel
, int rx_quota
)
1006 unsigned int read_ptr
;
1007 efx_qword_t event
, *p_event
;
1011 read_ptr
= channel
->eventq_read_ptr
;
1014 p_event
= falcon_event(channel
, read_ptr
);
1017 if (!falcon_event_present(&event
))
1021 EFX_TRACE(channel
->efx
, "channel %d event is "EFX_QWORD_FMT
"\n",
1022 channel
->channel
, EFX_QWORD_VAL(event
));
1024 /* Clear this event by marking it all ones */
1025 EFX_SET_QWORD(*p_event
);
1027 ev_code
= EFX_QWORD_FIELD(event
, EV_CODE
);
1030 case RX_IP_EV_DECODE
:
1031 falcon_handle_rx_event(channel
, &event
);
1034 case TX_IP_EV_DECODE
:
1035 falcon_handle_tx_event(channel
, &event
);
1037 case DRV_GEN_EV_DECODE
:
1038 channel
->eventq_magic
1039 = EFX_QWORD_FIELD(event
, EVQ_MAGIC
);
1040 EFX_LOG(channel
->efx
, "channel %d received generated "
1041 "event "EFX_QWORD_FMT
"\n", channel
->channel
,
1042 EFX_QWORD_VAL(event
));
1044 case GLOBAL_EV_DECODE
:
1045 falcon_handle_global_event(channel
, &event
);
1047 case DRIVER_EV_DECODE
:
1048 falcon_handle_driver_event(channel
, &event
);
1051 EFX_ERR(channel
->efx
, "channel %d unknown event type %d"
1052 " (data " EFX_QWORD_FMT
")\n", channel
->channel
,
1053 ev_code
, EFX_QWORD_VAL(event
));
1056 /* Increment read pointer */
1057 read_ptr
= (read_ptr
+ 1) & FALCON_EVQ_MASK
;
1059 } while (rx_packets
< rx_quota
);
1061 channel
->eventq_read_ptr
= read_ptr
;
1065 void falcon_set_int_moderation(struct efx_channel
*channel
)
1067 efx_dword_t timer_cmd
;
1068 struct efx_nic
*efx
= channel
->efx
;
1070 /* Set timer register */
1071 if (channel
->irq_moderation
) {
1072 /* Round to resolution supported by hardware. The value we
1073 * program is based at 0. So actual interrupt moderation
1074 * achieved is ((x + 1) * res).
1076 unsigned int res
= 5;
1077 channel
->irq_moderation
-= (channel
->irq_moderation
% res
);
1078 if (channel
->irq_moderation
< res
)
1079 channel
->irq_moderation
= res
;
1080 EFX_POPULATE_DWORD_2(timer_cmd
,
1081 TIMER_MODE
, TIMER_MODE_INT_HLDOFF
,
1083 (channel
->irq_moderation
/ res
) - 1);
1085 EFX_POPULATE_DWORD_2(timer_cmd
,
1086 TIMER_MODE
, TIMER_MODE_DIS
,
1089 falcon_writel_page_locked(efx
, &timer_cmd
, TIMER_CMD_REG_KER
,
1094 /* Allocate buffer table entries for event queue */
1095 int falcon_probe_eventq(struct efx_channel
*channel
)
1097 struct efx_nic
*efx
= channel
->efx
;
1098 unsigned int evq_size
;
1100 evq_size
= FALCON_EVQ_SIZE
* sizeof(efx_qword_t
);
1101 return falcon_alloc_special_buffer(efx
, &channel
->eventq
, evq_size
);
1104 void falcon_init_eventq(struct efx_channel
*channel
)
1106 efx_oword_t evq_ptr
;
1107 struct efx_nic
*efx
= channel
->efx
;
1109 EFX_LOG(efx
, "channel %d event queue in special buffers %d-%d\n",
1110 channel
->channel
, channel
->eventq
.index
,
1111 channel
->eventq
.index
+ channel
->eventq
.entries
- 1);
1113 /* Pin event queue buffer */
1114 falcon_init_special_buffer(efx
, &channel
->eventq
);
1116 /* Fill event queue with all ones (i.e. empty events) */
1117 memset(channel
->eventq
.addr
, 0xff, channel
->eventq
.len
);
1119 /* Push event queue to card */
1120 EFX_POPULATE_OWORD_3(evq_ptr
,
1122 EVQ_SIZE
, FALCON_EVQ_ORDER
,
1123 EVQ_BUF_BASE_ID
, channel
->eventq
.index
);
1124 falcon_write_table(efx
, &evq_ptr
, efx
->type
->evq_ptr_tbl_base
,
1127 falcon_set_int_moderation(channel
);
1130 void falcon_fini_eventq(struct efx_channel
*channel
)
1132 efx_oword_t eventq_ptr
;
1133 struct efx_nic
*efx
= channel
->efx
;
1135 /* Remove event queue from card */
1136 EFX_ZERO_OWORD(eventq_ptr
);
1137 falcon_write_table(efx
, &eventq_ptr
, efx
->type
->evq_ptr_tbl_base
,
1140 /* Unpin event queue */
1141 falcon_fini_special_buffer(efx
, &channel
->eventq
);
1144 /* Free buffers backing event queue */
1145 void falcon_remove_eventq(struct efx_channel
*channel
)
1147 falcon_free_special_buffer(channel
->efx
, &channel
->eventq
);
1151 /* Generates a test event on the event queue. A subsequent call to
1152 * process_eventq() should pick up the event and place the value of
1153 * "magic" into channel->eventq_magic;
1155 void falcon_generate_test_event(struct efx_channel
*channel
, unsigned int magic
)
1157 efx_qword_t test_event
;
1159 EFX_POPULATE_QWORD_2(test_event
,
1160 EV_CODE
, DRV_GEN_EV_DECODE
,
1162 falcon_generate_event(channel
, &test_event
);
1165 void falcon_sim_phy_event(struct efx_nic
*efx
)
1167 efx_qword_t phy_event
;
1169 EFX_POPULATE_QWORD_1(phy_event
, EV_CODE
, GLOBAL_EV_DECODE
);
1171 EFX_SET_OWORD_FIELD(phy_event
, XG_PHY_INTR
, 1);
1173 EFX_SET_OWORD_FIELD(phy_event
, G_PHY0_INTR
, 1);
1175 falcon_generate_event(&efx
->channel
[0], &phy_event
);
1178 /**************************************************************************
1182 **************************************************************************/
1185 static void falcon_poll_flush_events(struct efx_nic
*efx
)
1187 struct efx_channel
*channel
= &efx
->channel
[0];
1188 struct efx_tx_queue
*tx_queue
;
1189 struct efx_rx_queue
*rx_queue
;
1190 unsigned int read_ptr
= channel
->eventq_read_ptr
;
1191 unsigned int end_ptr
= (read_ptr
- 1) & FALCON_EVQ_MASK
;
1194 efx_qword_t
*event
= falcon_event(channel
, read_ptr
);
1195 int ev_code
, ev_sub_code
, ev_queue
;
1198 if (!falcon_event_present(event
))
1201 ev_code
= EFX_QWORD_FIELD(*event
, EV_CODE
);
1202 ev_sub_code
= EFX_QWORD_FIELD(*event
, DRIVER_EV_SUB_CODE
);
1203 if (ev_code
== DRIVER_EV_DECODE
&&
1204 ev_sub_code
== TX_DESCQ_FLS_DONE_EV_DECODE
) {
1205 ev_queue
= EFX_QWORD_FIELD(*event
,
1206 DRIVER_EV_TX_DESCQ_ID
);
1207 if (ev_queue
< EFX_TX_QUEUE_COUNT
) {
1208 tx_queue
= efx
->tx_queue
+ ev_queue
;
1209 tx_queue
->flushed
= true;
1211 } else if (ev_code
== DRIVER_EV_DECODE
&&
1212 ev_sub_code
== RX_DESCQ_FLS_DONE_EV_DECODE
) {
1213 ev_queue
= EFX_QWORD_FIELD(*event
,
1214 DRIVER_EV_RX_DESCQ_ID
);
1215 ev_failed
= EFX_QWORD_FIELD(*event
,
1216 DRIVER_EV_RX_FLUSH_FAIL
);
1217 if (ev_queue
< efx
->n_rx_queues
) {
1218 rx_queue
= efx
->rx_queue
+ ev_queue
;
1220 /* retry the rx flush */
1222 falcon_flush_rx_queue(rx_queue
);
1224 rx_queue
->flushed
= true;
1228 read_ptr
= (read_ptr
+ 1) & FALCON_EVQ_MASK
;
1229 } while (read_ptr
!= end_ptr
);
1232 /* Handle tx and rx flushes at the same time, since they run in
1233 * parallel in the hardware and there's no reason for us to
1235 int falcon_flush_queues(struct efx_nic
*efx
)
1237 struct efx_rx_queue
*rx_queue
;
1238 struct efx_tx_queue
*tx_queue
;
1242 /* Issue flush requests */
1243 efx_for_each_tx_queue(tx_queue
, efx
) {
1244 tx_queue
->flushed
= false;
1245 falcon_flush_tx_queue(tx_queue
);
1247 efx_for_each_rx_queue(rx_queue
, efx
) {
1248 rx_queue
->flushed
= false;
1249 falcon_flush_rx_queue(rx_queue
);
1252 /* Poll the evq looking for flush completions. Since we're not pushing
1253 * any more rx or tx descriptors at this point, we're in no danger of
1254 * overflowing the evq whilst we wait */
1255 for (i
= 0; i
< FALCON_FLUSH_POLL_COUNT
; ++i
) {
1256 msleep(FALCON_FLUSH_INTERVAL
);
1257 falcon_poll_flush_events(efx
);
1259 /* Check if every queue has been succesfully flushed */
1260 outstanding
= false;
1261 efx_for_each_tx_queue(tx_queue
, efx
)
1262 outstanding
|= !tx_queue
->flushed
;
1263 efx_for_each_rx_queue(rx_queue
, efx
)
1264 outstanding
|= !rx_queue
->flushed
;
1269 /* Mark the queues as all flushed. We're going to return failure
1270 * leading to a reset, or fake up success anyway. "flushed" now
1271 * indicates that we tried to flush. */
1272 efx_for_each_tx_queue(tx_queue
, efx
) {
1273 if (!tx_queue
->flushed
)
1274 EFX_ERR(efx
, "tx queue %d flush command timed out\n",
1276 tx_queue
->flushed
= true;
1278 efx_for_each_rx_queue(rx_queue
, efx
) {
1279 if (!rx_queue
->flushed
)
1280 EFX_ERR(efx
, "rx queue %d flush command timed out\n",
1282 rx_queue
->flushed
= true;
1285 if (EFX_WORKAROUND_7803(efx
))
1291 /**************************************************************************
1293 * Falcon hardware interrupts
1294 * The hardware interrupt handler does very little work; all the event
1295 * queue processing is carried out by per-channel tasklets.
1297 **************************************************************************/
1299 /* Enable/disable/generate Falcon interrupts */
1300 static inline void falcon_interrupts(struct efx_nic
*efx
, int enabled
,
1303 efx_oword_t int_en_reg_ker
;
1305 EFX_POPULATE_OWORD_2(int_en_reg_ker
,
1307 DRV_INT_EN_KER
, enabled
);
1308 falcon_write(efx
, &int_en_reg_ker
, INT_EN_REG_KER
);
1311 void falcon_enable_interrupts(struct efx_nic
*efx
)
1313 efx_oword_t int_adr_reg_ker
;
1314 struct efx_channel
*channel
;
1316 EFX_ZERO_OWORD(*((efx_oword_t
*) efx
->irq_status
.addr
));
1317 wmb(); /* Ensure interrupt vector is clear before interrupts enabled */
1319 /* Program address */
1320 EFX_POPULATE_OWORD_2(int_adr_reg_ker
,
1321 NORM_INT_VEC_DIS_KER
, EFX_INT_MODE_USE_MSI(efx
),
1322 INT_ADR_KER
, efx
->irq_status
.dma_addr
);
1323 falcon_write(efx
, &int_adr_reg_ker
, INT_ADR_REG_KER
);
1325 /* Enable interrupts */
1326 falcon_interrupts(efx
, 1, 0);
1328 /* Force processing of all the channels to get the EVQ RPTRs up to
1330 efx_for_each_channel(channel
, efx
)
1331 efx_schedule_channel(channel
);
1334 void falcon_disable_interrupts(struct efx_nic
*efx
)
1336 /* Disable interrupts */
1337 falcon_interrupts(efx
, 0, 0);
1340 /* Generate a Falcon test interrupt
1341 * Interrupt must already have been enabled, otherwise nasty things
1344 void falcon_generate_interrupt(struct efx_nic
*efx
)
1346 falcon_interrupts(efx
, 1, 1);
1349 /* Acknowledge a legacy interrupt from Falcon
1351 * This acknowledges a legacy (not MSI) interrupt via INT_ACK_KER_REG.
1353 * Due to SFC bug 3706 (silicon revision <=A1) reads can be duplicated in the
1354 * BIU. Interrupt acknowledge is read sensitive so must write instead
1355 * (then read to ensure the BIU collector is flushed)
1357 * NB most hardware supports MSI interrupts
1359 static inline void falcon_irq_ack_a1(struct efx_nic
*efx
)
1363 EFX_POPULATE_DWORD_1(reg
, INT_ACK_DUMMY_DATA
, 0xb7eb7e);
1364 falcon_writel(efx
, ®
, INT_ACK_REG_KER_A1
);
1365 falcon_readl(efx
, ®
, WORK_AROUND_BROKEN_PCI_READS_REG_KER_A1
);
1368 /* Process a fatal interrupt
1369 * Disable bus mastering ASAP and schedule a reset
1371 static irqreturn_t
falcon_fatal_interrupt(struct efx_nic
*efx
)
1373 struct falcon_nic_data
*nic_data
= efx
->nic_data
;
1374 efx_oword_t
*int_ker
= efx
->irq_status
.addr
;
1375 efx_oword_t fatal_intr
;
1376 int error
, mem_perr
;
1377 static int n_int_errors
;
1379 falcon_read(efx
, &fatal_intr
, FATAL_INTR_REG_KER
);
1380 error
= EFX_OWORD_FIELD(fatal_intr
, INT_KER_ERROR
);
1382 EFX_ERR(efx
, "SYSTEM ERROR " EFX_OWORD_FMT
" status "
1383 EFX_OWORD_FMT
": %s\n", EFX_OWORD_VAL(*int_ker
),
1384 EFX_OWORD_VAL(fatal_intr
),
1385 error
? "disabling bus mastering" : "no recognised error");
1389 /* If this is a memory parity error dump which blocks are offending */
1390 mem_perr
= EFX_OWORD_FIELD(fatal_intr
, MEM_PERR_INT_KER
);
1393 falcon_read(efx
, ®
, MEM_STAT_REG_KER
);
1394 EFX_ERR(efx
, "SYSTEM ERROR: memory parity error "
1395 EFX_OWORD_FMT
"\n", EFX_OWORD_VAL(reg
));
1398 /* Disable both devices */
1399 pci_clear_master(efx
->pci_dev
);
1400 if (FALCON_IS_DUAL_FUNC(efx
))
1401 pci_clear_master(nic_data
->pci_dev2
);
1402 falcon_disable_interrupts(efx
);
1404 if (++n_int_errors
< FALCON_MAX_INT_ERRORS
) {
1405 EFX_ERR(efx
, "SYSTEM ERROR - reset scheduled\n");
1406 efx_schedule_reset(efx
, RESET_TYPE_INT_ERROR
);
1408 EFX_ERR(efx
, "SYSTEM ERROR - max number of errors seen."
1409 "NIC will be disabled\n");
1410 efx_schedule_reset(efx
, RESET_TYPE_DISABLE
);
1416 /* Handle a legacy interrupt from Falcon
1417 * Acknowledges the interrupt and schedule event queue processing.
1419 static irqreturn_t
falcon_legacy_interrupt_b0(int irq
, void *dev_id
)
1421 struct efx_nic
*efx
= dev_id
;
1422 efx_oword_t
*int_ker
= efx
->irq_status
.addr
;
1423 struct efx_channel
*channel
;
1428 /* Read the ISR which also ACKs the interrupts */
1429 falcon_readl(efx
, ®
, INT_ISR0_B0
);
1430 queues
= EFX_EXTRACT_DWORD(reg
, 0, 31);
1432 /* Check to see if we have a serious error condition */
1433 syserr
= EFX_OWORD_FIELD(*int_ker
, FATAL_INT
);
1434 if (unlikely(syserr
))
1435 return falcon_fatal_interrupt(efx
);
1440 efx
->last_irq_cpu
= raw_smp_processor_id();
1441 EFX_TRACE(efx
, "IRQ %d on CPU %d status " EFX_DWORD_FMT
"\n",
1442 irq
, raw_smp_processor_id(), EFX_DWORD_VAL(reg
));
1444 /* Schedule processing of any interrupting queues */
1445 channel
= &efx
->channel
[0];
1448 efx_schedule_channel(channel
);
1457 static irqreturn_t
falcon_legacy_interrupt_a1(int irq
, void *dev_id
)
1459 struct efx_nic
*efx
= dev_id
;
1460 efx_oword_t
*int_ker
= efx
->irq_status
.addr
;
1461 struct efx_channel
*channel
;
1465 /* Check to see if this is our interrupt. If it isn't, we
1466 * exit without having touched the hardware.
1468 if (unlikely(EFX_OWORD_IS_ZERO(*int_ker
))) {
1469 EFX_TRACE(efx
, "IRQ %d on CPU %d not for me\n", irq
,
1470 raw_smp_processor_id());
1473 efx
->last_irq_cpu
= raw_smp_processor_id();
1474 EFX_TRACE(efx
, "IRQ %d on CPU %d status " EFX_OWORD_FMT
"\n",
1475 irq
, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker
));
1477 /* Check to see if we have a serious error condition */
1478 syserr
= EFX_OWORD_FIELD(*int_ker
, FATAL_INT
);
1479 if (unlikely(syserr
))
1480 return falcon_fatal_interrupt(efx
);
1482 /* Determine interrupting queues, clear interrupt status
1483 * register and acknowledge the device interrupt.
1485 BUILD_BUG_ON(INT_EVQS_WIDTH
> EFX_MAX_CHANNELS
);
1486 queues
= EFX_OWORD_FIELD(*int_ker
, INT_EVQS
);
1487 EFX_ZERO_OWORD(*int_ker
);
1488 wmb(); /* Ensure the vector is cleared before interrupt ack */
1489 falcon_irq_ack_a1(efx
);
1491 /* Schedule processing of any interrupting queues */
1492 channel
= &efx
->channel
[0];
1495 efx_schedule_channel(channel
);
1503 /* Handle an MSI interrupt from Falcon
1505 * Handle an MSI hardware interrupt. This routine schedules event
1506 * queue processing. No interrupt acknowledgement cycle is necessary.
1507 * Also, we never need to check that the interrupt is for us, since
1508 * MSI interrupts cannot be shared.
1510 static irqreturn_t
falcon_msi_interrupt(int irq
, void *dev_id
)
1512 struct efx_channel
*channel
= dev_id
;
1513 struct efx_nic
*efx
= channel
->efx
;
1514 efx_oword_t
*int_ker
= efx
->irq_status
.addr
;
1517 efx
->last_irq_cpu
= raw_smp_processor_id();
1518 EFX_TRACE(efx
, "IRQ %d on CPU %d status " EFX_OWORD_FMT
"\n",
1519 irq
, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker
));
1521 /* Check to see if we have a serious error condition */
1522 syserr
= EFX_OWORD_FIELD(*int_ker
, FATAL_INT
);
1523 if (unlikely(syserr
))
1524 return falcon_fatal_interrupt(efx
);
1526 /* Schedule processing of the channel */
1527 efx_schedule_channel(channel
);
1533 /* Setup RSS indirection table.
1534 * This maps from the hash value of the packet to RXQ
1536 static void falcon_setup_rss_indir_table(struct efx_nic
*efx
)
1539 unsigned long offset
;
1542 if (falcon_rev(efx
) < FALCON_REV_B0
)
1545 for (offset
= RX_RSS_INDIR_TBL_B0
;
1546 offset
< RX_RSS_INDIR_TBL_B0
+ 0x800;
1548 EFX_POPULATE_DWORD_1(dword
, RX_RSS_INDIR_ENT_B0
,
1549 i
% efx
->n_rx_queues
);
1550 falcon_writel(efx
, &dword
, offset
);
1555 /* Hook interrupt handler(s)
1556 * Try MSI and then legacy interrupts.
1558 int falcon_init_interrupt(struct efx_nic
*efx
)
1560 struct efx_channel
*channel
;
1563 if (!EFX_INT_MODE_USE_MSI(efx
)) {
1564 irq_handler_t handler
;
1565 if (falcon_rev(efx
) >= FALCON_REV_B0
)
1566 handler
= falcon_legacy_interrupt_b0
;
1568 handler
= falcon_legacy_interrupt_a1
;
1570 rc
= request_irq(efx
->legacy_irq
, handler
, IRQF_SHARED
,
1573 EFX_ERR(efx
, "failed to hook legacy IRQ %d\n",
1580 /* Hook MSI or MSI-X interrupt */
1581 efx_for_each_channel(channel
, efx
) {
1582 rc
= request_irq(channel
->irq
, falcon_msi_interrupt
,
1583 IRQF_PROBE_SHARED
, /* Not shared */
1584 channel
->name
, channel
);
1586 EFX_ERR(efx
, "failed to hook IRQ %d\n", channel
->irq
);
1594 efx_for_each_channel(channel
, efx
)
1595 free_irq(channel
->irq
, channel
);
1600 void falcon_fini_interrupt(struct efx_nic
*efx
)
1602 struct efx_channel
*channel
;
1605 /* Disable MSI/MSI-X interrupts */
1606 efx_for_each_channel(channel
, efx
) {
1608 free_irq(channel
->irq
, channel
);
1611 /* ACK legacy interrupt */
1612 if (falcon_rev(efx
) >= FALCON_REV_B0
)
1613 falcon_read(efx
, ®
, INT_ISR0_B0
);
1615 falcon_irq_ack_a1(efx
);
1617 /* Disable legacy interrupt */
1618 if (efx
->legacy_irq
)
1619 free_irq(efx
->legacy_irq
, efx
);
1622 /**************************************************************************
1626 **************************************************************************
1629 #define FALCON_SPI_MAX_LEN sizeof(efx_oword_t)
1631 static int falcon_spi_poll(struct efx_nic
*efx
)
1634 falcon_read(efx
, ®
, EE_SPI_HCMD_REG_KER
);
1635 return EFX_OWORD_FIELD(reg
, EE_SPI_HCMD_CMD_EN
) ? -EBUSY
: 0;
1638 /* Wait for SPI command completion */
1639 static int falcon_spi_wait(struct efx_nic
*efx
)
1641 /* Most commands will finish quickly, so we start polling at
1642 * very short intervals. Sometimes the command may have to
1643 * wait for VPD or expansion ROM access outside of our
1644 * control, so we allow up to 100 ms. */
1645 unsigned long timeout
= jiffies
+ 1 + DIV_ROUND_UP(HZ
, 10);
1648 for (i
= 0; i
< 10; i
++) {
1649 if (!falcon_spi_poll(efx
))
1655 if (!falcon_spi_poll(efx
))
1657 if (time_after_eq(jiffies
, timeout
)) {
1658 EFX_ERR(efx
, "timed out waiting for SPI\n");
1661 schedule_timeout_uninterruptible(1);
1665 int falcon_spi_cmd(const struct efx_spi_device
*spi
,
1666 unsigned int command
, int address
,
1667 const void *in
, void *out
, size_t len
)
1669 struct efx_nic
*efx
= spi
->efx
;
1670 bool addressed
= (address
>= 0);
1671 bool reading
= (out
!= NULL
);
1675 /* Input validation */
1676 if (len
> FALCON_SPI_MAX_LEN
)
1678 BUG_ON(!mutex_is_locked(&efx
->spi_lock
));
1680 /* Check that previous command is not still running */
1681 rc
= falcon_spi_poll(efx
);
1685 /* Program address register, if we have an address */
1687 EFX_POPULATE_OWORD_1(reg
, EE_SPI_HADR_ADR
, address
);
1688 falcon_write(efx
, ®
, EE_SPI_HADR_REG_KER
);
1691 /* Program data register, if we have data */
1693 memcpy(®
, in
, len
);
1694 falcon_write(efx
, ®
, EE_SPI_HDATA_REG_KER
);
1697 /* Issue read/write command */
1698 EFX_POPULATE_OWORD_7(reg
,
1699 EE_SPI_HCMD_CMD_EN
, 1,
1700 EE_SPI_HCMD_SF_SEL
, spi
->device_id
,
1701 EE_SPI_HCMD_DABCNT
, len
,
1702 EE_SPI_HCMD_READ
, reading
,
1703 EE_SPI_HCMD_DUBCNT
, 0,
1705 (addressed
? spi
->addr_len
: 0),
1706 EE_SPI_HCMD_ENC
, command
);
1707 falcon_write(efx
, ®
, EE_SPI_HCMD_REG_KER
);
1709 /* Wait for read/write to complete */
1710 rc
= falcon_spi_wait(efx
);
1716 falcon_read(efx
, ®
, EE_SPI_HDATA_REG_KER
);
1717 memcpy(out
, ®
, len
);
1724 falcon_spi_write_limit(const struct efx_spi_device
*spi
, size_t start
)
1726 return min(FALCON_SPI_MAX_LEN
,
1727 (spi
->block_size
- (start
& (spi
->block_size
- 1))));
1731 efx_spi_munge_command(const struct efx_spi_device
*spi
,
1732 const u8 command
, const unsigned int address
)
1734 return command
| (((address
>> 8) & spi
->munge_address
) << 3);
1737 /* Wait up to 10 ms for buffered write completion */
1738 int falcon_spi_wait_write(const struct efx_spi_device
*spi
)
1740 struct efx_nic
*efx
= spi
->efx
;
1741 unsigned long timeout
= jiffies
+ 1 + DIV_ROUND_UP(HZ
, 100);
1746 rc
= falcon_spi_cmd(spi
, SPI_RDSR
, -1, NULL
,
1747 &status
, sizeof(status
));
1750 if (!(status
& SPI_STATUS_NRDY
))
1752 if (time_after_eq(jiffies
, timeout
)) {
1753 EFX_ERR(efx
, "SPI write timeout on device %d"
1754 " last status=0x%02x\n",
1755 spi
->device_id
, status
);
1758 schedule_timeout_uninterruptible(1);
1762 int falcon_spi_read(const struct efx_spi_device
*spi
, loff_t start
,
1763 size_t len
, size_t *retlen
, u8
*buffer
)
1765 size_t block_len
, pos
= 0;
1766 unsigned int command
;
1770 block_len
= min(len
- pos
, FALCON_SPI_MAX_LEN
);
1772 command
= efx_spi_munge_command(spi
, SPI_READ
, start
+ pos
);
1773 rc
= falcon_spi_cmd(spi
, command
, start
+ pos
, NULL
,
1774 buffer
+ pos
, block_len
);
1779 /* Avoid locking up the system */
1781 if (signal_pending(current
)) {
1792 int falcon_spi_write(const struct efx_spi_device
*spi
, loff_t start
,
1793 size_t len
, size_t *retlen
, const u8
*buffer
)
1795 u8 verify_buffer
[FALCON_SPI_MAX_LEN
];
1796 size_t block_len
, pos
= 0;
1797 unsigned int command
;
1801 rc
= falcon_spi_cmd(spi
, SPI_WREN
, -1, NULL
, NULL
, 0);
1805 block_len
= min(len
- pos
,
1806 falcon_spi_write_limit(spi
, start
+ pos
));
1807 command
= efx_spi_munge_command(spi
, SPI_WRITE
, start
+ pos
);
1808 rc
= falcon_spi_cmd(spi
, command
, start
+ pos
,
1809 buffer
+ pos
, NULL
, block_len
);
1813 rc
= falcon_spi_wait_write(spi
);
1817 command
= efx_spi_munge_command(spi
, SPI_READ
, start
+ pos
);
1818 rc
= falcon_spi_cmd(spi
, command
, start
+ pos
,
1819 NULL
, verify_buffer
, block_len
);
1820 if (memcmp(verify_buffer
, buffer
+ pos
, block_len
)) {
1827 /* Avoid locking up the system */
1829 if (signal_pending(current
)) {
1840 /**************************************************************************
1844 **************************************************************************
1847 static int falcon_reset_macs(struct efx_nic
*efx
)
1852 if (falcon_rev(efx
) < FALCON_REV_B0
) {
1853 /* It's not safe to use GLB_CTL_REG to reset the
1854 * macs, so instead use the internal MAC resets
1856 if (!EFX_IS10G(efx
)) {
1857 EFX_POPULATE_OWORD_1(reg
, GM_SW_RST
, 1);
1858 falcon_write(efx
, ®
, GM_CFG1_REG
);
1861 EFX_POPULATE_OWORD_1(reg
, GM_SW_RST
, 0);
1862 falcon_write(efx
, ®
, GM_CFG1_REG
);
1866 EFX_POPULATE_OWORD_1(reg
, XM_CORE_RST
, 1);
1867 falcon_write(efx
, ®
, XM_GLB_CFG_REG
);
1869 for (count
= 0; count
< 10000; count
++) {
1870 falcon_read(efx
, ®
, XM_GLB_CFG_REG
);
1871 if (EFX_OWORD_FIELD(reg
, XM_CORE_RST
) == 0)
1876 EFX_ERR(efx
, "timed out waiting for XMAC core reset\n");
1881 /* MAC stats will fail whilst the TX fifo is draining. Serialise
1882 * the drain sequence with the statistics fetch */
1883 efx_stats_disable(efx
);
1885 falcon_read(efx
, ®
, MAC0_CTRL_REG_KER
);
1886 EFX_SET_OWORD_FIELD(reg
, TXFIFO_DRAIN_EN_B0
, 1);
1887 falcon_write(efx
, ®
, MAC0_CTRL_REG_KER
);
1889 falcon_read(efx
, ®
, GLB_CTL_REG_KER
);
1890 EFX_SET_OWORD_FIELD(reg
, RST_XGTX
, 1);
1891 EFX_SET_OWORD_FIELD(reg
, RST_XGRX
, 1);
1892 EFX_SET_OWORD_FIELD(reg
, RST_EM
, 1);
1893 falcon_write(efx
, ®
, GLB_CTL_REG_KER
);
1897 falcon_read(efx
, ®
, GLB_CTL_REG_KER
);
1898 if (!EFX_OWORD_FIELD(reg
, RST_XGTX
) &&
1899 !EFX_OWORD_FIELD(reg
, RST_XGRX
) &&
1900 !EFX_OWORD_FIELD(reg
, RST_EM
)) {
1901 EFX_LOG(efx
, "Completed MAC reset after %d loops\n",
1906 EFX_ERR(efx
, "MAC reset failed\n");
1913 efx_stats_enable(efx
);
1915 /* If we've reset the EM block and the link is up, then
1916 * we'll have to kick the XAUI link so the PHY can recover */
1917 if (efx
->link_up
&& EFX_IS10G(efx
) && EFX_WORKAROUND_5147(efx
))
1918 falcon_reset_xaui(efx
);
1923 void falcon_drain_tx_fifo(struct efx_nic
*efx
)
1927 if ((falcon_rev(efx
) < FALCON_REV_B0
) ||
1928 (efx
->loopback_mode
!= LOOPBACK_NONE
))
1931 falcon_read(efx
, ®
, MAC0_CTRL_REG_KER
);
1932 /* There is no point in draining more than once */
1933 if (EFX_OWORD_FIELD(reg
, TXFIFO_DRAIN_EN_B0
))
1936 falcon_reset_macs(efx
);
1939 void falcon_deconfigure_mac_wrapper(struct efx_nic
*efx
)
1943 if (falcon_rev(efx
) < FALCON_REV_B0
)
1946 /* Isolate the MAC -> RX */
1947 falcon_read(efx
, ®
, RX_CFG_REG_KER
);
1948 EFX_SET_OWORD_FIELD(reg
, RX_INGR_EN_B0
, 0);
1949 falcon_write(efx
, ®
, RX_CFG_REG_KER
);
1952 falcon_drain_tx_fifo(efx
);
1955 void falcon_reconfigure_mac_wrapper(struct efx_nic
*efx
)
1961 switch (efx
->link_speed
) {
1962 case 10000: link_speed
= 3; break;
1963 case 1000: link_speed
= 2; break;
1964 case 100: link_speed
= 1; break;
1965 default: link_speed
= 0; break;
1967 /* MAC_LINK_STATUS controls MAC backpressure but doesn't work
1968 * as advertised. Disable to ensure packets are not
1969 * indefinitely held and TX queue can be flushed at any point
1970 * while the link is down. */
1971 EFX_POPULATE_OWORD_5(reg
,
1972 MAC_XOFF_VAL
, 0xffff /* max pause time */,
1974 MAC_UC_PROM
, efx
->promiscuous
,
1975 MAC_LINK_STATUS
, 1, /* always set */
1976 MAC_SPEED
, link_speed
);
1977 /* On B0, MAC backpressure can be disabled and packets get
1979 if (falcon_rev(efx
) >= FALCON_REV_B0
) {
1980 EFX_SET_OWORD_FIELD(reg
, TXFIFO_DRAIN_EN_B0
,
1984 falcon_write(efx
, ®
, MAC0_CTRL_REG_KER
);
1986 /* Restore the multicast hash registers. */
1987 falcon_set_multicast_hash(efx
);
1989 /* Transmission of pause frames when RX crosses the threshold is
1990 * covered by RX_XOFF_MAC_EN and XM_TX_CFG_REG:XM_FCNTL.
1991 * Action on receipt of pause frames is controller by XM_DIS_FCNTL */
1992 tx_fc
= !!(efx
->link_fc
& EFX_FC_TX
);
1993 falcon_read(efx
, ®
, RX_CFG_REG_KER
);
1994 EFX_SET_OWORD_FIELD_VER(efx
, reg
, RX_XOFF_MAC_EN
, tx_fc
);
1996 /* Unisolate the MAC -> RX */
1997 if (falcon_rev(efx
) >= FALCON_REV_B0
)
1998 EFX_SET_OWORD_FIELD(reg
, RX_INGR_EN_B0
, 1);
1999 falcon_write(efx
, ®
, RX_CFG_REG_KER
);
2002 int falcon_dma_stats(struct efx_nic
*efx
, unsigned int done_offset
)
2008 if (disable_dma_stats
)
2011 /* Statistics fetch will fail if the MAC is in TX drain */
2012 if (falcon_rev(efx
) >= FALCON_REV_B0
) {
2014 falcon_read(efx
, &temp
, MAC0_CTRL_REG_KER
);
2015 if (EFX_OWORD_FIELD(temp
, TXFIFO_DRAIN_EN_B0
))
2019 dma_done
= (efx
->stats_buffer
.addr
+ done_offset
);
2020 *dma_done
= FALCON_STATS_NOT_DONE
;
2021 wmb(); /* ensure done flag is clear */
2023 /* Initiate DMA transfer of stats */
2024 EFX_POPULATE_OWORD_2(reg
,
2025 MAC_STAT_DMA_CMD
, 1,
2027 efx
->stats_buffer
.dma_addr
);
2028 falcon_write(efx
, ®
, MAC0_STAT_DMA_REG_KER
);
2030 /* Wait for transfer to complete */
2031 for (i
= 0; i
< 400; i
++) {
2032 if (*(volatile u32
*)dma_done
== FALCON_STATS_DONE
) {
2033 rmb(); /* Ensure the stats are valid. */
2039 EFX_ERR(efx
, "timed out waiting for statistics\n");
2043 /**************************************************************************
2045 * PHY access via GMII
2047 **************************************************************************
2050 /* Use the top bit of the MII PHY id to indicate the PHY type
2051 * (1G/10G), with the remaining bits as the actual PHY id.
2053 * This allows us to avoid leaking information from the mii_if_info
2054 * structure into other data structures.
2056 #define FALCON_PHY_ID_ID_WIDTH EFX_WIDTH(MD_PRT_DEV_ADR)
2057 #define FALCON_PHY_ID_ID_MASK ((1 << FALCON_PHY_ID_ID_WIDTH) - 1)
2058 #define FALCON_PHY_ID_WIDTH (FALCON_PHY_ID_ID_WIDTH + 1)
2059 #define FALCON_PHY_ID_MASK ((1 << FALCON_PHY_ID_WIDTH) - 1)
2060 #define FALCON_PHY_ID_10G (1 << (FALCON_PHY_ID_WIDTH - 1))
2063 /* Packing the clause 45 port and device fields into a single value */
2064 #define MD_PRT_ADR_COMP_LBN (MD_PRT_ADR_LBN - MD_DEV_ADR_LBN)
2065 #define MD_PRT_ADR_COMP_WIDTH MD_PRT_ADR_WIDTH
2066 #define MD_DEV_ADR_COMP_LBN 0
2067 #define MD_DEV_ADR_COMP_WIDTH MD_DEV_ADR_WIDTH
2070 /* Wait for GMII access to complete */
2071 static int falcon_gmii_wait(struct efx_nic
*efx
)
2073 efx_dword_t md_stat
;
2076 /* wait upto 50ms - taken max from datasheet */
2077 for (count
= 0; count
< 5000; count
++) {
2078 falcon_readl(efx
, &md_stat
, MD_STAT_REG_KER
);
2079 if (EFX_DWORD_FIELD(md_stat
, MD_BSY
) == 0) {
2080 if (EFX_DWORD_FIELD(md_stat
, MD_LNFL
) != 0 ||
2081 EFX_DWORD_FIELD(md_stat
, MD_BSERR
) != 0) {
2082 EFX_ERR(efx
, "error from GMII access "
2084 EFX_DWORD_VAL(md_stat
));
2091 EFX_ERR(efx
, "timed out waiting for GMII\n");
2095 /* Writes a GMII register of a PHY connected to Falcon using MDIO. */
2096 static void falcon_mdio_write(struct net_device
*net_dev
, int phy_id
,
2097 int addr
, int value
)
2099 struct efx_nic
*efx
= netdev_priv(net_dev
);
2100 unsigned int phy_id2
= phy_id
& FALCON_PHY_ID_ID_MASK
;
2103 /* The 'generic' prt/dev packing in mdio_10g.h is conveniently
2104 * chosen so that the only current user, Falcon, can take the
2105 * packed value and use them directly.
2106 * Fail to build if this assumption is broken.
2108 BUILD_BUG_ON(FALCON_PHY_ID_10G
!= MDIO45_XPRT_ID_IS10G
);
2109 BUILD_BUG_ON(FALCON_PHY_ID_ID_WIDTH
!= MDIO45_PRT_DEV_WIDTH
);
2110 BUILD_BUG_ON(MD_PRT_ADR_COMP_LBN
!= MDIO45_PRT_ID_COMP_LBN
);
2111 BUILD_BUG_ON(MD_DEV_ADR_COMP_LBN
!= MDIO45_DEV_ID_COMP_LBN
);
2113 if (phy_id2
== PHY_ADDR_INVALID
)
2116 /* See falcon_mdio_read for an explanation. */
2117 if (!(phy_id
& FALCON_PHY_ID_10G
)) {
2118 int mmd
= ffs(efx
->phy_op
->mmds
) - 1;
2119 EFX_TRACE(efx
, "Fixing erroneous clause22 write\n");
2120 phy_id2
= mdio_clause45_pack(phy_id2
, mmd
)
2121 & FALCON_PHY_ID_ID_MASK
;
2124 EFX_REGDUMP(efx
, "writing GMII %d register %02x with %04x\n", phy_id
,
2127 spin_lock_bh(&efx
->phy_lock
);
2129 /* Check MII not currently being accessed */
2130 if (falcon_gmii_wait(efx
) != 0)
2133 /* Write the address/ID register */
2134 EFX_POPULATE_OWORD_1(reg
, MD_PHY_ADR
, addr
);
2135 falcon_write(efx
, ®
, MD_PHY_ADR_REG_KER
);
2137 EFX_POPULATE_OWORD_1(reg
, MD_PRT_DEV_ADR
, phy_id2
);
2138 falcon_write(efx
, ®
, MD_ID_REG_KER
);
2141 EFX_POPULATE_OWORD_1(reg
, MD_TXD
, value
);
2142 falcon_write(efx
, ®
, MD_TXD_REG_KER
);
2144 EFX_POPULATE_OWORD_2(reg
,
2147 falcon_write(efx
, ®
, MD_CS_REG_KER
);
2149 /* Wait for data to be written */
2150 if (falcon_gmii_wait(efx
) != 0) {
2151 /* Abort the write operation */
2152 EFX_POPULATE_OWORD_2(reg
,
2155 falcon_write(efx
, ®
, MD_CS_REG_KER
);
2160 spin_unlock_bh(&efx
->phy_lock
);
2163 /* Reads a GMII register from a PHY connected to Falcon. If no value
2164 * could be read, -1 will be returned. */
2165 static int falcon_mdio_read(struct net_device
*net_dev
, int phy_id
, int addr
)
2167 struct efx_nic
*efx
= netdev_priv(net_dev
);
2168 unsigned int phy_addr
= phy_id
& FALCON_PHY_ID_ID_MASK
;
2172 if (phy_addr
== PHY_ADDR_INVALID
)
2175 /* Our PHY code knows whether it needs to talk clause 22(1G) or 45(10G)
2176 * but the generic Linux code does not make any distinction or have
2177 * any state for this.
2178 * We spot the case where someone tried to talk 22 to a 45 PHY and
2179 * redirect the request to the lowest numbered MMD as a clause45
2180 * request. This is enough to allow simple queries like id and link
2181 * state to succeed. TODO: We may need to do more in future.
2183 if (!(phy_id
& FALCON_PHY_ID_10G
)) {
2184 int mmd
= ffs(efx
->phy_op
->mmds
) - 1;
2185 EFX_TRACE(efx
, "Fixing erroneous clause22 read\n");
2186 phy_addr
= mdio_clause45_pack(phy_addr
, mmd
)
2187 & FALCON_PHY_ID_ID_MASK
;
2190 spin_lock_bh(&efx
->phy_lock
);
2192 /* Check MII not currently being accessed */
2193 if (falcon_gmii_wait(efx
) != 0)
2196 EFX_POPULATE_OWORD_1(reg
, MD_PHY_ADR
, addr
);
2197 falcon_write(efx
, ®
, MD_PHY_ADR_REG_KER
);
2199 EFX_POPULATE_OWORD_1(reg
, MD_PRT_DEV_ADR
, phy_addr
);
2200 falcon_write(efx
, ®
, MD_ID_REG_KER
);
2202 /* Request data to be read */
2203 EFX_POPULATE_OWORD_2(reg
, MD_RDC
, 1, MD_GC
, 0);
2204 falcon_write(efx
, ®
, MD_CS_REG_KER
);
2206 /* Wait for data to become available */
2207 value
= falcon_gmii_wait(efx
);
2209 falcon_read(efx
, ®
, MD_RXD_REG_KER
);
2210 value
= EFX_OWORD_FIELD(reg
, MD_RXD
);
2211 EFX_REGDUMP(efx
, "read from GMII %d register %02x, got %04x\n",
2212 phy_id
, addr
, value
);
2214 /* Abort the read operation */
2215 EFX_POPULATE_OWORD_2(reg
,
2218 falcon_write(efx
, ®
, MD_CS_REG_KER
);
2220 EFX_LOG(efx
, "read from GMII 0x%x register %02x, got "
2221 "error %d\n", phy_id
, addr
, value
);
2225 spin_unlock_bh(&efx
->phy_lock
);
2230 static void falcon_init_mdio(struct mii_if_info
*gmii
)
2232 gmii
->mdio_read
= falcon_mdio_read
;
2233 gmii
->mdio_write
= falcon_mdio_write
;
2234 gmii
->phy_id_mask
= FALCON_PHY_ID_MASK
;
2235 gmii
->reg_num_mask
= ((1 << EFX_WIDTH(MD_PHY_ADR
)) - 1);
2238 static int falcon_probe_phy(struct efx_nic
*efx
)
2240 switch (efx
->phy_type
) {
2241 case PHY_TYPE_SFX7101
:
2242 efx
->phy_op
= &falcon_sfx7101_phy_ops
;
2244 case PHY_TYPE_SFT9001A
:
2245 case PHY_TYPE_SFT9001B
:
2246 efx
->phy_op
= &falcon_sft9001_phy_ops
;
2248 case PHY_TYPE_QT2022C2
:
2249 case PHY_TYPE_QT2025C
:
2250 efx
->phy_op
= &falcon_xfp_phy_ops
;
2253 EFX_ERR(efx
, "Unknown PHY type %d\n",
2258 if (efx
->phy_op
->macs
& EFX_XMAC
)
2259 efx
->loopback_modes
|= ((1 << LOOPBACK_XGMII
) |
2260 (1 << LOOPBACK_XGXS
) |
2261 (1 << LOOPBACK_XAUI
));
2262 if (efx
->phy_op
->macs
& EFX_GMAC
)
2263 efx
->loopback_modes
|= (1 << LOOPBACK_GMAC
);
2264 efx
->loopback_modes
|= efx
->phy_op
->loopbacks
;
2269 int falcon_switch_mac(struct efx_nic
*efx
)
2271 struct efx_mac_operations
*old_mac_op
= efx
->mac_op
;
2272 efx_oword_t nic_stat
;
2276 /* Don't try to fetch MAC stats while we're switching MACs */
2277 efx_stats_disable(efx
);
2279 /* Internal loopbacks override the phy speed setting */
2280 if (efx
->loopback_mode
== LOOPBACK_GMAC
) {
2281 efx
->link_speed
= 1000;
2282 efx
->link_fd
= true;
2283 } else if (LOOPBACK_INTERNAL(efx
)) {
2284 efx
->link_speed
= 10000;
2285 efx
->link_fd
= true;
2288 WARN_ON(!mutex_is_locked(&efx
->mac_lock
));
2289 efx
->mac_op
= (EFX_IS10G(efx
) ?
2290 &falcon_xmac_operations
: &falcon_gmac_operations
);
2292 /* Always push the NIC_STAT_REG setting even if the mac hasn't
2293 * changed, because this function is run post online reset */
2294 falcon_read(efx
, &nic_stat
, NIC_STAT_REG
);
2295 strap_val
= EFX_IS10G(efx
) ? 5 : 3;
2296 if (falcon_rev(efx
) >= FALCON_REV_B0
) {
2297 EFX_SET_OWORD_FIELD(nic_stat
, EE_STRAP_EN
, 1);
2298 EFX_SET_OWORD_FIELD(nic_stat
, EE_STRAP_OVR
, strap_val
);
2299 falcon_write(efx
, &nic_stat
, NIC_STAT_REG
);
2301 /* Falcon A1 does not support 1G/10G speed switching
2302 * and must not be used with a PHY that does. */
2303 BUG_ON(EFX_OWORD_FIELD(nic_stat
, STRAP_PINS
) != strap_val
);
2306 if (old_mac_op
== efx
->mac_op
)
2309 EFX_LOG(efx
, "selected %cMAC\n", EFX_IS10G(efx
) ? 'X' : 'G');
2310 /* Not all macs support a mac-level link state */
2313 rc
= falcon_reset_macs(efx
);
2315 efx_stats_enable(efx
);
2319 /* This call is responsible for hooking in the MAC and PHY operations */
2320 int falcon_probe_port(struct efx_nic
*efx
)
2324 /* Hook in PHY operations table */
2325 rc
= falcon_probe_phy(efx
);
2329 /* Set up GMII structure for PHY */
2330 efx
->mii
.supports_gmii
= true;
2331 falcon_init_mdio(&efx
->mii
);
2333 /* Hardware flow ctrl. FalconA RX FIFO too small for pause generation */
2334 if (falcon_rev(efx
) >= FALCON_REV_B0
)
2335 efx
->wanted_fc
= EFX_FC_RX
| EFX_FC_TX
;
2337 efx
->wanted_fc
= EFX_FC_RX
;
2339 /* Allocate buffer for stats */
2340 rc
= falcon_alloc_buffer(efx
, &efx
->stats_buffer
,
2341 FALCON_MAC_STATS_SIZE
);
2344 EFX_LOG(efx
, "stats buffer at %llx (virt %p phys %lx)\n",
2345 (unsigned long long)efx
->stats_buffer
.dma_addr
,
2346 efx
->stats_buffer
.addr
,
2347 virt_to_phys(efx
->stats_buffer
.addr
));
2352 void falcon_remove_port(struct efx_nic
*efx
)
2354 falcon_free_buffer(efx
, &efx
->stats_buffer
);
2357 /**************************************************************************
2359 * Multicast filtering
2361 **************************************************************************
2364 void falcon_set_multicast_hash(struct efx_nic
*efx
)
2366 union efx_multicast_hash
*mc_hash
= &efx
->multicast_hash
;
2368 /* Broadcast packets go through the multicast hash filter.
2369 * ether_crc_le() of the broadcast address is 0xbe2612ff
2370 * so we always add bit 0xff to the mask.
2372 set_bit_le(0xff, mc_hash
->byte
);
2374 falcon_write(efx
, &mc_hash
->oword
[0], MAC_MCAST_HASH_REG0_KER
);
2375 falcon_write(efx
, &mc_hash
->oword
[1], MAC_MCAST_HASH_REG1_KER
);
2379 /**************************************************************************
2383 **************************************************************************/
2385 int falcon_read_nvram(struct efx_nic
*efx
, struct falcon_nvconfig
*nvconfig_out
)
2387 struct falcon_nvconfig
*nvconfig
;
2388 struct efx_spi_device
*spi
;
2390 int rc
, magic_num
, struct_ver
;
2391 __le16
*word
, *limit
;
2394 spi
= efx
->spi_flash
? efx
->spi_flash
: efx
->spi_eeprom
;
2398 region
= kmalloc(FALCON_NVCONFIG_END
, GFP_KERNEL
);
2401 nvconfig
= region
+ NVCONFIG_OFFSET
;
2403 mutex_lock(&efx
->spi_lock
);
2404 rc
= falcon_spi_read(spi
, 0, FALCON_NVCONFIG_END
, NULL
, region
);
2405 mutex_unlock(&efx
->spi_lock
);
2407 EFX_ERR(efx
, "Failed to read %s\n",
2408 efx
->spi_flash
? "flash" : "EEPROM");
2413 magic_num
= le16_to_cpu(nvconfig
->board_magic_num
);
2414 struct_ver
= le16_to_cpu(nvconfig
->board_struct_ver
);
2417 if (magic_num
!= NVCONFIG_BOARD_MAGIC_NUM
) {
2418 EFX_ERR(efx
, "NVRAM bad magic 0x%x\n", magic_num
);
2421 if (struct_ver
< 2) {
2422 EFX_ERR(efx
, "NVRAM has ancient version 0x%x\n", struct_ver
);
2424 } else if (struct_ver
< 4) {
2425 word
= &nvconfig
->board_magic_num
;
2426 limit
= (__le16
*) (nvconfig
+ 1);
2429 limit
= region
+ FALCON_NVCONFIG_END
;
2431 for (csum
= 0; word
< limit
; ++word
)
2432 csum
+= le16_to_cpu(*word
);
2434 if (~csum
& 0xffff) {
2435 EFX_ERR(efx
, "NVRAM has incorrect checksum\n");
2441 memcpy(nvconfig_out
, nvconfig
, sizeof(*nvconfig
));
2448 /* Registers tested in the falcon register test */
2452 } efx_test_registers
[] = {
2453 { ADR_REGION_REG_KER
,
2454 EFX_OWORD32(0x0001FFFF, 0x0001FFFF, 0x0001FFFF, 0x0001FFFF) },
2456 EFX_OWORD32(0xFFFFFFFE, 0x00017FFF, 0x00000000, 0x00000000) },
2458 EFX_OWORD32(0x7FFF0037, 0x00000000, 0x00000000, 0x00000000) },
2460 EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
2461 { MAC0_CTRL_REG_KER
,
2462 EFX_OWORD32(0xFFFF0000, 0x00000000, 0x00000000, 0x00000000) },
2463 { SRM_TX_DC_CFG_REG_KER
,
2464 EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
2465 { RX_DC_CFG_REG_KER
,
2466 EFX_OWORD32(0x0000000F, 0x00000000, 0x00000000, 0x00000000) },
2467 { RX_DC_PF_WM_REG_KER
,
2468 EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
2470 EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
2472 EFX_OWORD32(0x00007337, 0x00000000, 0x00000000, 0x00000000) },
2474 EFX_OWORD32(0x00001F1F, 0x00000000, 0x00000000, 0x00000000) },
2476 EFX_OWORD32(0x00000C68, 0x00000000, 0x00000000, 0x00000000) },
2478 EFX_OWORD32(0x00080164, 0x00000000, 0x00000000, 0x00000000) },
2480 EFX_OWORD32(0x07100A0C, 0x00000000, 0x00000000, 0x00000000) },
2482 EFX_OWORD32(0x00001FF8, 0x00000000, 0x00000000, 0x00000000) },
2484 EFX_OWORD32(0xFFFF0001, 0x00000000, 0x00000000, 0x00000000) },
2486 EFX_OWORD32(0xFFFFFFFF, 0x00000000, 0x00000000, 0x00000000) },
2488 EFX_OWORD32(0x0003FF0F, 0x00000000, 0x00000000, 0x00000000) },
2491 static bool efx_masked_compare_oword(const efx_oword_t
*a
, const efx_oword_t
*b
,
2492 const efx_oword_t
*mask
)
2494 return ((a
->u64
[0] ^ b
->u64
[0]) & mask
->u64
[0]) ||
2495 ((a
->u64
[1] ^ b
->u64
[1]) & mask
->u64
[1]);
2498 int falcon_test_registers(struct efx_nic
*efx
)
2500 unsigned address
= 0, i
, j
;
2501 efx_oword_t mask
, imask
, original
, reg
, buf
;
2503 /* Falcon should be in loopback to isolate the XMAC from the PHY */
2504 WARN_ON(!LOOPBACK_INTERNAL(efx
));
2506 for (i
= 0; i
< ARRAY_SIZE(efx_test_registers
); ++i
) {
2507 address
= efx_test_registers
[i
].address
;
2508 mask
= imask
= efx_test_registers
[i
].mask
;
2509 EFX_INVERT_OWORD(imask
);
2511 falcon_read(efx
, &original
, address
);
2513 /* bit sweep on and off */
2514 for (j
= 0; j
< 128; j
++) {
2515 if (!EFX_EXTRACT_OWORD32(mask
, j
, j
))
2518 /* Test this testable bit can be set in isolation */
2519 EFX_AND_OWORD(reg
, original
, mask
);
2520 EFX_SET_OWORD32(reg
, j
, j
, 1);
2522 falcon_write(efx
, ®
, address
);
2523 falcon_read(efx
, &buf
, address
);
2525 if (efx_masked_compare_oword(®
, &buf
, &mask
))
2528 /* Test this testable bit can be cleared in isolation */
2529 EFX_OR_OWORD(reg
, original
, mask
);
2530 EFX_SET_OWORD32(reg
, j
, j
, 0);
2532 falcon_write(efx
, ®
, address
);
2533 falcon_read(efx
, &buf
, address
);
2535 if (efx_masked_compare_oword(®
, &buf
, &mask
))
2539 falcon_write(efx
, &original
, address
);
2545 EFX_ERR(efx
, "wrote "EFX_OWORD_FMT
" read "EFX_OWORD_FMT
2546 " at address 0x%x mask "EFX_OWORD_FMT
"\n", EFX_OWORD_VAL(reg
),
2547 EFX_OWORD_VAL(buf
), address
, EFX_OWORD_VAL(mask
));
2551 /**************************************************************************
2555 **************************************************************************
2558 /* Resets NIC to known state. This routine must be called in process
2559 * context and is allowed to sleep. */
2560 int falcon_reset_hw(struct efx_nic
*efx
, enum reset_type method
)
2562 struct falcon_nic_data
*nic_data
= efx
->nic_data
;
2563 efx_oword_t glb_ctl_reg_ker
;
2566 EFX_LOG(efx
, "performing hardware reset (%d)\n", method
);
2568 /* Initiate device reset */
2569 if (method
== RESET_TYPE_WORLD
) {
2570 rc
= pci_save_state(efx
->pci_dev
);
2572 EFX_ERR(efx
, "failed to backup PCI state of primary "
2573 "function prior to hardware reset\n");
2576 if (FALCON_IS_DUAL_FUNC(efx
)) {
2577 rc
= pci_save_state(nic_data
->pci_dev2
);
2579 EFX_ERR(efx
, "failed to backup PCI state of "
2580 "secondary function prior to "
2581 "hardware reset\n");
2586 EFX_POPULATE_OWORD_2(glb_ctl_reg_ker
,
2587 EXT_PHY_RST_DUR
, 0x7,
2590 int reset_phy
= (method
== RESET_TYPE_INVISIBLE
?
2591 EXCLUDE_FROM_RESET
: 0);
2593 EFX_POPULATE_OWORD_7(glb_ctl_reg_ker
,
2594 EXT_PHY_RST_CTL
, reset_phy
,
2595 PCIE_CORE_RST_CTL
, EXCLUDE_FROM_RESET
,
2596 PCIE_NSTCK_RST_CTL
, EXCLUDE_FROM_RESET
,
2597 PCIE_SD_RST_CTL
, EXCLUDE_FROM_RESET
,
2598 EE_RST_CTL
, EXCLUDE_FROM_RESET
,
2599 EXT_PHY_RST_DUR
, 0x7 /* 10ms */,
2602 falcon_write(efx
, &glb_ctl_reg_ker
, GLB_CTL_REG_KER
);
2604 EFX_LOG(efx
, "waiting for hardware reset\n");
2605 schedule_timeout_uninterruptible(HZ
/ 20);
2607 /* Restore PCI configuration if needed */
2608 if (method
== RESET_TYPE_WORLD
) {
2609 if (FALCON_IS_DUAL_FUNC(efx
)) {
2610 rc
= pci_restore_state(nic_data
->pci_dev2
);
2612 EFX_ERR(efx
, "failed to restore PCI config for "
2613 "the secondary function\n");
2617 rc
= pci_restore_state(efx
->pci_dev
);
2619 EFX_ERR(efx
, "failed to restore PCI config for the "
2620 "primary function\n");
2623 EFX_LOG(efx
, "successfully restored PCI config\n");
2626 /* Assert that reset complete */
2627 falcon_read(efx
, &glb_ctl_reg_ker
, GLB_CTL_REG_KER
);
2628 if (EFX_OWORD_FIELD(glb_ctl_reg_ker
, SWRST
) != 0) {
2630 EFX_ERR(efx
, "timed out waiting for hardware reset\n");
2633 EFX_LOG(efx
, "hardware reset complete\n");
2637 /* pci_save_state() and pci_restore_state() MUST be called in pairs */
2640 pci_restore_state(efx
->pci_dev
);
2647 /* Zeroes out the SRAM contents. This routine must be called in
2648 * process context and is allowed to sleep.
2650 static int falcon_reset_sram(struct efx_nic
*efx
)
2652 efx_oword_t srm_cfg_reg_ker
, gpio_cfg_reg_ker
;
2655 /* Set the SRAM wake/sleep GPIO appropriately. */
2656 falcon_read(efx
, &gpio_cfg_reg_ker
, GPIO_CTL_REG_KER
);
2657 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker
, GPIO1_OEN
, 1);
2658 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker
, GPIO1_OUT
, 1);
2659 falcon_write(efx
, &gpio_cfg_reg_ker
, GPIO_CTL_REG_KER
);
2661 /* Initiate SRAM reset */
2662 EFX_POPULATE_OWORD_2(srm_cfg_reg_ker
,
2663 SRAM_OOB_BT_INIT_EN
, 1,
2664 SRM_NUM_BANKS_AND_BANK_SIZE
, 0);
2665 falcon_write(efx
, &srm_cfg_reg_ker
, SRM_CFG_REG_KER
);
2667 /* Wait for SRAM reset to complete */
2670 EFX_LOG(efx
, "waiting for SRAM reset (attempt %d)...\n", count
);
2672 /* SRAM reset is slow; expect around 16ms */
2673 schedule_timeout_uninterruptible(HZ
/ 50);
2675 /* Check for reset complete */
2676 falcon_read(efx
, &srm_cfg_reg_ker
, SRM_CFG_REG_KER
);
2677 if (!EFX_OWORD_FIELD(srm_cfg_reg_ker
, SRAM_OOB_BT_INIT_EN
)) {
2678 EFX_LOG(efx
, "SRAM reset complete\n");
2682 } while (++count
< 20); /* wait upto 0.4 sec */
2684 EFX_ERR(efx
, "timed out waiting for SRAM reset\n");
2688 static int falcon_spi_device_init(struct efx_nic
*efx
,
2689 struct efx_spi_device
**spi_device_ret
,
2690 unsigned int device_id
, u32 device_type
)
2692 struct efx_spi_device
*spi_device
;
2694 if (device_type
!= 0) {
2695 spi_device
= kzalloc(sizeof(*spi_device
), GFP_KERNEL
);
2698 spi_device
->device_id
= device_id
;
2700 1 << SPI_DEV_TYPE_FIELD(device_type
, SPI_DEV_TYPE_SIZE
);
2701 spi_device
->addr_len
=
2702 SPI_DEV_TYPE_FIELD(device_type
, SPI_DEV_TYPE_ADDR_LEN
);
2703 spi_device
->munge_address
= (spi_device
->size
== 1 << 9 &&
2704 spi_device
->addr_len
== 1);
2705 spi_device
->erase_command
=
2706 SPI_DEV_TYPE_FIELD(device_type
, SPI_DEV_TYPE_ERASE_CMD
);
2707 spi_device
->erase_size
=
2708 1 << SPI_DEV_TYPE_FIELD(device_type
,
2709 SPI_DEV_TYPE_ERASE_SIZE
);
2710 spi_device
->block_size
=
2711 1 << SPI_DEV_TYPE_FIELD(device_type
,
2712 SPI_DEV_TYPE_BLOCK_SIZE
);
2714 spi_device
->efx
= efx
;
2719 kfree(*spi_device_ret
);
2720 *spi_device_ret
= spi_device
;
2725 static void falcon_remove_spi_devices(struct efx_nic
*efx
)
2727 kfree(efx
->spi_eeprom
);
2728 efx
->spi_eeprom
= NULL
;
2729 kfree(efx
->spi_flash
);
2730 efx
->spi_flash
= NULL
;
2733 /* Extract non-volatile configuration */
2734 static int falcon_probe_nvconfig(struct efx_nic
*efx
)
2736 struct falcon_nvconfig
*nvconfig
;
2740 nvconfig
= kmalloc(sizeof(*nvconfig
), GFP_KERNEL
);
2744 rc
= falcon_read_nvram(efx
, nvconfig
);
2745 if (rc
== -EINVAL
) {
2746 EFX_ERR(efx
, "NVRAM is invalid therefore using defaults\n");
2747 efx
->phy_type
= PHY_TYPE_NONE
;
2748 efx
->mii
.phy_id
= PHY_ADDR_INVALID
;
2754 struct falcon_nvconfig_board_v2
*v2
= &nvconfig
->board_v2
;
2755 struct falcon_nvconfig_board_v3
*v3
= &nvconfig
->board_v3
;
2757 efx
->phy_type
= v2
->port0_phy_type
;
2758 efx
->mii
.phy_id
= v2
->port0_phy_addr
;
2759 board_rev
= le16_to_cpu(v2
->board_revision
);
2761 if (le16_to_cpu(nvconfig
->board_struct_ver
) >= 3) {
2762 __le32 fl
= v3
->spi_device_type
[EE_SPI_FLASH
];
2763 __le32 ee
= v3
->spi_device_type
[EE_SPI_EEPROM
];
2764 rc
= falcon_spi_device_init(efx
, &efx
->spi_flash
,
2769 rc
= falcon_spi_device_init(efx
, &efx
->spi_eeprom
,
2777 /* Read the MAC addresses */
2778 memcpy(efx
->mac_address
, nvconfig
->mac_address
[0], ETH_ALEN
);
2780 EFX_LOG(efx
, "PHY is %d phy_id %d\n", efx
->phy_type
, efx
->mii
.phy_id
);
2782 efx_set_board_info(efx
, board_rev
);
2788 falcon_remove_spi_devices(efx
);
2794 /* Probe the NIC variant (revision, ASIC vs FPGA, function count, port
2795 * count, port speed). Set workaround and feature flags accordingly.
2797 static int falcon_probe_nic_variant(struct efx_nic
*efx
)
2799 efx_oword_t altera_build
;
2800 efx_oword_t nic_stat
;
2802 falcon_read(efx
, &altera_build
, ALTERA_BUILD_REG_KER
);
2803 if (EFX_OWORD_FIELD(altera_build
, VER_ALL
)) {
2804 EFX_ERR(efx
, "Falcon FPGA not supported\n");
2808 falcon_read(efx
, &nic_stat
, NIC_STAT_REG
);
2810 switch (falcon_rev(efx
)) {
2813 EFX_ERR(efx
, "Falcon rev A0 not supported\n");
2817 if (EFX_OWORD_FIELD(nic_stat
, STRAP_PCIE
) == 0) {
2818 EFX_ERR(efx
, "Falcon rev A1 PCI-X not supported\n");
2827 EFX_ERR(efx
, "Unknown Falcon rev %d\n", falcon_rev(efx
));
2831 /* Initial assumed speed */
2832 efx
->link_speed
= EFX_OWORD_FIELD(nic_stat
, STRAP_10G
) ? 10000 : 1000;
2837 /* Probe all SPI devices on the NIC */
2838 static void falcon_probe_spi_devices(struct efx_nic
*efx
)
2840 efx_oword_t nic_stat
, gpio_ctl
, ee_vpd_cfg
;
2843 falcon_read(efx
, &gpio_ctl
, GPIO_CTL_REG_KER
);
2844 falcon_read(efx
, &nic_stat
, NIC_STAT_REG
);
2845 falcon_read(efx
, &ee_vpd_cfg
, EE_VPD_CFG_REG_KER
);
2847 if (EFX_OWORD_FIELD(gpio_ctl
, BOOTED_USING_NVDEVICE
)) {
2848 boot_dev
= (EFX_OWORD_FIELD(nic_stat
, SF_PRST
) ?
2849 EE_SPI_FLASH
: EE_SPI_EEPROM
);
2850 EFX_LOG(efx
, "Booted from %s\n",
2851 boot_dev
== EE_SPI_FLASH
? "flash" : "EEPROM");
2853 /* Disable VPD and set clock dividers to safe
2854 * values for initial programming. */
2856 EFX_LOG(efx
, "Booted from internal ASIC settings;"
2857 " setting SPI config\n");
2858 EFX_POPULATE_OWORD_3(ee_vpd_cfg
, EE_VPD_EN
, 0,
2859 /* 125 MHz / 7 ~= 20 MHz */
2861 /* 125 MHz / 63 ~= 2 MHz */
2862 EE_EE_CLOCK_DIV
, 63);
2863 falcon_write(efx
, &ee_vpd_cfg
, EE_VPD_CFG_REG_KER
);
2866 if (boot_dev
== EE_SPI_FLASH
)
2867 falcon_spi_device_init(efx
, &efx
->spi_flash
, EE_SPI_FLASH
,
2868 default_flash_type
);
2869 if (boot_dev
== EE_SPI_EEPROM
)
2870 falcon_spi_device_init(efx
, &efx
->spi_eeprom
, EE_SPI_EEPROM
,
2874 int falcon_probe_nic(struct efx_nic
*efx
)
2876 struct falcon_nic_data
*nic_data
;
2879 /* Allocate storage for hardware specific data */
2880 nic_data
= kzalloc(sizeof(*nic_data
), GFP_KERNEL
);
2883 efx
->nic_data
= nic_data
;
2885 /* Determine number of ports etc. */
2886 rc
= falcon_probe_nic_variant(efx
);
2890 /* Probe secondary function if expected */
2891 if (FALCON_IS_DUAL_FUNC(efx
)) {
2892 struct pci_dev
*dev
= pci_dev_get(efx
->pci_dev
);
2894 while ((dev
= pci_get_device(EFX_VENDID_SFC
, FALCON_A_S_DEVID
,
2896 if (dev
->bus
== efx
->pci_dev
->bus
&&
2897 dev
->devfn
== efx
->pci_dev
->devfn
+ 1) {
2898 nic_data
->pci_dev2
= dev
;
2902 if (!nic_data
->pci_dev2
) {
2903 EFX_ERR(efx
, "failed to find secondary function\n");
2909 /* Now we can reset the NIC */
2910 rc
= falcon_reset_hw(efx
, RESET_TYPE_ALL
);
2912 EFX_ERR(efx
, "failed to reset NIC\n");
2916 /* Allocate memory for INT_KER */
2917 rc
= falcon_alloc_buffer(efx
, &efx
->irq_status
, sizeof(efx_oword_t
));
2920 BUG_ON(efx
->irq_status
.dma_addr
& 0x0f);
2922 EFX_LOG(efx
, "INT_KER at %llx (virt %p phys %lx)\n",
2923 (unsigned long long)efx
->irq_status
.dma_addr
,
2924 efx
->irq_status
.addr
, virt_to_phys(efx
->irq_status
.addr
));
2926 falcon_probe_spi_devices(efx
);
2928 /* Read in the non-volatile configuration */
2929 rc
= falcon_probe_nvconfig(efx
);
2933 /* Initialise I2C adapter */
2934 efx
->i2c_adap
.owner
= THIS_MODULE
;
2935 nic_data
->i2c_data
= falcon_i2c_bit_operations
;
2936 nic_data
->i2c_data
.data
= efx
;
2937 efx
->i2c_adap
.algo_data
= &nic_data
->i2c_data
;
2938 efx
->i2c_adap
.dev
.parent
= &efx
->pci_dev
->dev
;
2939 strlcpy(efx
->i2c_adap
.name
, "SFC4000 GPIO", sizeof(efx
->i2c_adap
.name
));
2940 rc
= i2c_bit_add_bus(&efx
->i2c_adap
);
2947 falcon_remove_spi_devices(efx
);
2948 falcon_free_buffer(efx
, &efx
->irq_status
);
2951 if (nic_data
->pci_dev2
) {
2952 pci_dev_put(nic_data
->pci_dev2
);
2953 nic_data
->pci_dev2
= NULL
;
2957 kfree(efx
->nic_data
);
2961 /* This call performs hardware-specific global initialisation, such as
2962 * defining the descriptor cache sizes and number of RSS channels.
2963 * It does not set up any buffers, descriptor rings or event queues.
2965 int falcon_init_nic(struct efx_nic
*efx
)
2971 /* Use on-chip SRAM */
2972 falcon_read(efx
, &temp
, NIC_STAT_REG
);
2973 EFX_SET_OWORD_FIELD(temp
, ONCHIP_SRAM
, 1);
2974 falcon_write(efx
, &temp
, NIC_STAT_REG
);
2976 /* Set the source of the GMAC clock */
2977 if (falcon_rev(efx
) == FALCON_REV_B0
) {
2978 falcon_read(efx
, &temp
, GPIO_CTL_REG_KER
);
2979 EFX_SET_OWORD_FIELD(temp
, GPIO_USE_NIC_CLK
, true);
2980 falcon_write(efx
, &temp
, GPIO_CTL_REG_KER
);
2983 /* Set buffer table mode */
2984 EFX_POPULATE_OWORD_1(temp
, BUF_TBL_MODE
, BUF_TBL_MODE_FULL
);
2985 falcon_write(efx
, &temp
, BUF_TBL_CFG_REG_KER
);
2987 rc
= falcon_reset_sram(efx
);
2991 /* Set positions of descriptor caches in SRAM. */
2992 EFX_POPULATE_OWORD_1(temp
, SRM_TX_DC_BASE_ADR
, TX_DC_BASE
/ 8);
2993 falcon_write(efx
, &temp
, SRM_TX_DC_CFG_REG_KER
);
2994 EFX_POPULATE_OWORD_1(temp
, SRM_RX_DC_BASE_ADR
, RX_DC_BASE
/ 8);
2995 falcon_write(efx
, &temp
, SRM_RX_DC_CFG_REG_KER
);
2997 /* Set TX descriptor cache size. */
2998 BUILD_BUG_ON(TX_DC_ENTRIES
!= (16 << TX_DC_ENTRIES_ORDER
));
2999 EFX_POPULATE_OWORD_1(temp
, TX_DC_SIZE
, TX_DC_ENTRIES_ORDER
);
3000 falcon_write(efx
, &temp
, TX_DC_CFG_REG_KER
);
3002 /* Set RX descriptor cache size. Set low watermark to size-8, as
3003 * this allows most efficient prefetching.
3005 BUILD_BUG_ON(RX_DC_ENTRIES
!= (16 << RX_DC_ENTRIES_ORDER
));
3006 EFX_POPULATE_OWORD_1(temp
, RX_DC_SIZE
, RX_DC_ENTRIES_ORDER
);
3007 falcon_write(efx
, &temp
, RX_DC_CFG_REG_KER
);
3008 EFX_POPULATE_OWORD_1(temp
, RX_DC_PF_LWM
, RX_DC_ENTRIES
- 8);
3009 falcon_write(efx
, &temp
, RX_DC_PF_WM_REG_KER
);
3011 /* Clear the parity enables on the TX data fifos as
3012 * they produce false parity errors because of timing issues
3014 if (EFX_WORKAROUND_5129(efx
)) {
3015 falcon_read(efx
, &temp
, SPARE_REG_KER
);
3016 EFX_SET_OWORD_FIELD(temp
, MEM_PERR_EN_TX_DATA
, 0);
3017 falcon_write(efx
, &temp
, SPARE_REG_KER
);
3020 /* Enable all the genuinely fatal interrupts. (They are still
3021 * masked by the overall interrupt mask, controlled by
3022 * falcon_interrupts()).
3024 * Note: All other fatal interrupts are enabled
3026 EFX_POPULATE_OWORD_3(temp
,
3027 ILL_ADR_INT_KER_EN
, 1,
3028 RBUF_OWN_INT_KER_EN
, 1,
3029 TBUF_OWN_INT_KER_EN
, 1);
3030 EFX_INVERT_OWORD(temp
);
3031 falcon_write(efx
, &temp
, FATAL_INTR_REG_KER
);
3033 if (EFX_WORKAROUND_7244(efx
)) {
3034 falcon_read(efx
, &temp
, RX_FILTER_CTL_REG
);
3035 EFX_SET_OWORD_FIELD(temp
, UDP_FULL_SRCH_LIMIT
, 8);
3036 EFX_SET_OWORD_FIELD(temp
, UDP_WILD_SRCH_LIMIT
, 8);
3037 EFX_SET_OWORD_FIELD(temp
, TCP_FULL_SRCH_LIMIT
, 8);
3038 EFX_SET_OWORD_FIELD(temp
, TCP_WILD_SRCH_LIMIT
, 8);
3039 falcon_write(efx
, &temp
, RX_FILTER_CTL_REG
);
3042 falcon_setup_rss_indir_table(efx
);
3044 /* Setup RX. Wait for descriptor is broken and must
3045 * be disabled. RXDP recovery shouldn't be needed, but is.
3047 falcon_read(efx
, &temp
, RX_SELF_RST_REG_KER
);
3048 EFX_SET_OWORD_FIELD(temp
, RX_NODESC_WAIT_DIS
, 1);
3049 EFX_SET_OWORD_FIELD(temp
, RX_RECOVERY_EN
, 1);
3050 if (EFX_WORKAROUND_5583(efx
))
3051 EFX_SET_OWORD_FIELD(temp
, RX_ISCSI_DIS
, 1);
3052 falcon_write(efx
, &temp
, RX_SELF_RST_REG_KER
);
3054 /* Disable the ugly timer-based TX DMA backoff and allow TX DMA to be
3055 * controlled by the RX FIFO fill level. Set arbitration to one pkt/Q.
3057 falcon_read(efx
, &temp
, TX_CFG2_REG_KER
);
3058 EFX_SET_OWORD_FIELD(temp
, TX_RX_SPACER
, 0xfe);
3059 EFX_SET_OWORD_FIELD(temp
, TX_RX_SPACER_EN
, 1);
3060 EFX_SET_OWORD_FIELD(temp
, TX_ONE_PKT_PER_Q
, 1);
3061 EFX_SET_OWORD_FIELD(temp
, TX_CSR_PUSH_EN
, 0);
3062 EFX_SET_OWORD_FIELD(temp
, TX_DIS_NON_IP_EV
, 1);
3063 /* Enable SW_EV to inherit in char driver - assume harmless here */
3064 EFX_SET_OWORD_FIELD(temp
, TX_SW_EV_EN
, 1);
3065 /* Prefetch threshold 2 => fetch when descriptor cache half empty */
3066 EFX_SET_OWORD_FIELD(temp
, TX_PREF_THRESHOLD
, 2);
3067 /* Squash TX of packets of 16 bytes or less */
3068 if (falcon_rev(efx
) >= FALCON_REV_B0
&& EFX_WORKAROUND_9141(efx
))
3069 EFX_SET_OWORD_FIELD(temp
, TX_FLUSH_MIN_LEN_EN_B0
, 1);
3070 falcon_write(efx
, &temp
, TX_CFG2_REG_KER
);
3072 /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
3073 * descriptors (which is bad).
3075 falcon_read(efx
, &temp
, TX_CFG_REG_KER
);
3076 EFX_SET_OWORD_FIELD(temp
, TX_NO_EOP_DISC_EN
, 0);
3077 falcon_write(efx
, &temp
, TX_CFG_REG_KER
);
3080 falcon_read(efx
, &temp
, RX_CFG_REG_KER
);
3081 EFX_SET_OWORD_FIELD_VER(efx
, temp
, RX_DESC_PUSH_EN
, 0);
3082 if (EFX_WORKAROUND_7575(efx
))
3083 EFX_SET_OWORD_FIELD_VER(efx
, temp
, RX_USR_BUF_SIZE
,
3085 if (falcon_rev(efx
) >= FALCON_REV_B0
)
3086 EFX_SET_OWORD_FIELD(temp
, RX_INGR_EN_B0
, 1);
3088 /* RX FIFO flow control thresholds */
3089 thresh
= ((rx_xon_thresh_bytes
>= 0) ?
3090 rx_xon_thresh_bytes
: efx
->type
->rx_xon_thresh
);
3091 EFX_SET_OWORD_FIELD_VER(efx
, temp
, RX_XON_MAC_TH
, thresh
/ 256);
3092 thresh
= ((rx_xoff_thresh_bytes
>= 0) ?
3093 rx_xoff_thresh_bytes
: efx
->type
->rx_xoff_thresh
);
3094 EFX_SET_OWORD_FIELD_VER(efx
, temp
, RX_XOFF_MAC_TH
, thresh
/ 256);
3095 /* RX control FIFO thresholds [32 entries] */
3096 EFX_SET_OWORD_FIELD_VER(efx
, temp
, RX_XON_TX_TH
, 20);
3097 EFX_SET_OWORD_FIELD_VER(efx
, temp
, RX_XOFF_TX_TH
, 25);
3098 falcon_write(efx
, &temp
, RX_CFG_REG_KER
);
3100 /* Set destination of both TX and RX Flush events */
3101 if (falcon_rev(efx
) >= FALCON_REV_B0
) {
3102 EFX_POPULATE_OWORD_1(temp
, FLS_EVQ_ID
, 0);
3103 falcon_write(efx
, &temp
, DP_CTRL_REG
);
3109 void falcon_remove_nic(struct efx_nic
*efx
)
3111 struct falcon_nic_data
*nic_data
= efx
->nic_data
;
3114 /* Remove I2C adapter and clear it in preparation for a retry */
3115 rc
= i2c_del_adapter(&efx
->i2c_adap
);
3117 memset(&efx
->i2c_adap
, 0, sizeof(efx
->i2c_adap
));
3119 falcon_remove_spi_devices(efx
);
3120 falcon_free_buffer(efx
, &efx
->irq_status
);
3122 falcon_reset_hw(efx
, RESET_TYPE_ALL
);
3124 /* Release the second function after the reset */
3125 if (nic_data
->pci_dev2
) {
3126 pci_dev_put(nic_data
->pci_dev2
);
3127 nic_data
->pci_dev2
= NULL
;
3130 /* Tear down the private nic state */
3131 kfree(efx
->nic_data
);
3132 efx
->nic_data
= NULL
;
3135 void falcon_update_nic_stats(struct efx_nic
*efx
)
3139 falcon_read(efx
, &cnt
, RX_NODESC_DROP_REG_KER
);
3140 efx
->n_rx_nodesc_drop_cnt
+= EFX_OWORD_FIELD(cnt
, RX_NODESC_DROP_CNT
);
3143 /**************************************************************************
3145 * Revision-dependent attributes used by efx.c
3147 **************************************************************************
3150 struct efx_nic_type falcon_a_nic_type
= {
3152 .mem_map_size
= 0x20000,
3153 .txd_ptr_tbl_base
= TX_DESC_PTR_TBL_KER_A1
,
3154 .rxd_ptr_tbl_base
= RX_DESC_PTR_TBL_KER_A1
,
3155 .buf_tbl_base
= BUF_TBL_KER_A1
,
3156 .evq_ptr_tbl_base
= EVQ_PTR_TBL_KER_A1
,
3157 .evq_rptr_tbl_base
= EVQ_RPTR_REG_KER_A1
,
3158 .txd_ring_mask
= FALCON_TXD_RING_MASK
,
3159 .rxd_ring_mask
= FALCON_RXD_RING_MASK
,
3160 .evq_size
= FALCON_EVQ_SIZE
,
3161 .max_dma_mask
= FALCON_DMA_MASK
,
3162 .tx_dma_mask
= FALCON_TX_DMA_MASK
,
3163 .bug5391_mask
= 0xf,
3164 .rx_xoff_thresh
= 2048,
3165 .rx_xon_thresh
= 512,
3166 .rx_buffer_padding
= 0x24,
3167 .max_interrupt_mode
= EFX_INT_MODE_MSI
,
3168 .phys_addr_channels
= 4,
3171 struct efx_nic_type falcon_b_nic_type
= {
3173 /* Map everything up to and including the RSS indirection
3174 * table. Don't map MSI-X table, MSI-X PBA since Linux
3175 * requires that they not be mapped. */
3176 .mem_map_size
= RX_RSS_INDIR_TBL_B0
+ 0x800,
3177 .txd_ptr_tbl_base
= TX_DESC_PTR_TBL_KER_B0
,
3178 .rxd_ptr_tbl_base
= RX_DESC_PTR_TBL_KER_B0
,
3179 .buf_tbl_base
= BUF_TBL_KER_B0
,
3180 .evq_ptr_tbl_base
= EVQ_PTR_TBL_KER_B0
,
3181 .evq_rptr_tbl_base
= EVQ_RPTR_REG_KER_B0
,
3182 .txd_ring_mask
= FALCON_TXD_RING_MASK
,
3183 .rxd_ring_mask
= FALCON_RXD_RING_MASK
,
3184 .evq_size
= FALCON_EVQ_SIZE
,
3185 .max_dma_mask
= FALCON_DMA_MASK
,
3186 .tx_dma_mask
= FALCON_TX_DMA_MASK
,
3188 .rx_xoff_thresh
= 54272, /* ~80Kb - 3*max MTU */
3189 .rx_xon_thresh
= 27648, /* ~3*max MTU */
3190 .rx_buffer_padding
= 0,
3191 .max_interrupt_mode
= EFX_INT_MODE_MSIX
,
3192 .phys_addr_channels
= 32, /* Hardware limit is 64, but the legacy
3193 * interrupt handler only supports 32