include/asm-powerpc/mpic.h

   1 #ifndef _ASM_POWERPC_MPIC_H
   2 #define _ASM_POWERPC_MPIC_H
   3 #ifdef __KERNEL__
   4
   5 #include <linux/irq.h>
   6
   7 /*
   8  * Global registers
   9  */
  10
  11 #define MPIC_GREG_BASE                  0x01000
  12
  13 #define MPIC_GREG_FEATURE_0             0x00000
  14 #define         MPIC_GREG_FEATURE_LAST_SRC_MASK         0x07ff0000
  15 #define         MPIC_GREG_FEATURE_LAST_SRC_SHIFT        16
  16 #define         MPIC_GREG_FEATURE_LAST_CPU_MASK         0x00001f00
  17 #define         MPIC_GREG_FEATURE_LAST_CPU_SHIFT        8
  18 #define         MPIC_GREG_FEATURE_VERSION_MASK          0xff
  19 #define MPIC_GREG_FEATURE_1             0x00010
  20 #define MPIC_GREG_GLOBAL_CONF_0         0x00020
  21 #define         MPIC_GREG_GCONF_RESET                   0x80000000
  22 #define         MPIC_GREG_GCONF_8259_PTHROU_DIS         0x20000000
  23 #define         MPIC_GREG_GCONF_BASE_MASK               0x000fffff
  24 #define MPIC_GREG_GLOBAL_CONF_1         0x00030
  25 #define         MPIC_GREG_GLOBAL_CONF_1_SIE             0x08000000
  26 #define         MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK  0x70000000
  27 #define         MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(r)    \
  28                         (((r) << 28) & MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK)
  29 #define MPIC_GREG_VENDOR_0              0x00040
  30 #define MPIC_GREG_VENDOR_1              0x00050
  31 #define MPIC_GREG_VENDOR_2              0x00060
  32 #define MPIC_GREG_VENDOR_3              0x00070
  33 #define MPIC_GREG_VENDOR_ID             0x00080
  34 #define         MPIC_GREG_VENDOR_ID_STEPPING_MASK       0x00ff0000
  35 #define         MPIC_GREG_VENDOR_ID_STEPPING_SHIFT      16
  36 #define         MPIC_GREG_VENDOR_ID_DEVICE_ID_MASK      0x0000ff00
  37 #define         MPIC_GREG_VENDOR_ID_DEVICE_ID_SHIFT     8
  38 #define         MPIC_GREG_VENDOR_ID_VENDOR_ID_MASK      0x000000ff
  39 #define MPIC_GREG_PROCESSOR_INIT        0x00090
  40 #define MPIC_GREG_IPI_VECTOR_PRI_0      0x000a0
  41 #define MPIC_GREG_IPI_VECTOR_PRI_1      0x000b0
  42 #define MPIC_GREG_IPI_VECTOR_PRI_2      0x000c0
  43 #define MPIC_GREG_IPI_VECTOR_PRI_3      0x000d0
  44 #define MPIC_GREG_SPURIOUS              0x000e0
  45 #define MPIC_GREG_TIMER_FREQ            0x000f0
  46
  47 /*
  48  *
  49  * Timer registers
  50  */
  51 #define MPIC_TIMER_BASE                 0x01100
  52 #define MPIC_TIMER_STRIDE               0x40
  53
  54 #define MPIC_TIMER_CURRENT_CNT          0x00000
  55 #define MPIC_TIMER_BASE_CNT             0x00010
  56 #define MPIC_TIMER_VECTOR_PRI           0x00020
  57 #define MPIC_TIMER_DESTINATION          0x00030
  58
  59 /*
  60  * Per-Processor registers
  61  */
  62
  63 #define MPIC_CPU_THISBASE               0x00000
  64 #define MPIC_CPU_BASE                   0x20000
  65 #define MPIC_CPU_STRIDE                 0x01000
  66
  67 #define MPIC_CPU_IPI_DISPATCH_0         0x00040
  68 #define MPIC_CPU_IPI_DISPATCH_1         0x00050
  69 #define MPIC_CPU_IPI_DISPATCH_2         0x00060
  70 #define MPIC_CPU_IPI_DISPATCH_3         0x00070
  71 #define MPIC_CPU_CURRENT_TASK_PRI       0x00080
  72 #define         MPIC_CPU_TASKPRI_MASK                   0x0000000f
  73 #define MPIC_CPU_WHOAMI                 0x00090
  74 #define         MPIC_CPU_WHOAMI_MASK                    0x0000001f
  75 #define MPIC_CPU_INTACK                 0x000a0
  76 #define MPIC_CPU_EOI                    0x000b0
  77
  78 /*
  79  * Per-source registers
  80  */
  81
  82 #define MPIC_IRQ_BASE                   0x10000
  83 #define MPIC_IRQ_STRIDE                 0x00020
  84 #define MPIC_IRQ_VECTOR_PRI             0x00000
  85 #define         MPIC_VECPRI_MASK                        0x80000000
  86 #define         MPIC_VECPRI_ACTIVITY                    0x40000000      /* Read Only */
  87 #define         MPIC_VECPRI_PRIORITY_MASK               0x000f0000
  88 #define         MPIC_VECPRI_PRIORITY_SHIFT              16
  89 #define         MPIC_VECPRI_VECTOR_MASK                 0x000007ff
  90 #define         MPIC_VECPRI_POLARITY_POSITIVE           0x00800000
  91 #define         MPIC_VECPRI_POLARITY_NEGATIVE           0x00000000
  92 #define         MPIC_VECPRI_POLARITY_MASK               0x00800000
  93 #define         MPIC_VECPRI_SENSE_LEVEL                 0x00400000
  94 #define         MPIC_VECPRI_SENSE_EDGE                  0x00000000
  95 #define         MPIC_VECPRI_SENSE_MASK                  0x00400000
  96 #define MPIC_IRQ_DESTINATION            0x00010
  97
  98 #define MPIC_MAX_IRQ_SOURCES    2048
  99 #define MPIC_MAX_CPUS           32
 100 #define MPIC_MAX_ISU            32
 101
 102 /*
 103  * Special vector numbers (internal use only)
 104  */
 105 #define MPIC_VEC_SPURRIOUS      255
 106 #define MPIC_VEC_IPI_3          254
 107 #define MPIC_VEC_IPI_2          253
 108 #define MPIC_VEC_IPI_1          252
 109 #define MPIC_VEC_IPI_0          251
 110
 111 /* unused */
 112 #define MPIC_VEC_TIMER_3        250
 113 #define MPIC_VEC_TIMER_2        249
 114 #define MPIC_VEC_TIMER_1        248
 115 #define MPIC_VEC_TIMER_0        247
 116
 117 /* Type definition of the cascade handler */
 118 typedef int (*mpic_cascade_t)(struct pt_regs *regs, void *data);
 119
 120 #ifdef CONFIG_MPIC_BROKEN_U3
 121 /* Fixup table entry */
 122 struct mpic_irq_fixup
 123 {
 124         u8 __iomem      *base;
 125         u8 __iomem      *applebase;
 126         u32             data;
 127         unsigned int    index;
 128 };
 129 #endif /* CONFIG_MPIC_BROKEN_U3 */
 130
 131
 132 /* The instance data of a given MPIC */
 133 struct mpic
 134 {
 135         /* The "linux" controller struct */
 136         hw_irq_controller       hc_irq;
 137 #ifdef CONFIG_SMP
 138         hw_irq_controller       hc_ipi;
 139 #endif
 140         const char              *name;
 141         /* Flags */
 142         unsigned int            flags;
 143         /* How many irq sources in a given ISU */
 144         unsigned int            isu_size;
 145         unsigned int            isu_shift;
 146         unsigned int            isu_mask;
 147         /* Offset of irq vector numbers */
 148         unsigned int            irq_offset;
 149         unsigned int            irq_count;
 150         /* Offset of ipi vector numbers */
 151         unsigned int            ipi_offset;
 152         /* Number of sources */
 153         unsigned int            num_sources;
 154         /* Number of CPUs */
 155         unsigned int            num_cpus;
 156         /* cascade handler */
 157         mpic_cascade_t          cascade;
 158         void                    *cascade_data;
 159         unsigned int            cascade_vec;
 160         /* senses array */
 161         unsigned char           *senses;
 162         unsigned int            senses_count;
 163
 164 #ifdef CONFIG_MPIC_BROKEN_U3
 165         /* The fixup table */
 166         struct mpic_irq_fixup   *fixups;
 167         spinlock_t              fixup_lock;
 168 #endif
 169
 170         /* The various ioremap'ed bases */
 171         volatile u32 __iomem    *gregs;
 172         volatile u32 __iomem    *tmregs;
 173         volatile u32 __iomem    *cpuregs[MPIC_MAX_CPUS];
 174         volatile u32 __iomem    *isus[MPIC_MAX_ISU];
 175
 176         /* link */
 177         struct mpic             *next;
 178 };
 179
 180 /* This is the primary controller, only that one has IPIs and
 181  * has afinity control. A non-primary MPIC always uses CPU0
 182  * registers only
 183  */
 184 #define MPIC_PRIMARY                    0x00000001
 185 /* Set this for a big-endian MPIC */
 186 #define MPIC_BIG_ENDIAN                 0x00000002
 187 /* Broken U3 MPIC */
 188 #define MPIC_BROKEN_U3                  0x00000004
 189 /* Broken IPI registers (autodetected) */
 190 #define MPIC_BROKEN_IPI                 0x00000008
 191 /* MPIC wants a reset */
 192 #define MPIC_WANTS_RESET                0x00000010
 193
 194 /* Allocate the controller structure and setup the linux irq descs
 195  * for the range if interrupts passed in. No HW initialization is
 196  * actually performed.
 197  *
 198  * @phys_addr:  physial base address of the MPIC
 199  * @flags:      flags, see constants above
 200  * @isu_size:   number of interrupts in an ISU. Use 0 to use a
 201  *              standard ISU-less setup (aka powermac)
 202  * @irq_offset: first irq number to assign to this mpic
 203  * @irq_count:  number of irqs to use with this mpic IRQ sources. Pass 0
 204  *              to match the number of sources
 205  * @ipi_offset: first irq number to assign to this mpic IPI sources,
 206  *              used only on primary mpic
 207  * @senses:     array of sense values
 208  * @senses_num: number of entries in the array
 209  *
 210  * Note about the sense array. If none is passed, all interrupts are
 211  * setup to be level negative unless MPIC_BROKEN_U3 is set in which
 212  * case they are edge positive (and the array is ignored anyway).
 213  * The values in the array start at the first source of the MPIC,
 214  * that is senses[0] correspond to linux irq "irq_offset".
 215  */
 216 extern struct mpic *mpic_alloc(unsigned long phys_addr,
 217                                unsigned int flags,
 218                                unsigned int isu_size,
 219                                unsigned int irq_offset,
 220                                unsigned int irq_count,
 221                                unsigned int ipi_offset,
 222                                unsigned char *senses,
 223                                unsigned int senses_num,
 224                                const char *name);
 225
 226 /* Assign ISUs, to call before mpic_init()
 227  *
 228  * @mpic:       controller structure as returned by mpic_alloc()
 229  * @isu_num:    ISU number
 230  * @phys_addr:  physical address of the ISU
 231  */
 232 extern void mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
 233                             unsigned long phys_addr);
 234
 235 /* Initialize the controller. After this has been called, none of the above
 236  * should be called again for this mpic
 237  */
 238 extern void mpic_init(struct mpic *mpic);
 239
 240 /* Setup a cascade. Currently, only one cascade is supported this
 241  * way, though you can always do a normal request_irq() and add
 242  * other cascades this way. You should call this _after_ having
 243  * added all the ISUs
 244  *
 245  * @irq_no:     "linux" irq number of the cascade (that is offset'ed vector)
 246  * @handler:    cascade handler function
 247  */
 248 extern void mpic_setup_cascade(unsigned int irq_no, mpic_cascade_t hanlder,
 249                                void *data);
 250
 251 /*
 252  * All of the following functions must only be used after the
 253  * ISUs have been assigned and the controller fully initialized
 254  * with mpic_init()
 255  */
 256
 257
 258 /* Change/Read the priority of an interrupt. Default is 8 for irqs and
 259  * 10 for IPIs. You can call this on both IPIs and IRQ numbers, but the
 260  * IPI number is then the offset'ed (linux irq number mapped to the IPI)
 261  */
 262 extern void mpic_irq_set_priority(unsigned int irq, unsigned int pri);
 263 extern unsigned int mpic_irq_get_priority(unsigned int irq);
 264
 265 /* Setup a non-boot CPU */
 266 extern void mpic_setup_this_cpu(void);
 267
 268 /* Clean up for kexec (or cpu offline or ...) */
 269 extern void mpic_teardown_this_cpu(int secondary);
 270
 271 /* Get the current cpu priority for this cpu (0..15) */
 272 extern int mpic_cpu_get_priority(void);
 273
 274 /* Set the current cpu priority for this cpu */
 275 extern void mpic_cpu_set_priority(int prio);
 276
 277 /* Request IPIs on primary mpic */
 278 extern void mpic_request_ipis(void);
 279
 280 /* Send an IPI (non offseted number 0..3) */
 281 extern void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask);
 282
 283 /* Send a message (IPI) to a given target (cpu number or MSG_*) */
 284 void smp_mpic_message_pass(int target, int msg);
 285
 286 /* Fetch interrupt from a given mpic */
 287 extern int mpic_get_one_irq(struct mpic *mpic, struct pt_regs *regs);
 288 /* This one gets to the primary mpic */
 289 extern int mpic_get_irq(struct pt_regs *regs);
 290
 291 /* Set the EPIC clock ratio */
 292 void mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio);
 293
 294 /* Enable/Disable EPIC serial interrupt mode */
 295 void mpic_set_serial_int(struct mpic *mpic, int enable);
 296
 297 /* global mpic for pSeries */
 298 extern struct mpic *pSeries_mpic;
 299
 300 #endif /* __KERNEL__ */
 301 #endif  /* _ASM_POWERPC_MPIC_H */