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Merge branch 'linus' into x86/x2apic
[linux-2.6/verdex.git] / include / asm-x86 / processor.h
blobd2bf5fe8f4ffa19923ee68c297786b965ca226ba
1 #ifndef __ASM_X86_PROCESSOR_H
2 #define __ASM_X86_PROCESSOR_H
3
4 #include <asm/processor-flags.h>
5
6 /* Forward declaration, a strange C thing */
7 struct task_struct;
8 struct mm_struct;
9
10 #include <asm/vm86.h>
11 #include <asm/math_emu.h>
12 #include <asm/segment.h>
13 #include <asm/types.h>
14 #include <asm/sigcontext.h>
15 #include <asm/current.h>
16 #include <asm/cpufeature.h>
17 #include <asm/system.h>
18 #include <asm/page.h>
19 #include <asm/percpu.h>
20 #include <asm/msr.h>
21 #include <asm/desc_defs.h>
22 #include <asm/nops.h>
23
24 #include <linux/personality.h>
25 #include <linux/cpumask.h>
26 #include <linux/cache.h>
27 #include <linux/threads.h>
28 #include <linux/init.h>
29
30 /*
31 * Default implementation of macro that returns current
32 * instruction pointer ("program counter").
33 */
34 static inline void *current_text_addr(void)
35 {
36 void *pc;
37
38 asm volatile("mov $1f, %0; 1:":"=r" (pc));
39
40 return pc;
41 }
42
43 #ifdef CONFIG_X86_VSMP
44 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT)
45 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
46 #else
47 # define ARCH_MIN_TASKALIGN 16
48 # define ARCH_MIN_MMSTRUCT_ALIGN 0
49 #endif
50
51 /*
52 * CPU type and hardware bug flags. Kept separately for each CPU.
53 * Members of this structure are referenced in head.S, so think twice
54 * before touching them. [mj]
55 */
56
57 struct cpuinfo_x86 {
58 __u8 x86; /* CPU family */
59 __u8 x86_vendor; /* CPU vendor */
60 __u8 x86_model;
61 __u8 x86_mask;
62 #ifdef CONFIG_X86_32
63 char wp_works_ok; /* It doesn't on 386's */
64
65 /* Problems on some 486Dx4's and old 386's: */
66 char hlt_works_ok;
67 char hard_math;
68 char rfu;
69 char fdiv_bug;
70 char f00f_bug;
71 char coma_bug;
72 char pad0;
73 #else
74 /* Number of 4K pages in DTLB/ITLB combined(in pages): */
75 int x86_tlbsize;
76 __u8 x86_virt_bits;
77 __u8 x86_phys_bits;
78 /* CPUID returned core id bits: */
79 __u8 x86_coreid_bits;
80 /* Max extended CPUID function supported: */
81 __u32 extended_cpuid_level;
82 #endif
83 /* Maximum supported CPUID level, -1=no CPUID: */
84 int cpuid_level;
85 __u32 x86_capability[NCAPINTS];
86 char x86_vendor_id[16];
87 char x86_model_id[64];
88 /* in KB - valid for CPUS which support this call: */
89 int x86_cache_size;
90 int x86_cache_alignment; /* In bytes */
91 int x86_power;
92 unsigned long loops_per_jiffy;
93 #ifdef CONFIG_SMP
94 /* cpus sharing the last level cache: */
95 cpumask_t llc_shared_map;
96 #endif
97 /* cpuid returned max cores value: */
98 u16 x86_max_cores;
99 u16 apicid;
100 u16 initial_apicid;
101 u16 x86_clflush_size;
102 #ifdef CONFIG_SMP
103 /* number of cores as seen by the OS: */
104 u16 booted_cores;
105 /* Physical processor id: */
106 u16 phys_proc_id;
107 /* Core id: */
108 u16 cpu_core_id;
109 /* Index into per_cpu list: */
110 u16 cpu_index;
111 #endif
112 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
113
114 #define X86_VENDOR_INTEL 0
115 #define X86_VENDOR_CYRIX 1
116 #define X86_VENDOR_AMD 2
117 #define X86_VENDOR_UMC 3
118 #define X86_VENDOR_CENTAUR 5
119 #define X86_VENDOR_TRANSMETA 7
120 #define X86_VENDOR_NSC 8
121 #define X86_VENDOR_NUM 9
122
123 #define X86_VENDOR_UNKNOWN 0xff
124
125 /*
126 * capabilities of CPUs
127 */
128 extern struct cpuinfo_x86 boot_cpu_data;
129 extern struct cpuinfo_x86 new_cpu_data;
130
131 extern struct tss_struct doublefault_tss;
132 extern __u32 cleared_cpu_caps[NCAPINTS];
133
134 #ifdef CONFIG_SMP
135 DECLARE_PER_CPU(struct cpuinfo_x86, cpu_info);
136 #define cpu_data(cpu) per_cpu(cpu_info, cpu)
137 #define current_cpu_data __get_cpu_var(cpu_info)
138 #else
139 #define cpu_data(cpu) boot_cpu_data
140 #define current_cpu_data boot_cpu_data
141 #endif
142
143 static inline int hlt_works(int cpu)
144 {
145 #ifdef CONFIG_X86_32
146 return cpu_data(cpu).hlt_works_ok;
147 #else
148 return 1;
149 #endif
150 }
151
152 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
153
154 extern void cpu_detect(struct cpuinfo_x86 *c);
155
156 extern void early_cpu_init(void);
157 extern void identify_boot_cpu(void);
158 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
159 extern void print_cpu_info(struct cpuinfo_x86 *);
160 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
161 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
162 extern unsigned short num_cache_leaves;
163
164 extern void detect_extended_topology(struct cpuinfo_x86 *c);
165 #if defined(CONFIG_X86_HT) || defined(CONFIG_X86_64)
166 extern void detect_ht(struct cpuinfo_x86 *c);
167 #else
168 static inline void detect_ht(struct cpuinfo_x86 *c) {}
169 #endif
170
171 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
172 unsigned int *ecx, unsigned int *edx)
173 {
174 /* ecx is often an input as well as an output. */
175 asm("cpuid"
176 : "=a" (*eax),
177 "=b" (*ebx),
178 "=c" (*ecx),
179 "=d" (*edx)
180 : "0" (*eax), "2" (*ecx));
181 }
182
183 static inline void load_cr3(pgd_t *pgdir)
184 {
185 write_cr3(__pa(pgdir));
186 }
187
188 #ifdef CONFIG_X86_32
189 /* This is the TSS defined by the hardware. */
190 struct x86_hw_tss {
191 unsigned short back_link, __blh;
192 unsigned long sp0;
193 unsigned short ss0, __ss0h;
194 unsigned long sp1;
195 /* ss1 caches MSR_IA32_SYSENTER_CS: */
196 unsigned short ss1, __ss1h;
197 unsigned long sp2;
198 unsigned short ss2, __ss2h;
199 unsigned long __cr3;
200 unsigned long ip;
201 unsigned long flags;
202 unsigned long ax;
203 unsigned long cx;
204 unsigned long dx;
205 unsigned long bx;
206 unsigned long sp;
207 unsigned long bp;
208 unsigned long si;
209 unsigned long di;
210 unsigned short es, __esh;
211 unsigned short cs, __csh;
212 unsigned short ss, __ssh;
213 unsigned short ds, __dsh;
214 unsigned short fs, __fsh;
215 unsigned short gs, __gsh;
216 unsigned short ldt, __ldth;
217 unsigned short trace;
218 unsigned short io_bitmap_base;
219
220 } __attribute__((packed));
221 #else
222 struct x86_hw_tss {
223 u32 reserved1;
224 u64 sp0;
225 u64 sp1;
226 u64 sp2;
227 u64 reserved2;
228 u64 ist[7];
229 u32 reserved3;
230 u32 reserved4;
231 u16 reserved5;
232 u16 io_bitmap_base;
233
234 } __attribute__((packed)) ____cacheline_aligned;
235 #endif
236
237 /*
238 * IO-bitmap sizes:
239 */
240 #define IO_BITMAP_BITS 65536
241 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
242 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
243 #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap)
244 #define INVALID_IO_BITMAP_OFFSET 0x8000
245 #define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000
246
247 struct tss_struct {
248 /*
249 * The hardware state:
250 */
251 struct x86_hw_tss x86_tss;
252
253 /*
254 * The extra 1 is there because the CPU will access an
255 * additional byte beyond the end of the IO permission
256 * bitmap. The extra byte must be all 1 bits, and must
257 * be within the limit.
258 */
259 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
260 /*
261 * Cache the current maximum and the last task that used the bitmap:
262 */
263 unsigned long io_bitmap_max;
264 struct thread_struct *io_bitmap_owner;
265
266 /*
267 * .. and then another 0x100 bytes for the emergency kernel stack:
268 */
269 unsigned long stack[64];
270
271 } ____cacheline_aligned;
272
273 DECLARE_PER_CPU(struct tss_struct, init_tss);
274
275 /*
276 * Save the original ist values for checking stack pointers during debugging
277 */
278 struct orig_ist {
279 unsigned long ist[7];
280 };
281
282 #define MXCSR_DEFAULT 0x1f80
283
284 struct i387_fsave_struct {
285 u32 cwd; /* FPU Control Word */
286 u32 swd; /* FPU Status Word */
287 u32 twd; /* FPU Tag Word */
288 u32 fip; /* FPU IP Offset */
289 u32 fcs; /* FPU IP Selector */
290 u32 foo; /* FPU Operand Pointer Offset */
291 u32 fos; /* FPU Operand Pointer Selector */
292
293 /* 8*10 bytes for each FP-reg = 80 bytes: */
294 u32 st_space[20];
295
296 /* Software status information [not touched by FSAVE ]: */
297 u32 status;
298 };
299
300 struct i387_fxsave_struct {
301 u16 cwd; /* Control Word */
302 u16 swd; /* Status Word */
303 u16 twd; /* Tag Word */
304 u16 fop; /* Last Instruction Opcode */
305 union {
306 struct {
307 u64 rip; /* Instruction Pointer */
308 u64 rdp; /* Data Pointer */
309 };
310 struct {
311 u32 fip; /* FPU IP Offset */
312 u32 fcs; /* FPU IP Selector */
313 u32 foo; /* FPU Operand Offset */
314 u32 fos; /* FPU Operand Selector */
315 };
316 };
317 u32 mxcsr; /* MXCSR Register State */
318 u32 mxcsr_mask; /* MXCSR Mask */
319
320 /* 8*16 bytes for each FP-reg = 128 bytes: */
321 u32 st_space[32];
322
323 /* 16*16 bytes for each XMM-reg = 256 bytes: */
324 u32 xmm_space[64];
325
326 u32 padding[24];
327
328 } __attribute__((aligned(16)));
329
330 struct i387_soft_struct {
331 u32 cwd;
332 u32 swd;
333 u32 twd;
334 u32 fip;
335 u32 fcs;
336 u32 foo;
337 u32 fos;
338 /* 8*10 bytes for each FP-reg = 80 bytes: */
339 u32 st_space[20];
340 u8 ftop;
341 u8 changed;
342 u8 lookahead;
343 u8 no_update;
344 u8 rm;
345 u8 alimit;
346 struct info *info;
347 u32 entry_eip;
348 };
349
350 union thread_xstate {
351 struct i387_fsave_struct fsave;
352 struct i387_fxsave_struct fxsave;
353 struct i387_soft_struct soft;
354 };
355
356 #ifdef CONFIG_X86_64
357 DECLARE_PER_CPU(struct orig_ist, orig_ist);
358 #endif
359
360 extern void print_cpu_info(struct cpuinfo_x86 *);
361 extern unsigned int xstate_size;
362 extern void free_thread_xstate(struct task_struct *);
363 extern struct kmem_cache *task_xstate_cachep;
364 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
365 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
366 extern unsigned short num_cache_leaves;
367
368 struct thread_struct {
369 /* Cached TLS descriptors: */
370 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
371 unsigned long sp0;
372 unsigned long sp;
373 #ifdef CONFIG_X86_32
374 unsigned long sysenter_cs;
375 #else
376 unsigned long usersp; /* Copy from PDA */
377 unsigned short es;
378 unsigned short ds;
379 unsigned short fsindex;
380 unsigned short gsindex;
381 #endif
382 unsigned long ip;
383 unsigned long fs;
384 unsigned long gs;
385 /* Hardware debugging registers: */
386 unsigned long debugreg0;
387 unsigned long debugreg1;
388 unsigned long debugreg2;
389 unsigned long debugreg3;
390 unsigned long debugreg6;
391 unsigned long debugreg7;
392 /* Fault info: */
393 unsigned long cr2;
394 unsigned long trap_no;
395 unsigned long error_code;
396 /* floating point and extended processor state */
397 union thread_xstate *xstate;
398 #ifdef CONFIG_X86_32
399 /* Virtual 86 mode info */
400 struct vm86_struct __user *vm86_info;
401 unsigned long screen_bitmap;
402 unsigned long v86flags;
403 unsigned long v86mask;
404 unsigned long saved_sp0;
405 unsigned int saved_fs;
406 unsigned int saved_gs;
407 #endif
408 /* IO permissions: */
409 unsigned long *io_bitmap_ptr;
410 unsigned long iopl;
411 /* Max allowed port in the bitmap, in bytes: */
412 unsigned io_bitmap_max;
413 /* MSR_IA32_DEBUGCTLMSR value to switch in if TIF_DEBUGCTLMSR is set. */
414 unsigned long debugctlmsr;
415 /* Debug Store - if not 0 points to a DS Save Area configuration;
416 * goes into MSR_IA32_DS_AREA */
417 unsigned long ds_area_msr;
418 };
419
420 static inline unsigned long native_get_debugreg(int regno)
421 {
422 unsigned long val = 0; /* Damn you, gcc! */
423
424 switch (regno) {
425 case 0:
426 asm("mov %%db0, %0" :"=r" (val));
427 break;
428 case 1:
429 asm("mov %%db1, %0" :"=r" (val));
430 break;
431 case 2:
432 asm("mov %%db2, %0" :"=r" (val));
433 break;
434 case 3:
435 asm("mov %%db3, %0" :"=r" (val));
436 break;
437 case 6:
438 asm("mov %%db6, %0" :"=r" (val));
439 break;
440 case 7:
441 asm("mov %%db7, %0" :"=r" (val));
442 break;
443 default:
444 BUG();
445 }
446 return val;
447 }
448
449 static inline void native_set_debugreg(int regno, unsigned long value)
450 {
451 switch (regno) {
452 case 0:
453 asm("mov %0, %%db0" ::"r" (value));
454 break;
455 case 1:
456 asm("mov %0, %%db1" ::"r" (value));
457 break;
458 case 2:
459 asm("mov %0, %%db2" ::"r" (value));
460 break;
461 case 3:
462 asm("mov %0, %%db3" ::"r" (value));
463 break;
464 case 6:
465 asm("mov %0, %%db6" ::"r" (value));
466 break;
467 case 7:
468 asm("mov %0, %%db7" ::"r" (value));
469 break;
470 default:
471 BUG();
472 }
473 }
474
475 /*
476 * Set IOPL bits in EFLAGS from given mask
477 */
478 static inline void native_set_iopl_mask(unsigned mask)
479 {
480 #ifdef CONFIG_X86_32
481 unsigned int reg;
482
483 asm volatile ("pushfl;"
484 "popl %0;"
485 "andl %1, %0;"
486 "orl %2, %0;"
487 "pushl %0;"
488 "popfl"
489 : "=&r" (reg)
490 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
491 #endif
492 }
493
494 static inline void
495 native_load_sp0(struct tss_struct *tss, struct thread_struct *thread)
496 {
497 tss->x86_tss.sp0 = thread->sp0;
498 #ifdef CONFIG_X86_32
499 /* Only happens when SEP is enabled, no need to test "SEP"arately: */
500 if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
501 tss->x86_tss.ss1 = thread->sysenter_cs;
502 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
503 }
504 #endif
505 }
506
507 static inline void native_swapgs(void)
508 {
509 #ifdef CONFIG_X86_64
510 asm volatile("swapgs" ::: "memory");
511 #endif
512 }
513
514 #ifdef CONFIG_PARAVIRT
515 #include <asm/paravirt.h>
516 #else
517 #define __cpuid native_cpuid
518 #define paravirt_enabled() 0
519
520 /*
521 * These special macros can be used to get or set a debugging register
522 */
523 #define get_debugreg(var, register) \
524 (var) = native_get_debugreg(register)
525 #define set_debugreg(value, register) \
526 native_set_debugreg(register, value)
527
528 static inline void load_sp0(struct tss_struct *tss,
529 struct thread_struct *thread)
530 {
531 native_load_sp0(tss, thread);
532 }
533
534 #define set_iopl_mask native_set_iopl_mask
535 #endif /* CONFIG_PARAVIRT */
536
537 /*
538 * Save the cr4 feature set we're using (ie
539 * Pentium 4MB enable and PPro Global page
540 * enable), so that any CPU's that boot up
541 * after us can get the correct flags.
542 */
543 extern unsigned long mmu_cr4_features;
544
545 static inline void set_in_cr4(unsigned long mask)
546 {
547 unsigned cr4;
548
549 mmu_cr4_features |= mask;
550 cr4 = read_cr4();
551 cr4 |= mask;
552 write_cr4(cr4);
553 }
554
555 static inline void clear_in_cr4(unsigned long mask)
556 {
557 unsigned cr4;
558
559 mmu_cr4_features &= ~mask;
560 cr4 = read_cr4();
561 cr4 &= ~mask;
562 write_cr4(cr4);
563 }
564
565 struct microcode_header {
566 unsigned int hdrver;
567 unsigned int rev;
568 unsigned int date;
569 unsigned int sig;
570 unsigned int cksum;
571 unsigned int ldrver;
572 unsigned int pf;
573 unsigned int datasize;
574 unsigned int totalsize;
575 unsigned int reserved[3];
576 };
577
578 struct microcode {
579 struct microcode_header hdr;
580 unsigned int bits[0];
581 };
582
583 typedef struct microcode microcode_t;
584 typedef struct microcode_header microcode_header_t;
585
586 /* microcode format is extended from prescott processors */
587 struct extended_signature {
588 unsigned int sig;
589 unsigned int pf;
590 unsigned int cksum;
591 };
592
593 struct extended_sigtable {
594 unsigned int count;
595 unsigned int cksum;
596 unsigned int reserved[3];
597 struct extended_signature sigs[0];
598 };
599
600 typedef struct {
601 unsigned long seg;
602 } mm_segment_t;
603
604
605 /*
606 * create a kernel thread without removing it from tasklists
607 */
608 extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
609
610 /* Free all resources held by a thread. */
611 extern void release_thread(struct task_struct *);
612
613 /* Prepare to copy thread state - unlazy all lazy state */
614 extern void prepare_to_copy(struct task_struct *tsk);
615
616 unsigned long get_wchan(struct task_struct *p);
617
618 /*
619 * Generic CPUID function
620 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
621 * resulting in stale register contents being returned.
622 */
623 static inline void cpuid(unsigned int op,
624 unsigned int *eax, unsigned int *ebx,
625 unsigned int *ecx, unsigned int *edx)
626 {
627 *eax = op;
628 *ecx = 0;
629 __cpuid(eax, ebx, ecx, edx);
630 }
631
632 /* Some CPUID calls want 'count' to be placed in ecx */
633 static inline void cpuid_count(unsigned int op, int count,
634 unsigned int *eax, unsigned int *ebx,
635 unsigned int *ecx, unsigned int *edx)
636 {
637 *eax = op;
638 *ecx = count;
639 __cpuid(eax, ebx, ecx, edx);
640 }
641
642 /*
643 * CPUID functions returning a single datum
644 */
645 static inline unsigned int cpuid_eax(unsigned int op)
646 {
647 unsigned int eax, ebx, ecx, edx;
648
649 cpuid(op, &eax, &ebx, &ecx, &edx);
650
651 return eax;
652 }
653
654 static inline unsigned int cpuid_ebx(unsigned int op)
655 {
656 unsigned int eax, ebx, ecx, edx;
657
658 cpuid(op, &eax, &ebx, &ecx, &edx);
659
660 return ebx;
661 }
662
663 static inline unsigned int cpuid_ecx(unsigned int op)
664 {
665 unsigned int eax, ebx, ecx, edx;
666
667 cpuid(op, &eax, &ebx, &ecx, &edx);
668
669 return ecx;
670 }
671
672 static inline unsigned int cpuid_edx(unsigned int op)
673 {
674 unsigned int eax, ebx, ecx, edx;
675
676 cpuid(op, &eax, &ebx, &ecx, &edx);
677
678 return edx;
679 }
680
681 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
682 static inline void rep_nop(void)
683 {
684 asm volatile("rep; nop" ::: "memory");
685 }
686
687 static inline void cpu_relax(void)
688 {
689 rep_nop();
690 }
691
692 /* Stop speculative execution: */
693 static inline void sync_core(void)
694 {
695 int tmp;
696
697 asm volatile("cpuid" : "=a" (tmp) : "0" (1)
698 : "ebx", "ecx", "edx", "memory");
699 }
700
701 static inline void __monitor(const void *eax, unsigned long ecx,
702 unsigned long edx)
703 {
704 /* "monitor %eax, %ecx, %edx;" */
705 asm volatile(".byte 0x0f, 0x01, 0xc8;"
706 :: "a" (eax), "c" (ecx), "d"(edx));
707 }
708
709 static inline void __mwait(unsigned long eax, unsigned long ecx)
710 {
711 /* "mwait %eax, %ecx;" */
712 asm volatile(".byte 0x0f, 0x01, 0xc9;"
713 :: "a" (eax), "c" (ecx));
714 }
715
716 static inline void __sti_mwait(unsigned long eax, unsigned long ecx)
717 {
718 trace_hardirqs_on();
719 /* "mwait %eax, %ecx;" */
720 asm volatile("sti; .byte 0x0f, 0x01, 0xc9;"
721 :: "a" (eax), "c" (ecx));
722 }
723
724 extern void mwait_idle_with_hints(unsigned long eax, unsigned long ecx);
725
726 extern void select_idle_routine(const struct cpuinfo_x86 *c);
727
728 extern unsigned long boot_option_idle_override;
729 extern unsigned long idle_halt;
730 extern unsigned long idle_nomwait;
731
732 /*
733 * on systems with caches, caches must be flashed as the absolute
734 * last instruction before going into a suspended halt. Otherwise,
735 * dirty data can linger in the cache and become stale on resume,
736 * leading to strange errors.
737 *
738 * perform a variety of operations to guarantee that the compiler
739 * will not reorder instructions. wbinvd itself is serializing
740 * so the processor will not reorder.
741 *
742 * Systems without cache can just go into halt.
743 */
744 static inline void wbinvd_halt(void)
745 {
746 mb();
747 /* check for clflush to determine if wbinvd is legal */
748 if (cpu_has_clflush)
749 asm volatile("cli; wbinvd; 1: hlt; jmp 1b" : : : "memory");
750 else
751 while (1)
752 halt();
753 }
754
755 extern void enable_sep_cpu(void);
756 extern int sysenter_setup(void);
757
758 /* Defined in head.S */
759 extern struct desc_ptr early_gdt_descr;
760
761 extern void cpu_set_gdt(int);
762 extern void switch_to_new_gdt(void);
763 extern void cpu_init(void);
764 extern void init_gdt(int cpu);
765
766 static inline void update_debugctlmsr(unsigned long debugctlmsr)
767 {
768 #ifndef CONFIG_X86_DEBUGCTLMSR
769 if (boot_cpu_data.x86 < 6)
770 return;
771 #endif
772 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
773 }
774
775 /*
776 * from system description table in BIOS. Mostly for MCA use, but
777 * others may find it useful:
778 */
779 extern unsigned int machine_id;
780 extern unsigned int machine_submodel_id;
781 extern unsigned int BIOS_revision;
782
783 /* Boot loader type from the setup header: */
784 extern int bootloader_type;
785
786 extern char ignore_fpu_irq;
787
788 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
789 #define ARCH_HAS_PREFETCHW
790 #define ARCH_HAS_SPINLOCK_PREFETCH
791
792 #ifdef CONFIG_X86_32
793 # define BASE_PREFETCH ASM_NOP4
794 # define ARCH_HAS_PREFETCH
795 #else
796 # define BASE_PREFETCH "prefetcht0 (%1)"
797 #endif
798
799 /*
800 * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
801 *
802 * It's not worth to care about 3dnow prefetches for the K6
803 * because they are microcoded there and very slow.
804 */
805 static inline void prefetch(const void *x)
806 {
807 alternative_input(BASE_PREFETCH,
808 "prefetchnta (%1)",
809 X86_FEATURE_XMM,
810 "r" (x));
811 }
812
813 /*
814 * 3dnow prefetch to get an exclusive cache line.
815 * Useful for spinlocks to avoid one state transition in the
816 * cache coherency protocol:
817 */
818 static inline void prefetchw(const void *x)
819 {
820 alternative_input(BASE_PREFETCH,
821 "prefetchw (%1)",
822 X86_FEATURE_3DNOW,
823 "r" (x));
824 }
825
826 static inline void spin_lock_prefetch(const void *x)
827 {
828 prefetchw(x);
829 }
830
831 #ifdef CONFIG_X86_32
832 /*
833 * User space process size: 3GB (default).
834 */
835 #define TASK_SIZE PAGE_OFFSET
836 #define STACK_TOP TASK_SIZE
837 #define STACK_TOP_MAX STACK_TOP
838
839 #define INIT_THREAD { \
840 .sp0 = sizeof(init_stack) + (long)&init_stack, \
841 .vm86_info = NULL, \
842 .sysenter_cs = __KERNEL_CS, \
843 .io_bitmap_ptr = NULL, \
844 .fs = __KERNEL_PERCPU, \
845 }
846
847 /*
848 * Note that the .io_bitmap member must be extra-big. This is because
849 * the CPU will access an additional byte beyond the end of the IO
850 * permission bitmap. The extra byte must be all 1 bits, and must
851 * be within the limit.
852 */
853 #define INIT_TSS { \
854 .x86_tss = { \
855 .sp0 = sizeof(init_stack) + (long)&init_stack, \
856 .ss0 = __KERNEL_DS, \
857 .ss1 = __KERNEL_CS, \
858 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
859 }, \
860 .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 }, \
861 }
862
863 extern unsigned long thread_saved_pc(struct task_struct *tsk);
864
865 #define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
866 #define KSTK_TOP(info) \
867 ({ \
868 unsigned long *__ptr = (unsigned long *)(info); \
869 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
870 })
871
872 /*
873 * The below -8 is to reserve 8 bytes on top of the ring0 stack.
874 * This is necessary to guarantee that the entire "struct pt_regs"
875 * is accessable even if the CPU haven't stored the SS/ESP registers
876 * on the stack (interrupt gate does not save these registers
877 * when switching to the same priv ring).
878 * Therefore beware: accessing the ss/esp fields of the
879 * "struct pt_regs" is possible, but they may contain the
880 * completely wrong values.
881 */
882 #define task_pt_regs(task) \
883 ({ \
884 struct pt_regs *__regs__; \
885 __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
886 __regs__ - 1; \
887 })
888
889 #define KSTK_ESP(task) (task_pt_regs(task)->sp)
890
891 #else
892 /*
893 * User space process size. 47bits minus one guard page.
894 */
895 #define TASK_SIZE64 ((1UL << 47) - PAGE_SIZE)
896
897 /* This decides where the kernel will search for a free chunk of vm
898 * space during mmap's.
899 */
900 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \
901 0xc0000000 : 0xFFFFe000)
902
903 #define TASK_SIZE (test_thread_flag(TIF_IA32) ? \
904 IA32_PAGE_OFFSET : TASK_SIZE64)
905 #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_IA32)) ? \
906 IA32_PAGE_OFFSET : TASK_SIZE64)
907
908 #define STACK_TOP TASK_SIZE
909 #define STACK_TOP_MAX TASK_SIZE64
910
911 #define INIT_THREAD { \
912 .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
913 }
914
915 #define INIT_TSS { \
916 .x86_tss.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
917 }
918
919 /*
920 * Return saved PC of a blocked thread.
921 * What is this good for? it will be always the scheduler or ret_from_fork.
922 */
923 #define thread_saved_pc(t) (*(unsigned long *)((t)->thread.sp - 8))
924
925 #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1)
926 #define KSTK_ESP(tsk) -1 /* sorry. doesn't work for syscall. */
927 #endif /* CONFIG_X86_64 */
928
929 extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
930 unsigned long new_sp);
931
932 /*
933 * This decides where the kernel will search for a free chunk of vm
934 * space during mmap's.
935 */
936 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
937
938 #define KSTK_EIP(task) (task_pt_regs(task)->ip)
939
940 /* Get/set a process' ability to use the timestamp counter instruction */
941 #define GET_TSC_CTL(adr) get_tsc_mode((adr))
942 #define SET_TSC_CTL(val) set_tsc_mode((val))
943
944 extern int get_tsc_mode(unsigned long adr);
945 extern int set_tsc_mode(unsigned int val);
946
947 #endif
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