arch/powerpc/platforms/iseries/lpardata.c

   1 /*
   2  * Copyright 2001 Mike Corrigan, IBM Corp
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * as published by the Free Software Foundation; either version
   7  * 2 of the License, or (at your option) any later version.
   8  */
   9 #include <linux/types.h>
  10 #include <linux/threads.h>
  11 #include <linux/module.h>
  12 #include <linux/bitops.h>
  13 #include <asm/processor.h>
  14 #include <asm/ptrace.h>
  15 #include <asm/abs_addr.h>
  16 #include <asm/lppaca.h>
  17 #include <asm/iseries/it_lp_reg_save.h>
  18 #include <asm/paca.h>
  19 #include <asm/iseries/lpar_map.h>
  20 #include <asm/iseries/it_lp_queue.h>
  21 #include <asm/iseries/alpaca.h>
  22
  23 #include "naca.h"
  24 #include "vpd_areas.h"
  25 #include "spcomm_area.h"
  26 #include "ipl_parms.h"
  27 #include "processor_vpd.h"
  28 #include "release_data.h"
  29 #include "it_exp_vpd_panel.h"
  30 #include "it_lp_naca.h"
  31
  32 /* The HvReleaseData is the root of the information shared between
  33  * the hypervisor and Linux.
  34  */
  35 struct HvReleaseData hvReleaseData = {
  36         .xDesc = 0xc8a5d9c4,    /* "HvRD" ebcdic */
  37         .xSize = sizeof(struct HvReleaseData),
  38         .xVpdAreasPtrOffset = offsetof(struct naca_struct, xItVpdAreas),
  39         .xSlicNacaAddr = &naca,         /* 64-bit Naca address */
  40         .xMsNucDataOffset = LPARMAP_PHYS,
  41         .xFlags = HVREL_TAGSINACTIVE    /* tags inactive       */
  42                                         /* 64 bit              */
  43                                         /* shared processors   */
  44                                         /* HMT allowed         */
  45                   | 6,                  /* TEMP: This allows non-GA driver */
  46         .xVrmIndex = 4,                 /* We are v5r2m0               */
  47         .xMinSupportedPlicVrmIndex = 3,         /* v5r1m0 */
  48         .xMinCompatablePlicVrmIndex = 3,        /* v5r1m0 */
  49         .xVrmName = { 0xd3, 0x89, 0x95, 0xa4,   /* "Linux 2.4.64" ebcdic */
  50                 0xa7, 0x40, 0xf2, 0x4b,
  51                 0xf4, 0x4b, 0xf6, 0xf4 },
  52 };
  53
  54 /*
  55  * The NACA.  The first dword of the naca is required by the iSeries
  56  * hypervisor to point to itVpdAreas.  The hypervisor finds the NACA
  57  * through the pointer in hvReleaseData.
  58  */
  59 struct naca_struct naca = {
  60         .xItVpdAreas = &itVpdAreas,
  61         .xRamDisk = 0,
  62         .xRamDiskSize = 0,
  63 };
  64
  65 extern void system_reset_iSeries(void);
  66 extern void machine_check_iSeries(void);
  67 extern void data_access_iSeries(void);
  68 extern void instruction_access_iSeries(void);
  69 extern void hardware_interrupt_iSeries(void);
  70 extern void alignment_iSeries(void);
  71 extern void program_check_iSeries(void);
  72 extern void fp_unavailable_iSeries(void);
  73 extern void decrementer_iSeries(void);
  74 extern void trap_0a_iSeries(void);
  75 extern void trap_0b_iSeries(void);
  76 extern void system_call_iSeries(void);
  77 extern void single_step_iSeries(void);
  78 extern void trap_0e_iSeries(void);
  79 extern void performance_monitor_iSeries(void);
  80 extern void data_access_slb_iSeries(void);
  81 extern void instruction_access_slb_iSeries(void);
  82
  83 struct ItLpNaca itLpNaca = {
  84         .xDesc = 0xd397d581,            /* "LpNa" ebcdic */
  85         .xSize = 0x0400,                /* size of ItLpNaca */
  86         .xIntHdlrOffset = 0x0300,       /* offset to int array */
  87         .xMaxIntHdlrEntries = 19,       /* # ents */
  88         .xPrimaryLpIndex = 0,           /* Part # of primary */
  89         .xServiceLpIndex = 0,           /* Part # of serv */
  90         .xLpIndex = 0,                  /* Part # of me */
  91         .xMaxLpQueues = 0,              /* # of LP queues */
  92         .xLpQueueOffset = 0x100,        /* offset of start of LP queues */
  93         .xPirEnvironMode = 0,           /* Piranha stuff */
  94         .xPirConsoleMode = 0,
  95         .xPirDasdMode = 0,
  96         .flags = 0,
  97         .xSpVpdFormat = 0,
  98         .xIntProcRatio = 0,
  99         .xPlicVrmIndex = 0,             /* VRM index of PLIC */
 100         .xMinSupportedSlicVrmInd = 0,   /* min supported SLIC */
 101         .xMinCompatableSlicVrmInd = 0,  /* min compat SLIC */
 102         .xLoadAreaAddr = 0,             /* 64-bit addr of load area */
 103         .xLoadAreaChunks = 0,           /* chunks for load area */
 104         .xPaseSysCallCRMask = 0,        /* PASE mask */
 105         .xSlicSegmentTablePtr = 0,      /* seg table */
 106         .xOldLpQueue = { 0 },           /* Old LP Queue */
 107         .xInterruptHdlr = {
 108                 (u64)system_reset_iSeries,      /* 0x100 System Reset */
 109                 (u64)machine_check_iSeries,     /* 0x200 Machine Check */
 110                 (u64)data_access_iSeries,       /* 0x300 Data Access */
 111                 (u64)instruction_access_iSeries, /* 0x400 Instruction Access */
 112                 (u64)hardware_interrupt_iSeries, /* 0x500 External */
 113                 (u64)alignment_iSeries,         /* 0x600 Alignment */
 114                 (u64)program_check_iSeries,     /* 0x700 Program Check */
 115                 (u64)fp_unavailable_iSeries,    /* 0x800 FP Unavailable */
 116                 (u64)decrementer_iSeries,       /* 0x900 Decrementer */
 117                 (u64)trap_0a_iSeries,           /* 0xa00 Trap 0A */
 118                 (u64)trap_0b_iSeries,           /* 0xb00 Trap 0B */
 119                 (u64)system_call_iSeries,       /* 0xc00 System Call */
 120                 (u64)single_step_iSeries,       /* 0xd00 Single Step */
 121                 (u64)trap_0e_iSeries,           /* 0xe00 Trap 0E */
 122                 (u64)performance_monitor_iSeries,/* 0xf00 Performance Monitor */
 123                 0,                              /* int 0x1000 */
 124                 0,                              /* int 0x1010 */
 125                 0,                              /* int 0x1020 CPU ctls */
 126                 (u64)hardware_interrupt_iSeries, /* SC Ret Hdlr */
 127                 (u64)data_access_slb_iSeries,   /* 0x380 D-SLB */
 128                 (u64)instruction_access_slb_iSeries /* 0x480 I-SLB */
 129         }
 130 };
 131
 132 /* May be filled in by the hypervisor so cannot end up in the BSS */
 133 struct ItIplParmsReal xItIplParmsReal __attribute__((__section__(".data")));
 134
 135 /* May be filled in by the hypervisor so cannot end up in the BSS */
 136 struct ItExtVpdPanel xItExtVpdPanel __attribute__((__section__(".data")));
 137
 138 #define maxPhysicalProcessors 32
 139
 140 struct IoHriProcessorVpd xIoHriProcessorVpd[maxPhysicalProcessors] = {
 141         {
 142                 .xInstCacheOperandSize = 32,
 143                 .xDataCacheOperandSize = 32,
 144                 .xProcFreq     = 50000000,
 145                 .xTimeBaseFreq = 50000000,
 146                 .xPVR = 0x3600
 147         }
 148 };
 149
 150 /* Space for Main Store Vpd 27,200 bytes */
 151 /* May be filled in by the hypervisor so cannot end up in the BSS */
 152 u64    xMsVpd[3400] __attribute__((__section__(".data")));
 153
 154 /* Space for Recovery Log Buffer */
 155 /* May be filled in by the hypervisor so cannot end up in the BSS */
 156 u64    xRecoveryLogBuffer[32] __attribute__((__section__(".data")));
 157
 158 struct SpCommArea xSpCommArea = {
 159         .xDesc = 0xE2D7C3C2,
 160         .xFormat = 1,
 161 };
 162
 163 #define ALPACA_INIT(number)                                             \
 164 {                                                                       \
 165         .lppaca_ptr = &lppaca[number],                                  \
 166         .reg_save_ptr = &iseries_reg_save[number],                      \
 167 }
 168
 169 struct alpaca alpaca[] = {
 170         ALPACA_INIT( 0),
 171 #if NR_CPUS > 1
 172         ALPACA_INIT( 1), ALPACA_INIT( 2), ALPACA_INIT( 3),
 173 #if NR_CPUS > 4
 174         ALPACA_INIT( 4), ALPACA_INIT( 5), ALPACA_INIT( 6), ALPACA_INIT( 7),
 175 #if NR_CPUS > 8
 176         ALPACA_INIT( 8), ALPACA_INIT( 9), ALPACA_INIT(10), ALPACA_INIT(11),
 177         ALPACA_INIT(12), ALPACA_INIT(13), ALPACA_INIT(14), ALPACA_INIT(15),
 178         ALPACA_INIT(16), ALPACA_INIT(17), ALPACA_INIT(18), ALPACA_INIT(19),
 179         ALPACA_INIT(20), ALPACA_INIT(21), ALPACA_INIT(22), ALPACA_INIT(23),
 180         ALPACA_INIT(24), ALPACA_INIT(25), ALPACA_INIT(26), ALPACA_INIT(27),
 181         ALPACA_INIT(28), ALPACA_INIT(29), ALPACA_INIT(30), ALPACA_INIT(31),
 182 #if NR_CPUS > 32
 183         ALPACA_INIT(32), ALPACA_INIT(33), ALPACA_INIT(34), ALPACA_INIT(35),
 184         ALPACA_INIT(36), ALPACA_INIT(37), ALPACA_INIT(38), ALPACA_INIT(39),
 185         ALPACA_INIT(40), ALPACA_INIT(41), ALPACA_INIT(42), ALPACA_INIT(43),
 186         ALPACA_INIT(44), ALPACA_INIT(45), ALPACA_INIT(46), ALPACA_INIT(47),
 187         ALPACA_INIT(48), ALPACA_INIT(49), ALPACA_INIT(50), ALPACA_INIT(51),
 188         ALPACA_INIT(52), ALPACA_INIT(53), ALPACA_INIT(54), ALPACA_INIT(55),
 189         ALPACA_INIT(56), ALPACA_INIT(57), ALPACA_INIT(58), ALPACA_INIT(59),
 190         ALPACA_INIT(60), ALPACA_INIT(61), ALPACA_INIT(62), ALPACA_INIT(63),
 191 #endif
 192 #endif
 193 #endif
 194 #endif
 195 };
 196
 197 /* The LparMap data is now located at offset 0x6000 in head.S
 198  * It was put there so that the HvReleaseData could address it
 199  * with a 32-bit offset as required by the iSeries hypervisor
 200  *
 201  * The Naca has a pointer to the ItVpdAreas.  The hypervisor finds
 202  * the Naca via the HvReleaseData area.  The HvReleaseData has the
 203  * offset into the Naca of the pointer to the ItVpdAreas.
 204  */
 205 struct ItVpdAreas itVpdAreas = {
 206         .xSlicDesc = 0xc9a3e5c1,                /* "ItVA" */
 207         .xSlicSize = sizeof(struct ItVpdAreas),
 208         .xSlicVpdEntries = ItVpdMaxEntries,     /* # VPD array entries */
 209         .xSlicDmaEntries = ItDmaMaxEntries,     /* # DMA array entries */
 210         .xSlicMaxLogicalProcs = NR_CPUS * 2,    /* Max logical procs */
 211         .xSlicMaxPhysicalProcs = maxPhysicalProcessors, /* Max physical procs */
 212         .xSlicDmaToksOffset = offsetof(struct ItVpdAreas, xPlicDmaToks),
 213         .xSlicVpdAdrsOffset = offsetof(struct ItVpdAreas, xSlicVpdAdrs),
 214         .xSlicDmaLensOffset = offsetof(struct ItVpdAreas, xPlicDmaLens),
 215         .xSlicVpdLensOffset = offsetof(struct ItVpdAreas, xSlicVpdLens),
 216         .xSlicMaxSlotLabels = 0,                /* max slot labels */
 217         .xSlicMaxLpQueues = 1,                  /* max LP queues */
 218         .xPlicDmaLens = { 0 },                  /* DMA lengths */
 219         .xPlicDmaToks = { 0 },                  /* DMA tokens */
 220         .xSlicVpdLens = {                       /* VPD lengths */
 221                 0,0,0,                  /*  0 - 2 */
 222                 sizeof(xItExtVpdPanel), /*       3 Extended VPD   */
 223                 sizeof(struct alpaca),  /*       4 length of (fake) Paca  */
 224                 0,                      /*       5 */
 225                 sizeof(struct ItIplParmsReal),/* 6 length of IPL parms */
 226                 26992,                  /*       7 length of MS VPD */
 227                 0,                      /*       8 */
 228                 sizeof(struct ItLpNaca),/*       9 length of LP Naca */
 229                 0,                      /*      10 */
 230                 256,                    /*      11 length of Recovery Log Buf */
 231                 sizeof(struct SpCommArea), /*   12 length of SP Comm Area */
 232                 0,0,0,                  /* 13 - 15 */
 233                 sizeof(struct IoHriProcessorVpd),/* 16 length of Proc Vpd */
 234                 0,0,0,0,0,0,            /* 17 - 22  */
 235                 sizeof(struct hvlpevent_queue), /* 23 length of Lp Queue */
 236                 0,0                     /* 24 - 25 */
 237                 },
 238         .xSlicVpdAdrs = {                       /* VPD addresses */
 239                 0,0,0,                  /*       0 -  2 */
 240                 &xItExtVpdPanel,        /*       3 Extended VPD */
 241                 &alpaca[0],             /*       4 first (fake) Paca */
 242                 0,                      /*       5 */
 243                 &xItIplParmsReal,       /*       6 IPL parms */
 244                 &xMsVpd,                /*       7 MS Vpd */
 245                 0,                      /*       8 */
 246                 &itLpNaca,              /*       9 LpNaca */
 247                 0,                      /*      10 */
 248                 &xRecoveryLogBuffer,    /*      11 Recovery Log Buffer */
 249                 &xSpCommArea,           /*      12 SP Comm Area */
 250                 0,0,0,                  /* 13 - 15 */
 251                 &xIoHriProcessorVpd,    /*      16 Proc Vpd */
 252                 0,0,0,0,0,0,            /* 17 - 22 */
 253                 &hvlpevent_queue,       /*      23 Lp Queue */
 254                 0,0
 255         }
 256 };
 257
 258 struct ItLpRegSave iseries_reg_save[] = {
 259         [0 ... (NR_CPUS-1)] = {
 260                 .xDesc = 0xd397d9e2,    /* "LpRS" */
 261                 .xSize = sizeof(struct ItLpRegSave),
 262         },
 263 };