drivers/edac/edac_core.h

   1 /*
   2  * Defines, structures, APIs for edac_core module
   3  *
   4  * (C) 2007 Linux Networx (http://lnxi.com)
   5  * This file may be distributed under the terms of the
   6  * GNU General Public License.
   7  *
   8  * Written by Thayne Harbaugh
   9  * Based on work by Dan Hollis <goemon at anime dot net> and others.
  10  *      http://www.anime.net/~goemon/linux-ecc/
  11  *
  12  * NMI handling support added by
  13  *     Dave Peterson <dsp@llnl.gov> <dave_peterson@pobox.com>
  14  *
  15  * Refactored for multi-source files:
  16  *      Doug Thompson <norsk5@xmission.com>
  17  *
  18  */
  19
  20 #ifndef _EDAC_CORE_H_
  21 #define _EDAC_CORE_H_
  22
  23 #include <linux/kernel.h>
  24 #include <linux/types.h>
  25 #include <linux/module.h>
  26 #include <linux/spinlock.h>
  27 #include <linux/smp.h>
  28 #include <linux/pci.h>
  29 #include <linux/time.h>
  30 #include <linux/nmi.h>
  31 #include <linux/rcupdate.h>
  32 #include <linux/completion.h>
  33 #include <linux/kobject.h>
  34 #include <linux/platform_device.h>
  35 #include <linux/sysdev.h>
  36 #include <linux/workqueue.h>
  37
  38 #define EDAC_MC_LABEL_LEN       31
  39 #define EDAC_DEVICE_NAME_LEN    31
  40 #define EDAC_ATTRIB_VALUE_LEN   15
  41 #define MC_PROC_NAME_MAX_LEN    7
  42
  43 #if PAGE_SHIFT < 20
  44 #define PAGES_TO_MiB( pages )   ( ( pages ) >> ( 20 - PAGE_SHIFT ) )
  45 #else                           /* PAGE_SHIFT > 20 */
  46 #define PAGES_TO_MiB( pages )   ( ( pages ) << ( PAGE_SHIFT - 20 ) )
  47 #endif
  48
  49 #define edac_printk(level, prefix, fmt, arg...) \
  50         printk(level "EDAC " prefix ": " fmt, ##arg)
  51
  52 #define edac_printk_verbose(level, prefix, fmt, arg...) \
  53         printk(level "EDAC " prefix ": " "in %s, line at %d: " fmt,     \
  54                __FILE__, __LINE__, ##arg)
  55
  56 #define edac_mc_printk(mci, level, fmt, arg...) \
  57         printk(level "EDAC MC%d: " fmt, mci->mc_idx, ##arg)
  58
  59 #define edac_mc_chipset_printk(mci, level, prefix, fmt, arg...) \
  60         printk(level "EDAC " prefix " MC%d: " fmt, mci->mc_idx, ##arg)
  61
  62 /* edac_device printk */
  63 #define edac_device_printk(ctl, level, fmt, arg...) \
  64         printk(level "EDAC DEVICE%d: " fmt, ctl->dev_idx, ##arg)
  65
  66 /* edac_pci printk */
  67 #define edac_pci_printk(ctl, level, fmt, arg...) \
  68         printk(level "EDAC PCI%d: " fmt, ctl->pci_idx, ##arg)
  69
  70 /* prefixes for edac_printk() and edac_mc_printk() */
  71 #define EDAC_MC "MC"
  72 #define EDAC_PCI "PCI"
  73 #define EDAC_DEBUG "DEBUG"
  74
  75 #ifdef CONFIG_EDAC_DEBUG
  76 extern int edac_debug_level;
  77
  78 #ifndef CONFIG_EDAC_DEBUG_VERBOSE
  79 #define edac_debug_printk(level, fmt, arg...)                            \
  80         do {                                                             \
  81                 if (level <= edac_debug_level)                           \
  82                         edac_printk(KERN_DEBUG, EDAC_DEBUG, fmt, ##arg); \
  83         } while (0)
  84 #else  /* CONFIG_EDAC_DEBUG_VERBOSE */
  85 #define edac_debug_printk(level, fmt, arg...)                            \
  86         do {                                                             \
  87                 if (level <= edac_debug_level)                           \
  88                         edac_printk_verbose(KERN_DEBUG, EDAC_DEBUG, fmt, \
  89                                             ##arg);                     \
  90         } while (0)
  91 #endif
  92
  93 #define debugf0( ... ) edac_debug_printk(0, __VA_ARGS__ )
  94 #define debugf1( ... ) edac_debug_printk(1, __VA_ARGS__ )
  95 #define debugf2( ... ) edac_debug_printk(2, __VA_ARGS__ )
  96 #define debugf3( ... ) edac_debug_printk(3, __VA_ARGS__ )
  97 #define debugf4( ... ) edac_debug_printk(4, __VA_ARGS__ )
  98
  99 #else                           /* !CONFIG_EDAC_DEBUG */
 100
 101 #define debugf0( ... )
 102 #define debugf1( ... )
 103 #define debugf2( ... )
 104 #define debugf3( ... )
 105 #define debugf4( ... )
 106
 107 #endif                          /* !CONFIG_EDAC_DEBUG */
 108
 109 #define PCI_VEND_DEV(vend, dev) PCI_VENDOR_ID_ ## vend, \
 110         PCI_DEVICE_ID_ ## vend ## _ ## dev
 111
 112 #define edac_dev_name(dev) (dev)->dev_name
 113
 114 /* memory devices */
 115 enum dev_type {
 116         DEV_UNKNOWN = 0,
 117         DEV_X1,
 118         DEV_X2,
 119         DEV_X4,
 120         DEV_X8,
 121         DEV_X16,
 122         DEV_X32,                /* Do these parts exist? */
 123         DEV_X64                 /* Do these parts exist? */
 124 };
 125
 126 #define DEV_FLAG_UNKNOWN        BIT(DEV_UNKNOWN)
 127 #define DEV_FLAG_X1             BIT(DEV_X1)
 128 #define DEV_FLAG_X2             BIT(DEV_X2)
 129 #define DEV_FLAG_X4             BIT(DEV_X4)
 130 #define DEV_FLAG_X8             BIT(DEV_X8)
 131 #define DEV_FLAG_X16            BIT(DEV_X16)
 132 #define DEV_FLAG_X32            BIT(DEV_X32)
 133 #define DEV_FLAG_X64            BIT(DEV_X64)
 134
 135 /* memory types */
 136 enum mem_type {
 137         MEM_EMPTY = 0,          /* Empty csrow */
 138         MEM_RESERVED,           /* Reserved csrow type */
 139         MEM_UNKNOWN,            /* Unknown csrow type */
 140         MEM_FPM,                /* Fast page mode */
 141         MEM_EDO,                /* Extended data out */
 142         MEM_BEDO,               /* Burst Extended data out */
 143         MEM_SDR,                /* Single data rate SDRAM */
 144         MEM_RDR,                /* Registered single data rate SDRAM */
 145         MEM_DDR,                /* Double data rate SDRAM */
 146         MEM_RDDR,               /* Registered Double data rate SDRAM */
 147         MEM_RMBS,               /* Rambus DRAM */
 148         MEM_DDR2,               /* DDR2 RAM */
 149         MEM_FB_DDR2,            /* fully buffered DDR2 */
 150         MEM_RDDR2,              /* Registered DDR2 RAM */
 151         MEM_XDR,                /* Rambus XDR */
 152 };
 153
 154 #define MEM_FLAG_EMPTY          BIT(MEM_EMPTY)
 155 #define MEM_FLAG_RESERVED       BIT(MEM_RESERVED)
 156 #define MEM_FLAG_UNKNOWN        BIT(MEM_UNKNOWN)
 157 #define MEM_FLAG_FPM            BIT(MEM_FPM)
 158 #define MEM_FLAG_EDO            BIT(MEM_EDO)
 159 #define MEM_FLAG_BEDO           BIT(MEM_BEDO)
 160 #define MEM_FLAG_SDR            BIT(MEM_SDR)
 161 #define MEM_FLAG_RDR            BIT(MEM_RDR)
 162 #define MEM_FLAG_DDR            BIT(MEM_DDR)
 163 #define MEM_FLAG_RDDR           BIT(MEM_RDDR)
 164 #define MEM_FLAG_RMBS           BIT(MEM_RMBS)
 165 #define MEM_FLAG_DDR2           BIT(MEM_DDR2)
 166 #define MEM_FLAG_FB_DDR2        BIT(MEM_FB_DDR2)
 167 #define MEM_FLAG_RDDR2          BIT(MEM_RDDR2)
 168 #define MEM_FLAG_XDR            BIT(MEM_XDR)
 169
 170 /* chipset Error Detection and Correction capabilities and mode */
 171 enum edac_type {
 172         EDAC_UNKNOWN = 0,       /* Unknown if ECC is available */
 173         EDAC_NONE,              /* Doesnt support ECC */
 174         EDAC_RESERVED,          /* Reserved ECC type */
 175         EDAC_PARITY,            /* Detects parity errors */
 176         EDAC_EC,                /* Error Checking - no correction */
 177         EDAC_SECDED,            /* Single bit error correction, Double detection */
 178         EDAC_S2ECD2ED,          /* Chipkill x2 devices - do these exist? */
 179         EDAC_S4ECD4ED,          /* Chipkill x4 devices */
 180         EDAC_S8ECD8ED,          /* Chipkill x8 devices */
 181         EDAC_S16ECD16ED,        /* Chipkill x16 devices */
 182 };
 183
 184 #define EDAC_FLAG_UNKNOWN       BIT(EDAC_UNKNOWN)
 185 #define EDAC_FLAG_NONE          BIT(EDAC_NONE)
 186 #define EDAC_FLAG_PARITY        BIT(EDAC_PARITY)
 187 #define EDAC_FLAG_EC            BIT(EDAC_EC)
 188 #define EDAC_FLAG_SECDED        BIT(EDAC_SECDED)
 189 #define EDAC_FLAG_S2ECD2ED      BIT(EDAC_S2ECD2ED)
 190 #define EDAC_FLAG_S4ECD4ED      BIT(EDAC_S4ECD4ED)
 191 #define EDAC_FLAG_S8ECD8ED      BIT(EDAC_S8ECD8ED)
 192 #define EDAC_FLAG_S16ECD16ED    BIT(EDAC_S16ECD16ED)
 193
 194 /* scrubbing capabilities */
 195 enum scrub_type {
 196         SCRUB_UNKNOWN = 0,      /* Unknown if scrubber is available */
 197         SCRUB_NONE,             /* No scrubber */
 198         SCRUB_SW_PROG,          /* SW progressive (sequential) scrubbing */
 199         SCRUB_SW_SRC,           /* Software scrub only errors */
 200         SCRUB_SW_PROG_SRC,      /* Progressive software scrub from an error */
 201         SCRUB_SW_TUNABLE,       /* Software scrub frequency is tunable */
 202         SCRUB_HW_PROG,          /* HW progressive (sequential) scrubbing */
 203         SCRUB_HW_SRC,           /* Hardware scrub only errors */
 204         SCRUB_HW_PROG_SRC,      /* Progressive hardware scrub from an error */
 205         SCRUB_HW_TUNABLE        /* Hardware scrub frequency is tunable */
 206 };
 207
 208 #define SCRUB_FLAG_SW_PROG      BIT(SCRUB_SW_PROG)
 209 #define SCRUB_FLAG_SW_SRC       BIT(SCRUB_SW_SRC)
 210 #define SCRUB_FLAG_SW_PROG_SRC  BIT(SCRUB_SW_PROG_SRC)
 211 #define SCRUB_FLAG_SW_TUN       BIT(SCRUB_SW_SCRUB_TUNABLE)
 212 #define SCRUB_FLAG_HW_PROG      BIT(SCRUB_HW_PROG)
 213 #define SCRUB_FLAG_HW_SRC       BIT(SCRUB_HW_SRC)
 214 #define SCRUB_FLAG_HW_PROG_SRC  BIT(SCRUB_HW_PROG_SRC)
 215 #define SCRUB_FLAG_HW_TUN       BIT(SCRUB_HW_TUNABLE)
 216
 217 /* FIXME - should have notify capabilities: NMI, LOG, PROC, etc */
 218
 219 /* EDAC internal operation states */
 220 #define OP_ALLOC                0x100
 221 #define OP_RUNNING_POLL         0x201
 222 #define OP_RUNNING_INTERRUPT    0x202
 223 #define OP_RUNNING_POLL_INTR    0x203
 224 #define OP_OFFLINE              0x300
 225
 226 /*
 227  * There are several things to be aware of that aren't at all obvious:
 228  *
 229  *
 230  * SOCKETS, SOCKET SETS, BANKS, ROWS, CHIP-SELECT ROWS, CHANNELS, etc..
 231  *
 232  * These are some of the many terms that are thrown about that don't always
 233  * mean what people think they mean (Inconceivable!).  In the interest of
 234  * creating a common ground for discussion, terms and their definitions
 235  * will be established.
 236  *
 237  * Memory devices:      The individual chip on a memory stick.  These devices
 238  *                      commonly output 4 and 8 bits each.  Grouping several
 239  *                      of these in parallel provides 64 bits which is common
 240  *                      for a memory stick.
 241  *
 242  * Memory Stick:        A printed circuit board that agregates multiple
 243  *                      memory devices in parallel.  This is the atomic
 244  *                      memory component that is purchaseable by Joe consumer
 245  *                      and loaded into a memory socket.
 246  *
 247  * Socket:              A physical connector on the motherboard that accepts
 248  *                      a single memory stick.
 249  *
 250  * Channel:             Set of memory devices on a memory stick that must be
 251  *                      grouped in parallel with one or more additional
 252  *                      channels from other memory sticks.  This parallel
 253  *                      grouping of the output from multiple channels are
 254  *                      necessary for the smallest granularity of memory access.
 255  *                      Some memory controllers are capable of single channel -
 256  *                      which means that memory sticks can be loaded
 257  *                      individually.  Other memory controllers are only
 258  *                      capable of dual channel - which means that memory
 259  *                      sticks must be loaded as pairs (see "socket set").
 260  *
 261  * Chip-select row:     All of the memory devices that are selected together.
 262  *                      for a single, minimum grain of memory access.
 263  *                      This selects all of the parallel memory devices across
 264  *                      all of the parallel channels.  Common chip-select rows
 265  *                      for single channel are 64 bits, for dual channel 128
 266  *                      bits.
 267  *
 268  * Single-Ranked stick: A Single-ranked stick has 1 chip-select row of memmory.
 269  *                      Motherboards commonly drive two chip-select pins to
 270  *                      a memory stick. A single-ranked stick, will occupy
 271  *                      only one of those rows. The other will be unused.
 272  *
 273  * Double-Ranked stick: A double-ranked stick has two chip-select rows which
 274  *                      access different sets of memory devices.  The two
 275  *                      rows cannot be accessed concurrently.
 276  *
 277  * Double-sided stick:  DEPRECATED TERM, see Double-Ranked stick.
 278  *                      A double-sided stick has two chip-select rows which
 279  *                      access different sets of memory devices.  The two
 280  *                      rows cannot be accessed concurrently.  "Double-sided"
 281  *                      is irrespective of the memory devices being mounted
 282  *                      on both sides of the memory stick.
 283  *
 284  * Socket set:          All of the memory sticks that are required for for
 285  *                      a single memory access or all of the memory sticks
 286  *                      spanned by a chip-select row.  A single socket set
 287  *                      has two chip-select rows and if double-sided sticks
 288  *                      are used these will occupy those chip-select rows.
 289  *
 290  * Bank:                This term is avoided because it is unclear when
 291  *                      needing to distinguish between chip-select rows and
 292  *                      socket sets.
 293  *
 294  * Controller pages:
 295  *
 296  * Physical pages:
 297  *
 298  * Virtual pages:
 299  *
 300  *
 301  * STRUCTURE ORGANIZATION AND CHOICES
 302  *
 303  *
 304  *
 305  * PS - I enjoyed writing all that about as much as you enjoyed reading it.
 306  */
 307
 308 struct channel_info {
 309         int chan_idx;           /* channel index */
 310         u32 ce_count;           /* Correctable Errors for this CHANNEL */
 311         char label[EDAC_MC_LABEL_LEN + 1];      /* DIMM label on motherboard */
 312         struct csrow_info *csrow;       /* the parent */
 313 };
 314
 315 struct csrow_info {
 316         unsigned long first_page;       /* first page number in dimm */
 317         unsigned long last_page;        /* last page number in dimm */
 318         unsigned long page_mask;        /* used for interleaving -
 319                                          * 0UL for non intlv
 320                                          */
 321         u32 nr_pages;           /* number of pages in csrow */
 322         u32 grain;              /* granularity of reported error in bytes */
 323         int csrow_idx;          /* the chip-select row */
 324         enum dev_type dtype;    /* memory device type */
 325         u32 ue_count;           /* Uncorrectable Errors for this csrow */
 326         u32 ce_count;           /* Correctable Errors for this csrow */
 327         enum mem_type mtype;    /* memory csrow type */
 328         enum edac_type edac_mode;       /* EDAC mode for this csrow */
 329         struct mem_ctl_info *mci;       /* the parent */
 330
 331         struct kobject kobj;    /* sysfs kobject for this csrow */
 332
 333         /* channel information for this csrow */
 334         u32 nr_channels;
 335         struct channel_info *channels;
 336 };
 337
 338 /* mcidev_sysfs_attribute structure
 339  *      used for driver sysfs attributes and in mem_ctl_info
 340  *      sysfs top level entries
 341  */
 342 struct mcidev_sysfs_attribute {
 343         struct attribute attr;
 344         ssize_t (*show)(struct mem_ctl_info *,char *);
 345         ssize_t (*store)(struct mem_ctl_info *, const char *,size_t);
 346 };
 347
 348 /* MEMORY controller information structure
 349  */
 350 struct mem_ctl_info {
 351         struct list_head link;  /* for global list of mem_ctl_info structs */
 352
 353         struct module *owner;   /* Module owner of this control struct */
 354
 355         unsigned long mtype_cap;        /* memory types supported by mc */
 356         unsigned long edac_ctl_cap;     /* Mem controller EDAC capabilities */
 357         unsigned long edac_cap; /* configuration capabilities - this is
 358                                  * closely related to edac_ctl_cap.  The
 359                                  * difference is that the controller may be
 360                                  * capable of s4ecd4ed which would be listed
 361                                  * in edac_ctl_cap, but if channels aren't
 362                                  * capable of s4ecd4ed then the edac_cap would
 363                                  * not have that capability.
 364                                  */
 365         unsigned long scrub_cap;        /* chipset scrub capabilities */
 366         enum scrub_type scrub_mode;     /* current scrub mode */
 367
 368         /* Translates sdram memory scrub rate given in bytes/sec to the
 369            internal representation and configures whatever else needs
 370            to be configured.
 371          */
 372         int (*set_sdram_scrub_rate) (struct mem_ctl_info * mci, u32 * bw);
 373
 374         /* Get the current sdram memory scrub rate from the internal
 375            representation and converts it to the closest matching
 376            bandwith in bytes/sec.
 377          */
 378         int (*get_sdram_scrub_rate) (struct mem_ctl_info * mci, u32 * bw);
 379
 380
 381         /* pointer to edac checking routine */
 382         void (*edac_check) (struct mem_ctl_info * mci);
 383
 384         /*
 385          * Remaps memory pages: controller pages to physical pages.
 386          * For most MC's, this will be NULL.
 387          */
 388         /* FIXME - why not send the phys page to begin with? */
 389         unsigned long (*ctl_page_to_phys) (struct mem_ctl_info * mci,
 390                                            unsigned long page);
 391         int mc_idx;
 392         int nr_csrows;
 393         struct csrow_info *csrows;
 394         /*
 395          * FIXME - what about controllers on other busses? - IDs must be
 396          * unique.  dev pointer should be sufficiently unique, but
 397          * BUS:SLOT.FUNC numbers may not be unique.
 398          */
 399         struct device *dev;
 400         const char *mod_name;
 401         const char *mod_ver;
 402         const char *ctl_name;
 403         const char *dev_name;
 404         char proc_name[MC_PROC_NAME_MAX_LEN + 1];
 405         void *pvt_info;
 406         u32 ue_noinfo_count;    /* Uncorrectable Errors w/o info */
 407         u32 ce_noinfo_count;    /* Correctable Errors w/o info */
 408         u32 ue_count;           /* Total Uncorrectable Errors for this MC */
 409         u32 ce_count;           /* Total Correctable Errors for this MC */
 410         unsigned long start_time;       /* mci load start time (in jiffies) */
 411
 412         /* this stuff is for safe removal of mc devices from global list while
 413          * NMI handlers may be traversing list
 414          */
 415         struct rcu_head rcu;
 416         struct completion complete;
 417
 418         /* edac sysfs device control */
 419         struct kobject edac_mci_kobj;
 420
 421         /* Additional top controller level attributes, but specified
 422          * by the low level driver.
 423          *
 424          * Set by the low level driver to provide attributes at the
 425          * controller level, same level as 'ue_count' and 'ce_count' above.
 426          * An array of structures, NULL terminated
 427          *
 428          * If attributes are desired, then set to array of attributes
 429          * If no attributes are desired, leave NULL
 430          */
 431         struct mcidev_sysfs_attribute *mc_driver_sysfs_attributes;
 432
 433         /* work struct for this MC */
 434         struct delayed_work work;
 435
 436         /* the internal state of this controller instance */
 437         int op_state;
 438 };
 439
 440 /*
 441  * The following are the structures to provide for a generic
 442  * or abstract 'edac_device'. This set of structures and the
 443  * code that implements the APIs for the same, provide for
 444  * registering EDAC type devices which are NOT standard memory.
 445  *
 446  * CPU caches (L1 and L2)
 447  * DMA engines
 448  * Core CPU swithces
 449  * Fabric switch units
 450  * PCIe interface controllers
 451  * other EDAC/ECC type devices that can be monitored for
 452  * errors, etc.
 453  *
 454  * It allows for a 2 level set of hiearchry. For example:
 455  *
 456  * cache could be composed of L1, L2 and L3 levels of cache.
 457  * Each CPU core would have its own L1 cache, while sharing
 458  * L2 and maybe L3 caches.
 459  *
 460  * View them arranged, via the sysfs presentation:
 461  * /sys/devices/system/edac/..
 462  *
 463  *      mc/             <existing memory device directory>
 464  *      cpu/cpu0/..     <L1 and L2 block directory>
 465  *              /L1-cache/ce_count
 466  *                       /ue_count
 467  *              /L2-cache/ce_count
 468  *                       /ue_count
 469  *      cpu/cpu1/..     <L1 and L2 block directory>
 470  *              /L1-cache/ce_count
 471  *                       /ue_count
 472  *              /L2-cache/ce_count
 473  *                       /ue_count
 474  *      ...
 475  *
 476  *      the L1 and L2 directories would be "edac_device_block's"
 477  */
 478
 479 struct edac_device_counter {
 480         u32 ue_count;
 481         u32 ce_count;
 482 };
 483
 484 /* forward reference */
 485 struct edac_device_ctl_info;
 486 struct edac_device_block;
 487
 488 /* edac_dev_sysfs_attribute structure
 489  *      used for driver sysfs attributes in mem_ctl_info
 490  *      for extra controls and attributes:
 491  *              like high level error Injection controls
 492  */
 493 struct edac_dev_sysfs_attribute {
 494         struct attribute attr;
 495         ssize_t (*show)(struct edac_device_ctl_info *, char *);
 496         ssize_t (*store)(struct edac_device_ctl_info *, const char *, size_t);
 497 };
 498
 499 /* edac_dev_sysfs_block_attribute structure
 500  *
 501  *      used in leaf 'block' nodes for adding controls/attributes
 502  *
 503  *      each block in each instance of the containing control structure
 504  *      can have an array of the following. The show and store functions
 505  *      will be filled in with the show/store function in the
 506  *      low level driver.
 507  *
 508  *      The 'value' field will be the actual value field used for
 509  *      counting
 510  */
 511 struct edac_dev_sysfs_block_attribute {
 512         struct attribute attr;
 513         ssize_t (*show)(struct kobject *, struct attribute *, char *);
 514         ssize_t (*store)(struct kobject *, struct attribute *,
 515                         const char *, size_t);
 516         struct edac_device_block *block;
 517
 518         unsigned int value;
 519 };
 520
 521 /* device block control structure */
 522 struct edac_device_block {
 523         struct edac_device_instance *instance;  /* Up Pointer */
 524         char name[EDAC_DEVICE_NAME_LEN + 1];
 525
 526         struct edac_device_counter counters;    /* basic UE and CE counters */
 527
 528         int nr_attribs;         /* how many attributes */
 529
 530         /* this block's attributes, could be NULL */
 531         struct edac_dev_sysfs_block_attribute *block_attributes;
 532
 533         /* edac sysfs device control */
 534         struct kobject kobj;
 535 };
 536
 537 /* device instance control structure */
 538 struct edac_device_instance {
 539         struct edac_device_ctl_info *ctl;       /* Up pointer */
 540         char name[EDAC_DEVICE_NAME_LEN + 4];
 541
 542         struct edac_device_counter counters;    /* instance counters */
 543
 544         u32 nr_blocks;          /* how many blocks */
 545         struct edac_device_block *blocks;       /* block array */
 546
 547         /* edac sysfs device control */
 548         struct kobject kobj;
 549 };
 550
 551
 552 /*
 553  * Abstract edac_device control info structure
 554  *
 555  */
 556 struct edac_device_ctl_info {
 557         /* for global list of edac_device_ctl_info structs */
 558         struct list_head link;
 559
 560         struct module *owner;   /* Module owner of this control struct */
 561
 562         int dev_idx;
 563
 564         /* Per instance controls for this edac_device */
 565         int log_ue;             /* boolean for logging UEs */
 566         int log_ce;             /* boolean for logging CEs */
 567         int panic_on_ue;        /* boolean for panic'ing on an UE */
 568         unsigned poll_msec;     /* number of milliseconds to poll interval */
 569         unsigned long delay;    /* number of jiffies for poll_msec */
 570
 571         /* Additional top controller level attributes, but specified
 572          * by the low level driver.
 573          *
 574          * Set by the low level driver to provide attributes at the
 575          * controller level, same level as 'ue_count' and 'ce_count' above.
 576          * An array of structures, NULL terminated
 577          *
 578          * If attributes are desired, then set to array of attributes
 579          * If no attributes are desired, leave NULL
 580          */
 581         struct edac_dev_sysfs_attribute *sysfs_attributes;
 582
 583         /* pointer to main 'edac' class in sysfs */
 584         struct sysdev_class *edac_class;
 585
 586         /* the internal state of this controller instance */
 587         int op_state;
 588         /* work struct for this instance */
 589         struct delayed_work work;
 590
 591         /* pointer to edac polling checking routine:
 592          *      If NOT NULL: points to polling check routine
 593          *      If NULL: Then assumes INTERRUPT operation, where
 594          *              MC driver will receive events
 595          */
 596         void (*edac_check) (struct edac_device_ctl_info * edac_dev);
 597
 598         struct device *dev;     /* pointer to device structure */
 599
 600         const char *mod_name;   /* module name */
 601         const char *ctl_name;   /* edac controller  name */
 602         const char *dev_name;   /* pci/platform/etc... name */
 603
 604         void *pvt_info;         /* pointer to 'private driver' info */
 605
 606         unsigned long start_time;       /* edac_device load start time (jiffies) */
 607
 608         /* these are for safe removal of mc devices from global list while
 609          * NMI handlers may be traversing list
 610          */
 611         struct rcu_head rcu;
 612         struct completion removal_complete;
 613
 614         /* sysfs top name under 'edac' directory
 615          * and instance name:
 616          *      cpu/cpu0/...
 617          *      cpu/cpu1/...
 618          *      cpu/cpu2/...
 619          *      ...
 620          */
 621         char name[EDAC_DEVICE_NAME_LEN + 1];
 622
 623         /* Number of instances supported on this control structure
 624          * and the array of those instances
 625          */
 626         u32 nr_instances;
 627         struct edac_device_instance *instances;
 628
 629         /* Event counters for the this whole EDAC Device */
 630         struct edac_device_counter counters;
 631
 632         /* edac sysfs device control for the 'name'
 633          * device this structure controls
 634          */
 635         struct kobject kobj;
 636 };
 637
 638 /* To get from the instance's wq to the beginning of the ctl structure */
 639 #define to_edac_mem_ctl_work(w) \
 640                 container_of(w, struct mem_ctl_info, work)
 641
 642 #define to_edac_device_ctl_work(w) \
 643                 container_of(w,struct edac_device_ctl_info,work)
 644
 645 /*
 646  * The alloc() and free() functions for the 'edac_device' control info
 647  * structure. A MC driver will allocate one of these for each edac_device
 648  * it is going to control/register with the EDAC CORE.
 649  */
 650 extern struct edac_device_ctl_info *edac_device_alloc_ctl_info(
 651                 unsigned sizeof_private,
 652                 char *edac_device_name, unsigned nr_instances,
 653                 char *edac_block_name, unsigned nr_blocks,
 654                 unsigned offset_value,
 655                 struct edac_dev_sysfs_block_attribute *block_attributes,
 656                 unsigned nr_attribs,
 657                 int device_index);
 658
 659 /* The offset value can be:
 660  *      -1 indicating no offset value
 661  *      0 for zero-based block numbers
 662  *      1 for 1-based block number
 663  *      other for other-based block number
 664  */
 665 #define BLOCK_OFFSET_VALUE_OFF  ((unsigned) -1)
 666
 667 extern void edac_device_free_ctl_info(struct edac_device_ctl_info *ctl_info);
 668
 669 #ifdef CONFIG_PCI
 670
 671 struct edac_pci_counter {
 672         atomic_t pe_count;
 673         atomic_t npe_count;
 674 };
 675
 676 /*
 677  * Abstract edac_pci control info structure
 678  *
 679  */
 680 struct edac_pci_ctl_info {
 681         /* for global list of edac_pci_ctl_info structs */
 682         struct list_head link;
 683
 684         int pci_idx;
 685
 686         struct sysdev_class *edac_class;        /* pointer to class */
 687
 688         /* the internal state of this controller instance */
 689         int op_state;
 690         /* work struct for this instance */
 691         struct delayed_work work;
 692
 693         /* pointer to edac polling checking routine:
 694          *      If NOT NULL: points to polling check routine
 695          *      If NULL: Then assumes INTERRUPT operation, where
 696          *              MC driver will receive events
 697          */
 698         void (*edac_check) (struct edac_pci_ctl_info * edac_dev);
 699
 700         struct device *dev;     /* pointer to device structure */
 701
 702         const char *mod_name;   /* module name */
 703         const char *ctl_name;   /* edac controller  name */
 704         const char *dev_name;   /* pci/platform/etc... name */
 705
 706         void *pvt_info;         /* pointer to 'private driver' info */
 707
 708         unsigned long start_time;       /* edac_pci load start time (jiffies) */
 709
 710         /* these are for safe removal of devices from global list while
 711          * NMI handlers may be traversing list
 712          */
 713         struct rcu_head rcu;
 714         struct completion complete;
 715
 716         /* sysfs top name under 'edac' directory
 717          * and instance name:
 718          *      cpu/cpu0/...
 719          *      cpu/cpu1/...
 720          *      cpu/cpu2/...
 721          *      ...
 722          */
 723         char name[EDAC_DEVICE_NAME_LEN + 1];
 724
 725         /* Event counters for the this whole EDAC Device */
 726         struct edac_pci_counter counters;
 727
 728         /* edac sysfs device control for the 'name'
 729          * device this structure controls
 730          */
 731         struct kobject kobj;
 732         struct completion kobj_complete;
 733 };
 734
 735 #define to_edac_pci_ctl_work(w) \
 736                 container_of(w, struct edac_pci_ctl_info,work)
 737
 738 /* write all or some bits in a byte-register*/
 739 static inline void pci_write_bits8(struct pci_dev *pdev, int offset, u8 value,
 740                                    u8 mask)
 741 {
 742         if (mask != 0xff) {
 743                 u8 buf;
 744
 745                 pci_read_config_byte(pdev, offset, &buf);
 746                 value &= mask;
 747                 buf &= ~mask;
 748                 value |= buf;
 749         }
 750
 751         pci_write_config_byte(pdev, offset, value);
 752 }
 753
 754 /* write all or some bits in a word-register*/
 755 static inline void pci_write_bits16(struct pci_dev *pdev, int offset,
 756                                     u16 value, u16 mask)
 757 {
 758         if (mask != 0xffff) {
 759                 u16 buf;
 760
 761                 pci_read_config_word(pdev, offset, &buf);
 762                 value &= mask;
 763                 buf &= ~mask;
 764                 value |= buf;
 765         }
 766
 767         pci_write_config_word(pdev, offset, value);
 768 }
 769
 770 /*
 771  * pci_write_bits32
 772  *
 773  * edac local routine to do pci_write_config_dword, but adds
 774  * a mask parameter. If mask is all ones, ignore the mask.
 775  * Otherwise utilize the mask to isolate specified bits
 776  *
 777  * write all or some bits in a dword-register
 778  */
 779 static inline void pci_write_bits32(struct pci_dev *pdev, int offset,
 780                                     u32 value, u32 mask)
 781 {
 782         if (mask != 0xffffffff) {
 783                 u32 buf;
 784
 785                 pci_read_config_dword(pdev, offset, &buf);
 786                 value &= mask;
 787                 buf &= ~mask;
 788                 value |= buf;
 789         }
 790
 791         pci_write_config_dword(pdev, offset, value);
 792 }
 793
 794 #endif                          /* CONFIG_PCI */
 795
 796 extern struct mem_ctl_info *edac_mc_alloc(unsigned sz_pvt, unsigned nr_csrows,
 797                                           unsigned nr_chans, int edac_index);
 798 extern int edac_mc_add_mc(struct mem_ctl_info *mci);
 799 extern void edac_mc_free(struct mem_ctl_info *mci);
 800 extern struct mem_ctl_info *edac_mc_find(int idx);
 801 extern struct mem_ctl_info *edac_mc_del_mc(struct device *dev);
 802 extern int edac_mc_find_csrow_by_page(struct mem_ctl_info *mci,
 803                                       unsigned long page);
 804
 805 /*
 806  * The no info errors are used when error overflows are reported.
 807  * There are a limited number of error logging registers that can
 808  * be exausted.  When all registers are exhausted and an additional
 809  * error occurs then an error overflow register records that an
 810  * error occured and the type of error, but doesn't have any
 811  * further information.  The ce/ue versions make for cleaner
 812  * reporting logic and function interface - reduces conditional
 813  * statement clutter and extra function arguments.
 814  */
 815 extern void edac_mc_handle_ce(struct mem_ctl_info *mci,
 816                               unsigned long page_frame_number,
 817                               unsigned long offset_in_page,
 818                               unsigned long syndrome, int row, int channel,
 819                               const char *msg);
 820 extern void edac_mc_handle_ce_no_info(struct mem_ctl_info *mci,
 821                                       const char *msg);
 822 extern void edac_mc_handle_ue(struct mem_ctl_info *mci,
 823                               unsigned long page_frame_number,
 824                               unsigned long offset_in_page, int row,
 825                               const char *msg);
 826 extern void edac_mc_handle_ue_no_info(struct mem_ctl_info *mci,
 827                                       const char *msg);
 828 extern void edac_mc_handle_fbd_ue(struct mem_ctl_info *mci, unsigned int csrow,
 829                                   unsigned int channel0, unsigned int channel1,
 830                                   char *msg);
 831 extern void edac_mc_handle_fbd_ce(struct mem_ctl_info *mci, unsigned int csrow,
 832                                   unsigned int channel, char *msg);
 833
 834 /*
 835  * edac_device APIs
 836  */
 837 extern int edac_device_add_device(struct edac_device_ctl_info *edac_dev);
 838 extern struct edac_device_ctl_info *edac_device_del_device(struct device *dev);
 839 extern void edac_device_handle_ue(struct edac_device_ctl_info *edac_dev,
 840                                 int inst_nr, int block_nr, const char *msg);
 841 extern void edac_device_handle_ce(struct edac_device_ctl_info *edac_dev,
 842                                 int inst_nr, int block_nr, const char *msg);
 843
 844 /*
 845  * edac_pci APIs
 846  */
 847 extern struct edac_pci_ctl_info *edac_pci_alloc_ctl_info(unsigned int sz_pvt,
 848                                 const char *edac_pci_name);
 849
 850 extern void edac_pci_free_ctl_info(struct edac_pci_ctl_info *pci);
 851
 852 extern void edac_pci_reset_delay_period(struct edac_pci_ctl_info *pci,
 853                                 unsigned long value);
 854
 855 extern int edac_pci_alloc_index(void);
 856 extern int edac_pci_add_device(struct edac_pci_ctl_info *pci, int edac_idx);
 857 extern struct edac_pci_ctl_info *edac_pci_del_device(struct device *dev);
 858
 859 extern struct edac_pci_ctl_info *edac_pci_create_generic_ctl(
 860                                 struct device *dev,
 861                                 const char *mod_name);
 862
 863 extern void edac_pci_release_generic_ctl(struct edac_pci_ctl_info *pci);
 864 extern int edac_pci_create_sysfs(struct edac_pci_ctl_info *pci);
 865 extern void edac_pci_remove_sysfs(struct edac_pci_ctl_info *pci);
 866
 867 /*
 868  * edac misc APIs
 869  */
 870 extern char *edac_op_state_to_string(int op_state);
 871
 872 #endif                          /* _EDAC_CORE_H_ */