?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
sata_mv delayed eh handling
[linux-2.6/verdex.git] / drivers / ata / sata_mv.c
blob1991eb22e388a175484bacf079ba088ae2d226a6
1 /*
2 * sata_mv.c - Marvell SATA support
3 *
4 * Copyright 2008: Marvell Corporation, all rights reserved.
5 * Copyright 2005: EMC Corporation, all rights reserved.
6 * Copyright 2005 Red Hat, Inc. All rights reserved.
7 *
8 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2 of the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 */
24
25 /*
26 * sata_mv TODO list:
27 *
28 * --> Errata workaround for NCQ device errors.
29 *
30 * --> More errata workarounds for PCI-X.
31 *
32 * --> Complete a full errata audit for all chipsets to identify others.
33 *
34 * --> ATAPI support (Marvell claims the 60xx/70xx chips can do it).
35 *
36 * --> Investigate problems with PCI Message Signalled Interrupts (MSI).
37 *
38 * --> Cache frequently-accessed registers in mv_port_priv to reduce overhead.
39 *
40 * --> Develop a low-power-consumption strategy, and implement it.
41 *
42 * --> [Experiment, low priority] Investigate interrupt coalescing.
43 * Quite often, especially with PCI Message Signalled Interrupts (MSI),
44 * the overhead reduced by interrupt mitigation is quite often not
45 * worth the latency cost.
46 *
47 * --> [Experiment, Marvell value added] Is it possible to use target
48 * mode to cross-connect two Linux boxes with Marvell cards? If so,
49 * creating LibATA target mode support would be very interesting.
50 *
51 * Target mode, for those without docs, is the ability to directly
52 * connect two SATA ports.
53 */
54
55 #include <linux/kernel.h>
56 #include <linux/module.h>
57 #include <linux/pci.h>
58 #include <linux/init.h>
59 #include <linux/blkdev.h>
60 #include <linux/delay.h>
61 #include <linux/interrupt.h>
62 #include <linux/dmapool.h>
63 #include <linux/dma-mapping.h>
64 #include <linux/device.h>
65 #include <linux/platform_device.h>
66 #include <linux/ata_platform.h>
67 #include <linux/mbus.h>
68 #include <scsi/scsi_host.h>
69 #include <scsi/scsi_cmnd.h>
70 #include <scsi/scsi_device.h>
71 #include <linux/libata.h>
72
73 #define DRV_NAME "sata_mv"
74 #define DRV_VERSION "1.20"
75
76 enum {
77 /* BAR's are enumerated in terms of pci_resource_start() terms */
78 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
79 MV_IO_BAR = 2, /* offset 0x18: IO space */
80 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
81
82 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
83 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
84
85 MV_PCI_REG_BASE = 0,
86 MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */
87 MV_IRQ_COAL_CAUSE = (MV_IRQ_COAL_REG_BASE + 0x08),
88 MV_IRQ_COAL_CAUSE_LO = (MV_IRQ_COAL_REG_BASE + 0x88),
89 MV_IRQ_COAL_CAUSE_HI = (MV_IRQ_COAL_REG_BASE + 0x8c),
90 MV_IRQ_COAL_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xcc),
91 MV_IRQ_COAL_TIME_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xd0),
92
93 MV_SATAHC0_REG_BASE = 0x20000,
94 MV_FLASH_CTL_OFS = 0x1046c,
95 MV_GPIO_PORT_CTL_OFS = 0x104f0,
96 MV_RESET_CFG_OFS = 0x180d8,
97
98 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
99 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
100 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
101 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
102
103 MV_MAX_Q_DEPTH = 32,
104 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
105
106 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
107 * CRPB needs alignment on a 256B boundary. Size == 256B
108 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
109 */
110 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
111 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
112 MV_MAX_SG_CT = 256,
113 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
114
115 /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */
116 MV_PORT_HC_SHIFT = 2,
117 MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT), /* 4 */
118 /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */
119 MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */
120
121 /* Host Flags */
122 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
123 MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */
124 /* SoC integrated controllers, no PCI interface */
125 MV_FLAG_SOC = (1 << 28),
126
127 MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
128 ATA_FLAG_MMIO | ATA_FLAG_NO_ATAPI |
129 ATA_FLAG_PIO_POLLING,
130 MV_6XXX_FLAGS = MV_FLAG_IRQ_COALESCE,
131
132 CRQB_FLAG_READ = (1 << 0),
133 CRQB_TAG_SHIFT = 1,
134 CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */
135 CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */
136 CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */
137 CRQB_CMD_ADDR_SHIFT = 8,
138 CRQB_CMD_CS = (0x2 << 11),
139 CRQB_CMD_LAST = (1 << 15),
140
141 CRPB_FLAG_STATUS_SHIFT = 8,
142 CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */
143 CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */
144
145 EPRD_FLAG_END_OF_TBL = (1 << 31),
146
147 /* PCI interface registers */
148
149 PCI_COMMAND_OFS = 0xc00,
150 PCI_COMMAND_MRDTRIG = (1 << 7), /* PCI Master Read Trigger */
151
152 PCI_MAIN_CMD_STS_OFS = 0xd30,
153 STOP_PCI_MASTER = (1 << 2),
154 PCI_MASTER_EMPTY = (1 << 3),
155 GLOB_SFT_RST = (1 << 4),
156
157 MV_PCI_MODE_OFS = 0xd00,
158 MV_PCI_MODE_MASK = 0x30,
159
160 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
161 MV_PCI_DISC_TIMER = 0xd04,
162 MV_PCI_MSI_TRIGGER = 0xc38,
163 MV_PCI_SERR_MASK = 0xc28,
164 MV_PCI_XBAR_TMOUT_OFS = 0x1d04,
165 MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
166 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
167 MV_PCI_ERR_ATTRIBUTE = 0x1d48,
168 MV_PCI_ERR_COMMAND = 0x1d50,
169
170 PCI_IRQ_CAUSE_OFS = 0x1d58,
171 PCI_IRQ_MASK_OFS = 0x1d5c,
172 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
173
174 PCIE_IRQ_CAUSE_OFS = 0x1900,
175 PCIE_IRQ_MASK_OFS = 0x1910,
176 PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */
177
178 /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */
179 PCI_HC_MAIN_IRQ_CAUSE_OFS = 0x1d60,
180 PCI_HC_MAIN_IRQ_MASK_OFS = 0x1d64,
181 SOC_HC_MAIN_IRQ_CAUSE_OFS = 0x20020,
182 SOC_HC_MAIN_IRQ_MASK_OFS = 0x20024,
183 ERR_IRQ = (1 << 0), /* shift by port # */
184 DONE_IRQ = (1 << 1), /* shift by port # */
185 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
186 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
187 PCI_ERR = (1 << 18),
188 TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */
189 TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */
190 PORTS_0_3_COAL_DONE = (1 << 8),
191 PORTS_4_7_COAL_DONE = (1 << 17),
192 PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */
193 GPIO_INT = (1 << 22),
194 SELF_INT = (1 << 23),
195 TWSI_INT = (1 << 24),
196 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
197 HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */
198 HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */
199 HC_MAIN_MASKED_IRQS = (TRAN_LO_DONE | TRAN_HI_DONE |
200 PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE |
201 PORTS_0_7_COAL_DONE | GPIO_INT | TWSI_INT |
202 HC_MAIN_RSVD),
203 HC_MAIN_MASKED_IRQS_5 = (PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE |
204 HC_MAIN_RSVD_5),
205 HC_MAIN_MASKED_IRQS_SOC = (PORTS_0_3_COAL_DONE | HC_MAIN_RSVD_SOC),
206
207 /* SATAHC registers */
208 HC_CFG_OFS = 0,
209
210 HC_IRQ_CAUSE_OFS = 0x14,
211 DMA_IRQ = (1 << 0), /* shift by port # */
212 HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */
213 DEV_IRQ = (1 << 8), /* shift by port # */
214
215 /* Shadow block registers */
216 SHD_BLK_OFS = 0x100,
217 SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */
218
219 /* SATA registers */
220 SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */
221 SATA_ACTIVE_OFS = 0x350,
222 SATA_FIS_IRQ_CAUSE_OFS = 0x364,
223
224 LTMODE_OFS = 0x30c,
225 LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */
226
227 PHY_MODE3 = 0x310,
228 PHY_MODE4 = 0x314,
229 PHY_MODE2 = 0x330,
230 SATA_IFCTL_OFS = 0x344,
231 SATA_TESTCTL_OFS = 0x348,
232 SATA_IFSTAT_OFS = 0x34c,
233 VENDOR_UNIQUE_FIS_OFS = 0x35c,
234
235 FISCFG_OFS = 0x360,
236 FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */
237 FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */
238
239 MV5_PHY_MODE = 0x74,
240 MV5_LTMODE_OFS = 0x30,
241 MV5_PHY_CTL_OFS = 0x0C,
242 SATA_INTERFACE_CFG_OFS = 0x050,
243
244 MV_M2_PREAMP_MASK = 0x7e0,
245
246 /* Port registers */
247 EDMA_CFG_OFS = 0,
248 EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */
249 EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */
250 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
251 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
252 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
253 EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */
254 EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */
255
256 EDMA_ERR_IRQ_CAUSE_OFS = 0x8,
257 EDMA_ERR_IRQ_MASK_OFS = 0xc,
258 EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */
259 EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */
260 EDMA_ERR_DEV = (1 << 2), /* device error */
261 EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */
262 EDMA_ERR_DEV_CON = (1 << 4), /* device connected */
263 EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */
264 EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */
265 EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */
266 EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */
267 EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */
268 EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */
269 EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */
270 EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */
271 EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */
272
273 EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */
274 EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */
275 EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */
276 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */
277 EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */
278
279 EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */
280
281 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */
282 EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */
283 EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */
284 EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */
285 EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */
286 EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */
287
288 EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */
289
290 EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */
291 EDMA_ERR_OVERRUN_5 = (1 << 5),
292 EDMA_ERR_UNDERRUN_5 = (1 << 6),
293
294 EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 |
295 EDMA_ERR_LNK_CTRL_RX_1 |
296 EDMA_ERR_LNK_CTRL_RX_3 |
297 EDMA_ERR_LNK_CTRL_TX,
298
299 EDMA_EH_FREEZE = EDMA_ERR_D_PAR |
300 EDMA_ERR_PRD_PAR |
301 EDMA_ERR_DEV_DCON |
302 EDMA_ERR_DEV_CON |
303 EDMA_ERR_SERR |
304 EDMA_ERR_SELF_DIS |
305 EDMA_ERR_CRQB_PAR |
306 EDMA_ERR_CRPB_PAR |
307 EDMA_ERR_INTRL_PAR |
308 EDMA_ERR_IORDY |
309 EDMA_ERR_LNK_CTRL_RX_2 |
310 EDMA_ERR_LNK_DATA_RX |
311 EDMA_ERR_LNK_DATA_TX |
312 EDMA_ERR_TRANS_PROTO,
313
314 EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR |
315 EDMA_ERR_PRD_PAR |
316 EDMA_ERR_DEV_DCON |
317 EDMA_ERR_DEV_CON |
318 EDMA_ERR_OVERRUN_5 |
319 EDMA_ERR_UNDERRUN_5 |
320 EDMA_ERR_SELF_DIS_5 |
321 EDMA_ERR_CRQB_PAR |
322 EDMA_ERR_CRPB_PAR |
323 EDMA_ERR_INTRL_PAR |
324 EDMA_ERR_IORDY,
325
326 EDMA_REQ_Q_BASE_HI_OFS = 0x10,
327 EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */
328
329 EDMA_REQ_Q_OUT_PTR_OFS = 0x18,
330 EDMA_REQ_Q_PTR_SHIFT = 5,
331
332 EDMA_RSP_Q_BASE_HI_OFS = 0x1c,
333 EDMA_RSP_Q_IN_PTR_OFS = 0x20,
334 EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */
335 EDMA_RSP_Q_PTR_SHIFT = 3,
336
337 EDMA_CMD_OFS = 0x28, /* EDMA command register */
338 EDMA_EN = (1 << 0), /* enable EDMA */
339 EDMA_DS = (1 << 1), /* disable EDMA; self-negated */
340 EDMA_RESET = (1 << 2), /* reset eng/trans/link/phy */
341
342 EDMA_STATUS_OFS = 0x30, /* EDMA engine status */
343 EDMA_STATUS_CACHE_EMPTY = (1 << 6), /* GenIIe command cache empty */
344 EDMA_STATUS_IDLE = (1 << 7), /* GenIIe EDMA enabled/idle */
345
346 EDMA_IORDY_TMOUT_OFS = 0x34,
347 EDMA_ARB_CFG_OFS = 0x38,
348
349 EDMA_HALTCOND_OFS = 0x60, /* GenIIe halt conditions */
350
351 GEN_II_NCQ_MAX_SECTORS = 256, /* max sects/io on Gen2 w/NCQ */
352
353 /* Host private flags (hp_flags) */
354 MV_HP_FLAG_MSI = (1 << 0),
355 MV_HP_ERRATA_50XXB0 = (1 << 1),
356 MV_HP_ERRATA_50XXB2 = (1 << 2),
357 MV_HP_ERRATA_60X1B2 = (1 << 3),
358 MV_HP_ERRATA_60X1C0 = (1 << 4),
359 MV_HP_ERRATA_XX42A0 = (1 << 5),
360 MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */
361 MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */
362 MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */
363 MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */
364 MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */
365
366 /* Port private flags (pp_flags) */
367 MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */
368 MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */
369 MV_PP_FLAG_FBS_EN = (1 << 2), /* is EDMA set up for FBS? */
370 MV_PP_FLAG_DELAYED_EH = (1 << 3), /* delayed dev err handling */
371 };
372
373 #define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I)
374 #define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II)
375 #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
376 #define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE)
377 #define HAS_PCI(host) (!((host)->ports[0]->flags & MV_FLAG_SOC))
378
379 #define WINDOW_CTRL(i) (0x20030 + ((i) << 4))
380 #define WINDOW_BASE(i) (0x20034 + ((i) << 4))
381
382 enum {
383 /* DMA boundary 0xffff is required by the s/g splitting
384 * we need on /length/ in mv_fill-sg().
385 */
386 MV_DMA_BOUNDARY = 0xffffU,
387
388 /* mask of register bits containing lower 32 bits
389 * of EDMA request queue DMA address
390 */
391 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
392
393 /* ditto, for response queue */
394 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
395 };
396
397 enum chip_type {
398 chip_504x,
399 chip_508x,
400 chip_5080,
401 chip_604x,
402 chip_608x,
403 chip_6042,
404 chip_7042,
405 chip_soc,
406 };
407
408 /* Command ReQuest Block: 32B */
409 struct mv_crqb {
410 __le32 sg_addr;
411 __le32 sg_addr_hi;
412 __le16 ctrl_flags;
413 __le16 ata_cmd[11];
414 };
415
416 struct mv_crqb_iie {
417 __le32 addr;
418 __le32 addr_hi;
419 __le32 flags;
420 __le32 len;
421 __le32 ata_cmd[4];
422 };
423
424 /* Command ResPonse Block: 8B */
425 struct mv_crpb {
426 __le16 id;
427 __le16 flags;
428 __le32 tmstmp;
429 };
430
431 /* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
432 struct mv_sg {
433 __le32 addr;
434 __le32 flags_size;
435 __le32 addr_hi;
436 __le32 reserved;
437 };
438
439 struct mv_port_priv {
440 struct mv_crqb *crqb;
441 dma_addr_t crqb_dma;
442 struct mv_crpb *crpb;
443 dma_addr_t crpb_dma;
444 struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH];
445 dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH];
446
447 unsigned int req_idx;
448 unsigned int resp_idx;
449
450 u32 pp_flags;
451 unsigned int delayed_eh_pmp_map;
452 };
453
454 struct mv_port_signal {
455 u32 amps;
456 u32 pre;
457 };
458
459 struct mv_host_priv {
460 u32 hp_flags;
461 struct mv_port_signal signal[8];
462 const struct mv_hw_ops *ops;
463 int n_ports;
464 void __iomem *base;
465 void __iomem *main_irq_cause_addr;
466 void __iomem *main_irq_mask_addr;
467 u32 irq_cause_ofs;
468 u32 irq_mask_ofs;
469 u32 unmask_all_irqs;
470 /*
471 * These consistent DMA memory pools give us guaranteed
472 * alignment for hardware-accessed data structures,
473 * and less memory waste in accomplishing the alignment.
474 */
475 struct dma_pool *crqb_pool;
476 struct dma_pool *crpb_pool;
477 struct dma_pool *sg_tbl_pool;
478 };
479
480 struct mv_hw_ops {
481 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
482 unsigned int port);
483 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
484 void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
485 void __iomem *mmio);
486 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
487 unsigned int n_hc);
488 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
489 void (*reset_bus)(struct ata_host *host, void __iomem *mmio);
490 };
491
492 static int mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val);
493 static int mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
494 static int mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val);
495 static int mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
496 static int mv_port_start(struct ata_port *ap);
497 static void mv_port_stop(struct ata_port *ap);
498 static int mv_qc_defer(struct ata_queued_cmd *qc);
499 static void mv_qc_prep(struct ata_queued_cmd *qc);
500 static void mv_qc_prep_iie(struct ata_queued_cmd *qc);
501 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc);
502 static int mv_hardreset(struct ata_link *link, unsigned int *class,
503 unsigned long deadline);
504 static void mv_eh_freeze(struct ata_port *ap);
505 static void mv_eh_thaw(struct ata_port *ap);
506 static void mv6_dev_config(struct ata_device *dev);
507
508 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
509 unsigned int port);
510 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
511 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
512 void __iomem *mmio);
513 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
514 unsigned int n_hc);
515 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
516 static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio);
517
518 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
519 unsigned int port);
520 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
521 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
522 void __iomem *mmio);
523 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
524 unsigned int n_hc);
525 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
526 static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
527 void __iomem *mmio);
528 static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
529 void __iomem *mmio);
530 static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
531 void __iomem *mmio, unsigned int n_hc);
532 static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
533 void __iomem *mmio);
534 static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio);
535 static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio);
536 static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
537 unsigned int port_no);
538 static int mv_stop_edma(struct ata_port *ap);
539 static int mv_stop_edma_engine(void __iomem *port_mmio);
540 static void mv_edma_cfg(struct ata_port *ap, int want_ncq);
541
542 static void mv_pmp_select(struct ata_port *ap, int pmp);
543 static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
544 unsigned long deadline);
545 static int mv_softreset(struct ata_link *link, unsigned int *class,
546 unsigned long deadline);
547 static void mv_pmp_error_handler(struct ata_port *ap);
548
549 /* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below
550 * because we have to allow room for worst case splitting of
551 * PRDs for 64K boundaries in mv_fill_sg().
552 */
553 static struct scsi_host_template mv5_sht = {
554 ATA_BASE_SHT(DRV_NAME),
555 .sg_tablesize = MV_MAX_SG_CT / 2,
556 .dma_boundary = MV_DMA_BOUNDARY,
557 };
558
559 static struct scsi_host_template mv6_sht = {
560 ATA_NCQ_SHT(DRV_NAME),
561 .can_queue = MV_MAX_Q_DEPTH - 1,
562 .sg_tablesize = MV_MAX_SG_CT / 2,
563 .dma_boundary = MV_DMA_BOUNDARY,
564 };
565
566 static struct ata_port_operations mv5_ops = {
567 .inherits = &ata_sff_port_ops,
568
569 .qc_defer = mv_qc_defer,
570 .qc_prep = mv_qc_prep,
571 .qc_issue = mv_qc_issue,
572
573 .freeze = mv_eh_freeze,
574 .thaw = mv_eh_thaw,
575 .hardreset = mv_hardreset,
576 .error_handler = ata_std_error_handler, /* avoid SFF EH */
577 .post_internal_cmd = ATA_OP_NULL,
578
579 .scr_read = mv5_scr_read,
580 .scr_write = mv5_scr_write,
581
582 .port_start = mv_port_start,
583 .port_stop = mv_port_stop,
584 };
585
586 static struct ata_port_operations mv6_ops = {
587 .inherits = &mv5_ops,
588 .dev_config = mv6_dev_config,
589 .scr_read = mv_scr_read,
590 .scr_write = mv_scr_write,
591
592 .pmp_hardreset = mv_pmp_hardreset,
593 .pmp_softreset = mv_softreset,
594 .softreset = mv_softreset,
595 .error_handler = mv_pmp_error_handler,
596 };
597
598 static struct ata_port_operations mv_iie_ops = {
599 .inherits = &mv6_ops,
600 .dev_config = ATA_OP_NULL,
601 .qc_prep = mv_qc_prep_iie,
602 };
603
604 static const struct ata_port_info mv_port_info[] = {
605 { /* chip_504x */
606 .flags = MV_COMMON_FLAGS,
607 .pio_mask = 0x1f, /* pio0-4 */
608 .udma_mask = ATA_UDMA6,
609 .port_ops = &mv5_ops,
610 },
611 { /* chip_508x */
612 .flags = MV_COMMON_FLAGS | MV_FLAG_DUAL_HC,
613 .pio_mask = 0x1f, /* pio0-4 */
614 .udma_mask = ATA_UDMA6,
615 .port_ops = &mv5_ops,
616 },
617 { /* chip_5080 */
618 .flags = MV_COMMON_FLAGS | MV_FLAG_DUAL_HC,
619 .pio_mask = 0x1f, /* pio0-4 */
620 .udma_mask = ATA_UDMA6,
621 .port_ops = &mv5_ops,
622 },
623 { /* chip_604x */
624 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
625 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
626 ATA_FLAG_NCQ,
627 .pio_mask = 0x1f, /* pio0-4 */
628 .udma_mask = ATA_UDMA6,
629 .port_ops = &mv6_ops,
630 },
631 { /* chip_608x */
632 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
633 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
634 ATA_FLAG_NCQ | MV_FLAG_DUAL_HC,
635 .pio_mask = 0x1f, /* pio0-4 */
636 .udma_mask = ATA_UDMA6,
637 .port_ops = &mv6_ops,
638 },
639 { /* chip_6042 */
640 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
641 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
642 ATA_FLAG_NCQ,
643 .pio_mask = 0x1f, /* pio0-4 */
644 .udma_mask = ATA_UDMA6,
645 .port_ops = &mv_iie_ops,
646 },
647 { /* chip_7042 */
648 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
649 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
650 ATA_FLAG_NCQ,
651 .pio_mask = 0x1f, /* pio0-4 */
652 .udma_mask = ATA_UDMA6,
653 .port_ops = &mv_iie_ops,
654 },
655 { /* chip_soc */
656 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
657 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
658 ATA_FLAG_NCQ | MV_FLAG_SOC,
659 .pio_mask = 0x1f, /* pio0-4 */
660 .udma_mask = ATA_UDMA6,
661 .port_ops = &mv_iie_ops,
662 },
663 };
664
665 static const struct pci_device_id mv_pci_tbl[] = {
666 { PCI_VDEVICE(MARVELL, 0x5040), chip_504x },
667 { PCI_VDEVICE(MARVELL, 0x5041), chip_504x },
668 { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 },
669 { PCI_VDEVICE(MARVELL, 0x5081), chip_508x },
670 /* RocketRAID 1740/174x have different identifiers */
671 { PCI_VDEVICE(TTI, 0x1740), chip_508x },
672 { PCI_VDEVICE(TTI, 0x1742), chip_508x },
673
674 { PCI_VDEVICE(MARVELL, 0x6040), chip_604x },
675 { PCI_VDEVICE(MARVELL, 0x6041), chip_604x },
676 { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 },
677 { PCI_VDEVICE(MARVELL, 0x6080), chip_608x },
678 { PCI_VDEVICE(MARVELL, 0x6081), chip_608x },
679
680 { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x },
681
682 /* Adaptec 1430SA */
683 { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 },
684
685 /* Marvell 7042 support */
686 { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 },
687
688 /* Highpoint RocketRAID PCIe series */
689 { PCI_VDEVICE(TTI, 0x2300), chip_7042 },
690 { PCI_VDEVICE(TTI, 0x2310), chip_7042 },
691
692 { } /* terminate list */
693 };
694
695 static const struct mv_hw_ops mv5xxx_ops = {
696 .phy_errata = mv5_phy_errata,
697 .enable_leds = mv5_enable_leds,
698 .read_preamp = mv5_read_preamp,
699 .reset_hc = mv5_reset_hc,
700 .reset_flash = mv5_reset_flash,
701 .reset_bus = mv5_reset_bus,
702 };
703
704 static const struct mv_hw_ops mv6xxx_ops = {
705 .phy_errata = mv6_phy_errata,
706 .enable_leds = mv6_enable_leds,
707 .read_preamp = mv6_read_preamp,
708 .reset_hc = mv6_reset_hc,
709 .reset_flash = mv6_reset_flash,
710 .reset_bus = mv_reset_pci_bus,
711 };
712
713 static const struct mv_hw_ops mv_soc_ops = {
714 .phy_errata = mv6_phy_errata,
715 .enable_leds = mv_soc_enable_leds,
716 .read_preamp = mv_soc_read_preamp,
717 .reset_hc = mv_soc_reset_hc,
718 .reset_flash = mv_soc_reset_flash,
719 .reset_bus = mv_soc_reset_bus,
720 };
721
722 /*
723 * Functions
724 */
725
726 static inline void writelfl(unsigned long data, void __iomem *addr)
727 {
728 writel(data, addr);
729 (void) readl(addr); /* flush to avoid PCI posted write */
730 }
731
732 static inline unsigned int mv_hc_from_port(unsigned int port)
733 {
734 return port >> MV_PORT_HC_SHIFT;
735 }
736
737 static inline unsigned int mv_hardport_from_port(unsigned int port)
738 {
739 return port & MV_PORT_MASK;
740 }
741
742 /*
743 * Consolidate some rather tricky bit shift calculations.
744 * This is hot-path stuff, so not a function.
745 * Simple code, with two return values, so macro rather than inline.
746 *
747 * port is the sole input, in range 0..7.
748 * shift is one output, for use with main_irq_cause / main_irq_mask registers.
749 * hardport is the other output, in range 0..3.
750 *
751 * Note that port and hardport may be the same variable in some cases.
752 */
753 #define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \
754 { \
755 shift = mv_hc_from_port(port) * HC_SHIFT; \
756 hardport = mv_hardport_from_port(port); \
757 shift += hardport * 2; \
758 }
759
760 static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
761 {
762 return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
763 }
764
765 static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
766 unsigned int port)
767 {
768 return mv_hc_base(base, mv_hc_from_port(port));
769 }
770
771 static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
772 {
773 return mv_hc_base_from_port(base, port) +
774 MV_SATAHC_ARBTR_REG_SZ +
775 (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
776 }
777
778 static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
779 {
780 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
781 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
782
783 return hc_mmio + ofs;
784 }
785
786 static inline void __iomem *mv_host_base(struct ata_host *host)
787 {
788 struct mv_host_priv *hpriv = host->private_data;
789 return hpriv->base;
790 }
791
792 static inline void __iomem *mv_ap_base(struct ata_port *ap)
793 {
794 return mv_port_base(mv_host_base(ap->host), ap->port_no);
795 }
796
797 static inline int mv_get_hc_count(unsigned long port_flags)
798 {
799 return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
800 }
801
802 static void mv_set_edma_ptrs(void __iomem *port_mmio,
803 struct mv_host_priv *hpriv,
804 struct mv_port_priv *pp)
805 {
806 u32 index;
807
808 /*
809 * initialize request queue
810 */
811 pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
812 index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
813
814 WARN_ON(pp->crqb_dma & 0x3ff);
815 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS);
816 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index,
817 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
818
819 if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0)
820 writelfl((pp->crqb_dma & 0xffffffff) | index,
821 port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
822 else
823 writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
824
825 /*
826 * initialize response queue
827 */
828 pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
829 index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT;
830
831 WARN_ON(pp->crpb_dma & 0xff);
832 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS);
833
834 if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0)
835 writelfl((pp->crpb_dma & 0xffffffff) | index,
836 port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
837 else
838 writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
839
840 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index,
841 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
842 }
843
844 /**
845 * mv_start_dma - Enable eDMA engine
846 * @base: port base address
847 * @pp: port private data
848 *
849 * Verify the local cache of the eDMA state is accurate with a
850 * WARN_ON.
851 *
852 * LOCKING:
853 * Inherited from caller.
854 */
855 static void mv_start_dma(struct ata_port *ap, void __iomem *port_mmio,
856 struct mv_port_priv *pp, u8 protocol)
857 {
858 int want_ncq = (protocol == ATA_PROT_NCQ);
859
860 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
861 int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0);
862 if (want_ncq != using_ncq)
863 mv_stop_edma(ap);
864 }
865 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) {
866 struct mv_host_priv *hpriv = ap->host->private_data;
867 int hardport = mv_hardport_from_port(ap->port_no);
868 void __iomem *hc_mmio = mv_hc_base_from_port(
869 mv_host_base(ap->host), hardport);
870 u32 hc_irq_cause, ipending;
871
872 /* clear EDMA event indicators, if any */
873 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
874
875 /* clear EDMA interrupt indicator, if any */
876 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);
877 ipending = (DEV_IRQ | DMA_IRQ) << hardport;
878 if (hc_irq_cause & ipending) {
879 writelfl(hc_irq_cause & ~ipending,
880 hc_mmio + HC_IRQ_CAUSE_OFS);
881 }
882
883 mv_edma_cfg(ap, want_ncq);
884
885 /* clear FIS IRQ Cause */
886 writelfl(0, port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
887
888 mv_set_edma_ptrs(port_mmio, hpriv, pp);
889
890 writelfl(EDMA_EN, port_mmio + EDMA_CMD_OFS);
891 pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
892 }
893 }
894
895 static void mv_wait_for_edma_empty_idle(struct ata_port *ap)
896 {
897 void __iomem *port_mmio = mv_ap_base(ap);
898 const u32 empty_idle = (EDMA_STATUS_CACHE_EMPTY | EDMA_STATUS_IDLE);
899 const int per_loop = 5, timeout = (15 * 1000 / per_loop);
900 int i;
901
902 /*
903 * Wait for the EDMA engine to finish transactions in progress.
904 */
905 for (i = 0; i < timeout; ++i) {
906 u32 edma_stat = readl(port_mmio + EDMA_STATUS_OFS);
907 if ((edma_stat & empty_idle) == empty_idle)
908 break;
909 udelay(per_loop);
910 }
911 /* ata_port_printk(ap, KERN_INFO, "%s: %u+ usecs\n", __func__, i); */
912 }
913
914 /**
915 * mv_stop_edma_engine - Disable eDMA engine
916 * @port_mmio: io base address
917 *
918 * LOCKING:
919 * Inherited from caller.
920 */
921 static int mv_stop_edma_engine(void __iomem *port_mmio)
922 {
923 int i;
924
925 /* Disable eDMA. The disable bit auto clears. */
926 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
927
928 /* Wait for the chip to confirm eDMA is off. */
929 for (i = 10000; i > 0; i--) {
930 u32 reg = readl(port_mmio + EDMA_CMD_OFS);
931 if (!(reg & EDMA_EN))
932 return 0;
933 udelay(10);
934 }
935 return -EIO;
936 }
937
938 static int mv_stop_edma(struct ata_port *ap)
939 {
940 void __iomem *port_mmio = mv_ap_base(ap);
941 struct mv_port_priv *pp = ap->private_data;
942
943 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
944 return 0;
945 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
946 mv_wait_for_edma_empty_idle(ap);
947 if (mv_stop_edma_engine(port_mmio)) {
948 ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n");
949 return -EIO;
950 }
951 return 0;
952 }
953
954 #ifdef ATA_DEBUG
955 static void mv_dump_mem(void __iomem *start, unsigned bytes)
956 {
957 int b, w;
958 for (b = 0; b < bytes; ) {
959 DPRINTK("%p: ", start + b);
960 for (w = 0; b < bytes && w < 4; w++) {
961 printk("%08x ", readl(start + b));
962 b += sizeof(u32);
963 }
964 printk("\n");
965 }
966 }
967 #endif
968
969 static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
970 {
971 #ifdef ATA_DEBUG
972 int b, w;
973 u32 dw;
974 for (b = 0; b < bytes; ) {
975 DPRINTK("%02x: ", b);
976 for (w = 0; b < bytes && w < 4; w++) {
977 (void) pci_read_config_dword(pdev, b, &dw);
978 printk("%08x ", dw);
979 b += sizeof(u32);
980 }
981 printk("\n");
982 }
983 #endif
984 }
985 static void mv_dump_all_regs(void __iomem *mmio_base, int port,
986 struct pci_dev *pdev)
987 {
988 #ifdef ATA_DEBUG
989 void __iomem *hc_base = mv_hc_base(mmio_base,
990 port >> MV_PORT_HC_SHIFT);
991 void __iomem *port_base;
992 int start_port, num_ports, p, start_hc, num_hcs, hc;
993
994 if (0 > port) {
995 start_hc = start_port = 0;
996 num_ports = 8; /* shld be benign for 4 port devs */
997 num_hcs = 2;
998 } else {
999 start_hc = port >> MV_PORT_HC_SHIFT;
1000 start_port = port;
1001 num_ports = num_hcs = 1;
1002 }
1003 DPRINTK("All registers for port(s) %u-%u:\n", start_port,
1004 num_ports > 1 ? num_ports - 1 : start_port);
1005
1006 if (NULL != pdev) {
1007 DPRINTK("PCI config space regs:\n");
1008 mv_dump_pci_cfg(pdev, 0x68);
1009 }
1010 DPRINTK("PCI regs:\n");
1011 mv_dump_mem(mmio_base+0xc00, 0x3c);
1012 mv_dump_mem(mmio_base+0xd00, 0x34);
1013 mv_dump_mem(mmio_base+0xf00, 0x4);
1014 mv_dump_mem(mmio_base+0x1d00, 0x6c);
1015 for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
1016 hc_base = mv_hc_base(mmio_base, hc);
1017 DPRINTK("HC regs (HC %i):\n", hc);
1018 mv_dump_mem(hc_base, 0x1c);
1019 }
1020 for (p = start_port; p < start_port + num_ports; p++) {
1021 port_base = mv_port_base(mmio_base, p);
1022 DPRINTK("EDMA regs (port %i):\n", p);
1023 mv_dump_mem(port_base, 0x54);
1024 DPRINTK("SATA regs (port %i):\n", p);
1025 mv_dump_mem(port_base+0x300, 0x60);
1026 }
1027 #endif
1028 }
1029
1030 static unsigned int mv_scr_offset(unsigned int sc_reg_in)
1031 {
1032 unsigned int ofs;
1033
1034 switch (sc_reg_in) {
1035 case SCR_STATUS:
1036 case SCR_CONTROL:
1037 case SCR_ERROR:
1038 ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32));
1039 break;
1040 case SCR_ACTIVE:
1041 ofs = SATA_ACTIVE_OFS; /* active is not with the others */
1042 break;
1043 default:
1044 ofs = 0xffffffffU;
1045 break;
1046 }
1047 return ofs;
1048 }
1049
1050 static int mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val)
1051 {
1052 unsigned int ofs = mv_scr_offset(sc_reg_in);
1053
1054 if (ofs != 0xffffffffU) {
1055 *val = readl(mv_ap_base(ap) + ofs);
1056 return 0;
1057 } else
1058 return -EINVAL;
1059 }
1060
1061 static int mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
1062 {
1063 unsigned int ofs = mv_scr_offset(sc_reg_in);
1064
1065 if (ofs != 0xffffffffU) {
1066 writelfl(val, mv_ap_base(ap) + ofs);
1067 return 0;
1068 } else
1069 return -EINVAL;
1070 }
1071
1072 static void mv6_dev_config(struct ata_device *adev)
1073 {
1074 /*
1075 * Deal with Gen-II ("mv6") hardware quirks/restrictions:
1076 *
1077 * Gen-II does not support NCQ over a port multiplier
1078 * (no FIS-based switching).
1079 *
1080 * We don't have hob_nsect when doing NCQ commands on Gen-II.
1081 * See mv_qc_prep() for more info.
1082 */
1083 if (adev->flags & ATA_DFLAG_NCQ) {
1084 if (sata_pmp_attached(adev->link->ap)) {
1085 adev->flags &= ~ATA_DFLAG_NCQ;
1086 ata_dev_printk(adev, KERN_INFO,
1087 "NCQ disabled for command-based switching\n");
1088 } else if (adev->max_sectors > GEN_II_NCQ_MAX_SECTORS) {
1089 adev->max_sectors = GEN_II_NCQ_MAX_SECTORS;
1090 ata_dev_printk(adev, KERN_INFO,
1091 "max_sectors limited to %u for NCQ\n",
1092 adev->max_sectors);
1093 }
1094 }
1095 }
1096
1097 static int mv_qc_defer(struct ata_queued_cmd *qc)
1098 {
1099 struct ata_link *link = qc->dev->link;
1100 struct ata_port *ap = link->ap;
1101 struct mv_port_priv *pp = ap->private_data;
1102
1103 /*
1104 * Don't allow new commands if we're in a delayed EH state
1105 * for NCQ and/or FIS-based switching.
1106 */
1107 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
1108 return ATA_DEFER_PORT;
1109 /*
1110 * If the port is completely idle, then allow the new qc.
1111 */
1112 if (ap->nr_active_links == 0)
1113 return 0;
1114
1115 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
1116 /*
1117 * The port is operating in host queuing mode (EDMA).
1118 * It can accomodate a new qc if the qc protocol
1119 * is compatible with the current host queue mode.
1120 */
1121 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) {
1122 /*
1123 * The host queue (EDMA) is in NCQ mode.
1124 * If the new qc is also an NCQ command,
1125 * then allow the new qc.
1126 */
1127 if (qc->tf.protocol == ATA_PROT_NCQ)
1128 return 0;
1129 } else {
1130 /*
1131 * The host queue (EDMA) is in non-NCQ, DMA mode.
1132 * If the new qc is also a non-NCQ, DMA command,
1133 * then allow the new qc.
1134 */
1135 if (qc->tf.protocol == ATA_PROT_DMA)
1136 return 0;
1137 }
1138 }
1139 return ATA_DEFER_PORT;
1140 }
1141
1142 static void mv_config_fbs(void __iomem *port_mmio, int want_ncq, int want_fbs)
1143 {
1144 u32 new_fiscfg, old_fiscfg;
1145 u32 new_ltmode, old_ltmode;
1146 u32 new_haltcond, old_haltcond;
1147
1148 old_fiscfg = readl(port_mmio + FISCFG_OFS);
1149 old_ltmode = readl(port_mmio + LTMODE_OFS);
1150 old_haltcond = readl(port_mmio + EDMA_HALTCOND_OFS);
1151
1152 new_fiscfg = old_fiscfg & ~(FISCFG_SINGLE_SYNC | FISCFG_WAIT_DEV_ERR);
1153 new_ltmode = old_ltmode & ~LTMODE_BIT8;
1154 new_haltcond = old_haltcond | EDMA_ERR_DEV;
1155
1156 if (want_fbs) {
1157 new_fiscfg = old_fiscfg | FISCFG_SINGLE_SYNC;
1158 new_ltmode = old_ltmode | LTMODE_BIT8;
1159 }
1160
1161 if (new_fiscfg != old_fiscfg)
1162 writelfl(new_fiscfg, port_mmio + FISCFG_OFS);
1163 if (new_ltmode != old_ltmode)
1164 writelfl(new_ltmode, port_mmio + LTMODE_OFS);
1165 if (new_haltcond != old_haltcond)
1166 writelfl(new_haltcond, port_mmio + EDMA_HALTCOND_OFS);
1167 }
1168
1169 static void mv_60x1_errata_sata25(struct ata_port *ap, int want_ncq)
1170 {
1171 struct mv_host_priv *hpriv = ap->host->private_data;
1172 u32 old, new;
1173
1174 /* workaround for 88SX60x1 FEr SATA#25 (part 1) */
1175 old = readl(hpriv->base + MV_GPIO_PORT_CTL_OFS);
1176 if (want_ncq)
1177 new = old | (1 << 22);
1178 else
1179 new = old & ~(1 << 22);
1180 if (new != old)
1181 writel(new, hpriv->base + MV_GPIO_PORT_CTL_OFS);
1182 }
1183
1184 static void mv_edma_cfg(struct ata_port *ap, int want_ncq)
1185 {
1186 u32 cfg;
1187 struct mv_port_priv *pp = ap->private_data;
1188 struct mv_host_priv *hpriv = ap->host->private_data;
1189 void __iomem *port_mmio = mv_ap_base(ap);
1190
1191 /* set up non-NCQ EDMA configuration */
1192 cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */
1193 pp->pp_flags &= ~MV_PP_FLAG_FBS_EN;
1194
1195 if (IS_GEN_I(hpriv))
1196 cfg |= (1 << 8); /* enab config burst size mask */
1197
1198 else if (IS_GEN_II(hpriv)) {
1199 cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN;
1200 mv_60x1_errata_sata25(ap, want_ncq);
1201
1202 } else if (IS_GEN_IIE(hpriv)) {
1203 int want_fbs = sata_pmp_attached(ap);
1204 /*
1205 * Possible future enhancement:
1206 *
1207 * The chip can use FBS with non-NCQ, if we allow it,
1208 * But first we need to have the error handling in place
1209 * for this mode (datasheet section 7.3.15.4.2.3).
1210 * So disallow non-NCQ FBS for now.
1211 */
1212 want_fbs &= want_ncq;
1213
1214 mv_config_fbs(port_mmio, want_ncq, want_fbs);
1215
1216 if (want_fbs) {
1217 pp->pp_flags |= MV_PP_FLAG_FBS_EN;
1218 cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */
1219 }
1220
1221 cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */
1222 cfg |= (1 << 22); /* enab 4-entry host queue cache */
1223 if (HAS_PCI(ap->host))
1224 cfg |= (1 << 18); /* enab early completion */
1225 if (hpriv->hp_flags & MV_HP_CUT_THROUGH)
1226 cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */
1227 }
1228
1229 if (want_ncq) {
1230 cfg |= EDMA_CFG_NCQ;
1231 pp->pp_flags |= MV_PP_FLAG_NCQ_EN;
1232 } else
1233 pp->pp_flags &= ~MV_PP_FLAG_NCQ_EN;
1234
1235 writelfl(cfg, port_mmio + EDMA_CFG_OFS);
1236 }
1237
1238 static void mv_port_free_dma_mem(struct ata_port *ap)
1239 {
1240 struct mv_host_priv *hpriv = ap->host->private_data;
1241 struct mv_port_priv *pp = ap->private_data;
1242 int tag;
1243
1244 if (pp->crqb) {
1245 dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma);
1246 pp->crqb = NULL;
1247 }
1248 if (pp->crpb) {
1249 dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma);
1250 pp->crpb = NULL;
1251 }
1252 /*
1253 * For GEN_I, there's no NCQ, so we have only a single sg_tbl.
1254 * For later hardware, we have one unique sg_tbl per NCQ tag.
1255 */
1256 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1257 if (pp->sg_tbl[tag]) {
1258 if (tag == 0 || !IS_GEN_I(hpriv))
1259 dma_pool_free(hpriv->sg_tbl_pool,
1260 pp->sg_tbl[tag],
1261 pp->sg_tbl_dma[tag]);
1262 pp->sg_tbl[tag] = NULL;
1263 }
1264 }
1265 }
1266
1267 /**
1268 * mv_port_start - Port specific init/start routine.
1269 * @ap: ATA channel to manipulate
1270 *
1271 * Allocate and point to DMA memory, init port private memory,
1272 * zero indices.
1273 *
1274 * LOCKING:
1275 * Inherited from caller.
1276 */
1277 static int mv_port_start(struct ata_port *ap)
1278 {
1279 struct device *dev = ap->host->dev;
1280 struct mv_host_priv *hpriv = ap->host->private_data;
1281 struct mv_port_priv *pp;
1282 int tag;
1283
1284 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1285 if (!pp)
1286 return -ENOMEM;
1287 ap->private_data = pp;
1288
1289 pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma);
1290 if (!pp->crqb)
1291 return -ENOMEM;
1292 memset(pp->crqb, 0, MV_CRQB_Q_SZ);
1293
1294 pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma);
1295 if (!pp->crpb)
1296 goto out_port_free_dma_mem;
1297 memset(pp->crpb, 0, MV_CRPB_Q_SZ);
1298
1299 /*
1300 * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl.
1301 * For later hardware, we need one unique sg_tbl per NCQ tag.
1302 */
1303 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1304 if (tag == 0 || !IS_GEN_I(hpriv)) {
1305 pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool,
1306 GFP_KERNEL, &pp->sg_tbl_dma[tag]);
1307 if (!pp->sg_tbl[tag])
1308 goto out_port_free_dma_mem;
1309 } else {
1310 pp->sg_tbl[tag] = pp->sg_tbl[0];
1311 pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0];
1312 }
1313 }
1314 return 0;
1315
1316 out_port_free_dma_mem:
1317 mv_port_free_dma_mem(ap);
1318 return -ENOMEM;
1319 }
1320
1321 /**
1322 * mv_port_stop - Port specific cleanup/stop routine.
1323 * @ap: ATA channel to manipulate
1324 *
1325 * Stop DMA, cleanup port memory.
1326 *
1327 * LOCKING:
1328 * This routine uses the host lock to protect the DMA stop.
1329 */
1330 static void mv_port_stop(struct ata_port *ap)
1331 {
1332 mv_stop_edma(ap);
1333 mv_port_free_dma_mem(ap);
1334 }
1335
1336 /**
1337 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
1338 * @qc: queued command whose SG list to source from
1339 *
1340 * Populate the SG list and mark the last entry.
1341 *
1342 * LOCKING:
1343 * Inherited from caller.
1344 */
1345 static void mv_fill_sg(struct ata_queued_cmd *qc)
1346 {
1347 struct mv_port_priv *pp = qc->ap->private_data;
1348 struct scatterlist *sg;
1349 struct mv_sg *mv_sg, *last_sg = NULL;
1350 unsigned int si;
1351
1352 mv_sg = pp->sg_tbl[qc->tag];
1353 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1354 dma_addr_t addr = sg_dma_address(sg);
1355 u32 sg_len = sg_dma_len(sg);
1356
1357 while (sg_len) {
1358 u32 offset = addr & 0xffff;
1359 u32 len = sg_len;
1360
1361 if ((offset + sg_len > 0x10000))
1362 len = 0x10000 - offset;
1363
1364 mv_sg->addr = cpu_to_le32(addr & 0xffffffff);
1365 mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
1366 mv_sg->flags_size = cpu_to_le32(len & 0xffff);
1367
1368 sg_len -= len;
1369 addr += len;
1370
1371 last_sg = mv_sg;
1372 mv_sg++;
1373 }
1374 }
1375
1376 if (likely(last_sg))
1377 last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
1378 }
1379
1380 static void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last)
1381 {
1382 u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
1383 (last ? CRQB_CMD_LAST : 0);
1384 *cmdw = cpu_to_le16(tmp);
1385 }
1386
1387 /**
1388 * mv_qc_prep - Host specific command preparation.
1389 * @qc: queued command to prepare
1390 *
1391 * This routine simply redirects to the general purpose routine
1392 * if command is not DMA. Else, it handles prep of the CRQB
1393 * (command request block), does some sanity checking, and calls
1394 * the SG load routine.
1395 *
1396 * LOCKING:
1397 * Inherited from caller.
1398 */
1399 static void mv_qc_prep(struct ata_queued_cmd *qc)
1400 {
1401 struct ata_port *ap = qc->ap;
1402 struct mv_port_priv *pp = ap->private_data;
1403 __le16 *cw;
1404 struct ata_taskfile *tf;
1405 u16 flags = 0;
1406 unsigned in_index;
1407
1408 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1409 (qc->tf.protocol != ATA_PROT_NCQ))
1410 return;
1411
1412 /* Fill in command request block
1413 */
1414 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
1415 flags |= CRQB_FLAG_READ;
1416 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
1417 flags |= qc->tag << CRQB_TAG_SHIFT;
1418 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
1419
1420 /* get current queue index from software */
1421 in_index = pp->req_idx;
1422
1423 pp->crqb[in_index].sg_addr =
1424 cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
1425 pp->crqb[in_index].sg_addr_hi =
1426 cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
1427 pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags);
1428
1429 cw = &pp->crqb[in_index].ata_cmd[0];
1430 tf = &qc->tf;
1431
1432 /* Sadly, the CRQB cannot accomodate all registers--there are
1433 * only 11 bytes...so we must pick and choose required
1434 * registers based on the command. So, we drop feature and
1435 * hob_feature for [RW] DMA commands, but they are needed for
1436 * NCQ. NCQ will drop hob_nsect.
1437 */
1438 switch (tf->command) {
1439 case ATA_CMD_READ:
1440 case ATA_CMD_READ_EXT:
1441 case ATA_CMD_WRITE:
1442 case ATA_CMD_WRITE_EXT:
1443 case ATA_CMD_WRITE_FUA_EXT:
1444 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
1445 break;
1446 case ATA_CMD_FPDMA_READ:
1447 case ATA_CMD_FPDMA_WRITE:
1448 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
1449 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
1450 break;
1451 default:
1452 /* The only other commands EDMA supports in non-queued and
1453 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
1454 * of which are defined/used by Linux. If we get here, this
1455 * driver needs work.
1456 *
1457 * FIXME: modify libata to give qc_prep a return value and
1458 * return error here.
1459 */
1460 BUG_ON(tf->command);
1461 break;
1462 }
1463 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
1464 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
1465 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
1466 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
1467 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
1468 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
1469 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
1470 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
1471 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
1472
1473 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
1474 return;
1475 mv_fill_sg(qc);
1476 }
1477
1478 /**
1479 * mv_qc_prep_iie - Host specific command preparation.
1480 * @qc: queued command to prepare
1481 *
1482 * This routine simply redirects to the general purpose routine
1483 * if command is not DMA. Else, it handles prep of the CRQB
1484 * (command request block), does some sanity checking, and calls
1485 * the SG load routine.
1486 *
1487 * LOCKING:
1488 * Inherited from caller.
1489 */
1490 static void mv_qc_prep_iie(struct ata_queued_cmd *qc)
1491 {
1492 struct ata_port *ap = qc->ap;
1493 struct mv_port_priv *pp = ap->private_data;
1494 struct mv_crqb_iie *crqb;
1495 struct ata_taskfile *tf;
1496 unsigned in_index;
1497 u32 flags = 0;
1498
1499 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1500 (qc->tf.protocol != ATA_PROT_NCQ))
1501 return;
1502
1503 /* Fill in Gen IIE command request block */
1504 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
1505 flags |= CRQB_FLAG_READ;
1506
1507 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
1508 flags |= qc->tag << CRQB_TAG_SHIFT;
1509 flags |= qc->tag << CRQB_HOSTQ_SHIFT;
1510 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
1511
1512 /* get current queue index from software */
1513 in_index = pp->req_idx;
1514
1515 crqb = (struct mv_crqb_iie *) &pp->crqb[in_index];
1516 crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
1517 crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
1518 crqb->flags = cpu_to_le32(flags);
1519
1520 tf = &qc->tf;
1521 crqb->ata_cmd[0] = cpu_to_le32(
1522 (tf->command << 16) |
1523 (tf->feature << 24)
1524 );
1525 crqb->ata_cmd[1] = cpu_to_le32(
1526 (tf->lbal << 0) |
1527 (tf->lbam << 8) |
1528 (tf->lbah << 16) |
1529 (tf->device << 24)
1530 );
1531 crqb->ata_cmd[2] = cpu_to_le32(
1532 (tf->hob_lbal << 0) |
1533 (tf->hob_lbam << 8) |
1534 (tf->hob_lbah << 16) |
1535 (tf->hob_feature << 24)
1536 );
1537 crqb->ata_cmd[3] = cpu_to_le32(
1538 (tf->nsect << 0) |
1539 (tf->hob_nsect << 8)
1540 );
1541
1542 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
1543 return;
1544 mv_fill_sg(qc);
1545 }
1546
1547 /**
1548 * mv_qc_issue - Initiate a command to the host
1549 * @qc: queued command to start
1550 *
1551 * This routine simply redirects to the general purpose routine
1552 * if command is not DMA. Else, it sanity checks our local
1553 * caches of the request producer/consumer indices then enables
1554 * DMA and bumps the request producer index.
1555 *
1556 * LOCKING:
1557 * Inherited from caller.
1558 */
1559 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
1560 {
1561 struct ata_port *ap = qc->ap;
1562 void __iomem *port_mmio = mv_ap_base(ap);
1563 struct mv_port_priv *pp = ap->private_data;
1564 u32 in_index;
1565
1566 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1567 (qc->tf.protocol != ATA_PROT_NCQ)) {
1568 /*
1569 * We're about to send a non-EDMA capable command to the
1570 * port. Turn off EDMA so there won't be problems accessing
1571 * shadow block, etc registers.
1572 */
1573 mv_stop_edma(ap);
1574 mv_pmp_select(ap, qc->dev->link->pmp);
1575 return ata_sff_qc_issue(qc);
1576 }
1577
1578 mv_start_dma(ap, port_mmio, pp, qc->tf.protocol);
1579
1580 pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK;
1581 in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
1582
1583 /* and write the request in pointer to kick the EDMA to life */
1584 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index,
1585 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
1586
1587 return 0;
1588 }
1589
1590 static struct ata_queued_cmd *mv_get_active_qc(struct ata_port *ap)
1591 {
1592 struct mv_port_priv *pp = ap->private_data;
1593 struct ata_queued_cmd *qc;
1594
1595 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
1596 return NULL;
1597 qc = ata_qc_from_tag(ap, ap->link.active_tag);
1598 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
1599 qc = NULL;
1600 return qc;
1601 }
1602
1603 static void mv_pmp_error_handler(struct ata_port *ap)
1604 {
1605 unsigned int pmp, pmp_map;
1606 struct mv_port_priv *pp = ap->private_data;
1607
1608 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) {
1609 /*
1610 * Perform NCQ error analysis on failed PMPs
1611 * before we freeze the port entirely.
1612 *
1613 * The failed PMPs are marked earlier by mv_pmp_eh_prep().
1614 */
1615 pmp_map = pp->delayed_eh_pmp_map;
1616 pp->pp_flags &= ~MV_PP_FLAG_DELAYED_EH;
1617 for (pmp = 0; pmp_map != 0; pmp++) {
1618 unsigned int this_pmp = (1 << pmp);
1619 if (pmp_map & this_pmp) {
1620 struct ata_link *link = &ap->pmp_link[pmp];
1621 pmp_map &= ~this_pmp;
1622 ata_eh_analyze_ncq_error(link);
1623 }
1624 }
1625 ata_port_freeze(ap);
1626 }
1627 sata_pmp_error_handler(ap);
1628 }
1629
1630 static void mv_unexpected_intr(struct ata_port *ap, int edma_was_enabled)
1631 {
1632 struct ata_eh_info *ehi = &ap->link.eh_info;
1633 char *when = "idle";
1634
1635 ata_ehi_clear_desc(ehi);
1636 if (!ap || (ap->flags & ATA_FLAG_DISABLED)) {
1637 when = "disabled";
1638 } else if (edma_was_enabled) {
1639 when = "EDMA enabled";
1640 } else {
1641 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
1642 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
1643 when = "polling";
1644 }
1645 ata_ehi_push_desc(ehi, "unexpected device interrupt while %s", when);
1646 ehi->err_mask |= AC_ERR_OTHER;
1647 ehi->action |= ATA_EH_RESET;
1648 ata_port_freeze(ap);
1649 }
1650
1651 /**
1652 * mv_err_intr - Handle error interrupts on the port
1653 * @ap: ATA channel to manipulate
1654 * @qc: affected command (non-NCQ), or NULL
1655 *
1656 * Most cases require a full reset of the chip's state machine,
1657 * which also performs a COMRESET.
1658 * Also, if the port disabled DMA, update our cached copy to match.
1659 *
1660 * LOCKING:
1661 * Inherited from caller.
1662 */
1663 static void mv_err_intr(struct ata_port *ap)
1664 {
1665 void __iomem *port_mmio = mv_ap_base(ap);
1666 u32 edma_err_cause, eh_freeze_mask, serr = 0;
1667 struct mv_port_priv *pp = ap->private_data;
1668 struct mv_host_priv *hpriv = ap->host->private_data;
1669 unsigned int action = 0, err_mask = 0;
1670 struct ata_eh_info *ehi = &ap->link.eh_info;
1671 struct ata_queued_cmd *qc;
1672 int abort = 0;
1673
1674 /*
1675 * Read and clear the SError and err_cause bits.
1676 */
1677 sata_scr_read(&ap->link, SCR_ERROR, &serr);
1678 sata_scr_write_flush(&ap->link, SCR_ERROR, serr);
1679
1680 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1681 writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1682
1683 ata_port_printk(ap, KERN_INFO, "%s: err_cause=%08x pp_flags=0x%x\n",
1684 __func__, edma_err_cause, pp->pp_flags);
1685
1686 qc = mv_get_active_qc(ap);
1687 ata_ehi_clear_desc(ehi);
1688 ata_ehi_push_desc(ehi, "edma_err_cause=%08x pp_flags=%08x",
1689 edma_err_cause, pp->pp_flags);
1690 /*
1691 * All generations share these EDMA error cause bits:
1692 */
1693 if (edma_err_cause & EDMA_ERR_DEV) {
1694 err_mask |= AC_ERR_DEV;
1695 action |= ATA_EH_RESET;
1696 ata_ehi_push_desc(ehi, "dev error");
1697 }
1698 if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
1699 EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR |
1700 EDMA_ERR_INTRL_PAR)) {
1701 err_mask |= AC_ERR_ATA_BUS;
1702 action |= ATA_EH_RESET;
1703 ata_ehi_push_desc(ehi, "parity error");
1704 }
1705 if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) {
1706 ata_ehi_hotplugged(ehi);
1707 ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ?
1708 "dev disconnect" : "dev connect");
1709 action |= ATA_EH_RESET;
1710 }
1711
1712 /*
1713 * Gen-I has a different SELF_DIS bit,
1714 * different FREEZE bits, and no SERR bit:
1715 */
1716 if (IS_GEN_I(hpriv)) {
1717 eh_freeze_mask = EDMA_EH_FREEZE_5;
1718 if (edma_err_cause & EDMA_ERR_SELF_DIS_5) {
1719 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
1720 ata_ehi_push_desc(ehi, "EDMA self-disable");
1721 }
1722 } else {
1723 eh_freeze_mask = EDMA_EH_FREEZE;
1724 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
1725 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
1726 ata_ehi_push_desc(ehi, "EDMA self-disable");
1727 }
1728 if (edma_err_cause & EDMA_ERR_SERR) {
1729 ata_ehi_push_desc(ehi, "SError=%08x", serr);
1730 err_mask |= AC_ERR_ATA_BUS;
1731 action |= ATA_EH_RESET;
1732 }
1733 }
1734
1735 if (!err_mask) {
1736 err_mask = AC_ERR_OTHER;
1737 action |= ATA_EH_RESET;
1738 }
1739
1740 ehi->serror |= serr;
1741 ehi->action |= action;
1742
1743 if (qc)
1744 qc->err_mask |= err_mask;
1745 else
1746 ehi->err_mask |= err_mask;
1747
1748 if (err_mask == AC_ERR_DEV) {
1749 /*
1750 * Cannot do ata_port_freeze() here,
1751 * because it would kill PIO access,
1752 * which is needed for further diagnosis.
1753 */
1754 mv_eh_freeze(ap);
1755 abort = 1;
1756 } else if (edma_err_cause & eh_freeze_mask) {
1757 /*
1758 * Note to self: ata_port_freeze() calls ata_port_abort()
1759 */
1760 ata_port_freeze(ap);
1761 } else {
1762 abort = 1;
1763 }
1764
1765 if (abort) {
1766 if (qc)
1767 ata_link_abort(qc->dev->link);
1768 else
1769 ata_port_abort(ap);
1770 }
1771 }
1772
1773 static void mv_process_crpb_response(struct ata_port *ap,
1774 struct mv_crpb *response, unsigned int tag, int ncq_enabled)
1775 {
1776 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, tag);
1777
1778 if (qc) {
1779 u8 ata_status;
1780 u16 edma_status = le16_to_cpu(response->flags);
1781 /*
1782 * edma_status from a response queue entry:
1783 * LSB is from EDMA_ERR_IRQ_CAUSE_OFS (non-NCQ only).
1784 * MSB is saved ATA status from command completion.
1785 */
1786 if (!ncq_enabled) {
1787 u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV;
1788 if (err_cause) {
1789 /*
1790 * Error will be seen/handled by mv_err_intr().
1791 * So do nothing at all here.
1792 */
1793 return;
1794 }
1795 }
1796 ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT;
1797 if (!ac_err_mask(ata_status))
1798 ata_qc_complete(qc);
1799 /* else: leave it for mv_err_intr() */
1800 } else {
1801 ata_port_printk(ap, KERN_ERR, "%s: no qc for tag=%d\n",
1802 __func__, tag);
1803 }
1804 }
1805
1806 static void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp)
1807 {
1808 void __iomem *port_mmio = mv_ap_base(ap);
1809 struct mv_host_priv *hpriv = ap->host->private_data;
1810 u32 in_index;
1811 bool work_done = false;
1812 int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN);
1813
1814 /* Get the hardware queue position index */
1815 in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS)
1816 >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1817
1818 /* Process new responses from since the last time we looked */
1819 while (in_index != pp->resp_idx) {
1820 unsigned int tag;
1821 struct mv_crpb *response = &pp->crpb[pp->resp_idx];
1822
1823 pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK;
1824
1825 if (IS_GEN_I(hpriv)) {
1826 /* 50xx: no NCQ, only one command active at a time */
1827 tag = ap->link.active_tag;
1828 } else {
1829 /* Gen II/IIE: get command tag from CRPB entry */
1830 tag = le16_to_cpu(response->id) & 0x1f;
1831 }
1832 mv_process_crpb_response(ap, response, tag, ncq_enabled);
1833 work_done = true;
1834 }
1835
1836 /* Update the software queue position index in hardware */
1837 if (work_done)
1838 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) |
1839 (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT),
1840 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
1841 }
1842
1843 static void mv_port_intr(struct ata_port *ap, u32 port_cause)
1844 {
1845 struct mv_port_priv *pp;
1846 int edma_was_enabled;
1847
1848 if (!ap || (ap->flags & ATA_FLAG_DISABLED)) {
1849 mv_unexpected_intr(ap, 0);
1850 return;
1851 }
1852 /*
1853 * Grab a snapshot of the EDMA_EN flag setting,
1854 * so that we have a consistent view for this port,
1855 * even if something we call of our routines changes it.
1856 */
1857 pp = ap->private_data;
1858 edma_was_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN);
1859 /*
1860 * Process completed CRPB response(s) before other events.
1861 */
1862 if (edma_was_enabled && (port_cause & DONE_IRQ)) {
1863 mv_process_crpb_entries(ap, pp);
1864 }
1865 /*
1866 * Handle chip-reported errors, or continue on to handle PIO.
1867 */
1868 if (unlikely(port_cause & ERR_IRQ)) {
1869 mv_err_intr(ap);
1870 } else if (!edma_was_enabled) {
1871 struct ata_queued_cmd *qc = mv_get_active_qc(ap);
1872 if (qc)
1873 ata_sff_host_intr(ap, qc);
1874 else
1875 mv_unexpected_intr(ap, edma_was_enabled);
1876 }
1877 }
1878
1879 /**
1880 * mv_host_intr - Handle all interrupts on the given host controller
1881 * @host: host specific structure
1882 * @main_irq_cause: Main interrupt cause register for the chip.
1883 *
1884 * LOCKING:
1885 * Inherited from caller.
1886 */
1887 static int mv_host_intr(struct ata_host *host, u32 main_irq_cause)
1888 {
1889 struct mv_host_priv *hpriv = host->private_data;
1890 void __iomem *mmio = hpriv->base, *hc_mmio;
1891 unsigned int handled = 0, port;
1892
1893 for (port = 0; port < hpriv->n_ports; port++) {
1894 struct ata_port *ap = host->ports[port];
1895 unsigned int p, shift, hardport, port_cause;
1896
1897 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
1898 /*
1899 * Each hc within the host has its own hc_irq_cause register,
1900 * where the interrupting ports bits get ack'd.
1901 */
1902 if (hardport == 0) { /* first port on this hc ? */
1903 u32 hc_cause = (main_irq_cause >> shift) & HC0_IRQ_PEND;
1904 u32 port_mask, ack_irqs;
1905 /*
1906 * Skip this entire hc if nothing pending for any ports
1907 */
1908 if (!hc_cause) {
1909 port += MV_PORTS_PER_HC - 1;
1910 continue;
1911 }
1912 /*
1913 * We don't need/want to read the hc_irq_cause register,
1914 * because doing so hurts performance, and
1915 * main_irq_cause already gives us everything we need.
1916 *
1917 * But we do have to *write* to the hc_irq_cause to ack
1918 * the ports that we are handling this time through.
1919 *
1920 * This requires that we create a bitmap for those
1921 * ports which interrupted us, and use that bitmap
1922 * to ack (only) those ports via hc_irq_cause.
1923 */
1924 ack_irqs = 0;
1925 for (p = 0; p < MV_PORTS_PER_HC; ++p) {
1926 if ((port + p) >= hpriv->n_ports)
1927 break;
1928 port_mask = (DONE_IRQ | ERR_IRQ) << (p * 2);
1929 if (hc_cause & port_mask)
1930 ack_irqs |= (DMA_IRQ | DEV_IRQ) << p;
1931 }
1932 hc_mmio = mv_hc_base_from_port(mmio, port);
1933 writelfl(~ack_irqs, hc_mmio + HC_IRQ_CAUSE_OFS);
1934 handled = 1;
1935 }
1936 /*
1937 * Handle interrupts signalled for this port:
1938 */
1939 port_cause = (main_irq_cause >> shift) & (DONE_IRQ | ERR_IRQ);
1940 if (port_cause)
1941 mv_port_intr(ap, port_cause);
1942 }
1943 return handled;
1944 }
1945
1946 static int mv_pci_error(struct ata_host *host, void __iomem *mmio)
1947 {
1948 struct mv_host_priv *hpriv = host->private_data;
1949 struct ata_port *ap;
1950 struct ata_queued_cmd *qc;
1951 struct ata_eh_info *ehi;
1952 unsigned int i, err_mask, printed = 0;
1953 u32 err_cause;
1954
1955 err_cause = readl(mmio + hpriv->irq_cause_ofs);
1956
1957 dev_printk(KERN_ERR, host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n",
1958 err_cause);
1959
1960 DPRINTK("All regs @ PCI error\n");
1961 mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev));
1962
1963 writelfl(0, mmio + hpriv->irq_cause_ofs);
1964
1965 for (i = 0; i < host->n_ports; i++) {
1966 ap = host->ports[i];
1967 if (!ata_link_offline(&ap->link)) {
1968 ehi = &ap->link.eh_info;
1969 ata_ehi_clear_desc(ehi);
1970 if (!printed++)
1971 ata_ehi_push_desc(ehi,
1972 "PCI err cause 0x%08x", err_cause);
1973 err_mask = AC_ERR_HOST_BUS;
1974 ehi->action = ATA_EH_RESET;
1975 qc = ata_qc_from_tag(ap, ap->link.active_tag);
1976 if (qc)
1977 qc->err_mask |= err_mask;
1978 else
1979 ehi->err_mask |= err_mask;
1980
1981 ata_port_freeze(ap);
1982 }
1983 }
1984 return 1; /* handled */
1985 }
1986
1987 /**
1988 * mv_interrupt - Main interrupt event handler
1989 * @irq: unused
1990 * @dev_instance: private data; in this case the host structure
1991 *
1992 * Read the read only register to determine if any host
1993 * controllers have pending interrupts. If so, call lower level
1994 * routine to handle. Also check for PCI errors which are only
1995 * reported here.
1996 *
1997 * LOCKING:
1998 * This routine holds the host lock while processing pending
1999 * interrupts.
2000 */
2001 static irqreturn_t mv_interrupt(int irq, void *dev_instance)
2002 {
2003 struct ata_host *host = dev_instance;
2004 struct mv_host_priv *hpriv = host->private_data;
2005 unsigned int handled = 0;
2006 u32 main_irq_cause, main_irq_mask;
2007
2008 spin_lock(&host->lock);
2009 main_irq_cause = readl(hpriv->main_irq_cause_addr);
2010 main_irq_mask = readl(hpriv->main_irq_mask_addr);
2011 /*
2012 * Deal with cases where we either have nothing pending, or have read
2013 * a bogus register value which can indicate HW removal or PCI fault.
2014 */
2015 if ((main_irq_cause & main_irq_mask) && (main_irq_cause != 0xffffffffU)) {
2016 if (unlikely((main_irq_cause & PCI_ERR) && HAS_PCI(host)))
2017 handled = mv_pci_error(host, hpriv->base);
2018 else
2019 handled = mv_host_intr(host, main_irq_cause);
2020 }
2021 spin_unlock(&host->lock);
2022 return IRQ_RETVAL(handled);
2023 }
2024
2025 static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
2026 {
2027 unsigned int ofs;
2028
2029 switch (sc_reg_in) {
2030 case SCR_STATUS:
2031 case SCR_ERROR:
2032 case SCR_CONTROL:
2033 ofs = sc_reg_in * sizeof(u32);
2034 break;
2035 default:
2036 ofs = 0xffffffffU;
2037 break;
2038 }
2039 return ofs;
2040 }
2041
2042 static int mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val)
2043 {
2044 struct mv_host_priv *hpriv = ap->host->private_data;
2045 void __iomem *mmio = hpriv->base;
2046 void __iomem *addr = mv5_phy_base(mmio, ap->port_no);
2047 unsigned int ofs = mv5_scr_offset(sc_reg_in);
2048
2049 if (ofs != 0xffffffffU) {
2050 *val = readl(addr + ofs);
2051 return 0;
2052 } else
2053 return -EINVAL;
2054 }
2055
2056 static int mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
2057 {
2058 struct mv_host_priv *hpriv = ap->host->private_data;
2059 void __iomem *mmio = hpriv->base;
2060 void __iomem *addr = mv5_phy_base(mmio, ap->port_no);
2061 unsigned int ofs = mv5_scr_offset(sc_reg_in);
2062
2063 if (ofs != 0xffffffffU) {
2064 writelfl(val, addr + ofs);
2065 return 0;
2066 } else
2067 return -EINVAL;
2068 }
2069
2070 static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio)
2071 {
2072 struct pci_dev *pdev = to_pci_dev(host->dev);
2073 int early_5080;
2074
2075 early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0);
2076
2077 if (!early_5080) {
2078 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
2079 tmp |= (1 << 0);
2080 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
2081 }
2082
2083 mv_reset_pci_bus(host, mmio);
2084 }
2085
2086 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
2087 {
2088 writel(0x0fcfffff, mmio + MV_FLASH_CTL_OFS);
2089 }
2090
2091 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
2092 void __iomem *mmio)
2093 {
2094 void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
2095 u32 tmp;
2096
2097 tmp = readl(phy_mmio + MV5_PHY_MODE);
2098
2099 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
2100 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
2101 }
2102
2103 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
2104 {
2105 u32 tmp;
2106
2107 writel(0, mmio + MV_GPIO_PORT_CTL_OFS);
2108
2109 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
2110
2111 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
2112 tmp |= ~(1 << 0);
2113 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
2114 }
2115
2116 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
2117 unsigned int port)
2118 {
2119 void __iomem *phy_mmio = mv5_phy_base(mmio, port);
2120 const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
2121 u32 tmp;
2122 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
2123
2124 if (fix_apm_sq) {
2125 tmp = readl(phy_mmio + MV5_LTMODE_OFS);
2126 tmp |= (1 << 19);
2127 writel(tmp, phy_mmio + MV5_LTMODE_OFS);
2128
2129 tmp = readl(phy_mmio + MV5_PHY_CTL_OFS);
2130 tmp &= ~0x3;
2131 tmp |= 0x1;
2132 writel(tmp, phy_mmio + MV5_PHY_CTL_OFS);
2133 }
2134
2135 tmp = readl(phy_mmio + MV5_PHY_MODE);
2136 tmp &= ~mask;
2137 tmp |= hpriv->signal[port].pre;
2138 tmp |= hpriv->signal[port].amps;
2139 writel(tmp, phy_mmio + MV5_PHY_MODE);
2140 }
2141
2142
2143 #undef ZERO
2144 #define ZERO(reg) writel(0, port_mmio + (reg))
2145 static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
2146 unsigned int port)
2147 {
2148 void __iomem *port_mmio = mv_port_base(mmio, port);
2149
2150 mv_reset_channel(hpriv, mmio, port);
2151
2152 ZERO(0x028); /* command */
2153 writel(0x11f, port_mmio + EDMA_CFG_OFS);
2154 ZERO(0x004); /* timer */
2155 ZERO(0x008); /* irq err cause */
2156 ZERO(0x00c); /* irq err mask */
2157 ZERO(0x010); /* rq bah */
2158 ZERO(0x014); /* rq inp */
2159 ZERO(0x018); /* rq outp */
2160 ZERO(0x01c); /* respq bah */
2161 ZERO(0x024); /* respq outp */
2162 ZERO(0x020); /* respq inp */
2163 ZERO(0x02c); /* test control */
2164 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS);
2165 }
2166 #undef ZERO
2167
2168 #define ZERO(reg) writel(0, hc_mmio + (reg))
2169 static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2170 unsigned int hc)
2171 {
2172 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
2173 u32 tmp;
2174
2175 ZERO(0x00c);
2176 ZERO(0x010);
2177 ZERO(0x014);
2178 ZERO(0x018);
2179
2180 tmp = readl(hc_mmio + 0x20);
2181 tmp &= 0x1c1c1c1c;
2182 tmp |= 0x03030303;
2183 writel(tmp, hc_mmio + 0x20);
2184 }
2185 #undef ZERO
2186
2187 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2188 unsigned int n_hc)
2189 {
2190 unsigned int hc, port;
2191
2192 for (hc = 0; hc < n_hc; hc++) {
2193 for (port = 0; port < MV_PORTS_PER_HC; port++)
2194 mv5_reset_hc_port(hpriv, mmio,
2195 (hc * MV_PORTS_PER_HC) + port);
2196
2197 mv5_reset_one_hc(hpriv, mmio, hc);
2198 }
2199
2200 return 0;
2201 }
2202
2203 #undef ZERO
2204 #define ZERO(reg) writel(0, mmio + (reg))
2205 static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio)
2206 {
2207 struct mv_host_priv *hpriv = host->private_data;
2208 u32 tmp;
2209
2210 tmp = readl(mmio + MV_PCI_MODE_OFS);
2211 tmp &= 0xff00ffff;
2212 writel(tmp, mmio + MV_PCI_MODE_OFS);
2213
2214 ZERO(MV_PCI_DISC_TIMER);
2215 ZERO(MV_PCI_MSI_TRIGGER);
2216 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT_OFS);
2217 ZERO(PCI_HC_MAIN_IRQ_MASK_OFS);
2218 ZERO(MV_PCI_SERR_MASK);
2219 ZERO(hpriv->irq_cause_ofs);
2220 ZERO(hpriv->irq_mask_ofs);
2221 ZERO(MV_PCI_ERR_LOW_ADDRESS);
2222 ZERO(MV_PCI_ERR_HIGH_ADDRESS);
2223 ZERO(MV_PCI_ERR_ATTRIBUTE);
2224 ZERO(MV_PCI_ERR_COMMAND);
2225 }
2226 #undef ZERO
2227
2228 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
2229 {
2230 u32 tmp;
2231
2232 mv5_reset_flash(hpriv, mmio);
2233
2234 tmp = readl(mmio + MV_GPIO_PORT_CTL_OFS);
2235 tmp &= 0x3;
2236 tmp |= (1 << 5) | (1 << 6);
2237 writel(tmp, mmio + MV_GPIO_PORT_CTL_OFS);
2238 }
2239
2240 /**
2241 * mv6_reset_hc - Perform the 6xxx global soft reset
2242 * @mmio: base address of the HBA
2243 *
2244 * This routine only applies to 6xxx parts.
2245 *
2246 * LOCKING:
2247 * Inherited from caller.
2248 */
2249 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2250 unsigned int n_hc)
2251 {
2252 void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS;
2253 int i, rc = 0;
2254 u32 t;
2255
2256 /* Following procedure defined in PCI "main command and status
2257 * register" table.
2258 */
2259 t = readl(reg);
2260 writel(t | STOP_PCI_MASTER, reg);
2261
2262 for (i = 0; i < 1000; i++) {
2263 udelay(1);
2264 t = readl(reg);
2265 if (PCI_MASTER_EMPTY & t)
2266 break;
2267 }
2268 if (!(PCI_MASTER_EMPTY & t)) {
2269 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
2270 rc = 1;
2271 goto done;
2272 }
2273
2274 /* set reset */
2275 i = 5;
2276 do {
2277 writel(t | GLOB_SFT_RST, reg);
2278 t = readl(reg);
2279 udelay(1);
2280 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
2281
2282 if (!(GLOB_SFT_RST & t)) {
2283 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
2284 rc = 1;
2285 goto done;
2286 }
2287
2288 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
2289 i = 5;
2290 do {
2291 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
2292 t = readl(reg);
2293 udelay(1);
2294 } while ((GLOB_SFT_RST & t) && (i-- > 0));
2295
2296 if (GLOB_SFT_RST & t) {
2297 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
2298 rc = 1;
2299 }
2300 done:
2301 return rc;
2302 }
2303
2304 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
2305 void __iomem *mmio)
2306 {
2307 void __iomem *port_mmio;
2308 u32 tmp;
2309
2310 tmp = readl(mmio + MV_RESET_CFG_OFS);
2311 if ((tmp & (1 << 0)) == 0) {
2312 hpriv->signal[idx].amps = 0x7 << 8;
2313 hpriv->signal[idx].pre = 0x1 << 5;
2314 return;
2315 }
2316
2317 port_mmio = mv_port_base(mmio, idx);
2318 tmp = readl(port_mmio + PHY_MODE2);
2319
2320 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
2321 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
2322 }
2323
2324 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
2325 {
2326 writel(0x00000060, mmio + MV_GPIO_PORT_CTL_OFS);
2327 }
2328
2329 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
2330 unsigned int port)
2331 {
2332 void __iomem *port_mmio = mv_port_base(mmio, port);
2333
2334 u32 hp_flags = hpriv->hp_flags;
2335 int fix_phy_mode2 =
2336 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
2337 int fix_phy_mode4 =
2338 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
2339 u32 m2, tmp;
2340
2341 if (fix_phy_mode2) {
2342 m2 = readl(port_mmio + PHY_MODE2);
2343 m2 &= ~(1 << 16);
2344 m2 |= (1 << 31);
2345 writel(m2, port_mmio + PHY_MODE2);
2346
2347 udelay(200);
2348
2349 m2 = readl(port_mmio + PHY_MODE2);
2350 m2 &= ~((1 << 16) | (1 << 31));
2351 writel(m2, port_mmio + PHY_MODE2);
2352
2353 udelay(200);
2354 }
2355
2356 /* who knows what this magic does */
2357 tmp = readl(port_mmio + PHY_MODE3);
2358 tmp &= ~0x7F800000;
2359 tmp |= 0x2A800000;
2360 writel(tmp, port_mmio + PHY_MODE3);
2361
2362 if (fix_phy_mode4) {
2363 u32 m4;
2364
2365 m4 = readl(port_mmio + PHY_MODE4);
2366
2367 if (hp_flags & MV_HP_ERRATA_60X1B2)
2368 tmp = readl(port_mmio + PHY_MODE3);
2369
2370 /* workaround for errata FEr SATA#10 (part 1) */
2371 m4 = (m4 & ~(1 << 1)) | (1 << 0);
2372
2373 writel(m4, port_mmio + PHY_MODE4);
2374
2375 if (hp_flags & MV_HP_ERRATA_60X1B2)
2376 writel(tmp, port_mmio + PHY_MODE3);
2377 }
2378
2379 /* Revert values of pre-emphasis and signal amps to the saved ones */
2380 m2 = readl(port_mmio + PHY_MODE2);
2381
2382 m2 &= ~MV_M2_PREAMP_MASK;
2383 m2 |= hpriv->signal[port].amps;
2384 m2 |= hpriv->signal[port].pre;
2385 m2 &= ~(1 << 16);
2386
2387 /* according to mvSata 3.6.1, some IIE values are fixed */
2388 if (IS_GEN_IIE(hpriv)) {
2389 m2 &= ~0xC30FF01F;
2390 m2 |= 0x0000900F;
2391 }
2392
2393 writel(m2, port_mmio + PHY_MODE2);
2394 }
2395
2396 /* TODO: use the generic LED interface to configure the SATA Presence */
2397 /* & Acitivy LEDs on the board */
2398 static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
2399 void __iomem *mmio)
2400 {
2401 return;
2402 }
2403
2404 static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
2405 void __iomem *mmio)
2406 {
2407 void __iomem *port_mmio;
2408 u32 tmp;
2409
2410 port_mmio = mv_port_base(mmio, idx);
2411 tmp = readl(port_mmio + PHY_MODE2);
2412
2413 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
2414 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
2415 }
2416
2417 #undef ZERO
2418 #define ZERO(reg) writel(0, port_mmio + (reg))
2419 static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv,
2420 void __iomem *mmio, unsigned int port)
2421 {
2422 void __iomem *port_mmio = mv_port_base(mmio, port);
2423
2424 mv_reset_channel(hpriv, mmio, port);
2425
2426 ZERO(0x028); /* command */
2427 writel(0x101f, port_mmio + EDMA_CFG_OFS);
2428 ZERO(0x004); /* timer */
2429 ZERO(0x008); /* irq err cause */
2430 ZERO(0x00c); /* irq err mask */
2431 ZERO(0x010); /* rq bah */
2432 ZERO(0x014); /* rq inp */
2433 ZERO(0x018); /* rq outp */
2434 ZERO(0x01c); /* respq bah */
2435 ZERO(0x024); /* respq outp */
2436 ZERO(0x020); /* respq inp */
2437 ZERO(0x02c); /* test control */
2438 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS);
2439 }
2440
2441 #undef ZERO
2442
2443 #define ZERO(reg) writel(0, hc_mmio + (reg))
2444 static void mv_soc_reset_one_hc(struct mv_host_priv *hpriv,
2445 void __iomem *mmio)
2446 {
2447 void __iomem *hc_mmio = mv_hc_base(mmio, 0);
2448
2449 ZERO(0x00c);
2450 ZERO(0x010);
2451 ZERO(0x014);
2452
2453 }
2454
2455 #undef ZERO
2456
2457 static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
2458 void __iomem *mmio, unsigned int n_hc)
2459 {
2460 unsigned int port;
2461
2462 for (port = 0; port < hpriv->n_ports; port++)
2463 mv_soc_reset_hc_port(hpriv, mmio, port);
2464
2465 mv_soc_reset_one_hc(hpriv, mmio);
2466
2467 return 0;
2468 }
2469
2470 static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
2471 void __iomem *mmio)
2472 {
2473 return;
2474 }
2475
2476 static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio)
2477 {
2478 return;
2479 }
2480
2481 static void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i)
2482 {
2483 u32 ifcfg = readl(port_mmio + SATA_INTERFACE_CFG_OFS);
2484
2485 ifcfg = (ifcfg & 0xf7f) | 0x9b1000; /* from chip spec */
2486 if (want_gen2i)
2487 ifcfg |= (1 << 7); /* enable gen2i speed */
2488 writelfl(ifcfg, port_mmio + SATA_INTERFACE_CFG_OFS);
2489 }
2490
2491 static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
2492 unsigned int port_no)
2493 {
2494 void __iomem *port_mmio = mv_port_base(mmio, port_no);
2495
2496 /*
2497 * The datasheet warns against setting EDMA_RESET when EDMA is active
2498 * (but doesn't say what the problem might be). So we first try
2499 * to disable the EDMA engine before doing the EDMA_RESET operation.
2500 */
2501 mv_stop_edma_engine(port_mmio);
2502 writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS);
2503
2504 if (!IS_GEN_I(hpriv)) {
2505 /* Enable 3.0gb/s link speed: this survives EDMA_RESET */
2506 mv_setup_ifcfg(port_mmio, 1);
2507 }
2508 /*
2509 * Strobing EDMA_RESET here causes a hard reset of the SATA transport,
2510 * link, and physical layers. It resets all SATA interface registers
2511 * (except for SATA_INTERFACE_CFG), and issues a COMRESET to the dev.
2512 */
2513 writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS);
2514 udelay(25); /* allow reset propagation */
2515 writelfl(0, port_mmio + EDMA_CMD_OFS);
2516
2517 hpriv->ops->phy_errata(hpriv, mmio, port_no);
2518
2519 if (IS_GEN_I(hpriv))
2520 mdelay(1);
2521 }
2522
2523 static void mv_pmp_select(struct ata_port *ap, int pmp)
2524 {
2525 if (sata_pmp_supported(ap)) {
2526 void __iomem *port_mmio = mv_ap_base(ap);
2527 u32 reg = readl(port_mmio + SATA_IFCTL_OFS);
2528 int old = reg & 0xf;
2529
2530 if (old != pmp) {
2531 reg = (reg & ~0xf) | pmp;
2532 writelfl(reg, port_mmio + SATA_IFCTL_OFS);
2533 }
2534 }
2535 }
2536
2537 static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
2538 unsigned long deadline)
2539 {
2540 mv_pmp_select(link->ap, sata_srst_pmp(link));
2541 return sata_std_hardreset(link, class, deadline);
2542 }
2543
2544 static int mv_softreset(struct ata_link *link, unsigned int *class,
2545 unsigned long deadline)
2546 {
2547 mv_pmp_select(link->ap, sata_srst_pmp(link));
2548 return ata_sff_softreset(link, class, deadline);
2549 }
2550
2551 static int mv_hardreset(struct ata_link *link, unsigned int *class,
2552 unsigned long deadline)
2553 {
2554 struct ata_port *ap = link->ap;
2555 struct mv_host_priv *hpriv = ap->host->private_data;
2556 struct mv_port_priv *pp = ap->private_data;
2557 void __iomem *mmio = hpriv->base;
2558 int rc, attempts = 0, extra = 0;
2559 u32 sstatus;
2560 bool online;
2561
2562 mv_reset_channel(hpriv, mmio, ap->port_no);
2563 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
2564
2565 /* Workaround for errata FEr SATA#10 (part 2) */
2566 do {
2567 const unsigned long *timing =
2568 sata_ehc_deb_timing(&link->eh_context);
2569
2570 rc = sata_link_hardreset(link, timing, deadline + extra,
2571 &online, NULL);
2572 if (rc)
2573 return rc;
2574 sata_scr_read(link, SCR_STATUS, &sstatus);
2575 if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) {
2576 /* Force 1.5gb/s link speed and try again */
2577 mv_setup_ifcfg(mv_ap_base(ap), 0);
2578 if (time_after(jiffies + HZ, deadline))
2579 extra = HZ; /* only extend it once, max */
2580 }
2581 } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123);
2582
2583 return rc;
2584 }
2585
2586 static void mv_eh_freeze(struct ata_port *ap)
2587 {
2588 struct mv_host_priv *hpriv = ap->host->private_data;
2589 unsigned int shift, hardport, port = ap->port_no;
2590 u32 main_irq_mask;
2591
2592 /* FIXME: handle coalescing completion events properly */
2593
2594 mv_stop_edma(ap);
2595 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
2596
2597 /* disable assertion of portN err, done events */
2598 main_irq_mask = readl(hpriv->main_irq_mask_addr);
2599 main_irq_mask &= ~((DONE_IRQ | ERR_IRQ) << shift);
2600 writelfl(main_irq_mask, hpriv->main_irq_mask_addr);
2601 }
2602
2603 static void mv_eh_thaw(struct ata_port *ap)
2604 {
2605 struct mv_host_priv *hpriv = ap->host->private_data;
2606 unsigned int shift, hardport, port = ap->port_no;
2607 void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port);
2608 void __iomem *port_mmio = mv_ap_base(ap);
2609 u32 main_irq_mask, hc_irq_cause;
2610
2611 /* FIXME: handle coalescing completion events properly */
2612
2613 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
2614
2615 /* clear EDMA errors on this port */
2616 writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2617
2618 /* clear pending irq events */
2619 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);
2620 hc_irq_cause &= ~((DEV_IRQ | DMA_IRQ) << hardport);
2621 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
2622
2623 /* enable assertion of portN err, done events */
2624 main_irq_mask = readl(hpriv->main_irq_mask_addr);
2625 main_irq_mask |= ((DONE_IRQ | ERR_IRQ) << shift);
2626 writelfl(main_irq_mask, hpriv->main_irq_mask_addr);
2627 }
2628
2629 /**
2630 * mv_port_init - Perform some early initialization on a single port.
2631 * @port: libata data structure storing shadow register addresses
2632 * @port_mmio: base address of the port
2633 *
2634 * Initialize shadow register mmio addresses, clear outstanding
2635 * interrupts on the port, and unmask interrupts for the future
2636 * start of the port.
2637 *
2638 * LOCKING:
2639 * Inherited from caller.
2640 */
2641 static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
2642 {
2643 void __iomem *shd_base = port_mmio + SHD_BLK_OFS;
2644 unsigned serr_ofs;
2645
2646 /* PIO related setup
2647 */
2648 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
2649 port->error_addr =
2650 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
2651 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
2652 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
2653 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
2654 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
2655 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
2656 port->status_addr =
2657 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
2658 /* special case: control/altstatus doesn't have ATA_REG_ address */
2659 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS;
2660
2661 /* unused: */
2662 port->cmd_addr = port->bmdma_addr = port->scr_addr = NULL;
2663
2664 /* Clear any currently outstanding port interrupt conditions */
2665 serr_ofs = mv_scr_offset(SCR_ERROR);
2666 writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs);
2667 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2668
2669 /* unmask all non-transient EDMA error interrupts */
2670 writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK_OFS);
2671
2672 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
2673 readl(port_mmio + EDMA_CFG_OFS),
2674 readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS),
2675 readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS));
2676 }
2677
2678 static unsigned int mv_in_pcix_mode(struct ata_host *host)
2679 {
2680 struct mv_host_priv *hpriv = host->private_data;
2681 void __iomem *mmio = hpriv->base;
2682 u32 reg;
2683
2684 if (!HAS_PCI(host) || !IS_PCIE(hpriv))
2685 return 0; /* not PCI-X capable */
2686 reg = readl(mmio + MV_PCI_MODE_OFS);
2687 if ((reg & MV_PCI_MODE_MASK) == 0)
2688 return 0; /* conventional PCI mode */
2689 return 1; /* chip is in PCI-X mode */
2690 }
2691
2692 static int mv_pci_cut_through_okay(struct ata_host *host)
2693 {
2694 struct mv_host_priv *hpriv = host->private_data;
2695 void __iomem *mmio = hpriv->base;
2696 u32 reg;
2697
2698 if (!mv_in_pcix_mode(host)) {
2699 reg = readl(mmio + PCI_COMMAND_OFS);
2700 if (reg & PCI_COMMAND_MRDTRIG)
2701 return 0; /* not okay */
2702 }
2703 return 1; /* okay */
2704 }
2705
2706 static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
2707 {
2708 struct pci_dev *pdev = to_pci_dev(host->dev);
2709 struct mv_host_priv *hpriv = host->private_data;
2710 u32 hp_flags = hpriv->hp_flags;
2711
2712 switch (board_idx) {
2713 case chip_5080:
2714 hpriv->ops = &mv5xxx_ops;
2715 hp_flags |= MV_HP_GEN_I;
2716
2717 switch (pdev->revision) {
2718 case 0x1:
2719 hp_flags |= MV_HP_ERRATA_50XXB0;
2720 break;
2721 case 0x3:
2722 hp_flags |= MV_HP_ERRATA_50XXB2;
2723 break;
2724 default:
2725 dev_printk(KERN_WARNING, &pdev->dev,
2726 "Applying 50XXB2 workarounds to unknown rev\n");
2727 hp_flags |= MV_HP_ERRATA_50XXB2;
2728 break;
2729 }
2730 break;
2731
2732 case chip_504x:
2733 case chip_508x:
2734 hpriv->ops = &mv5xxx_ops;
2735 hp_flags |= MV_HP_GEN_I;
2736
2737 switch (pdev->revision) {
2738 case 0x0:
2739 hp_flags |= MV_HP_ERRATA_50XXB0;
2740 break;
2741 case 0x3:
2742 hp_flags |= MV_HP_ERRATA_50XXB2;
2743 break;
2744 default:
2745 dev_printk(KERN_WARNING, &pdev->dev,
2746 "Applying B2 workarounds to unknown rev\n");
2747 hp_flags |= MV_HP_ERRATA_50XXB2;
2748 break;
2749 }
2750 break;
2751
2752 case chip_604x:
2753 case chip_608x:
2754 hpriv->ops = &mv6xxx_ops;
2755 hp_flags |= MV_HP_GEN_II;
2756
2757 switch (pdev->revision) {
2758 case 0x7:
2759 hp_flags |= MV_HP_ERRATA_60X1B2;
2760 break;
2761 case 0x9:
2762 hp_flags |= MV_HP_ERRATA_60X1C0;
2763 break;
2764 default:
2765 dev_printk(KERN_WARNING, &pdev->dev,
2766 "Applying B2 workarounds to unknown rev\n");
2767 hp_flags |= MV_HP_ERRATA_60X1B2;
2768 break;
2769 }
2770 break;
2771
2772 case chip_7042:
2773 hp_flags |= MV_HP_PCIE | MV_HP_CUT_THROUGH;
2774 if (pdev->vendor == PCI_VENDOR_ID_TTI &&
2775 (pdev->device == 0x2300 || pdev->device == 0x2310))
2776 {
2777 /*
2778 * Highpoint RocketRAID PCIe 23xx series cards:
2779 *
2780 * Unconfigured drives are treated as "Legacy"
2781 * by the BIOS, and it overwrites sector 8 with
2782 * a "Lgcy" metadata block prior to Linux boot.
2783 *
2784 * Configured drives (RAID or JBOD) leave sector 8
2785 * alone, but instead overwrite a high numbered
2786 * sector for the RAID metadata. This sector can
2787 * be determined exactly, by truncating the physical
2788 * drive capacity to a nice even GB value.
2789 *
2790 * RAID metadata is at: (dev->n_sectors & ~0xfffff)
2791 *
2792 * Warn the user, lest they think we're just buggy.
2793 */
2794 printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID"
2795 " BIOS CORRUPTS DATA on all attached drives,"
2796 " regardless of if/how they are configured."
2797 " BEWARE!\n");
2798 printk(KERN_WARNING DRV_NAME ": For data safety, do not"
2799 " use sectors 8-9 on \"Legacy\" drives,"
2800 " and avoid the final two gigabytes on"
2801 " all RocketRAID BIOS initialized drives.\n");
2802 }
2803 /* drop through */
2804 case chip_6042:
2805 hpriv->ops = &mv6xxx_ops;
2806 hp_flags |= MV_HP_GEN_IIE;
2807 if (board_idx == chip_6042 && mv_pci_cut_through_okay(host))
2808 hp_flags |= MV_HP_CUT_THROUGH;
2809
2810 switch (pdev->revision) {
2811 case 0x0:
2812 hp_flags |= MV_HP_ERRATA_XX42A0;
2813 break;
2814 case 0x1:
2815 hp_flags |= MV_HP_ERRATA_60X1C0;
2816 break;
2817 default:
2818 dev_printk(KERN_WARNING, &pdev->dev,
2819 "Applying 60X1C0 workarounds to unknown rev\n");
2820 hp_flags |= MV_HP_ERRATA_60X1C0;
2821 break;
2822 }
2823 break;
2824 case chip_soc:
2825 hpriv->ops = &mv_soc_ops;
2826 hp_flags |= MV_HP_ERRATA_60X1C0;
2827 break;
2828
2829 default:
2830 dev_printk(KERN_ERR, host->dev,
2831 "BUG: invalid board index %u\n", board_idx);
2832 return 1;
2833 }
2834
2835 hpriv->hp_flags = hp_flags;
2836 if (hp_flags & MV_HP_PCIE) {
2837 hpriv->irq_cause_ofs = PCIE_IRQ_CAUSE_OFS;
2838 hpriv->irq_mask_ofs = PCIE_IRQ_MASK_OFS;
2839 hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS;
2840 } else {
2841 hpriv->irq_cause_ofs = PCI_IRQ_CAUSE_OFS;
2842 hpriv->irq_mask_ofs = PCI_IRQ_MASK_OFS;
2843 hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS;
2844 }
2845
2846 return 0;
2847 }
2848
2849 /**
2850 * mv_init_host - Perform some early initialization of the host.
2851 * @host: ATA host to initialize
2852 * @board_idx: controller index
2853 *
2854 * If possible, do an early global reset of the host. Then do
2855 * our port init and clear/unmask all/relevant host interrupts.
2856 *
2857 * LOCKING:
2858 * Inherited from caller.
2859 */
2860 static int mv_init_host(struct ata_host *host, unsigned int board_idx)
2861 {
2862 int rc = 0, n_hc, port, hc;
2863 struct mv_host_priv *hpriv = host->private_data;
2864 void __iomem *mmio = hpriv->base;
2865
2866 rc = mv_chip_id(host, board_idx);
2867 if (rc)
2868 goto done;
2869
2870 if (HAS_PCI(host)) {
2871 hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE_OFS;
2872 hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK_OFS;
2873 } else {
2874 hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE_OFS;
2875 hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK_OFS;
2876 }
2877
2878 /* global interrupt mask: 0 == mask everything */
2879 writel(0, hpriv->main_irq_mask_addr);
2880
2881 n_hc = mv_get_hc_count(host->ports[0]->flags);
2882
2883 for (port = 0; port < host->n_ports; port++)
2884 hpriv->ops->read_preamp(hpriv, port, mmio);
2885
2886 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
2887 if (rc)
2888 goto done;
2889
2890 hpriv->ops->reset_flash(hpriv, mmio);
2891 hpriv->ops->reset_bus(host, mmio);
2892 hpriv->ops->enable_leds(hpriv, mmio);
2893
2894 for (port = 0; port < host->n_ports; port++) {
2895 struct ata_port *ap = host->ports[port];
2896 void __iomem *port_mmio = mv_port_base(mmio, port);
2897
2898 mv_port_init(&ap->ioaddr, port_mmio);
2899
2900 #ifdef CONFIG_PCI
2901 if (HAS_PCI(host)) {
2902 unsigned int offset = port_mmio - mmio;
2903 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio");
2904 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port");
2905 }
2906 #endif
2907 }
2908
2909 for (hc = 0; hc < n_hc; hc++) {
2910 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
2911
2912 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
2913 "(before clear)=0x%08x\n", hc,
2914 readl(hc_mmio + HC_CFG_OFS),
2915 readl(hc_mmio + HC_IRQ_CAUSE_OFS));
2916
2917 /* Clear any currently outstanding hc interrupt conditions */
2918 writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS);
2919 }
2920
2921 if (HAS_PCI(host)) {
2922 /* Clear any currently outstanding host interrupt conditions */
2923 writelfl(0, mmio + hpriv->irq_cause_ofs);
2924
2925 /* and unmask interrupt generation for host regs */
2926 writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_ofs);
2927 if (IS_GEN_I(hpriv))
2928 writelfl(~HC_MAIN_MASKED_IRQS_5,
2929 hpriv->main_irq_mask_addr);
2930 else
2931 writelfl(~HC_MAIN_MASKED_IRQS,
2932 hpriv->main_irq_mask_addr);
2933
2934 VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x "
2935 "PCI int cause/mask=0x%08x/0x%08x\n",
2936 readl(hpriv->main_irq_cause_addr),
2937 readl(hpriv->main_irq_mask_addr),
2938 readl(mmio + hpriv->irq_cause_ofs),
2939 readl(mmio + hpriv->irq_mask_ofs));
2940 } else {
2941 writelfl(~HC_MAIN_MASKED_IRQS_SOC,
2942 hpriv->main_irq_mask_addr);
2943 VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x\n",
2944 readl(hpriv->main_irq_cause_addr),
2945 readl(hpriv->main_irq_mask_addr));
2946 }
2947 done:
2948 return rc;
2949 }
2950
2951 static int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev)
2952 {
2953 hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ,
2954 MV_CRQB_Q_SZ, 0);
2955 if (!hpriv->crqb_pool)
2956 return -ENOMEM;
2957
2958 hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ,
2959 MV_CRPB_Q_SZ, 0);
2960 if (!hpriv->crpb_pool)
2961 return -ENOMEM;
2962
2963 hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ,
2964 MV_SG_TBL_SZ, 0);
2965 if (!hpriv->sg_tbl_pool)
2966 return -ENOMEM;
2967
2968 return 0;
2969 }
2970
2971 static void mv_conf_mbus_windows(struct mv_host_priv *hpriv,
2972 struct mbus_dram_target_info *dram)
2973 {
2974 int i;
2975
2976 for (i = 0; i < 4; i++) {
2977 writel(0, hpriv->base + WINDOW_CTRL(i));
2978 writel(0, hpriv->base + WINDOW_BASE(i));
2979 }
2980
2981 for (i = 0; i < dram->num_cs; i++) {
2982 struct mbus_dram_window *cs = dram->cs + i;
2983
2984 writel(((cs->size - 1) & 0xffff0000) |
2985 (cs->mbus_attr << 8) |
2986 (dram->mbus_dram_target_id << 4) | 1,
2987 hpriv->base + WINDOW_CTRL(i));
2988 writel(cs->base, hpriv->base + WINDOW_BASE(i));
2989 }
2990 }
2991
2992 /**
2993 * mv_platform_probe - handle a positive probe of an soc Marvell
2994 * host
2995 * @pdev: platform device found
2996 *
2997 * LOCKING:
2998 * Inherited from caller.
2999 */
3000 static int mv_platform_probe(struct platform_device *pdev)
3001 {
3002 static int printed_version;
3003 const struct mv_sata_platform_data *mv_platform_data;
3004 const struct ata_port_info *ppi[] =
3005 { &mv_port_info[chip_soc], NULL };
3006 struct ata_host *host;
3007 struct mv_host_priv *hpriv;
3008 struct resource *res;
3009 int n_ports, rc;
3010
3011 if (!printed_version++)
3012 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
3013
3014 /*
3015 * Simple resource validation ..
3016 */
3017 if (unlikely(pdev->num_resources != 2)) {
3018 dev_err(&pdev->dev, "invalid number of resources\n");
3019 return -EINVAL;
3020 }
3021
3022 /*
3023 * Get the register base first
3024 */
3025 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3026 if (res == NULL)
3027 return -EINVAL;
3028
3029 /* allocate host */
3030 mv_platform_data = pdev->dev.platform_data;
3031 n_ports = mv_platform_data->n_ports;
3032
3033 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
3034 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
3035
3036 if (!host || !hpriv)
3037 return -ENOMEM;
3038 host->private_data = hpriv;
3039 hpriv->n_ports = n_ports;
3040
3041 host->iomap = NULL;
3042 hpriv->base = devm_ioremap(&pdev->dev, res->start,
3043 res->end - res->start + 1);
3044 hpriv->base -= MV_SATAHC0_REG_BASE;
3045
3046 /*
3047 * (Re-)program MBUS remapping windows if we are asked to.
3048 */
3049 if (mv_platform_data->dram != NULL)
3050 mv_conf_mbus_windows(hpriv, mv_platform_data->dram);
3051
3052 rc = mv_create_dma_pools(hpriv, &pdev->dev);
3053 if (rc)
3054 return rc;
3055
3056 /* initialize adapter */
3057 rc = mv_init_host(host, chip_soc);
3058 if (rc)
3059 return rc;
3060
3061 dev_printk(KERN_INFO, &pdev->dev,
3062 "slots %u ports %d\n", (unsigned)MV_MAX_Q_DEPTH,
3063 host->n_ports);
3064
3065 return ata_host_activate(host, platform_get_irq(pdev, 0), mv_interrupt,
3066 IRQF_SHARED, &mv6_sht);
3067 }
3068
3069 /*
3070 *
3071 * mv_platform_remove - unplug a platform interface
3072 * @pdev: platform device
3073 *
3074 * A platform bus SATA device has been unplugged. Perform the needed
3075 * cleanup. Also called on module unload for any active devices.
3076 */
3077 static int __devexit mv_platform_remove(struct platform_device *pdev)
3078 {
3079 struct device *dev = &pdev->dev;
3080 struct ata_host *host = dev_get_drvdata(dev);
3081
3082 ata_host_detach(host);
3083 return 0;
3084 }
3085
3086 static struct platform_driver mv_platform_driver = {
3087 .probe = mv_platform_probe,
3088 .remove = __devexit_p(mv_platform_remove),
3089 .driver = {
3090 .name = DRV_NAME,
3091 .owner = THIS_MODULE,
3092 },
3093 };
3094
3095
3096 #ifdef CONFIG_PCI
3097 static int mv_pci_init_one(struct pci_dev *pdev,
3098 const struct pci_device_id *ent);
3099
3100
3101 static struct pci_driver mv_pci_driver = {
3102 .name = DRV_NAME,
3103 .id_table = mv_pci_tbl,
3104 .probe = mv_pci_init_one,
3105 .remove = ata_pci_remove_one,
3106 };
3107
3108 /*
3109 * module options
3110 */
3111 static int msi; /* Use PCI msi; either zero (off, default) or non-zero */
3112
3113
3114 /* move to PCI layer or libata core? */
3115 static int pci_go_64(struct pci_dev *pdev)
3116 {
3117 int rc;
3118
3119 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3120 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3121 if (rc) {
3122 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3123 if (rc) {
3124 dev_printk(KERN_ERR, &pdev->dev,
3125 "64-bit DMA enable failed\n");
3126 return rc;
3127 }
3128 }
3129 } else {
3130 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3131 if (rc) {
3132 dev_printk(KERN_ERR, &pdev->dev,
3133 "32-bit DMA enable failed\n");
3134 return rc;
3135 }
3136 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3137 if (rc) {
3138 dev_printk(KERN_ERR, &pdev->dev,
3139 "32-bit consistent DMA enable failed\n");
3140 return rc;
3141 }
3142 }
3143
3144 return rc;
3145 }
3146
3147 /**
3148 * mv_print_info - Dump key info to kernel log for perusal.
3149 * @host: ATA host to print info about
3150 *
3151 * FIXME: complete this.
3152 *
3153 * LOCKING:
3154 * Inherited from caller.
3155 */
3156 static void mv_print_info(struct ata_host *host)
3157 {
3158 struct pci_dev *pdev = to_pci_dev(host->dev);
3159 struct mv_host_priv *hpriv = host->private_data;
3160 u8 scc;
3161 const char *scc_s, *gen;
3162
3163 /* Use this to determine the HW stepping of the chip so we know
3164 * what errata to workaround
3165 */
3166 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
3167 if (scc == 0)
3168 scc_s = "SCSI";
3169 else if (scc == 0x01)
3170 scc_s = "RAID";
3171 else
3172 scc_s = "?";
3173
3174 if (IS_GEN_I(hpriv))
3175 gen = "I";
3176 else if (IS_GEN_II(hpriv))
3177 gen = "II";
3178 else if (IS_GEN_IIE(hpriv))
3179 gen = "IIE";
3180 else
3181 gen = "?";
3182
3183 dev_printk(KERN_INFO, &pdev->dev,
3184 "Gen-%s %u slots %u ports %s mode IRQ via %s\n",
3185 gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports,
3186 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
3187 }
3188
3189 /**
3190 * mv_pci_init_one - handle a positive probe of a PCI Marvell host
3191 * @pdev: PCI device found
3192 * @ent: PCI device ID entry for the matched host
3193 *
3194 * LOCKING:
3195 * Inherited from caller.
3196 */
3197 static int mv_pci_init_one(struct pci_dev *pdev,
3198 const struct pci_device_id *ent)
3199 {
3200 static int printed_version;
3201 unsigned int board_idx = (unsigned int)ent->driver_data;
3202 const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL };
3203 struct ata_host *host;
3204 struct mv_host_priv *hpriv;
3205 int n_ports, rc;
3206
3207 if (!printed_version++)
3208 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
3209
3210 /* allocate host */
3211 n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC;
3212
3213 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
3214 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
3215 if (!host || !hpriv)
3216 return -ENOMEM;
3217 host->private_data = hpriv;
3218 hpriv->n_ports = n_ports;
3219
3220 /* acquire resources */
3221 rc = pcim_enable_device(pdev);
3222 if (rc)
3223 return rc;
3224
3225 rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME);
3226 if (rc == -EBUSY)
3227 pcim_pin_device(pdev);
3228 if (rc)
3229 return rc;
3230 host->iomap = pcim_iomap_table(pdev);
3231 hpriv->base = host->iomap[MV_PRIMARY_BAR];
3232
3233 rc = pci_go_64(pdev);
3234 if (rc)
3235 return rc;
3236
3237 rc = mv_create_dma_pools(hpriv, &pdev->dev);
3238 if (rc)
3239 return rc;
3240
3241 /* initialize adapter */
3242 rc = mv_init_host(host, board_idx);
3243 if (rc)
3244 return rc;
3245
3246 /* Enable interrupts */
3247 if (msi && pci_enable_msi(pdev))
3248 pci_intx(pdev, 1);
3249
3250 mv_dump_pci_cfg(pdev, 0x68);
3251 mv_print_info(host);
3252
3253 pci_set_master(pdev);
3254 pci_try_set_mwi(pdev);
3255 return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED,
3256 IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht);
3257 }
3258 #endif
3259
3260 static int mv_platform_probe(struct platform_device *pdev);
3261 static int __devexit mv_platform_remove(struct platform_device *pdev);
3262
3263 static int __init mv_init(void)
3264 {
3265 int rc = -ENODEV;
3266 #ifdef CONFIG_PCI
3267 rc = pci_register_driver(&mv_pci_driver);
3268 if (rc < 0)
3269 return rc;
3270 #endif
3271 rc = platform_driver_register(&mv_platform_driver);
3272
3273 #ifdef CONFIG_PCI
3274 if (rc < 0)
3275 pci_unregister_driver(&mv_pci_driver);
3276 #endif
3277 return rc;
3278 }
3279
3280 static void __exit mv_exit(void)
3281 {
3282 #ifdef CONFIG_PCI
3283 pci_unregister_driver(&mv_pci_driver);
3284 #endif
3285 platform_driver_unregister(&mv_platform_driver);
3286 }
3287
3288 MODULE_AUTHOR("Brett Russ");
3289 MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
3290 MODULE_LICENSE("GPL");
3291 MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
3292 MODULE_VERSION(DRV_VERSION);
3293 MODULE_ALIAS("platform:" DRV_NAME);
3294
3295 #ifdef CONFIG_PCI
3296 module_param(msi, int, 0444);
3297 MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)");
3298 #endif
3299
3300 module_init(mv_init);
3301 module_exit(mv_exit);
Verdex Pro support