drivers/pcmcia/m32r_cfc.c

   1 /*
   2  *  drivers/pcmcia/m32r_cfc.c
   3  *
   4  *  Device driver for the CFC functionality of M32R.
   5  *
   6  *  Copyright (c) 2001, 2002, 2003, 2004
   7  *    Hiroyuki Kondo, Naoto Sugai, Hayato Fujiwara
   8  */
   9
  10 #include <linux/module.h>
  11 #include <linux/moduleparam.h>
  12 #include <linux/init.h>
  13 #include <linux/config.h>
  14 #include <linux/types.h>
  15 #include <linux/fcntl.h>
  16 #include <linux/string.h>
  17 #include <linux/kernel.h>
  18 #include <linux/errno.h>
  19 #include <linux/timer.h>
  20 #include <linux/sched.h>
  21 #include <linux/slab.h>
  22 #include <linux/ioport.h>
  23 #include <linux/delay.h>
  24 #include <linux/workqueue.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/device.h>
  27 #include <linux/bitops.h>
  28 #include <asm/irq.h>
  29 #include <asm/io.h>
  30 #include <asm/system.h>
  31
  32 #include <pcmcia/version.h>
  33 #include <pcmcia/cs_types.h>
  34 #include <pcmcia/ss.h>
  35 #include <pcmcia/cs.h>
  36
  37 #undef MAX_IO_WIN       /* FIXME */
  38 #define MAX_IO_WIN 1
  39 #undef MAX_WIN          /* FIXME */
  40 #define MAX_WIN 1
  41
  42 #include "m32r_cfc.h"
  43
  44 #ifdef DEBUG
  45 static int m32r_cfc_debug;
  46 module_param(m32r_cfc_debug, int, 0644);
  47 #define debug(lvl, fmt, arg...) do {                            \
  48         if (m32r_cfc_debug > (lvl))                             \
  49                 printk(KERN_DEBUG "m32r_cfc: " fmt , ## arg);   \
  50 } while (0)
  51 #else
  52 #define debug(n, args...) do { } while (0)
  53 #endif
  54
  55 /* Poll status interval -- 0 means default to interrupt */
  56 static int poll_interval = 0;
  57
  58 typedef enum pcc_space { as_none = 0, as_comm, as_attr, as_io } pcc_as_t;
  59
  60 typedef struct pcc_socket {
  61         u_short                 type, flags;
  62         struct pcmcia_socket    socket;
  63         unsigned int            number;
  64         kio_addr_t              ioaddr;
  65         u_long                  mapaddr;
  66         u_long                  base;   /* PCC register base */
  67         u_char                  cs_irq1, cs_irq2, intr;
  68         pccard_io_map           io_map[MAX_IO_WIN];
  69         pccard_mem_map          mem_map[MAX_WIN];
  70         u_char                  io_win;
  71         u_char                  mem_win;
  72         pcc_as_t                current_space;
  73         u_char                  last_iodbex;
  74 #ifdef CONFIG_PROC_FS
  75         struct proc_dir_entry *proc;
  76 #endif
  77 } pcc_socket_t;
  78
  79 static int pcc_sockets = 0;
  80 static pcc_socket_t socket[M32R_MAX_PCC] = {
  81         { 0, }, /* ... */
  82 };
  83
  84 /*====================================================================*/
  85
  86 static unsigned int pcc_get(u_short, unsigned int);
  87 static void pcc_set(u_short, unsigned int , unsigned int );
  88
  89 static DEFINE_SPINLOCK(pcc_lock);
  90
  91 #if !defined(CONFIG_PLAT_USRV)
  92 static inline u_long pcc_port2addr(unsigned long port, int size) {
  93         u_long addr = 0;
  94         u_long odd;
  95
  96         if (size == 1) {        /* byte access */
  97                 odd = (port&1) << 11;
  98                 port -= port & 1;
  99                 addr = CFC_IO_MAPBASE_BYTE - CFC_IOPORT_BASE + odd + port;
 100         } else if (size == 2)
 101                 addr = CFC_IO_MAPBASE_WORD - CFC_IOPORT_BASE + port;
 102
 103         return addr;
 104 }
 105 #else   /* CONFIG_PLAT_USRV */
 106 static inline u_long pcc_port2addr(unsigned long port, int size) {
 107         u_long odd;
 108         u_long addr = ((port - CFC_IOPORT_BASE) & 0xf000) << 8;
 109
 110         if (size == 1) {        /* byte access */
 111                 odd = port & 1;
 112                 port -= odd;
 113                 odd <<= 11;
 114                 addr = (addr | CFC_IO_MAPBASE_BYTE) + odd + (port & 0xfff);
 115         } else if (size == 2)   /* word access */
 116                 addr = (addr | CFC_IO_MAPBASE_WORD) + (port & 0xfff);
 117
 118         return addr;
 119 }
 120 #endif  /* CONFIG_PLAT_USRV */
 121
 122 void pcc_ioread_byte(int sock, unsigned long port, void *buf, size_t size,
 123         size_t nmemb, int flag)
 124 {
 125         u_long addr;
 126         unsigned char *bp = (unsigned char *)buf;
 127         unsigned long flags;
 128
 129         debug(3, "m32r_cfc: pcc_ioread_byte: sock=%d, port=%#lx, buf=%p, "
 130                  "size=%u, nmemb=%d, flag=%d\n",
 131                   sock, port, buf, size, nmemb, flag);
 132
 133         addr = pcc_port2addr(port, 1);
 134         if (!addr) {
 135                 printk("m32r_cfc:ioread_byte null port :%#lx\n",port);
 136                 return;
 137         }
 138         debug(3, "m32r_cfc: pcc_ioread_byte: addr=%#lx\n", addr);
 139
 140         spin_lock_irqsave(&pcc_lock, flags);
 141         /* read Byte */
 142         while (nmemb--)
 143                 *bp++ = readb(addr);
 144         spin_unlock_irqrestore(&pcc_lock, flags);
 145 }
 146
 147 void pcc_ioread_word(int sock, unsigned long port, void *buf, size_t size,
 148         size_t nmemb, int flag)
 149 {
 150         u_long addr;
 151         unsigned short *bp = (unsigned short *)buf;
 152         unsigned long flags;
 153
 154         debug(3, "m32r_cfc: pcc_ioread_word: sock=%d, port=%#lx, "
 155                  "buf=%p, size=%u, nmemb=%d, flag=%d\n",
 156                  sock, port, buf, size, nmemb, flag);
 157
 158         if (size != 2)
 159                 printk("m32r_cfc: ioread_word :illigal size %u : %#lx\n", size,
 160                         port);
 161         if (size == 9)
 162                 printk("m32r_cfc: ioread_word :insw \n");
 163
 164         addr = pcc_port2addr(port, 2);
 165         if (!addr) {
 166                 printk("m32r_cfc:ioread_word null port :%#lx\n",port);
 167                 return;
 168         }
 169         debug(3, "m32r_cfc: pcc_ioread_word: addr=%#lx\n", addr);
 170
 171         spin_lock_irqsave(&pcc_lock, flags);
 172         /* read Word */
 173         while (nmemb--)
 174                 *bp++ = readw(addr);
 175         spin_unlock_irqrestore(&pcc_lock, flags);
 176 }
 177
 178 void pcc_iowrite_byte(int sock, unsigned long port, void *buf, size_t size,
 179         size_t nmemb, int flag)
 180 {
 181         u_long addr;
 182         unsigned char *bp = (unsigned char *)buf;
 183         unsigned long flags;
 184
 185         debug(3, "m32r_cfc: pcc_iowrite_byte: sock=%d, port=%#lx, "
 186                  "buf=%p, size=%u, nmemb=%d, flag=%d\n",
 187                  sock, port, buf, size, nmemb, flag);
 188
 189         /* write Byte */
 190         addr = pcc_port2addr(port, 1);
 191         if (!addr) {
 192                 printk("m32r_cfc:iowrite_byte null port:%#lx\n",port);
 193                 return;
 194         }
 195         debug(3, "m32r_cfc: pcc_iowrite_byte: addr=%#lx\n", addr);
 196
 197         spin_lock_irqsave(&pcc_lock, flags);
 198         while (nmemb--)
 199                 writeb(*bp++, addr);
 200         spin_unlock_irqrestore(&pcc_lock, flags);
 201 }
 202
 203 void pcc_iowrite_word(int sock, unsigned long port, void *buf, size_t size,
 204         size_t nmemb, int flag)
 205 {
 206         u_long addr;
 207         unsigned short *bp = (unsigned short *)buf;
 208         unsigned long flags;
 209
 210         debug(3, "m32r_cfc: pcc_iowrite_word: sock=%d, port=%#lx, "
 211                  "buf=%p, size=%u, nmemb=%d, flag=%d\n",
 212                  sock, port, buf, size, nmemb, flag);
 213
 214         if(size != 2)
 215                 printk("m32r_cfc: iowrite_word :illigal size %u : %#lx\n",
 216                         size, port);
 217         if(size == 9)
 218                 printk("m32r_cfc: iowrite_word :outsw \n");
 219
 220         addr = pcc_port2addr(port, 2);
 221         if (!addr) {
 222                 printk("m32r_cfc:iowrite_word null addr :%#lx\n",port);
 223                 return;
 224         }
 225 #if 1
 226         if (addr & 1) {
 227                 printk("m32r_cfc:iowrite_word port addr (%#lx):%#lx\n", port,
 228                         addr);
 229                 return;
 230         }
 231 #endif
 232         debug(3, "m32r_cfc: pcc_iowrite_word: addr=%#lx\n", addr);
 233
 234         spin_lock_irqsave(&pcc_lock, flags);
 235         while (nmemb--)
 236                 writew(*bp++, addr);
 237         spin_unlock_irqrestore(&pcc_lock, flags);
 238 }
 239
 240 /*====================================================================*/
 241
 242 #define IS_REGISTERED           0x2000
 243 #define IS_ALIVE                0x8000
 244
 245 typedef struct pcc_t {
 246         char                    *name;
 247         u_short                 flags;
 248 } pcc_t;
 249
 250 static pcc_t pcc[] = {
 251 #if !defined(CONFIG_PLAT_USRV)
 252         { "m32r_cfc", 0 }, { "", 0 },
 253 #else   /* CONFIG_PLAT_USRV */
 254         { "m32r_cfc", 0 }, { "m32r_cfc", 0 }, { "m32r_cfc", 0 },
 255         { "m32r_cfc", 0 }, { "m32r_cfc", 0 }, { "", 0 },
 256 #endif  /* CONFIG_PLAT_USRV */
 257 };
 258
 259 static irqreturn_t pcc_interrupt(int, void *, struct pt_regs *);
 260
 261 /*====================================================================*/
 262
 263 static struct timer_list poll_timer;
 264
 265 static unsigned int pcc_get(u_short sock, unsigned int reg)
 266 {
 267         unsigned int val = inw(reg);
 268         debug(3, "m32r_cfc: pcc_get: reg(0x%08x)=0x%04x\n", reg, val);
 269         return val;
 270 }
 271
 272
 273 static void pcc_set(u_short sock, unsigned int reg, unsigned int data)
 274 {
 275         outw(data, reg);
 276         debug(3, "m32r_cfc: pcc_set: reg(0x%08x)=0x%04x\n", reg, data);
 277 }
 278
 279 /*======================================================================
 280
 281         See if a card is present, powered up, in IO mode, and already
 282         bound to a (non PC Card) Linux driver.  We leave these alone.
 283
 284         We make an exception for cards that seem to be serial devices.
 285
 286 ======================================================================*/
 287
 288 static int __init is_alive(u_short sock)
 289 {
 290         unsigned int stat;
 291
 292         debug(3, "m32r_cfc: is_alive:\n");
 293
 294         printk("CF: ");
 295         stat = pcc_get(sock, (unsigned int)PLD_CFSTS);
 296         if (!stat)
 297                 printk("No ");
 298         printk("Card is detected at socket %d : stat = 0x%08x\n", sock, stat);
 299         debug(3, "m32r_cfc: is_alive: sock stat is 0x%04x\n", stat);
 300
 301         return 0;
 302 }
 303
 304 static void add_pcc_socket(ulong base, int irq, ulong mapaddr, kio_addr_t ioaddr)
 305 {
 306         pcc_socket_t *t = &socket[pcc_sockets];
 307
 308         debug(3, "m32r_cfc: add_pcc_socket: base=%#lx, irq=%d, "
 309                  "mapaddr=%#lx, ioaddr=%08x\n",
 310                  base, irq, mapaddr, ioaddr);
 311
 312         /* add sockets */
 313         t->ioaddr = ioaddr;
 314         t->mapaddr = mapaddr;
 315 #if !defined(CONFIG_PLAT_USRV)
 316         t->base = 0;
 317         t->flags = 0;
 318         t->cs_irq1 = irq;               // insert irq
 319         t->cs_irq2 = irq + 1;           // eject irq
 320 #else   /* CONFIG_PLAT_USRV */
 321         t->base = base;
 322         t->flags = 0;
 323         t->cs_irq1 = 0;                 // insert irq
 324         t->cs_irq2 = 0;                 // eject irq
 325 #endif  /* CONFIG_PLAT_USRV */
 326
 327         if (is_alive(pcc_sockets))
 328                 t->flags |= IS_ALIVE;
 329
 330         /* add pcc */
 331 #if !defined(CONFIG_PLAT_USRV)
 332         request_region((unsigned int)PLD_CFRSTCR, 0x20, "m32r_cfc");
 333 #else   /* CONFIG_PLAT_USRV */
 334         {
 335                 unsigned int reg_base;
 336
 337                 reg_base = (unsigned int)PLD_CFRSTCR;
 338                 reg_base |= pcc_sockets << 8;
 339                 request_region(reg_base, 0x20, "m32r_cfc");
 340         }
 341 #endif  /* CONFIG_PLAT_USRV */
 342         printk(KERN_INFO "  %s ", pcc[pcc_sockets].name);
 343         printk("pcc at 0x%08lx\n", t->base);
 344
 345         /* Update socket interrupt information, capabilities */
 346         t->socket.features |= (SS_CAP_PCCARD | SS_CAP_STATIC_MAP);
 347         t->socket.map_size = M32R_PCC_MAPSIZE;
 348         t->socket.io_offset = ioaddr;   /* use for io access offset */
 349         t->socket.irq_mask = 0;
 350 #if !defined(CONFIG_PLAT_USRV)
 351         t->socket.pci_irq = PLD_IRQ_CFIREQ ;    /* card interrupt */
 352 #else   /* CONFIG_PLAT_USRV */
 353         t->socket.pci_irq = PLD_IRQ_CF0 + pcc_sockets;
 354 #endif  /* CONFIG_PLAT_USRV */
 355
 356 #ifndef CONFIG_PLAT_USRV
 357         /* insert interrupt */
 358         request_irq(irq, pcc_interrupt, 0, "m32r_cfc", pcc_interrupt);
 359         /* eject interrupt */
 360         request_irq(irq+1, pcc_interrupt, 0, "m32r_cfc", pcc_interrupt);
 361
 362         debug(3, "m32r_cfc: enable CFMSK, RDYSEL\n");
 363         pcc_set(pcc_sockets, (unsigned int)PLD_CFIMASK, 0x01);
 364 #endif  /* CONFIG_PLAT_USRV */
 365 #if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_USRV) || defined(CONFIG_PLAT_OPSPUT)
 366         pcc_set(pcc_sockets, (unsigned int)PLD_CFCR1, 0x0200);
 367 #endif
 368         pcc_sockets++;
 369
 370         return;
 371 }
 372
 373
 374 /*====================================================================*/
 375
 376 static irqreturn_t pcc_interrupt(int irq, void *dev, struct pt_regs *regs)
 377 {
 378         int i;
 379         u_int events = 0;
 380         int handled = 0;
 381
 382         debug(3, "m32r_cfc: pcc_interrupt: irq=%d, dev=%p, regs=%p\n",
 383                 irq, dev, regs);
 384         for (i = 0; i < pcc_sockets; i++) {
 385                 if (socket[i].cs_irq1 != irq && socket[i].cs_irq2 != irq)
 386                         continue;
 387
 388                 handled = 1;
 389                 debug(3, "m32r_cfc: pcc_interrupt: socket %d irq 0x%02x ",
 390                         i, irq);
 391                 events |= SS_DETECT;    /* insert or eject */
 392                 if (events)
 393                         pcmcia_parse_events(&socket[i].socket, events);
 394         }
 395         debug(3, "m32r_cfc: pcc_interrupt: done\n");
 396
 397         return IRQ_RETVAL(handled);
 398 } /* pcc_interrupt */
 399
 400 static void pcc_interrupt_wrapper(u_long data)
 401 {
 402         debug(3, "m32r_cfc: pcc_interrupt_wrapper:\n");
 403         pcc_interrupt(0, NULL, NULL);
 404         init_timer(&poll_timer);
 405         poll_timer.expires = jiffies + poll_interval;
 406         add_timer(&poll_timer);
 407 }
 408
 409 /*====================================================================*/
 410
 411 static int _pcc_get_status(u_short sock, u_int *value)
 412 {
 413         u_int status;
 414
 415         debug(3, "m32r_cfc: _pcc_get_status:\n");
 416         status = pcc_get(sock, (unsigned int)PLD_CFSTS);
 417         *value = (status) ? SS_DETECT : 0;
 418         debug(3, "m32r_cfc: _pcc_get_status: status=0x%08x\n", status);
 419
 420 #if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_USRV) || defined(CONFIG_PLAT_OPSPUT)
 421         if ( status ) {
 422                 /* enable CF power */
 423                 status = inw((unsigned int)PLD_CPCR);
 424                 if (!(status & PLD_CPCR_CF)) {
 425                         debug(3, "m32r_cfc: _pcc_get_status: "
 426                                  "power on (CPCR=0x%08x)\n", status);
 427                         status |= PLD_CPCR_CF;
 428                         outw(status, (unsigned int)PLD_CPCR);
 429                         udelay(100);
 430                 }
 431                 *value |= SS_POWERON;
 432
 433                 pcc_set(sock, (unsigned int)PLD_CFBUFCR,0);/* enable buffer */
 434                 udelay(100);
 435
 436                 *value |= SS_READY;             /* always ready */
 437                 *value |= SS_3VCARD;
 438         } else {
 439                 /* disable CF power */
 440                 status = inw((unsigned int)PLD_CPCR);
 441                 status &= ~PLD_CPCR_CF;
 442                 outw(status, (unsigned int)PLD_CPCR);
 443                 udelay(100);
 444                 debug(3, "m32r_cfc: _pcc_get_status: "
 445                          "power off (CPCR=0x%08x)\n", status);
 446         }
 447 #elif defined(CONFIG_PLAT_MAPPI2) || defined(CONFIG_PLAT_MAPPI3)
 448         if ( status ) {
 449                 status = pcc_get(sock, (unsigned int)PLD_CPCR);
 450                 if (status == 0) { /* power off */
 451                         pcc_set(sock, (unsigned int)PLD_CPCR, 1);
 452                         pcc_set(sock, (unsigned int)PLD_CFBUFCR,0); /* force buffer off for ZA-36 */
 453                         udelay(50);
 454                 }
 455                 *value |= SS_POWERON;
 456
 457                 pcc_set(sock, (unsigned int)PLD_CFBUFCR,0);
 458                 udelay(50);
 459                 pcc_set(sock, (unsigned int)PLD_CFRSTCR, 0x0101);
 460                 udelay(25); /* for IDE reset */
 461                 pcc_set(sock, (unsigned int)PLD_CFRSTCR, 0x0100);
 462                 mdelay(2);  /* for IDE reset */
 463
 464                 *value |= SS_READY;
 465                 *value |= SS_3VCARD;
 466         } else {
 467                 /* disable CF power */
 468                 pcc_set(sock, (unsigned int)PLD_CPCR, 0);
 469                 udelay(100);
 470                 debug(3, "m32r_cfc: _pcc_get_status: "
 471                          "power off (CPCR=0x%08x)\n", status);
 472         }
 473 #else
 474 #error no platform configuration
 475 #endif
 476         debug(3, "m32r_cfc: _pcc_get_status: GetStatus(%d) = %#4.4x\n",
 477                  sock, *value);
 478         return 0;
 479 } /* _get_status */
 480
 481 /*====================================================================*/
 482
 483 static int _pcc_get_socket(u_short sock, socket_state_t *state)
 484 {
 485 //      pcc_socket_t *t = &socket[sock];
 486
 487         state->flags = 0;
 488         state->csc_mask = SS_DETECT;
 489         state->csc_mask |= SS_READY;
 490         state->io_irq = 0;
 491         state->Vcc = 33;        /* 3.3V fixed */
 492         state->Vpp = 33;
 493
 494         debug(3, "m32r_cfc: GetSocket(%d) = flags %#3.3x, Vcc %d, Vpp %d, "
 495                   "io_irq %d, csc_mask %#2.2x\n", sock, state->flags,
 496                   state->Vcc, state->Vpp, state->io_irq, state->csc_mask);
 497         return 0;
 498 } /* _get_socket */
 499
 500 /*====================================================================*/
 501
 502 static int _pcc_set_socket(u_short sock, socket_state_t *state)
 503 {
 504         debug(3, "m32r_cfc: SetSocket(%d, flags %#3.3x, Vcc %d, Vpp %d, "
 505                   "io_irq %d, csc_mask %#2.2x)\n", sock, state->flags,
 506                   state->Vcc, state->Vpp, state->io_irq, state->csc_mask);
 507
 508 #if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_USRV) || defined(CONFIG_PLAT_OPSPUT) || defined(CONFIG_PLAT_MAPPI2) || defined(CONFIG_PLAT_MAPPI3)
 509         if (state->Vcc) {
 510                 if ((state->Vcc != 50) && (state->Vcc != 33))
 511                         return -EINVAL;
 512                 /* accept 5V and 3.3V */
 513         }
 514 #endif
 515         if (state->flags & SS_RESET) {
 516                 debug(3, ":RESET\n");
 517                 pcc_set(sock,(unsigned int)PLD_CFRSTCR,0x101);
 518         }else{
 519                 pcc_set(sock,(unsigned int)PLD_CFRSTCR,0x100);
 520         }
 521         if (state->flags & SS_OUTPUT_ENA){
 522                 debug(3, ":OUTPUT_ENA\n");
 523                 /* bit clear */
 524                 pcc_set(sock,(unsigned int)PLD_CFBUFCR,0);
 525         } else {
 526                 pcc_set(sock,(unsigned int)PLD_CFBUFCR,1);
 527         }
 528
 529 #ifdef DEBUG
 530         if(state->flags & SS_IOCARD){
 531                 debug(3, ":IOCARD");
 532         }
 533         if (state->flags & SS_PWR_AUTO) {
 534                 debug(3, ":PWR_AUTO");
 535         }
 536         if (state->csc_mask & SS_DETECT)
 537                 debug(3, ":csc-SS_DETECT");
 538         if (state->flags & SS_IOCARD) {
 539                 if (state->csc_mask & SS_STSCHG)
 540                         debug(3, ":STSCHG");
 541         } else {
 542                 if (state->csc_mask & SS_BATDEAD)
 543                         debug(3, ":BATDEAD");
 544                 if (state->csc_mask & SS_BATWARN)
 545                         debug(3, ":BATWARN");
 546                 if (state->csc_mask & SS_READY)
 547                         debug(3, ":READY");
 548         }
 549         debug(3, "\n");
 550 #endif
 551         return 0;
 552 } /* _set_socket */
 553
 554 /*====================================================================*/
 555
 556 static int _pcc_set_io_map(u_short sock, struct pccard_io_map *io)
 557 {
 558         u_char map;
 559
 560         debug(3, "m32r_cfc: SetIOMap(%d, %d, %#2.2x, %d ns, "
 561                   "%#lx-%#lx)\n", sock, io->map, io->flags,
 562                   io->speed, io->start, io->stop);
 563         map = io->map;
 564
 565         return 0;
 566 } /* _set_io_map */
 567
 568 /*====================================================================*/
 569
 570 static int _pcc_set_mem_map(u_short sock, struct pccard_mem_map *mem)
 571 {
 572
 573         u_char map = mem->map;
 574         u_long addr;
 575         pcc_socket_t *t = &socket[sock];
 576
 577         debug(3, "m32r_cfc: SetMemMap(%d, %d, %#2.2x, %d ns, "
 578                  "%#lx, %#x)\n", sock, map, mem->flags,
 579                  mem->speed, mem->static_start, mem->card_start);
 580
 581         /*
 582          * sanity check
 583          */
 584         if ((map > MAX_WIN) || (mem->card_start > 0x3ffffff)){
 585                 return -EINVAL;
 586         }
 587
 588         /*
 589          * de-activate
 590          */
 591         if ((mem->flags & MAP_ACTIVE) == 0) {
 592                 t->current_space = as_none;
 593                 return 0;
 594         }
 595
 596         /*
 597          * Set mode
 598          */
 599         if (mem->flags & MAP_ATTRIB) {
 600                 t->current_space = as_attr;
 601         } else {
 602                 t->current_space = as_comm;
 603         }
 604
 605         /*
 606          * Set address
 607          */
 608         addr = t->mapaddr + (mem->card_start & M32R_PCC_MAPMASK);
 609         mem->static_start = addr + mem->card_start;
 610
 611         return 0;
 612
 613 } /* _set_mem_map */
 614
 615 #if 0 /* driver model ordering issue */
 616 /*======================================================================
 617
 618         Routines for accessing socket information and register dumps via
 619         /proc/bus/pccard/...
 620
 621 ======================================================================*/
 622
 623 static ssize_t show_info(struct class_device *class_dev, char *buf)
 624 {
 625         pcc_socket_t *s = container_of(class_dev, struct pcc_socket,
 626                 socket.dev);
 627
 628         return sprintf(buf, "type:     %s\nbase addr:    0x%08lx\n",
 629                 pcc[s->type].name, s->base);
 630 }
 631
 632 static ssize_t show_exca(struct class_device *class_dev, char *buf)
 633 {
 634         /* FIXME */
 635
 636         return 0;
 637 }
 638
 639 static CLASS_DEVICE_ATTR(info, S_IRUGO, show_info, NULL);
 640 static CLASS_DEVICE_ATTR(exca, S_IRUGO, show_exca, NULL);
 641 #endif
 642
 643 /*====================================================================*/
 644
 645 /* this is horribly ugly... proper locking needs to be done here at
 646  * some time... */
 647 #define LOCKED(x) do {                                  \
 648         int retval;                                     \
 649         unsigned long flags;                            \
 650         spin_lock_irqsave(&pcc_lock, flags);            \
 651         retval = x;                                     \
 652         spin_unlock_irqrestore(&pcc_lock, flags);       \
 653         return retval;                                  \
 654 } while (0)
 655
 656
 657 static int pcc_get_status(struct pcmcia_socket *s, u_int *value)
 658 {
 659         unsigned int sock = container_of(s, struct pcc_socket, socket)->number;
 660
 661         if (socket[sock].flags & IS_ALIVE) {
 662                 debug(3, "m32r_cfc: pcc_get_status: sock(%d) -EINVAL\n", sock);
 663                 *value = 0;
 664                 return -EINVAL;
 665         }
 666         debug(3, "m32r_cfc: pcc_get_status: sock(%d)\n", sock);
 667         LOCKED(_pcc_get_status(sock, value));
 668 }
 669
 670 static int pcc_get_socket(struct pcmcia_socket *s, socket_state_t *state)
 671 {
 672         unsigned int sock = container_of(s, struct pcc_socket, socket)->number;
 673
 674         if (socket[sock].flags & IS_ALIVE) {
 675                 debug(3, "m32r_cfc: pcc_get_socket: sock(%d) -EINVAL\n", sock);
 676                 return -EINVAL;
 677         }
 678         debug(3, "m32r_cfc: pcc_get_socket: sock(%d)\n", sock);
 679         LOCKED(_pcc_get_socket(sock, state));
 680 }
 681
 682 static int pcc_set_socket(struct pcmcia_socket *s, socket_state_t *state)
 683 {
 684         unsigned int sock = container_of(s, struct pcc_socket, socket)->number;
 685
 686         if (socket[sock].flags & IS_ALIVE) {
 687                 debug(3, "m32r_cfc: pcc_set_socket: sock(%d) -EINVAL\n", sock);
 688                 return -EINVAL;
 689         }
 690         debug(3, "m32r_cfc: pcc_set_socket: sock(%d)\n", sock);
 691         LOCKED(_pcc_set_socket(sock, state));
 692 }
 693
 694 static int pcc_set_io_map(struct pcmcia_socket *s, struct pccard_io_map *io)
 695 {
 696         unsigned int sock = container_of(s, struct pcc_socket, socket)->number;
 697
 698         if (socket[sock].flags & IS_ALIVE) {
 699                 debug(3, "m32r_cfc: pcc_set_io_map: sock(%d) -EINVAL\n", sock);
 700                 return -EINVAL;
 701         }
 702         debug(3, "m32r_cfc: pcc_set_io_map: sock(%d)\n", sock);
 703         LOCKED(_pcc_set_io_map(sock, io));
 704 }
 705
 706 static int pcc_set_mem_map(struct pcmcia_socket *s, struct pccard_mem_map *mem)
 707 {
 708         unsigned int sock = container_of(s, struct pcc_socket, socket)->number;
 709
 710         if (socket[sock].flags & IS_ALIVE) {
 711                 debug(3, "m32r_cfc: pcc_set_mem_map: sock(%d) -EINVAL\n", sock);
 712                 return -EINVAL;
 713         }
 714         debug(3, "m32r_cfc: pcc_set_mem_map: sock(%d)\n", sock);
 715         LOCKED(_pcc_set_mem_map(sock, mem));
 716 }
 717
 718 static int pcc_init(struct pcmcia_socket *s)
 719 {
 720         debug(3, "m32r_cfc: pcc_init()\n");
 721         return 0;
 722 }
 723
 724 static struct pccard_operations pcc_operations = {
 725         .init                   = pcc_init,
 726         .get_status             = pcc_get_status,
 727         .get_socket             = pcc_get_socket,
 728         .set_socket             = pcc_set_socket,
 729         .set_io_map             = pcc_set_io_map,
 730         .set_mem_map            = pcc_set_mem_map,
 731 };
 732
 733 /*====================================================================*/
 734
 735 static int m32r_pcc_suspend(struct device *dev, pm_message_t state, u32 level)
 736 {
 737         int ret = 0;
 738         if (level == SUSPEND_SAVE_STATE)
 739                 ret = pcmcia_socket_dev_suspend(dev, state);
 740         return ret;
 741 }
 742
 743 static int m32r_pcc_resume(struct device *dev, u32 level)
 744 {
 745         int ret = 0;
 746         if (level == RESUME_RESTORE_STATE)
 747                 ret = pcmcia_socket_dev_resume(dev);
 748         return ret;
 749 }
 750
 751
 752 static struct device_driver pcc_driver = {
 753         .name = "cfc",
 754         .bus = &platform_bus_type,
 755         .suspend = m32r_pcc_suspend,
 756         .resume = m32r_pcc_resume,
 757 };
 758
 759 static struct platform_device pcc_device = {
 760         .name = "cfc",
 761         .id = 0,
 762 };
 763
 764 /*====================================================================*/
 765
 766 static int __init init_m32r_pcc(void)
 767 {
 768         int i, ret;
 769
 770         ret = driver_register(&pcc_driver);
 771         if (ret)
 772                 return ret;
 773
 774         ret = platform_device_register(&pcc_device);
 775         if (ret){
 776                 driver_unregister(&pcc_driver);
 777                 return ret;
 778         }
 779
 780 #if defined(CONFIG_PLAT_MAPPI2) || defined(CONFIG_PLAT_MAPPI3)
 781         pcc_set(0, (unsigned int)PLD_CFCR0, 0x0f0f);
 782         pcc_set(0, (unsigned int)PLD_CFCR1, 0x0200);
 783 #endif
 784
 785         pcc_sockets = 0;
 786
 787 #if !defined(CONFIG_PLAT_USRV)
 788         add_pcc_socket(M32R_PCC0_BASE, PLD_IRQ_CFC_INSERT, CFC_ATTR_MAPBASE,
 789                        CFC_IOPORT_BASE);
 790 #else   /* CONFIG_PLAT_USRV */
 791         {
 792                 ulong base, mapaddr;
 793                 kio_addr_t ioaddr;
 794
 795                 for (i = 0 ; i < M32R_MAX_PCC ; i++) {
 796                         base = (ulong)PLD_CFRSTCR;
 797                         base = base | (i << 8);
 798                         ioaddr = (i + 1) << 12;
 799                         mapaddr = CFC_ATTR_MAPBASE | (i << 20);
 800                         add_pcc_socket(base, 0, mapaddr, ioaddr);
 801                 }
 802         }
 803 #endif  /* CONFIG_PLAT_USRV */
 804
 805         if (pcc_sockets == 0) {
 806                 printk("socket is not found.\n");
 807                 platform_device_unregister(&pcc_device);
 808                 driver_unregister(&pcc_driver);
 809                 return -ENODEV;
 810         }
 811
 812         /* Set up interrupt handler(s) */
 813
 814         for (i = 0 ; i < pcc_sockets ; i++) {
 815                 socket[i].socket.dev.dev = &pcc_device.dev;
 816                 socket[i].socket.ops = &pcc_operations;
 817                 socket[i].socket.resource_ops = &pccard_nonstatic_ops;
 818                 socket[i].socket.owner = THIS_MODULE;
 819                 socket[i].number = i;
 820                 ret = pcmcia_register_socket(&socket[i].socket);
 821                 if (!ret)
 822                         socket[i].flags |= IS_REGISTERED;
 823
 824 #if 0   /* driver model ordering issue */
 825                 class_device_create_file(&socket[i].socket.dev,
 826                                          &class_device_attr_info);
 827                 class_device_create_file(&socket[i].socket.dev,
 828                                          &class_device_attr_exca);
 829 #endif
 830         }
 831
 832         /* Finally, schedule a polling interrupt */
 833         if (poll_interval != 0) {
 834                 poll_timer.function = pcc_interrupt_wrapper;
 835                 poll_timer.data = 0;
 836                 init_timer(&poll_timer);
 837                 poll_timer.expires = jiffies + poll_interval;
 838                 add_timer(&poll_timer);
 839         }
 840
 841         return 0;
 842 } /* init_m32r_pcc */
 843
 844 static void __exit exit_m32r_pcc(void)
 845 {
 846         int i;
 847
 848         for (i = 0; i < pcc_sockets; i++)
 849                 if (socket[i].flags & IS_REGISTERED)
 850                         pcmcia_unregister_socket(&socket[i].socket);
 851
 852         platform_device_unregister(&pcc_device);
 853         if (poll_interval != 0)
 854                 del_timer_sync(&poll_timer);
 855
 856         driver_unregister(&pcc_driver);
 857 } /* exit_m32r_pcc */
 858
 859 module_init(init_m32r_pcc);
 860 module_exit(exit_m32r_pcc);
 861 MODULE_LICENSE("Dual MPL/GPL");
 862 /*====================================================================*/