2 * File: drivers/spi/bfin5xx_spi.c
4 * Author: Luke Yang (Analog Devices Inc.)
6 * Created: March. 10th 2006
7 * Description: SPI controller driver for Blackfin 5xx
8 * Bugs: Enter bugs at http://blackfin.uclinux.org/
11 * March 10, 2006 bfin5xx_spi.c Created. (Luke Yang)
12 * August 7, 2006 added full duplex mode (Axel Weiss & Luke Yang)
14 * Copyright 2004-2006 Analog Devices Inc.
16 * This program is free software ; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation ; either version 2, or (at your option)
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY ; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
26 * You should have received a copy of the GNU General Public License
27 * along with this program ; see the file COPYING.
28 * If not, write to the Free Software Foundation,
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
32 #include <linux/init.h>
33 #include <linux/module.h>
34 #include <linux/device.h>
35 #include <linux/ioport.h>
36 #include <linux/errno.h>
37 #include <linux/interrupt.h>
38 #include <linux/platform_device.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/spi/spi.h>
41 #include <linux/workqueue.h>
42 #include <linux/errno.h>
43 #include <linux/delay.h>
47 #include <asm/delay.h>
50 #include <asm/bfin5xx_spi.h>
52 MODULE_AUTHOR("Luke Yang");
53 MODULE_DESCRIPTION("Blackfin 5xx SPI Contoller");
54 MODULE_LICENSE("GPL");
56 #define IS_DMA_ALIGNED(x) (((u32)(x)&0x07)==0)
58 #define DEFINE_SPI_REG(reg, off) \
59 static inline u16 read_##reg(void) \
60 { return *(volatile unsigned short*)(SPI0_REGBASE + off); } \
61 static inline void write_##reg(u16 v) \
62 {*(volatile unsigned short*)(SPI0_REGBASE + off) = v;\
65 DEFINE_SPI_REG(CTRL
, 0x00)
66 DEFINE_SPI_REG(FLAG
, 0x04)
67 DEFINE_SPI_REG(STAT
, 0x08)
68 DEFINE_SPI_REG(TDBR
, 0x0C)
69 DEFINE_SPI_REG(RDBR
, 0x10)
70 DEFINE_SPI_REG(BAUD
, 0x14)
71 DEFINE_SPI_REG(SHAW
, 0x18)
72 #define START_STATE ((void*)0)
73 #define RUNNING_STATE ((void*)1)
74 #define DONE_STATE ((void*)2)
75 #define ERROR_STATE ((void*)-1)
76 #define QUEUE_RUNNING 0
77 #define QUEUE_STOPPED 1
81 /* Driver model hookup */
82 struct platform_device
*pdev
;
84 /* SPI framework hookup */
85 struct spi_master
*master
;
88 struct bfin5xx_spi_master
*master_info
;
90 /* Driver message queue */
91 struct workqueue_struct
*workqueue
;
92 struct work_struct pump_messages
;
94 struct list_head queue
;
98 /* Message Transfer pump */
99 struct tasklet_struct pump_transfers
;
101 /* Current message transfer state info */
102 struct spi_message
*cur_msg
;
103 struct spi_transfer
*cur_transfer
;
104 struct chip_data
*cur_chip
;
117 void (*write
) (struct driver_data
*);
118 void (*read
) (struct driver_data
*);
119 void (*duplex
) (struct driver_data
*);
129 u8 width
; /* 0 or 1 */
131 u8 bits_per_word
; /* 8 or 16 */
132 u8 cs_change_per_word
;
134 void (*write
) (struct driver_data
*);
135 void (*read
) (struct driver_data
*);
136 void (*duplex
) (struct driver_data
*);
139 static void bfin_spi_enable(struct driver_data
*drv_data
)
144 write_CTRL(cr
| BIT_CTL_ENABLE
);
148 static void bfin_spi_disable(struct driver_data
*drv_data
)
153 write_CTRL(cr
& (~BIT_CTL_ENABLE
));
157 /* Caculate the SPI_BAUD register value based on input HZ */
158 static u16
hz_to_spi_baud(u32 speed_hz
)
160 u_long sclk
= get_sclk();
161 u16 spi_baud
= (sclk
/ (2 * speed_hz
));
163 if ((sclk
% (2 * speed_hz
)) > 0)
169 static int flush(struct driver_data
*drv_data
)
171 unsigned long limit
= loops_per_jiffy
<< 1;
173 /* wait for stop and clear stat */
174 while (!(read_STAT() & BIT_STAT_SPIF
) && limit
--)
177 write_STAT(BIT_STAT_CLR
);
182 /* stop controller and re-config current chip*/
183 static void restore_state(struct driver_data
*drv_data
)
185 struct chip_data
*chip
= drv_data
->cur_chip
;
187 /* Clear status and disable clock */
188 write_STAT(BIT_STAT_CLR
);
189 bfin_spi_disable(drv_data
);
190 dev_dbg(&drv_data
->pdev
->dev
, "restoring spi ctl state\n");
192 #if defined(CONFIG_BF534) || defined(CONFIG_BF536) || defined(CONFIG_BF537)
193 dev_dbg(&drv_data
->pdev
->dev
,
194 "chip select number is %d\n", chip
->chip_select_num
);
196 switch (chip
->chip_select_num
) {
198 bfin_write_PORTF_FER(bfin_read_PORTF_FER() | 0x3c00);
204 bfin_write_PORT_MUX(bfin_read_PORT_MUX() | PJSE_SPI
);
206 bfin_write_PORTF_FER(bfin_read_PORTF_FER() | 0x3800);
211 bfin_write_PORT_MUX(bfin_read_PORT_MUX() | PFS4E_SPI
);
213 bfin_write_PORTF_FER(bfin_read_PORTF_FER() | 0x3840);
218 bfin_write_PORT_MUX(bfin_read_PORT_MUX() | PFS5E_SPI
);
220 bfin_write_PORTF_FER(bfin_read_PORTF_FER() | 0x3820);
225 bfin_write_PORT_MUX(bfin_read_PORT_MUX() | PFS6E_SPI
);
227 bfin_write_PORTF_FER(bfin_read_PORTF_FER() | 0x3810);
232 bfin_write_PORT_MUX(bfin_read_PORT_MUX() | PJCE_SPI
);
234 bfin_write_PORTF_FER(bfin_read_PORTF_FER() | 0x3800);
240 /* Load the registers */
241 write_CTRL(chip
->ctl_reg
);
242 write_BAUD(chip
->baud
);
243 write_FLAG(chip
->flag
);
246 /* used to kick off transfer in rx mode */
247 static unsigned short dummy_read(void)
254 static void null_writer(struct driver_data
*drv_data
)
256 u8 n_bytes
= drv_data
->n_bytes
;
258 while (drv_data
->tx
< drv_data
->tx_end
) {
260 while ((read_STAT() & BIT_STAT_TXS
))
262 drv_data
->tx
+= n_bytes
;
266 static void null_reader(struct driver_data
*drv_data
)
268 u8 n_bytes
= drv_data
->n_bytes
;
271 while (drv_data
->rx
< drv_data
->rx_end
) {
272 while (!(read_STAT() & BIT_STAT_RXS
))
275 drv_data
->rx
+= n_bytes
;
279 static void u8_writer(struct driver_data
*drv_data
)
281 dev_dbg(&drv_data
->pdev
->dev
,
282 "cr8-s is 0x%x\n", read_STAT());
283 while (drv_data
->tx
< drv_data
->tx_end
) {
284 write_TDBR(*(u8
*) (drv_data
->tx
));
285 while (read_STAT() & BIT_STAT_TXS
)
290 /* poll for SPI completion before returning */
291 while (!(read_STAT() & BIT_STAT_SPIF
))
295 static void u8_cs_chg_writer(struct driver_data
*drv_data
)
297 struct chip_data
*chip
= drv_data
->cur_chip
;
299 while (drv_data
->tx
< drv_data
->tx_end
) {
300 write_FLAG(chip
->flag
);
303 write_TDBR(*(u8
*) (drv_data
->tx
));
304 while (read_STAT() & BIT_STAT_TXS
)
306 while (!(read_STAT() & BIT_STAT_SPIF
))
308 write_FLAG(0xFF00 | chip
->flag
);
310 if (chip
->cs_chg_udelay
)
311 udelay(chip
->cs_chg_udelay
);
318 static void u8_reader(struct driver_data
*drv_data
)
320 dev_dbg(&drv_data
->pdev
->dev
,
321 "cr-8 is 0x%x\n", read_STAT());
323 /* clear TDBR buffer before read(else it will be shifted out) */
328 while (drv_data
->rx
< drv_data
->rx_end
- 1) {
329 while (!(read_STAT() & BIT_STAT_RXS
))
331 *(u8
*) (drv_data
->rx
) = read_RDBR();
335 while (!(read_STAT() & BIT_STAT_RXS
))
337 *(u8
*) (drv_data
->rx
) = read_SHAW();
341 static void u8_cs_chg_reader(struct driver_data
*drv_data
)
343 struct chip_data
*chip
= drv_data
->cur_chip
;
345 while (drv_data
->rx
< drv_data
->rx_end
) {
346 write_FLAG(chip
->flag
);
349 read_RDBR(); /* kick off */
350 while (!(read_STAT() & BIT_STAT_RXS
))
352 while (!(read_STAT() & BIT_STAT_SPIF
))
354 *(u8
*) (drv_data
->rx
) = read_SHAW();
355 write_FLAG(0xFF00 | chip
->flag
);
357 if (chip
->cs_chg_udelay
)
358 udelay(chip
->cs_chg_udelay
);
365 static void u8_duplex(struct driver_data
*drv_data
)
367 /* in duplex mode, clk is triggered by writing of TDBR */
368 while (drv_data
->rx
< drv_data
->rx_end
) {
369 write_TDBR(*(u8
*) (drv_data
->tx
));
370 while (!(read_STAT() & BIT_STAT_SPIF
))
372 while (!(read_STAT() & BIT_STAT_RXS
))
374 *(u8
*) (drv_data
->rx
) = read_RDBR();
380 static void u8_cs_chg_duplex(struct driver_data
*drv_data
)
382 struct chip_data
*chip
= drv_data
->cur_chip
;
384 while (drv_data
->rx
< drv_data
->rx_end
) {
385 write_FLAG(chip
->flag
);
388 write_TDBR(*(u8
*) (drv_data
->tx
));
389 while (!(read_STAT() & BIT_STAT_SPIF
))
391 while (!(read_STAT() & BIT_STAT_RXS
))
393 *(u8
*) (drv_data
->rx
) = read_RDBR();
394 write_FLAG(0xFF00 | chip
->flag
);
396 if (chip
->cs_chg_udelay
)
397 udelay(chip
->cs_chg_udelay
);
405 static void u16_writer(struct driver_data
*drv_data
)
407 dev_dbg(&drv_data
->pdev
->dev
,
408 "cr16 is 0x%x\n", read_STAT());
410 while (drv_data
->tx
< drv_data
->tx_end
) {
411 write_TDBR(*(u16
*) (drv_data
->tx
));
412 while ((read_STAT() & BIT_STAT_TXS
))
417 /* poll for SPI completion before returning */
418 while (!(read_STAT() & BIT_STAT_SPIF
))
422 static void u16_cs_chg_writer(struct driver_data
*drv_data
)
424 struct chip_data
*chip
= drv_data
->cur_chip
;
426 while (drv_data
->tx
< drv_data
->tx_end
) {
427 write_FLAG(chip
->flag
);
430 write_TDBR(*(u16
*) (drv_data
->tx
));
431 while ((read_STAT() & BIT_STAT_TXS
))
433 while (!(read_STAT() & BIT_STAT_SPIF
))
435 write_FLAG(0xFF00 | chip
->flag
);
437 if (chip
->cs_chg_udelay
)
438 udelay(chip
->cs_chg_udelay
);
445 static void u16_reader(struct driver_data
*drv_data
)
447 dev_dbg(&drv_data
->pdev
->dev
,
448 "cr-16 is 0x%x\n", read_STAT());
451 while (drv_data
->rx
< (drv_data
->rx_end
- 2)) {
452 while (!(read_STAT() & BIT_STAT_RXS
))
454 *(u16
*) (drv_data
->rx
) = read_RDBR();
458 while (!(read_STAT() & BIT_STAT_RXS
))
460 *(u16
*) (drv_data
->rx
) = read_SHAW();
464 static void u16_cs_chg_reader(struct driver_data
*drv_data
)
466 struct chip_data
*chip
= drv_data
->cur_chip
;
468 while (drv_data
->rx
< drv_data
->rx_end
) {
469 write_FLAG(chip
->flag
);
472 read_RDBR(); /* kick off */
473 while (!(read_STAT() & BIT_STAT_RXS
))
475 while (!(read_STAT() & BIT_STAT_SPIF
))
477 *(u16
*) (drv_data
->rx
) = read_SHAW();
478 write_FLAG(0xFF00 | chip
->flag
);
480 if (chip
->cs_chg_udelay
)
481 udelay(chip
->cs_chg_udelay
);
488 static void u16_duplex(struct driver_data
*drv_data
)
490 /* in duplex mode, clk is triggered by writing of TDBR */
491 while (drv_data
->tx
< drv_data
->tx_end
) {
492 write_TDBR(*(u16
*) (drv_data
->tx
));
493 while (!(read_STAT() & BIT_STAT_SPIF
))
495 while (!(read_STAT() & BIT_STAT_RXS
))
497 *(u16
*) (drv_data
->rx
) = read_RDBR();
503 static void u16_cs_chg_duplex(struct driver_data
*drv_data
)
505 struct chip_data
*chip
= drv_data
->cur_chip
;
507 while (drv_data
->tx
< drv_data
->tx_end
) {
508 write_FLAG(chip
->flag
);
511 write_TDBR(*(u16
*) (drv_data
->tx
));
512 while (!(read_STAT() & BIT_STAT_SPIF
))
514 while (!(read_STAT() & BIT_STAT_RXS
))
516 *(u16
*) (drv_data
->rx
) = read_RDBR();
517 write_FLAG(0xFF00 | chip
->flag
);
519 if (chip
->cs_chg_udelay
)
520 udelay(chip
->cs_chg_udelay
);
528 /* test if ther is more transfer to be done */
529 static void *next_transfer(struct driver_data
*drv_data
)
531 struct spi_message
*msg
= drv_data
->cur_msg
;
532 struct spi_transfer
*trans
= drv_data
->cur_transfer
;
534 /* Move to next transfer */
535 if (trans
->transfer_list
.next
!= &msg
->transfers
) {
536 drv_data
->cur_transfer
=
537 list_entry(trans
->transfer_list
.next
,
538 struct spi_transfer
, transfer_list
);
539 return RUNNING_STATE
;
545 * caller already set message->status;
546 * dma and pio irqs are blocked give finished message back
548 static void giveback(struct driver_data
*drv_data
)
550 struct spi_transfer
*last_transfer
;
552 struct spi_message
*msg
;
554 spin_lock_irqsave(&drv_data
->lock
, flags
);
555 msg
= drv_data
->cur_msg
;
556 drv_data
->cur_msg
= NULL
;
557 drv_data
->cur_transfer
= NULL
;
558 drv_data
->cur_chip
= NULL
;
559 queue_work(drv_data
->workqueue
, &drv_data
->pump_messages
);
560 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
562 last_transfer
= list_entry(msg
->transfers
.prev
,
563 struct spi_transfer
, transfer_list
);
567 /* disable chip select signal. And not stop spi in autobuffer mode */
568 if (drv_data
->tx_dma
!= 0xFFFF) {
570 bfin_spi_disable(drv_data
);
574 msg
->complete(msg
->context
);
577 static irqreturn_t
dma_irq_handler(int irq
, void *dev_id
)
579 struct driver_data
*drv_data
= (struct driver_data
*)dev_id
;
580 struct spi_message
*msg
= drv_data
->cur_msg
;
582 dev_dbg(&drv_data
->pdev
->dev
, "in dma_irq_handler\n");
583 clear_dma_irqstat(CH_SPI
);
586 * wait for the last transaction shifted out. yes, these two
587 * while loops are supposed to be the same (see the HRM).
589 if (drv_data
->tx
!= NULL
) {
590 while (bfin_read_SPI_STAT() & TXS
)
592 while (bfin_read_SPI_STAT() & TXS
)
596 while (!(bfin_read_SPI_STAT() & SPIF
))
599 bfin_spi_disable(drv_data
);
601 msg
->actual_length
+= drv_data
->len_in_bytes
;
603 /* Move to next transfer */
604 msg
->state
= next_transfer(drv_data
);
606 /* Schedule transfer tasklet */
607 tasklet_schedule(&drv_data
->pump_transfers
);
609 /* free the irq handler before next transfer */
610 dev_dbg(&drv_data
->pdev
->dev
,
611 "disable dma channel irq%d\n",
613 dma_disable_irq(CH_SPI
);
618 static void pump_transfers(unsigned long data
)
620 struct driver_data
*drv_data
= (struct driver_data
*)data
;
621 struct spi_message
*message
= NULL
;
622 struct spi_transfer
*transfer
= NULL
;
623 struct spi_transfer
*previous
= NULL
;
624 struct chip_data
*chip
= NULL
;
626 u16 cr
, dma_width
, dma_config
;
627 u32 tranf_success
= 1;
629 /* Get current state information */
630 message
= drv_data
->cur_msg
;
631 transfer
= drv_data
->cur_transfer
;
632 chip
= drv_data
->cur_chip
;
635 * if msg is error or done, report it back using complete() callback
638 /* Handle for abort */
639 if (message
->state
== ERROR_STATE
) {
640 message
->status
= -EIO
;
645 /* Handle end of message */
646 if (message
->state
== DONE_STATE
) {
652 /* Delay if requested at end of transfer */
653 if (message
->state
== RUNNING_STATE
) {
654 previous
= list_entry(transfer
->transfer_list
.prev
,
655 struct spi_transfer
, transfer_list
);
656 if (previous
->delay_usecs
)
657 udelay(previous
->delay_usecs
);
660 /* Setup the transfer state based on the type of transfer */
661 if (flush(drv_data
) == 0) {
662 dev_err(&drv_data
->pdev
->dev
, "pump_transfers: flush failed\n");
663 message
->status
= -EIO
;
668 if (transfer
->tx_buf
!= NULL
) {
669 drv_data
->tx
= (void *)transfer
->tx_buf
;
670 drv_data
->tx_end
= drv_data
->tx
+ transfer
->len
;
671 dev_dbg(&drv_data
->pdev
->dev
, "tx_buf is %p, tx_end is %p\n",
672 transfer
->tx_buf
, drv_data
->tx_end
);
677 if (transfer
->rx_buf
!= NULL
) {
678 drv_data
->rx
= transfer
->rx_buf
;
679 drv_data
->rx_end
= drv_data
->rx
+ transfer
->len
;
680 dev_dbg(&drv_data
->pdev
->dev
, "rx_buf is %p, rx_end is %p\n",
681 transfer
->rx_buf
, drv_data
->rx_end
);
686 drv_data
->rx_dma
= transfer
->rx_dma
;
687 drv_data
->tx_dma
= transfer
->tx_dma
;
688 drv_data
->len_in_bytes
= transfer
->len
;
691 if (width
== CFG_SPI_WORDSIZE16
) {
692 drv_data
->len
= (transfer
->len
) >> 1;
694 drv_data
->len
= transfer
->len
;
696 drv_data
->write
= drv_data
->tx
? chip
->write
: null_writer
;
697 drv_data
->read
= drv_data
->rx
? chip
->read
: null_reader
;
698 drv_data
->duplex
= chip
->duplex
? chip
->duplex
: null_writer
;
699 dev_dbg(&drv_data
->pdev
->dev
,
700 "transfer: drv_data->write is %p, chip->write is %p, null_wr is %p\n",
701 drv_data
->write
, chip
->write
, null_writer
);
703 /* speed and width has been set on per message */
704 message
->state
= RUNNING_STATE
;
707 /* restore spi status for each spi transfer */
708 if (transfer
->speed_hz
) {
709 write_BAUD(hz_to_spi_baud(transfer
->speed_hz
));
711 write_BAUD(chip
->baud
);
713 write_FLAG(chip
->flag
);
715 dev_dbg(&drv_data
->pdev
->dev
,
716 "now pumping a transfer: width is %d, len is %d\n",
717 width
, transfer
->len
);
720 * Try to map dma buffer and do a dma transfer if
721 * successful use different way to r/w according to
722 * drv_data->cur_chip->enable_dma
724 if (drv_data
->cur_chip
->enable_dma
&& drv_data
->len
> 6) {
726 write_STAT(BIT_STAT_CLR
);
728 clear_dma_irqstat(CH_SPI
);
729 bfin_spi_disable(drv_data
);
731 /* config dma channel */
732 dev_dbg(&drv_data
->pdev
->dev
, "doing dma transfer\n");
733 if (width
== CFG_SPI_WORDSIZE16
) {
734 set_dma_x_count(CH_SPI
, drv_data
->len
);
735 set_dma_x_modify(CH_SPI
, 2);
736 dma_width
= WDSIZE_16
;
738 set_dma_x_count(CH_SPI
, drv_data
->len
);
739 set_dma_x_modify(CH_SPI
, 1);
740 dma_width
= WDSIZE_8
;
743 /* set transfer width,direction. And enable spi */
744 cr
= (read_CTRL() & (~BIT_CTL_TIMOD
));
746 /* dirty hack for autobuffer DMA mode */
747 if (drv_data
->tx_dma
== 0xFFFF) {
748 dev_dbg(&drv_data
->pdev
->dev
,
749 "doing autobuffer DMA out.\n");
751 /* no irq in autobuffer mode */
753 (DMAFLOW_AUTO
| RESTART
| dma_width
| DI_EN
);
754 set_dma_config(CH_SPI
, dma_config
);
755 set_dma_start_addr(CH_SPI
, (unsigned long)drv_data
->tx
);
757 write_CTRL(cr
| CFG_SPI_DMAWRITE
| (width
<< 8) |
758 (CFG_SPI_ENABLE
<< 14));
760 /* just return here, there can only be one transfer in this mode */
766 /* In dma mode, rx or tx must be NULL in one transfer */
767 if (drv_data
->rx
!= NULL
) {
768 /* set transfer mode, and enable SPI */
769 dev_dbg(&drv_data
->pdev
->dev
, "doing DMA in.\n");
771 /* disable SPI before write to TDBR */
772 write_CTRL(cr
& ~BIT_CTL_ENABLE
);
774 /* clear tx reg soformer data is not shifted out */
777 set_dma_x_count(CH_SPI
, drv_data
->len
);
780 dma_enable_irq(CH_SPI
);
781 dma_config
= (WNR
| RESTART
| dma_width
| DI_EN
);
782 set_dma_config(CH_SPI
, dma_config
);
783 set_dma_start_addr(CH_SPI
, (unsigned long)drv_data
->rx
);
787 CFG_SPI_DMAREAD
| (width
<< 8) | (CFG_SPI_ENABLE
<<
789 /* set transfer mode, and enable SPI */
791 } else if (drv_data
->tx
!= NULL
) {
792 dev_dbg(&drv_data
->pdev
->dev
, "doing DMA out.\n");
795 dma_enable_irq(CH_SPI
);
796 dma_config
= (RESTART
| dma_width
| DI_EN
);
797 set_dma_config(CH_SPI
, dma_config
);
798 set_dma_start_addr(CH_SPI
, (unsigned long)drv_data
->tx
);
801 write_CTRL(cr
| CFG_SPI_DMAWRITE
| (width
<< 8) |
802 (CFG_SPI_ENABLE
<< 14));
806 /* IO mode write then read */
807 dev_dbg(&drv_data
->pdev
->dev
, "doing IO transfer\n");
809 write_STAT(BIT_STAT_CLR
);
811 if (drv_data
->tx
!= NULL
&& drv_data
->rx
!= NULL
) {
812 /* full duplex mode */
813 BUG_ON((drv_data
->tx_end
- drv_data
->tx
) !=
814 (drv_data
->rx_end
- drv_data
->rx
));
815 cr
= (read_CTRL() & (~BIT_CTL_TIMOD
));
816 cr
|= CFG_SPI_WRITE
| (width
<< 8) |
817 (CFG_SPI_ENABLE
<< 14);
818 dev_dbg(&drv_data
->pdev
->dev
,
819 "IO duplex: cr is 0x%x\n", cr
);
824 drv_data
->duplex(drv_data
);
826 if (drv_data
->tx
!= drv_data
->tx_end
)
828 } else if (drv_data
->tx
!= NULL
) {
829 /* write only half duplex */
830 cr
= (read_CTRL() & (~BIT_CTL_TIMOD
));
831 cr
|= CFG_SPI_WRITE
| (width
<< 8) |
832 (CFG_SPI_ENABLE
<< 14);
833 dev_dbg(&drv_data
->pdev
->dev
,
834 "IO write: cr is 0x%x\n", cr
);
839 drv_data
->write(drv_data
);
841 if (drv_data
->tx
!= drv_data
->tx_end
)
843 } else if (drv_data
->rx
!= NULL
) {
844 /* read only half duplex */
845 cr
= (read_CTRL() & (~BIT_CTL_TIMOD
));
846 cr
|= CFG_SPI_READ
| (width
<< 8) |
847 (CFG_SPI_ENABLE
<< 14);
848 dev_dbg(&drv_data
->pdev
->dev
,
849 "IO read: cr is 0x%x\n", cr
);
854 drv_data
->read(drv_data
);
855 if (drv_data
->rx
!= drv_data
->rx_end
)
859 if (!tranf_success
) {
860 dev_dbg(&drv_data
->pdev
->dev
,
861 "IO write error!\n");
862 message
->state
= ERROR_STATE
;
864 /* Update total byte transfered */
865 message
->actual_length
+= drv_data
->len
;
867 /* Move to next transfer of this msg */
868 message
->state
= next_transfer(drv_data
);
871 /* Schedule next transfer tasklet */
872 tasklet_schedule(&drv_data
->pump_transfers
);
877 /* pop a msg from queue and kick off real transfer */
878 static void pump_messages(struct work_struct
*work
)
880 struct driver_data
*drv_data
= container_of(work
, struct driver_data
, pump_messages
);
883 /* Lock queue and check for queue work */
884 spin_lock_irqsave(&drv_data
->lock
, flags
);
885 if (list_empty(&drv_data
->queue
) || drv_data
->run
== QUEUE_STOPPED
) {
886 /* pumper kicked off but no work to do */
888 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
892 /* Make sure we are not already running a message */
893 if (drv_data
->cur_msg
) {
894 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
898 /* Extract head of queue */
899 drv_data
->cur_msg
= list_entry(drv_data
->queue
.next
,
900 struct spi_message
, queue
);
901 list_del_init(&drv_data
->cur_msg
->queue
);
903 /* Initial message state */
904 drv_data
->cur_msg
->state
= START_STATE
;
905 drv_data
->cur_transfer
= list_entry(drv_data
->cur_msg
->transfers
.next
,
906 struct spi_transfer
, transfer_list
);
908 /* Setup the SSP using the per chip configuration */
909 drv_data
->cur_chip
= spi_get_ctldata(drv_data
->cur_msg
->spi
);
910 restore_state(drv_data
);
911 dev_dbg(&drv_data
->pdev
->dev
,
912 "got a message to pump, state is set to: baud %d, flag 0x%x, ctl 0x%x\n",
913 drv_data
->cur_chip
->baud
, drv_data
->cur_chip
->flag
,
914 drv_data
->cur_chip
->ctl_reg
);
916 dev_dbg(&drv_data
->pdev
->dev
,
917 "the first transfer len is %d\n",
918 drv_data
->cur_transfer
->len
);
920 /* Mark as busy and launch transfers */
921 tasklet_schedule(&drv_data
->pump_transfers
);
924 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
928 * got a msg to transfer, queue it in drv_data->queue.
929 * And kick off message pumper
931 static int transfer(struct spi_device
*spi
, struct spi_message
*msg
)
933 struct driver_data
*drv_data
= spi_master_get_devdata(spi
->master
);
936 spin_lock_irqsave(&drv_data
->lock
, flags
);
938 if (drv_data
->run
== QUEUE_STOPPED
) {
939 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
943 msg
->actual_length
= 0;
944 msg
->status
= -EINPROGRESS
;
945 msg
->state
= START_STATE
;
947 dev_dbg(&spi
->dev
, "adding an msg in transfer() \n");
948 list_add_tail(&msg
->queue
, &drv_data
->queue
);
950 if (drv_data
->run
== QUEUE_RUNNING
&& !drv_data
->busy
)
951 queue_work(drv_data
->workqueue
, &drv_data
->pump_messages
);
953 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
958 /* first setup for new devices */
959 static int setup(struct spi_device
*spi
)
961 struct bfin5xx_spi_chip
*chip_info
= NULL
;
962 struct chip_data
*chip
;
963 struct driver_data
*drv_data
= spi_master_get_devdata(spi
->master
);
966 /* Abort device setup if requested features are not supported */
967 if (spi
->mode
& ~(SPI_CPOL
| SPI_CPHA
| SPI_LSB_FIRST
)) {
968 dev_err(&spi
->dev
, "requested mode not fully supported\n");
972 /* Zero (the default) here means 8 bits */
973 if (!spi
->bits_per_word
)
974 spi
->bits_per_word
= 8;
976 if (spi
->bits_per_word
!= 8 && spi
->bits_per_word
!= 16)
979 /* Only alloc (or use chip_info) on first setup */
980 chip
= spi_get_ctldata(spi
);
982 chip
= kzalloc(sizeof(struct chip_data
), GFP_KERNEL
);
986 chip
->enable_dma
= 0;
987 chip_info
= spi
->controller_data
;
990 /* chip_info isn't always needed */
992 chip
->enable_dma
= chip_info
->enable_dma
!= 0
993 && drv_data
->master_info
->enable_dma
;
994 chip
->ctl_reg
= chip_info
->ctl_reg
;
995 chip
->bits_per_word
= chip_info
->bits_per_word
;
996 chip
->cs_change_per_word
= chip_info
->cs_change_per_word
;
997 chip
->cs_chg_udelay
= chip_info
->cs_chg_udelay
;
1000 /* translate common spi framework into our register */
1001 if (spi
->mode
& SPI_CPOL
)
1002 chip
->ctl_reg
|= CPOL
;
1003 if (spi
->mode
& SPI_CPHA
)
1004 chip
->ctl_reg
|= CPHA
;
1005 if (spi
->mode
& SPI_LSB_FIRST
)
1006 chip
->ctl_reg
|= LSBF
;
1007 /* we dont support running in slave mode (yet?) */
1008 chip
->ctl_reg
|= MSTR
;
1011 * if any one SPI chip is registered and wants DMA, request the
1012 * DMA channel for it
1014 if (chip
->enable_dma
&& !dma_requested
) {
1015 /* register dma irq handler */
1016 if (request_dma(CH_SPI
, "BF53x_SPI_DMA") < 0) {
1018 "Unable to request BlackFin SPI DMA channel\n");
1021 if (set_dma_callback(CH_SPI
, (void *)dma_irq_handler
, drv_data
)
1023 dev_dbg(&spi
->dev
, "Unable to set dma callback\n");
1026 dma_disable_irq(CH_SPI
);
1031 * Notice: for blackfin, the speed_hz is the value of register
1032 * SPI_BAUD, not the real baudrate
1034 chip
->baud
= hz_to_spi_baud(spi
->max_speed_hz
);
1035 spi_flg
= ~(1 << (spi
->chip_select
));
1036 chip
->flag
= ((u16
) spi_flg
<< 8) | (1 << (spi
->chip_select
));
1037 chip
->chip_select_num
= spi
->chip_select
;
1039 switch (chip
->bits_per_word
) {
1042 chip
->width
= CFG_SPI_WORDSIZE8
;
1043 chip
->read
= chip
->cs_change_per_word
?
1044 u8_cs_chg_reader
: u8_reader
;
1045 chip
->write
= chip
->cs_change_per_word
?
1046 u8_cs_chg_writer
: u8_writer
;
1047 chip
->duplex
= chip
->cs_change_per_word
?
1048 u8_cs_chg_duplex
: u8_duplex
;
1053 chip
->width
= CFG_SPI_WORDSIZE16
;
1054 chip
->read
= chip
->cs_change_per_word
?
1055 u16_cs_chg_reader
: u16_reader
;
1056 chip
->write
= chip
->cs_change_per_word
?
1057 u16_cs_chg_writer
: u16_writer
;
1058 chip
->duplex
= chip
->cs_change_per_word
?
1059 u16_cs_chg_duplex
: u16_duplex
;
1063 dev_err(&spi
->dev
, "%d bits_per_word is not supported\n",
1064 chip
->bits_per_word
);
1069 dev_dbg(&spi
->dev
, "setup spi chip %s, width is %d, dma is %d,",
1070 spi
->modalias
, chip
->width
, chip
->enable_dma
);
1071 dev_dbg(&spi
->dev
, "ctl_reg is 0x%x, flag_reg is 0x%x\n",
1072 chip
->ctl_reg
, chip
->flag
);
1074 spi_set_ctldata(spi
, chip
);
1080 * callback for spi framework.
1081 * clean driver specific data
1083 static void cleanup(struct spi_device
*spi
)
1085 struct chip_data
*chip
= spi_get_ctldata((struct spi_device
*)spi
);
1090 static inline int init_queue(struct driver_data
*drv_data
)
1092 INIT_LIST_HEAD(&drv_data
->queue
);
1093 spin_lock_init(&drv_data
->lock
);
1095 drv_data
->run
= QUEUE_STOPPED
;
1098 /* init transfer tasklet */
1099 tasklet_init(&drv_data
->pump_transfers
,
1100 pump_transfers
, (unsigned long)drv_data
);
1102 /* init messages workqueue */
1103 INIT_WORK(&drv_data
->pump_messages
, pump_messages
);
1104 drv_data
->workqueue
=
1105 create_singlethread_workqueue(drv_data
->master
->cdev
.dev
->bus_id
);
1106 if (drv_data
->workqueue
== NULL
)
1112 static inline int start_queue(struct driver_data
*drv_data
)
1114 unsigned long flags
;
1116 spin_lock_irqsave(&drv_data
->lock
, flags
);
1118 if (drv_data
->run
== QUEUE_RUNNING
|| drv_data
->busy
) {
1119 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
1123 drv_data
->run
= QUEUE_RUNNING
;
1124 drv_data
->cur_msg
= NULL
;
1125 drv_data
->cur_transfer
= NULL
;
1126 drv_data
->cur_chip
= NULL
;
1127 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
1129 queue_work(drv_data
->workqueue
, &drv_data
->pump_messages
);
1134 static inline int stop_queue(struct driver_data
*drv_data
)
1136 unsigned long flags
;
1137 unsigned limit
= 500;
1140 spin_lock_irqsave(&drv_data
->lock
, flags
);
1143 * This is a bit lame, but is optimized for the common execution path.
1144 * A wait_queue on the drv_data->busy could be used, but then the common
1145 * execution path (pump_messages) would be required to call wake_up or
1146 * friends on every SPI message. Do this instead
1148 drv_data
->run
= QUEUE_STOPPED
;
1149 while (!list_empty(&drv_data
->queue
) && drv_data
->busy
&& limit
--) {
1150 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
1152 spin_lock_irqsave(&drv_data
->lock
, flags
);
1155 if (!list_empty(&drv_data
->queue
) || drv_data
->busy
)
1158 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
1163 static inline int destroy_queue(struct driver_data
*drv_data
)
1167 status
= stop_queue(drv_data
);
1171 destroy_workqueue(drv_data
->workqueue
);
1176 static int __init
bfin5xx_spi_probe(struct platform_device
*pdev
)
1178 struct device
*dev
= &pdev
->dev
;
1179 struct bfin5xx_spi_master
*platform_info
;
1180 struct spi_master
*master
;
1181 struct driver_data
*drv_data
= 0;
1184 platform_info
= dev
->platform_data
;
1186 /* Allocate master with space for drv_data */
1187 master
= spi_alloc_master(dev
, sizeof(struct driver_data
) + 16);
1189 dev_err(&pdev
->dev
, "can not alloc spi_master\n");
1192 drv_data
= spi_master_get_devdata(master
);
1193 drv_data
->master
= master
;
1194 drv_data
->master_info
= platform_info
;
1195 drv_data
->pdev
= pdev
;
1197 master
->bus_num
= pdev
->id
;
1198 master
->num_chipselect
= platform_info
->num_chipselect
;
1199 master
->cleanup
= cleanup
;
1200 master
->setup
= setup
;
1201 master
->transfer
= transfer
;
1203 /* Initial and start queue */
1204 status
= init_queue(drv_data
);
1206 dev_err(&pdev
->dev
, "problem initializing queue\n");
1207 goto out_error_queue_alloc
;
1209 status
= start_queue(drv_data
);
1211 dev_err(&pdev
->dev
, "problem starting queue\n");
1212 goto out_error_queue_alloc
;
1215 /* Register with the SPI framework */
1216 platform_set_drvdata(pdev
, drv_data
);
1217 status
= spi_register_master(master
);
1219 dev_err(&pdev
->dev
, "problem registering spi master\n");
1220 goto out_error_queue_alloc
;
1222 dev_dbg(&pdev
->dev
, "controller probe successfully\n");
1225 out_error_queue_alloc
:
1226 destroy_queue(drv_data
);
1227 spi_master_put(master
);
1231 /* stop hardware and remove the driver */
1232 static int __devexit
bfin5xx_spi_remove(struct platform_device
*pdev
)
1234 struct driver_data
*drv_data
= platform_get_drvdata(pdev
);
1240 /* Remove the queue */
1241 status
= destroy_queue(drv_data
);
1245 /* Disable the SSP at the peripheral and SOC level */
1246 bfin_spi_disable(drv_data
);
1249 if (drv_data
->master_info
->enable_dma
) {
1250 if (dma_channel_active(CH_SPI
))
1254 /* Disconnect from the SPI framework */
1255 spi_unregister_master(drv_data
->master
);
1257 /* Prevent double remove */
1258 platform_set_drvdata(pdev
, NULL
);
1264 static int bfin5xx_spi_suspend(struct platform_device
*pdev
, pm_message_t state
)
1266 struct driver_data
*drv_data
= platform_get_drvdata(pdev
);
1269 status
= stop_queue(drv_data
);
1274 bfin_spi_disable(drv_data
);
1279 static int bfin5xx_spi_resume(struct platform_device
*pdev
)
1281 struct driver_data
*drv_data
= platform_get_drvdata(pdev
);
1284 /* Enable the SPI interface */
1285 bfin_spi_enable(drv_data
);
1287 /* Start the queue running */
1288 status
= start_queue(drv_data
);
1290 dev_err(&pdev
->dev
, "problem starting queue (%d)\n", status
);
1297 #define bfin5xx_spi_suspend NULL
1298 #define bfin5xx_spi_resume NULL
1299 #endif /* CONFIG_PM */
1301 static struct platform_driver bfin5xx_spi_driver
= {
1303 .name
= "bfin-spi-master",
1304 .owner
= THIS_MODULE
,
1306 .suspend
= bfin5xx_spi_suspend
,
1307 .resume
= bfin5xx_spi_resume
,
1308 .remove
= __devexit_p(bfin5xx_spi_remove
),
1311 static int __init
bfin5xx_spi_init(void)
1313 return platform_driver_probe(&bfin5xx_spi_driver
, bfin5xx_spi_probe
);
1315 module_init(bfin5xx_spi_init
);
1317 static void __exit
bfin5xx_spi_exit(void)
1319 platform_driver_unregister(&bfin5xx_spi_driver
);
1321 module_exit(bfin5xx_spi_exit
);