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V4L/DVB (11321): pxa_camera: Redesign DMA handling
[linux-2.6/verdex.git] / drivers / media / video / pxa_camera.c
bloba2f98ec14d9a35cd618ceed86d97d6777c720610
1 /*
2 * V4L2 Driver for PXA camera host
3 *
4 * Copyright (C) 2006, Sascha Hauer, Pengutronix
5 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/io.h>
16 #include <linux/delay.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/errno.h>
19 #include <linux/fs.h>
20 #include <linux/interrupt.h>
21 #include <linux/kernel.h>
22 #include <linux/mm.h>
23 #include <linux/moduleparam.h>
24 #include <linux/time.h>
25 #include <linux/version.h>
26 #include <linux/device.h>
27 #include <linux/platform_device.h>
28 #include <linux/clk.h>
29
30 #include <media/v4l2-common.h>
31 #include <media/v4l2-dev.h>
32 #include <media/videobuf-dma-sg.h>
33 #include <media/soc_camera.h>
34
35 #include <linux/videodev2.h>
36
37 #include <mach/dma.h>
38 #include <mach/camera.h>
39
40 #define PXA_CAM_VERSION_CODE KERNEL_VERSION(0, 0, 5)
41 #define PXA_CAM_DRV_NAME "pxa27x-camera"
42
43 /* Camera Interface */
44 #define CICR0 0x0000
45 #define CICR1 0x0004
46 #define CICR2 0x0008
47 #define CICR3 0x000C
48 #define CICR4 0x0010
49 #define CISR 0x0014
50 #define CIFR 0x0018
51 #define CITOR 0x001C
52 #define CIBR0 0x0028
53 #define CIBR1 0x0030
54 #define CIBR2 0x0038
55
56 #define CICR0_DMAEN (1 << 31) /* DMA request enable */
57 #define CICR0_PAR_EN (1 << 30) /* Parity enable */
58 #define CICR0_SL_CAP_EN (1 << 29) /* Capture enable for slave mode */
59 #define CICR0_ENB (1 << 28) /* Camera interface enable */
60 #define CICR0_DIS (1 << 27) /* Camera interface disable */
61 #define CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */
62 #define CICR0_TOM (1 << 9) /* Time-out mask */
63 #define CICR0_RDAVM (1 << 8) /* Receive-data-available mask */
64 #define CICR0_FEM (1 << 7) /* FIFO-empty mask */
65 #define CICR0_EOLM (1 << 6) /* End-of-line mask */
66 #define CICR0_PERRM (1 << 5) /* Parity-error mask */
67 #define CICR0_QDM (1 << 4) /* Quick-disable mask */
68 #define CICR0_CDM (1 << 3) /* Disable-done mask */
69 #define CICR0_SOFM (1 << 2) /* Start-of-frame mask */
70 #define CICR0_EOFM (1 << 1) /* End-of-frame mask */
71 #define CICR0_FOM (1 << 0) /* FIFO-overrun mask */
72
73 #define CICR1_TBIT (1 << 31) /* Transparency bit */
74 #define CICR1_RGBT_CONV (0x3 << 29) /* RGBT conversion mask */
75 #define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */
76 #define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */
77 #define CICR1_RGB_F (1 << 11) /* RGB format */
78 #define CICR1_YCBCR_F (1 << 10) /* YCbCr format */
79 #define CICR1_RGB_BPP (0x7 << 7) /* RGB bis per pixel mask */
80 #define CICR1_RAW_BPP (0x3 << 5) /* Raw bis per pixel mask */
81 #define CICR1_COLOR_SP (0x3 << 3) /* Color space mask */
82 #define CICR1_DW (0x7 << 0) /* Data width mask */
83
84 #define CICR2_BLW (0xff << 24) /* Beginning-of-line pixel clock
85 wait count mask */
86 #define CICR2_ELW (0xff << 16) /* End-of-line pixel clock
87 wait count mask */
88 #define CICR2_HSW (0x3f << 10) /* Horizontal sync pulse width mask */
89 #define CICR2_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
90 wait count mask */
91 #define CICR2_FSW (0x7 << 0) /* Frame stabilization
92 wait count mask */
93
94 #define CICR3_BFW (0xff << 24) /* Beginning-of-frame line clock
95 wait count mask */
96 #define CICR3_EFW (0xff << 16) /* End-of-frame line clock
97 wait count mask */
98 #define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */
99 #define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
100 wait count mask */
101 #define CICR3_LPF (0x7ff << 0) /* Lines per frame mask */
102
103 #define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */
104 #define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */
105 #define CICR4_PCP (1 << 22) /* Pixel clock polarity */
106 #define CICR4_HSP (1 << 21) /* Horizontal sync polarity */
107 #define CICR4_VSP (1 << 20) /* Vertical sync polarity */
108 #define CICR4_MCLK_EN (1 << 19) /* MCLK enable */
109 #define CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */
110 #define CICR4_DIV (0xff << 0) /* Clock divisor mask */
111
112 #define CISR_FTO (1 << 15) /* FIFO time-out */
113 #define CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */
114 #define CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */
115 #define CISR_RDAV_0 (1 << 12) /* Channel 0 receive data available */
116 #define CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO empty */
117 #define CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO empty */
118 #define CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO empty */
119 #define CISR_EOL (1 << 8) /* End of line */
120 #define CISR_PAR_ERR (1 << 7) /* Parity error */
121 #define CISR_CQD (1 << 6) /* Camera interface quick disable */
122 #define CISR_CDD (1 << 5) /* Camera interface disable done */
123 #define CISR_SOF (1 << 4) /* Start of frame */
124 #define CISR_EOF (1 << 3) /* End of frame */
125 #define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */
126 #define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */
127 #define CISR_IFO_0 (1 << 0) /* FIFO overrun for Channel 0 */
128
129 #define CIFR_FLVL2 (0x7f << 23) /* FIFO 2 level mask */
130 #define CIFR_FLVL1 (0x7f << 16) /* FIFO 1 level mask */
131 #define CIFR_FLVL0 (0xff << 8) /* FIFO 0 level mask */
132 #define CIFR_THL_0 (0x3 << 4) /* Threshold Level for Channel 0 FIFO */
133 #define CIFR_RESET_F (1 << 3) /* Reset input FIFOs */
134 #define CIFR_FEN2 (1 << 2) /* FIFO enable for channel 2 */
135 #define CIFR_FEN1 (1 << 1) /* FIFO enable for channel 1 */
136 #define CIFR_FEN0 (1 << 0) /* FIFO enable for channel 0 */
137
138 #define CICR0_SIM_MP (0 << 24)
139 #define CICR0_SIM_SP (1 << 24)
140 #define CICR0_SIM_MS (2 << 24)
141 #define CICR0_SIM_EP (3 << 24)
142 #define CICR0_SIM_ES (4 << 24)
143
144 #define CICR1_DW_VAL(x) ((x) & CICR1_DW) /* Data bus width */
145 #define CICR1_PPL_VAL(x) (((x) << 15) & CICR1_PPL) /* Pixels per line */
146 #define CICR1_COLOR_SP_VAL(x) (((x) << 3) & CICR1_COLOR_SP) /* color space */
147 #define CICR1_RGB_BPP_VAL(x) (((x) << 7) & CICR1_RGB_BPP) /* bpp for rgb */
148 #define CICR1_RGBT_CONV_VAL(x) (((x) << 29) & CICR1_RGBT_CONV) /* rgbt conv */
149
150 #define CICR2_BLW_VAL(x) (((x) << 24) & CICR2_BLW) /* Beginning-of-line pixel clock wait count */
151 #define CICR2_ELW_VAL(x) (((x) << 16) & CICR2_ELW) /* End-of-line pixel clock wait count */
152 #define CICR2_HSW_VAL(x) (((x) << 10) & CICR2_HSW) /* Horizontal sync pulse width */
153 #define CICR2_BFPW_VAL(x) (((x) << 3) & CICR2_BFPW) /* Beginning-of-frame pixel clock wait count */
154 #define CICR2_FSW_VAL(x) (((x) << 0) & CICR2_FSW) /* Frame stabilization wait count */
155
156 #define CICR3_BFW_VAL(x) (((x) << 24) & CICR3_BFW) /* Beginning-of-frame line clock wait count */
157 #define CICR3_EFW_VAL(x) (((x) << 16) & CICR3_EFW) /* End-of-frame line clock wait count */
158 #define CICR3_VSW_VAL(x) (((x) << 11) & CICR3_VSW) /* Vertical sync pulse width */
159 #define CICR3_LPF_VAL(x) (((x) << 0) & CICR3_LPF) /* Lines per frame */
160
161 #define CICR0_IRQ_MASK (CICR0_TOM | CICR0_RDAVM | CICR0_FEM | CICR0_EOLM | \
162 CICR0_PERRM | CICR0_QDM | CICR0_CDM | CICR0_SOFM | \
163 CICR0_EOFM | CICR0_FOM)
164
165 /*
166 * YUV422P picture size should be a multiple of 16, so the heuristic aligns
167 * height, width on 4 byte boundaries to reach the 16 multiple for the size.
168 */
169 #define YUV422P_X_Y_ALIGN 4
170 #define YUV422P_SIZE_ALIGN YUV422P_X_Y_ALIGN * YUV422P_X_Y_ALIGN
171
172 /*
173 * Structures
174 */
175 enum pxa_camera_active_dma {
176 DMA_Y = 0x1,
177 DMA_U = 0x2,
178 DMA_V = 0x4,
179 };
180
181 /* descriptor needed for the PXA DMA engine */
182 struct pxa_cam_dma {
183 dma_addr_t sg_dma;
184 struct pxa_dma_desc *sg_cpu;
185 size_t sg_size;
186 int sglen;
187 };
188
189 /* buffer for one video frame */
190 struct pxa_buffer {
191 /* common v4l buffer stuff -- must be first */
192 struct videobuf_buffer vb;
193
194 const struct soc_camera_data_format *fmt;
195
196 /* our descriptor lists for Y, U and V channels */
197 struct pxa_cam_dma dmas[3];
198
199 int inwork;
200
201 enum pxa_camera_active_dma active_dma;
202 };
203
204 struct pxa_camera_dev {
205 struct device *dev;
206 /* PXA27x is only supposed to handle one camera on its Quick Capture
207 * interface. If anyone ever builds hardware to enable more than
208 * one camera, they will have to modify this driver too */
209 struct soc_camera_device *icd;
210 struct clk *clk;
211
212 unsigned int irq;
213 void __iomem *base;
214
215 int channels;
216 unsigned int dma_chans[3];
217
218 struct pxacamera_platform_data *pdata;
219 struct resource *res;
220 unsigned long platform_flags;
221 unsigned long ciclk;
222 unsigned long mclk;
223 u32 mclk_divisor;
224
225 struct list_head capture;
226
227 spinlock_t lock;
228
229 struct pxa_buffer *active;
230 struct pxa_dma_desc *sg_tail[3];
231
232 u32 save_cicr[5];
233 };
234
235 static const char *pxa_cam_driver_description = "PXA_Camera";
236
237 static unsigned int vid_limit = 16; /* Video memory limit, in Mb */
238
239 /*
240 * Videobuf operations
241 */
242 static int pxa_videobuf_setup(struct videobuf_queue *vq, unsigned int *count,
243 unsigned int *size)
244 {
245 struct soc_camera_device *icd = vq->priv_data;
246
247 dev_dbg(&icd->dev, "count=%d, size=%d\n", *count, *size);
248
249 *size = roundup(icd->width * icd->height *
250 ((icd->current_fmt->depth + 7) >> 3), 8);
251
252 if (0 == *count)
253 *count = 32;
254 while (*size * *count > vid_limit * 1024 * 1024)
255 (*count)--;
256
257 return 0;
258 }
259
260 static void free_buffer(struct videobuf_queue *vq, struct pxa_buffer *buf)
261 {
262 struct soc_camera_device *icd = vq->priv_data;
263 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
264 struct pxa_camera_dev *pcdev = ici->priv;
265 struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb);
266 int i;
267
268 BUG_ON(in_interrupt());
269
270 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
271 &buf->vb, buf->vb.baddr, buf->vb.bsize);
272
273 /* This waits until this buffer is out of danger, i.e., until it is no
274 * longer in STATE_QUEUED or STATE_ACTIVE */
275 videobuf_waiton(&buf->vb, 0, 0);
276 videobuf_dma_unmap(vq, dma);
277 videobuf_dma_free(dma);
278
279 for (i = 0; i < ARRAY_SIZE(buf->dmas); i++) {
280 if (buf->dmas[i].sg_cpu)
281 dma_free_coherent(pcdev->dev, buf->dmas[i].sg_size,
282 buf->dmas[i].sg_cpu,
283 buf->dmas[i].sg_dma);
284 buf->dmas[i].sg_cpu = NULL;
285 }
286
287 buf->vb.state = VIDEOBUF_NEEDS_INIT;
288 }
289
290 static int calculate_dma_sglen(struct scatterlist *sglist, int sglen,
291 int sg_first_ofs, int size)
292 {
293 int i, offset, dma_len, xfer_len;
294 struct scatterlist *sg;
295
296 offset = sg_first_ofs;
297 for_each_sg(sglist, sg, sglen, i) {
298 dma_len = sg_dma_len(sg);
299
300 /* PXA27x Developer's Manual 27.4.4.1: round up to 8 bytes */
301 xfer_len = roundup(min(dma_len - offset, size), 8);
302
303 size = max(0, size - xfer_len);
304 offset = 0;
305 if (size == 0)
306 break;
307 }
308
309 BUG_ON(size != 0);
310 return i + 1;
311 }
312
313 /**
314 * pxa_init_dma_channel - init dma descriptors
315 * @pcdev: pxa camera device
316 * @buf: pxa buffer to find pxa dma channel
317 * @dma: dma video buffer
318 * @channel: dma channel (0 => 'Y', 1 => 'U', 2 => 'V')
319 * @cibr: camera Receive Buffer Register
320 * @size: bytes to transfer
321 * @sg_first: first element of sg_list
322 * @sg_first_ofs: offset in first element of sg_list
323 *
324 * Prepares the pxa dma descriptors to transfer one camera channel.
325 * Beware sg_first and sg_first_ofs are both input and output parameters.
326 *
327 * Returns 0 or -ENOMEM if no coherent memory is available
328 */
329 static int pxa_init_dma_channel(struct pxa_camera_dev *pcdev,
330 struct pxa_buffer *buf,
331 struct videobuf_dmabuf *dma, int channel,
332 int cibr, int size,
333 struct scatterlist **sg_first, int *sg_first_ofs)
334 {
335 struct pxa_cam_dma *pxa_dma = &buf->dmas[channel];
336 struct scatterlist *sg;
337 int i, offset, sglen;
338 int dma_len = 0, xfer_len = 0;
339
340 if (pxa_dma->sg_cpu)
341 dma_free_coherent(pcdev->dev, pxa_dma->sg_size,
342 pxa_dma->sg_cpu, pxa_dma->sg_dma);
343
344 sglen = calculate_dma_sglen(*sg_first, dma->sglen,
345 *sg_first_ofs, size);
346
347 pxa_dma->sg_size = (sglen + 1) * sizeof(struct pxa_dma_desc);
348 pxa_dma->sg_cpu = dma_alloc_coherent(pcdev->dev, pxa_dma->sg_size,
349 &pxa_dma->sg_dma, GFP_KERNEL);
350 if (!pxa_dma->sg_cpu)
351 return -ENOMEM;
352
353 pxa_dma->sglen = sglen;
354 offset = *sg_first_ofs;
355
356 dev_dbg(pcdev->dev, "DMA: sg_first=%p, sglen=%d, ofs=%d, dma.desc=%x\n",
357 *sg_first, sglen, *sg_first_ofs, pxa_dma->sg_dma);
358
359
360 for_each_sg(*sg_first, sg, sglen, i) {
361 dma_len = sg_dma_len(sg);
362
363 /* PXA27x Developer's Manual 27.4.4.1: round up to 8 bytes */
364 xfer_len = roundup(min(dma_len - offset, size), 8);
365
366 size = max(0, size - xfer_len);
367
368 pxa_dma->sg_cpu[i].dsadr = pcdev->res->start + cibr;
369 pxa_dma->sg_cpu[i].dtadr = sg_dma_address(sg) + offset;
370 pxa_dma->sg_cpu[i].dcmd =
371 DCMD_FLOWSRC | DCMD_BURST8 | DCMD_INCTRGADDR | xfer_len;
372 #ifdef DEBUG
373 if (!i)
374 pxa_dma->sg_cpu[i].dcmd |= DCMD_STARTIRQEN;
375 #endif
376 pxa_dma->sg_cpu[i].ddadr =
377 pxa_dma->sg_dma + (i + 1) * sizeof(struct pxa_dma_desc);
378
379 dev_vdbg(pcdev->dev, "DMA: desc.%08x->@phys=0x%08x, len=%d\n",
380 pxa_dma->sg_dma + i * sizeof(struct pxa_dma_desc),
381 sg_dma_address(sg) + offset, xfer_len);
382 offset = 0;
383
384 if (size == 0)
385 break;
386 }
387
388 pxa_dma->sg_cpu[sglen].ddadr = DDADR_STOP;
389 pxa_dma->sg_cpu[sglen].dcmd = DCMD_FLOWSRC | DCMD_BURST8 | DCMD_ENDIRQEN;
390
391 /*
392 * Handle 1 special case :
393 * - in 3 planes (YUV422P format), we might finish with xfer_len equal
394 * to dma_len (end on PAGE boundary). In this case, the sg element
395 * for next plane should be the next after the last used to store the
396 * last scatter gather RAM page
397 */
398 if (xfer_len >= dma_len) {
399 *sg_first_ofs = xfer_len - dma_len;
400 *sg_first = sg_next(sg);
401 } else {
402 *sg_first_ofs = xfer_len;
403 *sg_first = sg;
404 }
405
406 return 0;
407 }
408
409 static void pxa_videobuf_set_actdma(struct pxa_camera_dev *pcdev,
410 struct pxa_buffer *buf)
411 {
412 buf->active_dma = DMA_Y;
413 if (pcdev->channels == 3)
414 buf->active_dma |= DMA_U | DMA_V;
415 }
416
417 /*
418 * Please check the DMA prepared buffer structure in :
419 * Documentation/video4linux/pxa_camera.txt
420 * Please check also in pxa_camera_check_link_miss() to understand why DMA chain
421 * modification while DMA chain is running will work anyway.
422 */
423 static int pxa_videobuf_prepare(struct videobuf_queue *vq,
424 struct videobuf_buffer *vb, enum v4l2_field field)
425 {
426 struct soc_camera_device *icd = vq->priv_data;
427 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
428 struct pxa_camera_dev *pcdev = ici->priv;
429 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
430 int ret;
431 int size_y, size_u = 0, size_v = 0;
432
433 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
434 vb, vb->baddr, vb->bsize);
435
436 /* Added list head initialization on alloc */
437 WARN_ON(!list_empty(&vb->queue));
438
439 #ifdef DEBUG
440 /* This can be useful if you want to see if we actually fill
441 * the buffer with something */
442 memset((void *)vb->baddr, 0xaa, vb->bsize);
443 #endif
444
445 BUG_ON(NULL == icd->current_fmt);
446
447 /* I think, in buf_prepare you only have to protect global data,
448 * the actual buffer is yours */
449 buf->inwork = 1;
450
451 if (buf->fmt != icd->current_fmt ||
452 vb->width != icd->width ||
453 vb->height != icd->height ||
454 vb->field != field) {
455 buf->fmt = icd->current_fmt;
456 vb->width = icd->width;
457 vb->height = icd->height;
458 vb->field = field;
459 vb->state = VIDEOBUF_NEEDS_INIT;
460 }
461
462 vb->size = vb->width * vb->height * ((buf->fmt->depth + 7) >> 3);
463 if (0 != vb->baddr && vb->bsize < vb->size) {
464 ret = -EINVAL;
465 goto out;
466 }
467
468 if (vb->state == VIDEOBUF_NEEDS_INIT) {
469 int size = vb->size;
470 int next_ofs = 0;
471 struct videobuf_dmabuf *dma = videobuf_to_dma(vb);
472 struct scatterlist *sg;
473
474 ret = videobuf_iolock(vq, vb, NULL);
475 if (ret)
476 goto fail;
477
478 if (pcdev->channels == 3) {
479 size_y = size / 2;
480 size_u = size_v = size / 4;
481 } else {
482 size_y = size;
483 }
484
485 sg = dma->sglist;
486
487 /* init DMA for Y channel */
488 ret = pxa_init_dma_channel(pcdev, buf, dma, 0, CIBR0, size_y,
489 &sg, &next_ofs);
490 if (ret) {
491 dev_err(pcdev->dev,
492 "DMA initialization for Y/RGB failed\n");
493 goto fail;
494 }
495
496 /* init DMA for U channel */
497 if (size_u)
498 ret = pxa_init_dma_channel(pcdev, buf, dma, 1, CIBR1,
499 size_u, &sg, &next_ofs);
500 if (ret) {
501 dev_err(pcdev->dev,
502 "DMA initialization for U failed\n");
503 goto fail_u;
504 }
505
506 /* init DMA for V channel */
507 if (size_v)
508 ret = pxa_init_dma_channel(pcdev, buf, dma, 2, CIBR2,
509 size_v, &sg, &next_ofs);
510 if (ret) {
511 dev_err(pcdev->dev,
512 "DMA initialization for V failed\n");
513 goto fail_v;
514 }
515
516 vb->state = VIDEOBUF_PREPARED;
517 }
518
519 buf->inwork = 0;
520 pxa_videobuf_set_actdma(pcdev, buf);
521
522 return 0;
523
524 fail_v:
525 dma_free_coherent(pcdev->dev, buf->dmas[1].sg_size,
526 buf->dmas[1].sg_cpu, buf->dmas[1].sg_dma);
527 fail_u:
528 dma_free_coherent(pcdev->dev, buf->dmas[0].sg_size,
529 buf->dmas[0].sg_cpu, buf->dmas[0].sg_dma);
530 fail:
531 free_buffer(vq, buf);
532 out:
533 buf->inwork = 0;
534 return ret;
535 }
536
537 /**
538 * pxa_dma_start_channels - start DMA channel for active buffer
539 * @pcdev: pxa camera device
540 *
541 * Initialize DMA channels to the beginning of the active video buffer, and
542 * start these channels.
543 */
544 static void pxa_dma_start_channels(struct pxa_camera_dev *pcdev)
545 {
546 int i;
547 struct pxa_buffer *active;
548
549 active = pcdev->active;
550
551 for (i = 0; i < pcdev->channels; i++) {
552 dev_dbg(pcdev->dev, "%s (channel=%d) ddadr=%08x\n", __func__,
553 i, active->dmas[i].sg_dma);
554 DDADR(pcdev->dma_chans[i]) = active->dmas[i].sg_dma;
555 DCSR(pcdev->dma_chans[i]) = DCSR_RUN;
556 }
557 }
558
559 static void pxa_dma_stop_channels(struct pxa_camera_dev *pcdev)
560 {
561 int i;
562
563 for (i = 0; i < pcdev->channels; i++) {
564 dev_dbg(pcdev->dev, "%s (channel=%d)\n", __func__, i);
565 DCSR(pcdev->dma_chans[i]) = 0;
566 }
567 }
568
569 static void pxa_dma_update_sg_tail(struct pxa_camera_dev *pcdev,
570 struct pxa_buffer *buf)
571 {
572 int i;
573
574 for (i = 0; i < pcdev->channels; i++)
575 pcdev->sg_tail[i] = buf->dmas[i].sg_cpu + buf->dmas[i].sglen;
576 }
577
578 static void pxa_dma_add_tail_buf(struct pxa_camera_dev *pcdev,
579 struct pxa_buffer *buf)
580 {
581 int i;
582 struct pxa_dma_desc *buf_last_desc;
583
584 for (i = 0; i < pcdev->channels; i++) {
585 buf_last_desc = buf->dmas[i].sg_cpu + buf->dmas[i].sglen;
586 buf_last_desc->ddadr = DDADR_STOP;
587
588 if (!pcdev->sg_tail[i])
589 continue;
590 pcdev->sg_tail[i]->ddadr = buf->dmas[i].sg_dma;
591 }
592
593 pxa_dma_update_sg_tail(pcdev, buf);
594 }
595
596 /**
597 * pxa_camera_start_capture - start video capturing
598 * @pcdev: camera device
599 *
600 * Launch capturing. DMA channels should not be active yet. They should get
601 * activated at the end of frame interrupt, to capture only whole frames, and
602 * never begin the capture of a partial frame.
603 */
604 static void pxa_camera_start_capture(struct pxa_camera_dev *pcdev)
605 {
606 unsigned long cicr0, cifr;
607
608 dev_dbg(pcdev->dev, "%s\n", __func__);
609 /* Reset the FIFOs */
610 cifr = __raw_readl(pcdev->base + CIFR) | CIFR_RESET_F;
611 __raw_writel(cifr, pcdev->base + CIFR);
612 /* Enable End-Of-Frame Interrupt */
613 cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_ENB;
614 cicr0 &= ~CICR0_EOFM;
615 __raw_writel(cicr0, pcdev->base + CICR0);
616 }
617
618 static void pxa_camera_stop_capture(struct pxa_camera_dev *pcdev)
619 {
620 unsigned long cicr0;
621
622 pxa_dma_stop_channels(pcdev);
623
624 cicr0 = __raw_readl(pcdev->base + CICR0) & ~CICR0_ENB;
625 __raw_writel(cicr0, pcdev->base + CICR0);
626
627 dev_dbg(pcdev->dev, "%s\n", __func__);
628 }
629
630 static void pxa_videobuf_queue(struct videobuf_queue *vq,
631 struct videobuf_buffer *vb)
632 {
633 struct soc_camera_device *icd = vq->priv_data;
634 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
635 struct pxa_camera_dev *pcdev = ici->priv;
636 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
637 unsigned long flags;
638
639 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d active=%p\n", __func__,
640 vb, vb->baddr, vb->bsize, pcdev->active);
641
642 spin_lock_irqsave(&pcdev->lock, flags);
643
644 list_add_tail(&vb->queue, &pcdev->capture);
645
646 vb->state = VIDEOBUF_ACTIVE;
647 pxa_dma_add_tail_buf(pcdev, buf);
648
649 if (!pcdev->active)
650 pxa_camera_start_capture(pcdev);
651
652 spin_unlock_irqrestore(&pcdev->lock, flags);
653 }
654
655 static void pxa_videobuf_release(struct videobuf_queue *vq,
656 struct videobuf_buffer *vb)
657 {
658 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
659 #ifdef DEBUG
660 struct soc_camera_device *icd = vq->priv_data;
661
662 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
663 vb, vb->baddr, vb->bsize);
664
665 switch (vb->state) {
666 case VIDEOBUF_ACTIVE:
667 dev_dbg(&icd->dev, "%s (active)\n", __func__);
668 break;
669 case VIDEOBUF_QUEUED:
670 dev_dbg(&icd->dev, "%s (queued)\n", __func__);
671 break;
672 case VIDEOBUF_PREPARED:
673 dev_dbg(&icd->dev, "%s (prepared)\n", __func__);
674 break;
675 default:
676 dev_dbg(&icd->dev, "%s (unknown)\n", __func__);
677 break;
678 }
679 #endif
680
681 free_buffer(vq, buf);
682 }
683
684 static void pxa_camera_wakeup(struct pxa_camera_dev *pcdev,
685 struct videobuf_buffer *vb,
686 struct pxa_buffer *buf)
687 {
688 int i;
689
690 /* _init is used to debug races, see comment in pxa_camera_reqbufs() */
691 list_del_init(&vb->queue);
692 vb->state = VIDEOBUF_DONE;
693 do_gettimeofday(&vb->ts);
694 vb->field_count++;
695 wake_up(&vb->done);
696 dev_dbg(pcdev->dev, "%s dequeud buffer (vb=0x%p)\n", __func__, vb);
697
698 if (list_empty(&pcdev->capture)) {
699 pxa_camera_stop_capture(pcdev);
700 pcdev->active = NULL;
701 for (i = 0; i < pcdev->channels; i++)
702 pcdev->sg_tail[i] = NULL;
703 return;
704 }
705
706 pcdev->active = list_entry(pcdev->capture.next,
707 struct pxa_buffer, vb.queue);
708 }
709
710 /**
711 * pxa_camera_check_link_miss - check missed DMA linking
712 * @pcdev: camera device
713 *
714 * The DMA chaining is done with DMA running. This means a tiny temporal window
715 * remains, where a buffer is queued on the chain, while the chain is already
716 * stopped. This means the tailed buffer would never be transfered by DMA.
717 * This function restarts the capture for this corner case, where :
718 * - DADR() == DADDR_STOP
719 * - a videobuffer is queued on the pcdev->capture list
720 *
721 * Please check the "DMA hot chaining timeslice issue" in
722 * Documentation/video4linux/pxa_camera.txt
723 *
724 * Context: should only be called within the dma irq handler
725 */
726 static void pxa_camera_check_link_miss(struct pxa_camera_dev *pcdev)
727 {
728 int i, is_dma_stopped = 1;
729
730 for (i = 0; i < pcdev->channels; i++)
731 if (DDADR(pcdev->dma_chans[i]) != DDADR_STOP)
732 is_dma_stopped = 0;
733 dev_dbg(pcdev->dev, "%s : top queued buffer=%p, dma_stopped=%d\n",
734 __func__, pcdev->active, is_dma_stopped);
735 if (pcdev->active && is_dma_stopped)
736 pxa_camera_start_capture(pcdev);
737 }
738
739 static void pxa_camera_dma_irq(int channel, struct pxa_camera_dev *pcdev,
740 enum pxa_camera_active_dma act_dma)
741 {
742 struct pxa_buffer *buf;
743 unsigned long flags;
744 u32 status, camera_status, overrun;
745 struct videobuf_buffer *vb;
746
747 spin_lock_irqsave(&pcdev->lock, flags);
748
749 status = DCSR(channel);
750 DCSR(channel) = status;
751
752 camera_status = __raw_readl(pcdev->base + CISR);
753 overrun = CISR_IFO_0;
754 if (pcdev->channels == 3)
755 overrun |= CISR_IFO_1 | CISR_IFO_2;
756
757 if (status & DCSR_BUSERR) {
758 dev_err(pcdev->dev, "DMA Bus Error IRQ!\n");
759 goto out;
760 }
761
762 if (!(status & (DCSR_ENDINTR | DCSR_STARTINTR))) {
763 dev_err(pcdev->dev, "Unknown DMA IRQ source, "
764 "status: 0x%08x\n", status);
765 goto out;
766 }
767
768 if (!pcdev->active) {
769 dev_err(pcdev->dev, "DMA End IRQ with no active buffer!\n");
770 goto out;
771 }
772
773 vb = &pcdev->active->vb;
774 buf = container_of(vb, struct pxa_buffer, vb);
775 WARN_ON(buf->inwork || list_empty(&vb->queue));
776
777 dev_dbg(pcdev->dev, "%s channel=%d %s%s(vb=0x%p) dma.desc=%x\n",
778 __func__, channel, status & DCSR_STARTINTR ? "SOF " : "",
779 status & DCSR_ENDINTR ? "EOF " : "", vb, DDADR(channel));
780
781 if (status & DCSR_ENDINTR) {
782 if (camera_status & overrun) {
783 dev_dbg(pcdev->dev, "FIFO overrun! CISR: %x\n",
784 camera_status);
785 pxa_camera_stop_capture(pcdev);
786 pxa_camera_start_capture(pcdev);
787 goto out;
788 }
789 buf->active_dma &= ~act_dma;
790 if (!buf->active_dma) {
791 pxa_camera_wakeup(pcdev, vb, buf);
792 pxa_camera_check_link_miss(pcdev);
793 }
794 }
795
796 out:
797 spin_unlock_irqrestore(&pcdev->lock, flags);
798 }
799
800 static void pxa_camera_dma_irq_y(int channel, void *data)
801 {
802 struct pxa_camera_dev *pcdev = data;
803 pxa_camera_dma_irq(channel, pcdev, DMA_Y);
804 }
805
806 static void pxa_camera_dma_irq_u(int channel, void *data)
807 {
808 struct pxa_camera_dev *pcdev = data;
809 pxa_camera_dma_irq(channel, pcdev, DMA_U);
810 }
811
812 static void pxa_camera_dma_irq_v(int channel, void *data)
813 {
814 struct pxa_camera_dev *pcdev = data;
815 pxa_camera_dma_irq(channel, pcdev, DMA_V);
816 }
817
818 static struct videobuf_queue_ops pxa_videobuf_ops = {
819 .buf_setup = pxa_videobuf_setup,
820 .buf_prepare = pxa_videobuf_prepare,
821 .buf_queue = pxa_videobuf_queue,
822 .buf_release = pxa_videobuf_release,
823 };
824
825 static void pxa_camera_init_videobuf(struct videobuf_queue *q,
826 struct soc_camera_device *icd)
827 {
828 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
829 struct pxa_camera_dev *pcdev = ici->priv;
830
831 /* We must pass NULL as dev pointer, then all pci_* dma operations
832 * transform to normal dma_* ones. */
833 videobuf_queue_sg_init(q, &pxa_videobuf_ops, NULL, &pcdev->lock,
834 V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_NONE,
835 sizeof(struct pxa_buffer), icd);
836 }
837
838 static u32 mclk_get_divisor(struct pxa_camera_dev *pcdev)
839 {
840 unsigned long mclk = pcdev->mclk;
841 u32 div;
842 unsigned long lcdclk;
843
844 lcdclk = clk_get_rate(pcdev->clk);
845 pcdev->ciclk = lcdclk;
846
847 /* mclk <= ciclk / 4 (27.4.2) */
848 if (mclk > lcdclk / 4) {
849 mclk = lcdclk / 4;
850 dev_warn(pcdev->dev, "Limiting master clock to %lu\n", mclk);
851 }
852
853 /* We verify mclk != 0, so if anyone breaks it, here comes their Oops */
854 div = (lcdclk + 2 * mclk - 1) / (2 * mclk) - 1;
855
856 /* If we're not supplying MCLK, leave it at 0 */
857 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
858 pcdev->mclk = lcdclk / (2 * (div + 1));
859
860 dev_dbg(pcdev->dev, "LCD clock %luHz, target freq %luHz, "
861 "divisor %u\n", lcdclk, mclk, div);
862
863 return div;
864 }
865
866 static void recalculate_fifo_timeout(struct pxa_camera_dev *pcdev,
867 unsigned long pclk)
868 {
869 /* We want a timeout > 1 pixel time, not ">=" */
870 u32 ciclk_per_pixel = pcdev->ciclk / pclk + 1;
871
872 __raw_writel(ciclk_per_pixel, pcdev->base + CITOR);
873 }
874
875 static void pxa_camera_activate(struct pxa_camera_dev *pcdev)
876 {
877 struct pxacamera_platform_data *pdata = pcdev->pdata;
878 u32 cicr4 = 0;
879
880 dev_dbg(pcdev->dev, "Registered platform device at %p data %p\n",
881 pcdev, pdata);
882
883 if (pdata && pdata->init) {
884 dev_dbg(pcdev->dev, "%s: Init gpios\n", __func__);
885 pdata->init(pcdev->dev);
886 }
887
888 /* disable all interrupts */
889 __raw_writel(0x3ff, pcdev->base + CICR0);
890
891 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
892 cicr4 |= CICR4_PCLK_EN;
893 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
894 cicr4 |= CICR4_MCLK_EN;
895 if (pcdev->platform_flags & PXA_CAMERA_PCP)
896 cicr4 |= CICR4_PCP;
897 if (pcdev->platform_flags & PXA_CAMERA_HSP)
898 cicr4 |= CICR4_HSP;
899 if (pcdev->platform_flags & PXA_CAMERA_VSP)
900 cicr4 |= CICR4_VSP;
901
902 __raw_writel(pcdev->mclk_divisor | cicr4, pcdev->base + CICR4);
903
904 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
905 /* Initialise the timeout under the assumption pclk = mclk */
906 recalculate_fifo_timeout(pcdev, pcdev->mclk);
907 else
908 /* "Safe default" - 13MHz */
909 recalculate_fifo_timeout(pcdev, 13000000);
910
911 clk_enable(pcdev->clk);
912 }
913
914 static void pxa_camera_deactivate(struct pxa_camera_dev *pcdev)
915 {
916 clk_disable(pcdev->clk);
917 }
918
919 static irqreturn_t pxa_camera_irq(int irq, void *data)
920 {
921 struct pxa_camera_dev *pcdev = data;
922 unsigned long status, cicr0;
923 struct pxa_buffer *buf;
924 struct videobuf_buffer *vb;
925
926 status = __raw_readl(pcdev->base + CISR);
927 dev_dbg(pcdev->dev, "Camera interrupt status 0x%lx\n", status);
928
929 if (!status)
930 return IRQ_NONE;
931
932 __raw_writel(status, pcdev->base + CISR);
933
934 if (status & CISR_EOF) {
935 pcdev->active = list_first_entry(&pcdev->capture,
936 struct pxa_buffer, vb.queue);
937 vb = &pcdev->active->vb;
938 buf = container_of(vb, struct pxa_buffer, vb);
939 pxa_videobuf_set_actdma(pcdev, buf);
940
941 pxa_dma_start_channels(pcdev);
942
943 cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_EOFM;
944 __raw_writel(cicr0, pcdev->base + CICR0);
945 }
946
947 return IRQ_HANDLED;
948 }
949
950 /*
951 * The following two functions absolutely depend on the fact, that
952 * there can be only one camera on PXA quick capture interface
953 * Called with .video_lock held
954 */
955 static int pxa_camera_add_device(struct soc_camera_device *icd)
956 {
957 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
958 struct pxa_camera_dev *pcdev = ici->priv;
959 int ret;
960
961 if (pcdev->icd) {
962 ret = -EBUSY;
963 goto ebusy;
964 }
965
966 dev_info(&icd->dev, "PXA Camera driver attached to camera %d\n",
967 icd->devnum);
968
969 pxa_camera_activate(pcdev);
970 ret = icd->ops->init(icd);
971
972 if (!ret)
973 pcdev->icd = icd;
974
975 ebusy:
976 return ret;
977 }
978
979 /* Called with .video_lock held */
980 static void pxa_camera_remove_device(struct soc_camera_device *icd)
981 {
982 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
983 struct pxa_camera_dev *pcdev = ici->priv;
984
985 BUG_ON(icd != pcdev->icd);
986
987 dev_info(&icd->dev, "PXA Camera driver detached from camera %d\n",
988 icd->devnum);
989
990 /* disable capture, disable interrupts */
991 __raw_writel(0x3ff, pcdev->base + CICR0);
992
993 /* Stop DMA engine */
994 DCSR(pcdev->dma_chans[0]) = 0;
995 DCSR(pcdev->dma_chans[1]) = 0;
996 DCSR(pcdev->dma_chans[2]) = 0;
997
998 icd->ops->release(icd);
999
1000 pxa_camera_deactivate(pcdev);
1001
1002 pcdev->icd = NULL;
1003 }
1004
1005 static int test_platform_param(struct pxa_camera_dev *pcdev,
1006 unsigned char buswidth, unsigned long *flags)
1007 {
1008 /*
1009 * Platform specified synchronization and pixel clock polarities are
1010 * only a recommendation and are only used during probing. The PXA270
1011 * quick capture interface supports both.
1012 */
1013 *flags = (pcdev->platform_flags & PXA_CAMERA_MASTER ?
1014 SOCAM_MASTER : SOCAM_SLAVE) |
1015 SOCAM_HSYNC_ACTIVE_HIGH |
1016 SOCAM_HSYNC_ACTIVE_LOW |
1017 SOCAM_VSYNC_ACTIVE_HIGH |
1018 SOCAM_VSYNC_ACTIVE_LOW |
1019 SOCAM_DATA_ACTIVE_HIGH |
1020 SOCAM_PCLK_SAMPLE_RISING |
1021 SOCAM_PCLK_SAMPLE_FALLING;
1022
1023 /* If requested data width is supported by the platform, use it */
1024 switch (buswidth) {
1025 case 10:
1026 if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_10))
1027 return -EINVAL;
1028 *flags |= SOCAM_DATAWIDTH_10;
1029 break;
1030 case 9:
1031 if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_9))
1032 return -EINVAL;
1033 *flags |= SOCAM_DATAWIDTH_9;
1034 break;
1035 case 8:
1036 if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8))
1037 return -EINVAL;
1038 *flags |= SOCAM_DATAWIDTH_8;
1039 break;
1040 default:
1041 return -EINVAL;
1042 }
1043
1044 return 0;
1045 }
1046
1047 static int pxa_camera_set_bus_param(struct soc_camera_device *icd, __u32 pixfmt)
1048 {
1049 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1050 struct pxa_camera_dev *pcdev = ici->priv;
1051 unsigned long dw, bpp, bus_flags, camera_flags, common_flags;
1052 u32 cicr0, cicr1, cicr2, cicr3, cicr4 = 0;
1053 int ret = test_platform_param(pcdev, icd->buswidth, &bus_flags);
1054
1055 if (ret < 0)
1056 return ret;
1057
1058 camera_flags = icd->ops->query_bus_param(icd);
1059
1060 common_flags = soc_camera_bus_param_compatible(camera_flags, bus_flags);
1061 if (!common_flags)
1062 return -EINVAL;
1063
1064 pcdev->channels = 1;
1065
1066 /* Make choises, based on platform preferences */
1067 if ((common_flags & SOCAM_HSYNC_ACTIVE_HIGH) &&
1068 (common_flags & SOCAM_HSYNC_ACTIVE_LOW)) {
1069 if (pcdev->platform_flags & PXA_CAMERA_HSP)
1070 common_flags &= ~SOCAM_HSYNC_ACTIVE_HIGH;
1071 else
1072 common_flags &= ~SOCAM_HSYNC_ACTIVE_LOW;
1073 }
1074
1075 if ((common_flags & SOCAM_VSYNC_ACTIVE_HIGH) &&
1076 (common_flags & SOCAM_VSYNC_ACTIVE_LOW)) {
1077 if (pcdev->platform_flags & PXA_CAMERA_VSP)
1078 common_flags &= ~SOCAM_VSYNC_ACTIVE_HIGH;
1079 else
1080 common_flags &= ~SOCAM_VSYNC_ACTIVE_LOW;
1081 }
1082
1083 if ((common_flags & SOCAM_PCLK_SAMPLE_RISING) &&
1084 (common_flags & SOCAM_PCLK_SAMPLE_FALLING)) {
1085 if (pcdev->platform_flags & PXA_CAMERA_PCP)
1086 common_flags &= ~SOCAM_PCLK_SAMPLE_RISING;
1087 else
1088 common_flags &= ~SOCAM_PCLK_SAMPLE_FALLING;
1089 }
1090
1091 ret = icd->ops->set_bus_param(icd, common_flags);
1092 if (ret < 0)
1093 return ret;
1094
1095 /* Datawidth is now guaranteed to be equal to one of the three values.
1096 * We fix bit-per-pixel equal to data-width... */
1097 switch (common_flags & SOCAM_DATAWIDTH_MASK) {
1098 case SOCAM_DATAWIDTH_10:
1099 dw = 4;
1100 bpp = 0x40;
1101 break;
1102 case SOCAM_DATAWIDTH_9:
1103 dw = 3;
1104 bpp = 0x20;
1105 break;
1106 default:
1107 /* Actually it can only be 8 now,
1108 * default is just to silence compiler warnings */
1109 case SOCAM_DATAWIDTH_8:
1110 dw = 2;
1111 bpp = 0;
1112 }
1113
1114 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1115 cicr4 |= CICR4_PCLK_EN;
1116 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
1117 cicr4 |= CICR4_MCLK_EN;
1118 if (common_flags & SOCAM_PCLK_SAMPLE_FALLING)
1119 cicr4 |= CICR4_PCP;
1120 if (common_flags & SOCAM_HSYNC_ACTIVE_LOW)
1121 cicr4 |= CICR4_HSP;
1122 if (common_flags & SOCAM_VSYNC_ACTIVE_LOW)
1123 cicr4 |= CICR4_VSP;
1124
1125 cicr0 = __raw_readl(pcdev->base + CICR0);
1126 if (cicr0 & CICR0_ENB)
1127 __raw_writel(cicr0 & ~CICR0_ENB, pcdev->base + CICR0);
1128
1129 cicr1 = CICR1_PPL_VAL(icd->width - 1) | bpp | dw;
1130
1131 switch (pixfmt) {
1132 case V4L2_PIX_FMT_YUV422P:
1133 pcdev->channels = 3;
1134 cicr1 |= CICR1_YCBCR_F;
1135 /*
1136 * Normally, pxa bus wants as input UYVY format. We allow all
1137 * reorderings of the YUV422 format, as no processing is done,
1138 * and the YUV stream is just passed through without any
1139 * transformation. Note that UYVY is the only format that
1140 * should be used if pxa framebuffer Overlay2 is used.
1141 */
1142 case V4L2_PIX_FMT_UYVY:
1143 case V4L2_PIX_FMT_VYUY:
1144 case V4L2_PIX_FMT_YUYV:
1145 case V4L2_PIX_FMT_YVYU:
1146 cicr1 |= CICR1_COLOR_SP_VAL(2);
1147 break;
1148 case V4L2_PIX_FMT_RGB555:
1149 cicr1 |= CICR1_RGB_BPP_VAL(1) | CICR1_RGBT_CONV_VAL(2) |
1150 CICR1_TBIT | CICR1_COLOR_SP_VAL(1);
1151 break;
1152 case V4L2_PIX_FMT_RGB565:
1153 cicr1 |= CICR1_COLOR_SP_VAL(1) | CICR1_RGB_BPP_VAL(2);
1154 break;
1155 }
1156
1157 cicr2 = 0;
1158 cicr3 = CICR3_LPF_VAL(icd->height - 1) |
1159 CICR3_BFW_VAL(min((unsigned short)255, icd->y_skip_top));
1160 cicr4 |= pcdev->mclk_divisor;
1161
1162 __raw_writel(cicr1, pcdev->base + CICR1);
1163 __raw_writel(cicr2, pcdev->base + CICR2);
1164 __raw_writel(cicr3, pcdev->base + CICR3);
1165 __raw_writel(cicr4, pcdev->base + CICR4);
1166
1167 /* CIF interrupts are not used, only DMA */
1168 cicr0 = (cicr0 & CICR0_ENB) | (pcdev->platform_flags & PXA_CAMERA_MASTER ?
1169 CICR0_SIM_MP : (CICR0_SL_CAP_EN | CICR0_SIM_SP));
1170 cicr0 |= CICR0_DMAEN | CICR0_IRQ_MASK;
1171 __raw_writel(cicr0, pcdev->base + CICR0);
1172
1173 return 0;
1174 }
1175
1176 static int pxa_camera_try_bus_param(struct soc_camera_device *icd,
1177 unsigned char buswidth)
1178 {
1179 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1180 struct pxa_camera_dev *pcdev = ici->priv;
1181 unsigned long bus_flags, camera_flags;
1182 int ret = test_platform_param(pcdev, buswidth, &bus_flags);
1183
1184 if (ret < 0)
1185 return ret;
1186
1187 camera_flags = icd->ops->query_bus_param(icd);
1188
1189 return soc_camera_bus_param_compatible(camera_flags, bus_flags) ? 0 : -EINVAL;
1190 }
1191
1192 static const struct soc_camera_data_format pxa_camera_formats[] = {
1193 {
1194 .name = "Planar YUV422 16 bit",
1195 .depth = 16,
1196 .fourcc = V4L2_PIX_FMT_YUV422P,
1197 .colorspace = V4L2_COLORSPACE_JPEG,
1198 },
1199 };
1200
1201 static bool buswidth_supported(struct soc_camera_device *icd, int depth)
1202 {
1203 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1204 struct pxa_camera_dev *pcdev = ici->priv;
1205
1206 switch (depth) {
1207 case 8:
1208 return !!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8);
1209 case 9:
1210 return !!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_9);
1211 case 10:
1212 return !!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_10);
1213 }
1214 return false;
1215 }
1216
1217 static int required_buswidth(const struct soc_camera_data_format *fmt)
1218 {
1219 switch (fmt->fourcc) {
1220 case V4L2_PIX_FMT_UYVY:
1221 case V4L2_PIX_FMT_VYUY:
1222 case V4L2_PIX_FMT_YUYV:
1223 case V4L2_PIX_FMT_YVYU:
1224 case V4L2_PIX_FMT_RGB565:
1225 case V4L2_PIX_FMT_RGB555:
1226 return 8;
1227 default:
1228 return fmt->depth;
1229 }
1230 }
1231
1232 static int pxa_camera_get_formats(struct soc_camera_device *icd, int idx,
1233 struct soc_camera_format_xlate *xlate)
1234 {
1235 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1236 int formats = 0, buswidth, ret;
1237
1238 buswidth = required_buswidth(icd->formats + idx);
1239
1240 if (!buswidth_supported(icd, buswidth))
1241 return 0;
1242
1243 ret = pxa_camera_try_bus_param(icd, buswidth);
1244 if (ret < 0)
1245 return 0;
1246
1247 switch (icd->formats[idx].fourcc) {
1248 case V4L2_PIX_FMT_UYVY:
1249 formats++;
1250 if (xlate) {
1251 xlate->host_fmt = &pxa_camera_formats[0];
1252 xlate->cam_fmt = icd->formats + idx;
1253 xlate->buswidth = buswidth;
1254 xlate++;
1255 dev_dbg(&ici->dev, "Providing format %s using %s\n",
1256 pxa_camera_formats[0].name,
1257 icd->formats[idx].name);
1258 }
1259 case V4L2_PIX_FMT_VYUY:
1260 case V4L2_PIX_FMT_YUYV:
1261 case V4L2_PIX_FMT_YVYU:
1262 case V4L2_PIX_FMT_RGB565:
1263 case V4L2_PIX_FMT_RGB555:
1264 formats++;
1265 if (xlate) {
1266 xlate->host_fmt = icd->formats + idx;
1267 xlate->cam_fmt = icd->formats + idx;
1268 xlate->buswidth = buswidth;
1269 xlate++;
1270 dev_dbg(&ici->dev, "Providing format %s packed\n",
1271 icd->formats[idx].name);
1272 }
1273 break;
1274 default:
1275 /* Generic pass-through */
1276 formats++;
1277 if (xlate) {
1278 xlate->host_fmt = icd->formats + idx;
1279 xlate->cam_fmt = icd->formats + idx;
1280 xlate->buswidth = icd->formats[idx].depth;
1281 xlate++;
1282 dev_dbg(&ici->dev,
1283 "Providing format %s in pass-through mode\n",
1284 icd->formats[idx].name);
1285 }
1286 }
1287
1288 return formats;
1289 }
1290
1291 static int pxa_camera_set_crop(struct soc_camera_device *icd,
1292 struct v4l2_rect *rect)
1293 {
1294 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1295 struct pxa_camera_dev *pcdev = ici->priv;
1296 struct soc_camera_sense sense = {
1297 .master_clock = pcdev->mclk,
1298 .pixel_clock_max = pcdev->ciclk / 4,
1299 };
1300 int ret;
1301
1302 /* If PCLK is used to latch data from the sensor, check sense */
1303 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1304 icd->sense = &sense;
1305
1306 ret = icd->ops->set_crop(icd, rect);
1307
1308 icd->sense = NULL;
1309
1310 if (ret < 0) {
1311 dev_warn(&ici->dev, "Failed to crop to %ux%u@%u:%u\n",
1312 rect->width, rect->height, rect->left, rect->top);
1313 } else if (sense.flags & SOCAM_SENSE_PCLK_CHANGED) {
1314 if (sense.pixel_clock > sense.pixel_clock_max) {
1315 dev_err(&ici->dev,
1316 "pixel clock %lu set by the camera too high!",
1317 sense.pixel_clock);
1318 return -EIO;
1319 }
1320 recalculate_fifo_timeout(pcdev, sense.pixel_clock);
1321 }
1322
1323 return ret;
1324 }
1325
1326 static int pxa_camera_set_fmt(struct soc_camera_device *icd,
1327 struct v4l2_format *f)
1328 {
1329 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1330 struct pxa_camera_dev *pcdev = ici->priv;
1331 const struct soc_camera_data_format *cam_fmt = NULL;
1332 const struct soc_camera_format_xlate *xlate = NULL;
1333 struct soc_camera_sense sense = {
1334 .master_clock = pcdev->mclk,
1335 .pixel_clock_max = pcdev->ciclk / 4,
1336 };
1337 struct v4l2_pix_format *pix = &f->fmt.pix;
1338 struct v4l2_format cam_f = *f;
1339 int ret;
1340
1341 xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat);
1342 if (!xlate) {
1343 dev_warn(&ici->dev, "Format %x not found\n", pix->pixelformat);
1344 return -EINVAL;
1345 }
1346
1347 cam_fmt = xlate->cam_fmt;
1348
1349 /* If PCLK is used to latch data from the sensor, check sense */
1350 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1351 icd->sense = &sense;
1352
1353 cam_f.fmt.pix.pixelformat = cam_fmt->fourcc;
1354 ret = icd->ops->set_fmt(icd, &cam_f);
1355
1356 icd->sense = NULL;
1357
1358 if (ret < 0) {
1359 dev_warn(&ici->dev, "Failed to configure for format %x\n",
1360 pix->pixelformat);
1361 } else if (sense.flags & SOCAM_SENSE_PCLK_CHANGED) {
1362 if (sense.pixel_clock > sense.pixel_clock_max) {
1363 dev_err(&ici->dev,
1364 "pixel clock %lu set by the camera too high!",
1365 sense.pixel_clock);
1366 return -EIO;
1367 }
1368 recalculate_fifo_timeout(pcdev, sense.pixel_clock);
1369 }
1370
1371 if (!ret) {
1372 icd->buswidth = xlate->buswidth;
1373 icd->current_fmt = xlate->host_fmt;
1374 }
1375
1376 return ret;
1377 }
1378
1379 static int pxa_camera_try_fmt(struct soc_camera_device *icd,
1380 struct v4l2_format *f)
1381 {
1382 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1383 const struct soc_camera_format_xlate *xlate;
1384 struct v4l2_pix_format *pix = &f->fmt.pix;
1385 __u32 pixfmt = pix->pixelformat;
1386 enum v4l2_field field;
1387 int ret;
1388
1389 xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
1390 if (!xlate) {
1391 dev_warn(&ici->dev, "Format %x not found\n", pixfmt);
1392 return -EINVAL;
1393 }
1394
1395 /* limit to pxa hardware capabilities */
1396 if (pix->height < 32)
1397 pix->height = 32;
1398 if (pix->height > 2048)
1399 pix->height = 2048;
1400 if (pix->width < 48)
1401 pix->width = 48;
1402 if (pix->width > 2048)
1403 pix->width = 2048;
1404 pix->width &= ~0x01;
1405
1406 /*
1407 * YUV422P planar format requires images size to be a 16 bytes
1408 * multiple. If not, zeros will be inserted between Y and U planes, and
1409 * U and V planes, and YUV422P standard would be violated.
1410 */
1411 if (xlate->host_fmt->fourcc == V4L2_PIX_FMT_YUV422P) {
1412 if (!IS_ALIGNED(pix->width * pix->height, YUV422P_SIZE_ALIGN))
1413 pix->height = ALIGN(pix->height, YUV422P_X_Y_ALIGN);
1414 if (!IS_ALIGNED(pix->width * pix->height, YUV422P_SIZE_ALIGN))
1415 pix->width = ALIGN(pix->width, YUV422P_X_Y_ALIGN);
1416 }
1417
1418 pix->bytesperline = pix->width *
1419 DIV_ROUND_UP(xlate->host_fmt->depth, 8);
1420 pix->sizeimage = pix->height * pix->bytesperline;
1421
1422 /* camera has to see its format, but the user the original one */
1423 pix->pixelformat = xlate->cam_fmt->fourcc;
1424 /* limit to sensor capabilities */
1425 ret = icd->ops->try_fmt(icd, f);
1426 pix->pixelformat = xlate->host_fmt->fourcc;
1427
1428 field = pix->field;
1429
1430 if (field == V4L2_FIELD_ANY) {
1431 pix->field = V4L2_FIELD_NONE;
1432 } else if (field != V4L2_FIELD_NONE) {
1433 dev_err(&icd->dev, "Field type %d unsupported.\n", field);
1434 return -EINVAL;
1435 }
1436
1437 return ret;
1438 }
1439
1440 static int pxa_camera_reqbufs(struct soc_camera_file *icf,
1441 struct v4l2_requestbuffers *p)
1442 {
1443 int i;
1444
1445 /* This is for locking debugging only. I removed spinlocks and now I
1446 * check whether .prepare is ever called on a linked buffer, or whether
1447 * a dma IRQ can occur for an in-work or unlinked buffer. Until now
1448 * it hadn't triggered */
1449 for (i = 0; i < p->count; i++) {
1450 struct pxa_buffer *buf = container_of(icf->vb_vidq.bufs[i],
1451 struct pxa_buffer, vb);
1452 buf->inwork = 0;
1453 INIT_LIST_HEAD(&buf->vb.queue);
1454 }
1455
1456 return 0;
1457 }
1458
1459 static unsigned int pxa_camera_poll(struct file *file, poll_table *pt)
1460 {
1461 struct soc_camera_file *icf = file->private_data;
1462 struct pxa_buffer *buf;
1463
1464 buf = list_entry(icf->vb_vidq.stream.next, struct pxa_buffer,
1465 vb.stream);
1466
1467 poll_wait(file, &buf->vb.done, pt);
1468
1469 if (buf->vb.state == VIDEOBUF_DONE ||
1470 buf->vb.state == VIDEOBUF_ERROR)
1471 return POLLIN|POLLRDNORM;
1472
1473 return 0;
1474 }
1475
1476 static int pxa_camera_querycap(struct soc_camera_host *ici,
1477 struct v4l2_capability *cap)
1478 {
1479 /* cap->name is set by the firendly caller:-> */
1480 strlcpy(cap->card, pxa_cam_driver_description, sizeof(cap->card));
1481 cap->version = PXA_CAM_VERSION_CODE;
1482 cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
1483
1484 return 0;
1485 }
1486
1487 static int pxa_camera_suspend(struct soc_camera_device *icd, pm_message_t state)
1488 {
1489 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1490 struct pxa_camera_dev *pcdev = ici->priv;
1491 int i = 0, ret = 0;
1492
1493 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR0);
1494 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR1);
1495 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR2);
1496 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR3);
1497 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR4);
1498
1499 if ((pcdev->icd) && (pcdev->icd->ops->suspend))
1500 ret = pcdev->icd->ops->suspend(pcdev->icd, state);
1501
1502 return ret;
1503 }
1504
1505 static int pxa_camera_resume(struct soc_camera_device *icd)
1506 {
1507 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1508 struct pxa_camera_dev *pcdev = ici->priv;
1509 int i = 0, ret = 0;
1510
1511 DRCMR(68) = pcdev->dma_chans[0] | DRCMR_MAPVLD;
1512 DRCMR(69) = pcdev->dma_chans[1] | DRCMR_MAPVLD;
1513 DRCMR(70) = pcdev->dma_chans[2] | DRCMR_MAPVLD;
1514
1515 __raw_writel(pcdev->save_cicr[i++] & ~CICR0_ENB, pcdev->base + CICR0);
1516 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR1);
1517 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR2);
1518 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR3);
1519 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR4);
1520
1521 if ((pcdev->icd) && (pcdev->icd->ops->resume))
1522 ret = pcdev->icd->ops->resume(pcdev->icd);
1523
1524 /* Restart frame capture if active buffer exists */
1525 if (!ret && pcdev->active)
1526 pxa_camera_start_capture(pcdev);
1527
1528 return ret;
1529 }
1530
1531 static struct soc_camera_host_ops pxa_soc_camera_host_ops = {
1532 .owner = THIS_MODULE,
1533 .add = pxa_camera_add_device,
1534 .remove = pxa_camera_remove_device,
1535 .suspend = pxa_camera_suspend,
1536 .resume = pxa_camera_resume,
1537 .set_crop = pxa_camera_set_crop,
1538 .get_formats = pxa_camera_get_formats,
1539 .set_fmt = pxa_camera_set_fmt,
1540 .try_fmt = pxa_camera_try_fmt,
1541 .init_videobuf = pxa_camera_init_videobuf,
1542 .reqbufs = pxa_camera_reqbufs,
1543 .poll = pxa_camera_poll,
1544 .querycap = pxa_camera_querycap,
1545 .set_bus_param = pxa_camera_set_bus_param,
1546 };
1547
1548 /* Should be allocated dynamically too, but we have only one. */
1549 static struct soc_camera_host pxa_soc_camera_host = {
1550 .drv_name = PXA_CAM_DRV_NAME,
1551 .ops = &pxa_soc_camera_host_ops,
1552 };
1553
1554 static int pxa_camera_probe(struct platform_device *pdev)
1555 {
1556 struct pxa_camera_dev *pcdev;
1557 struct resource *res;
1558 void __iomem *base;
1559 int irq;
1560 int err = 0;
1561
1562 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1563 irq = platform_get_irq(pdev, 0);
1564 if (!res || irq < 0) {
1565 err = -ENODEV;
1566 goto exit;
1567 }
1568
1569 pcdev = kzalloc(sizeof(*pcdev), GFP_KERNEL);
1570 if (!pcdev) {
1571 dev_err(&pdev->dev, "Could not allocate pcdev\n");
1572 err = -ENOMEM;
1573 goto exit;
1574 }
1575
1576 pcdev->clk = clk_get(&pdev->dev, NULL);
1577 if (IS_ERR(pcdev->clk)) {
1578 err = PTR_ERR(pcdev->clk);
1579 goto exit_kfree;
1580 }
1581
1582 dev_set_drvdata(&pdev->dev, pcdev);
1583 pcdev->res = res;
1584
1585 pcdev->pdata = pdev->dev.platform_data;
1586 pcdev->platform_flags = pcdev->pdata->flags;
1587 if (!(pcdev->platform_flags & (PXA_CAMERA_DATAWIDTH_8 |
1588 PXA_CAMERA_DATAWIDTH_9 | PXA_CAMERA_DATAWIDTH_10))) {
1589 /* Platform hasn't set available data widths. This is bad.
1590 * Warn and use a default. */
1591 dev_warn(&pdev->dev, "WARNING! Platform hasn't set available "
1592 "data widths, using default 10 bit\n");
1593 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10;
1594 }
1595 pcdev->mclk = pcdev->pdata->mclk_10khz * 10000;
1596 if (!pcdev->mclk) {
1597 dev_warn(&pdev->dev,
1598 "mclk == 0! Please, fix your platform data. "
1599 "Using default 20MHz\n");
1600 pcdev->mclk = 20000000;
1601 }
1602
1603 pcdev->dev = &pdev->dev;
1604 pcdev->mclk_divisor = mclk_get_divisor(pcdev);
1605
1606 INIT_LIST_HEAD(&pcdev->capture);
1607 spin_lock_init(&pcdev->lock);
1608
1609 /*
1610 * Request the regions.
1611 */
1612 if (!request_mem_region(res->start, res->end - res->start + 1,
1613 PXA_CAM_DRV_NAME)) {
1614 err = -EBUSY;
1615 goto exit_clk;
1616 }
1617
1618 base = ioremap(res->start, res->end - res->start + 1);
1619 if (!base) {
1620 err = -ENOMEM;
1621 goto exit_release;
1622 }
1623 pcdev->irq = irq;
1624 pcdev->base = base;
1625
1626 /* request dma */
1627 err = pxa_request_dma("CI_Y", DMA_PRIO_HIGH,
1628 pxa_camera_dma_irq_y, pcdev);
1629 if (err < 0) {
1630 dev_err(pcdev->dev, "Can't request DMA for Y\n");
1631 goto exit_iounmap;
1632 }
1633 pcdev->dma_chans[0] = err;
1634 dev_dbg(pcdev->dev, "got DMA channel %d\n", pcdev->dma_chans[0]);
1635
1636 err = pxa_request_dma("CI_U", DMA_PRIO_HIGH,
1637 pxa_camera_dma_irq_u, pcdev);
1638 if (err < 0) {
1639 dev_err(pcdev->dev, "Can't request DMA for U\n");
1640 goto exit_free_dma_y;
1641 }
1642 pcdev->dma_chans[1] = err;
1643 dev_dbg(pcdev->dev, "got DMA channel (U) %d\n", pcdev->dma_chans[1]);
1644
1645 err = pxa_request_dma("CI_V", DMA_PRIO_HIGH,
1646 pxa_camera_dma_irq_v, pcdev);
1647 if (err < 0) {
1648 dev_err(pcdev->dev, "Can't request DMA for V\n");
1649 goto exit_free_dma_u;
1650 }
1651 pcdev->dma_chans[2] = err;
1652 dev_dbg(pcdev->dev, "got DMA channel (V) %d\n", pcdev->dma_chans[2]);
1653
1654 DRCMR(68) = pcdev->dma_chans[0] | DRCMR_MAPVLD;
1655 DRCMR(69) = pcdev->dma_chans[1] | DRCMR_MAPVLD;
1656 DRCMR(70) = pcdev->dma_chans[2] | DRCMR_MAPVLD;
1657
1658 /* request irq */
1659 err = request_irq(pcdev->irq, pxa_camera_irq, 0, PXA_CAM_DRV_NAME,
1660 pcdev);
1661 if (err) {
1662 dev_err(pcdev->dev, "Camera interrupt register failed \n");
1663 goto exit_free_dma;
1664 }
1665
1666 pxa_soc_camera_host.priv = pcdev;
1667 pxa_soc_camera_host.dev.parent = &pdev->dev;
1668 pxa_soc_camera_host.nr = pdev->id;
1669 err = soc_camera_host_register(&pxa_soc_camera_host);
1670 if (err)
1671 goto exit_free_irq;
1672
1673 return 0;
1674
1675 exit_free_irq:
1676 free_irq(pcdev->irq, pcdev);
1677 exit_free_dma:
1678 pxa_free_dma(pcdev->dma_chans[2]);
1679 exit_free_dma_u:
1680 pxa_free_dma(pcdev->dma_chans[1]);
1681 exit_free_dma_y:
1682 pxa_free_dma(pcdev->dma_chans[0]);
1683 exit_iounmap:
1684 iounmap(base);
1685 exit_release:
1686 release_mem_region(res->start, res->end - res->start + 1);
1687 exit_clk:
1688 clk_put(pcdev->clk);
1689 exit_kfree:
1690 kfree(pcdev);
1691 exit:
1692 return err;
1693 }
1694
1695 static int __devexit pxa_camera_remove(struct platform_device *pdev)
1696 {
1697 struct pxa_camera_dev *pcdev = platform_get_drvdata(pdev);
1698 struct resource *res;
1699
1700 clk_put(pcdev->clk);
1701
1702 pxa_free_dma(pcdev->dma_chans[0]);
1703 pxa_free_dma(pcdev->dma_chans[1]);
1704 pxa_free_dma(pcdev->dma_chans[2]);
1705 free_irq(pcdev->irq, pcdev);
1706
1707 soc_camera_host_unregister(&pxa_soc_camera_host);
1708
1709 iounmap(pcdev->base);
1710
1711 res = pcdev->res;
1712 release_mem_region(res->start, res->end - res->start + 1);
1713
1714 kfree(pcdev);
1715
1716 dev_info(&pdev->dev, "PXA Camera driver unloaded\n");
1717
1718 return 0;
1719 }
1720
1721 static struct platform_driver pxa_camera_driver = {
1722 .driver = {
1723 .name = PXA_CAM_DRV_NAME,
1724 },
1725 .probe = pxa_camera_probe,
1726 .remove = __exit_p(pxa_camera_remove),
1727 };
1728
1729
1730 static int __devinit pxa_camera_init(void)
1731 {
1732 return platform_driver_register(&pxa_camera_driver);
1733 }
1734
1735 static void __exit pxa_camera_exit(void)
1736 {
1737 platform_driver_unregister(&pxa_camera_driver);
1738 }
1739
1740 module_init(pxa_camera_init);
1741 module_exit(pxa_camera_exit);
1742
1743 MODULE_DESCRIPTION("PXA27x SoC Camera Host driver");
1744 MODULE_AUTHOR("Guennadi Liakhovetski <kernel@pengutronix.de>");
1745 MODULE_LICENSE("GPL");
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