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[PATCH] uml: separate libc-dependent umid code
[linux-2.6/verdex.git] / drivers / char / drm / r128_cce.c
blob7452753d4d01d2c0ba8c9c4d6cecd51c95044cfd
1 /* r128_cce.c -- ATI Rage 128 driver -*- linux-c -*-
2 * Created: Wed Apr 5 19:24:19 2000 by kevin@precisioninsight.com
3 *
4 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 *
27 * Authors:
28 * Gareth Hughes <gareth@valinux.com>
29 */
30
31 #include "drmP.h"
32 #include "drm.h"
33 #include "r128_drm.h"
34 #include "r128_drv.h"
35
36 #define R128_FIFO_DEBUG 0
37
38 /* CCE microcode (from ATI) */
39 static u32 r128_cce_microcode[] = {
40 0, 276838400, 0, 268449792, 2, 142, 2, 145, 0, 1076765731, 0,
41 1617039951, 0, 774592877, 0, 1987540286, 0, 2307490946U, 0,
42 599558925, 0, 589505315, 0, 596487092, 0, 589505315, 1,
43 11544576, 1, 206848, 1, 311296, 1, 198656, 2, 912273422, 11,
44 262144, 0, 0, 1, 33559837, 1, 7438, 1, 14809, 1, 6615, 12, 28,
45 1, 6614, 12, 28, 2, 23, 11, 18874368, 0, 16790922, 1, 409600, 9,
46 30, 1, 147854772, 16, 420483072, 3, 8192, 0, 10240, 1, 198656,
47 1, 15630, 1, 51200, 10, 34858, 9, 42, 1, 33559823, 2, 10276, 1,
48 15717, 1, 15718, 2, 43, 1, 15936948, 1, 570480831, 1, 14715071,
49 12, 322123831, 1, 33953125, 12, 55, 1, 33559908, 1, 15718, 2,
50 46, 4, 2099258, 1, 526336, 1, 442623, 4, 4194365, 1, 509952, 1,
51 459007, 3, 0, 12, 92, 2, 46, 12, 176, 1, 15734, 1, 206848, 1,
52 18432, 1, 133120, 1, 100670734, 1, 149504, 1, 165888, 1,
53 15975928, 1, 1048576, 6, 3145806, 1, 15715, 16, 2150645232U, 2,
54 268449859, 2, 10307, 12, 176, 1, 15734, 1, 15735, 1, 15630, 1,
55 15631, 1, 5253120, 6, 3145810, 16, 2150645232U, 1, 15864, 2, 82,
56 1, 343310, 1, 1064207, 2, 3145813, 1, 15728, 1, 7817, 1, 15729,
57 3, 15730, 12, 92, 2, 98, 1, 16168, 1, 16167, 1, 16002, 1, 16008,
58 1, 15974, 1, 15975, 1, 15990, 1, 15976, 1, 15977, 1, 15980, 0,
59 15981, 1, 10240, 1, 5253120, 1, 15720, 1, 198656, 6, 110, 1,
60 180224, 1, 103824738, 2, 112, 2, 3145839, 0, 536885440, 1,
61 114880, 14, 125, 12, 206975, 1, 33559995, 12, 198784, 0,
62 33570236, 1, 15803, 0, 15804, 3, 294912, 1, 294912, 3, 442370,
63 1, 11544576, 0, 811612160, 1, 12593152, 1, 11536384, 1,
64 14024704, 7, 310382726, 0, 10240, 1, 14796, 1, 14797, 1, 14793,
65 1, 14794, 0, 14795, 1, 268679168, 1, 9437184, 1, 268449792, 1,
66 198656, 1, 9452827, 1, 1075854602, 1, 1075854603, 1, 557056, 1,
67 114880, 14, 159, 12, 198784, 1, 1109409213, 12, 198783, 1,
68 1107312059, 12, 198784, 1, 1109409212, 2, 162, 1, 1075854781, 1,
69 1073757627, 1, 1075854780, 1, 540672, 1, 10485760, 6, 3145894,
70 16, 274741248, 9, 168, 3, 4194304, 3, 4209949, 0, 0, 0, 256, 14,
71 174, 1, 114857, 1, 33560007, 12, 176, 0, 10240, 1, 114858, 1,
72 33560018, 1, 114857, 3, 33560007, 1, 16008, 1, 114874, 1,
73 33560360, 1, 114875, 1, 33560154, 0, 15963, 0, 256, 0, 4096, 1,
74 409611, 9, 188, 0, 10240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
75 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
76 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
77 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
78 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
79 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
80 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
81 };
82
83 static int R128_READ_PLL(drm_device_t * dev, int addr)
84 {
85 drm_r128_private_t *dev_priv = dev->dev_private;
86
87 R128_WRITE8(R128_CLOCK_CNTL_INDEX, addr & 0x1f);
88 return R128_READ(R128_CLOCK_CNTL_DATA);
89 }
90
91 #if R128_FIFO_DEBUG
92 static void r128_status(drm_r128_private_t * dev_priv)
93 {
94 printk("GUI_STAT = 0x%08x\n",
95 (unsigned int)R128_READ(R128_GUI_STAT));
96 printk("PM4_STAT = 0x%08x\n",
97 (unsigned int)R128_READ(R128_PM4_STAT));
98 printk("PM4_BUFFER_DL_WPTR = 0x%08x\n",
99 (unsigned int)R128_READ(R128_PM4_BUFFER_DL_WPTR));
100 printk("PM4_BUFFER_DL_RPTR = 0x%08x\n",
101 (unsigned int)R128_READ(R128_PM4_BUFFER_DL_RPTR));
102 printk("PM4_MICRO_CNTL = 0x%08x\n",
103 (unsigned int)R128_READ(R128_PM4_MICRO_CNTL));
104 printk("PM4_BUFFER_CNTL = 0x%08x\n",
105 (unsigned int)R128_READ(R128_PM4_BUFFER_CNTL));
106 }
107 #endif
108
109 /* ================================================================
110 * Engine, FIFO control
111 */
112
113 static int r128_do_pixcache_flush(drm_r128_private_t * dev_priv)
114 {
115 u32 tmp;
116 int i;
117
118 tmp = R128_READ(R128_PC_NGUI_CTLSTAT) | R128_PC_FLUSH_ALL;
119 R128_WRITE(R128_PC_NGUI_CTLSTAT, tmp);
120
121 for (i = 0; i < dev_priv->usec_timeout; i++) {
122 if (!(R128_READ(R128_PC_NGUI_CTLSTAT) & R128_PC_BUSY)) {
123 return 0;
124 }
125 DRM_UDELAY(1);
126 }
127
128 #if R128_FIFO_DEBUG
129 DRM_ERROR("failed!\n");
130 #endif
131 return DRM_ERR(EBUSY);
132 }
133
134 static int r128_do_wait_for_fifo(drm_r128_private_t * dev_priv, int entries)
135 {
136 int i;
137
138 for (i = 0; i < dev_priv->usec_timeout; i++) {
139 int slots = R128_READ(R128_GUI_STAT) & R128_GUI_FIFOCNT_MASK;
140 if (slots >= entries)
141 return 0;
142 DRM_UDELAY(1);
143 }
144
145 #if R128_FIFO_DEBUG
146 DRM_ERROR("failed!\n");
147 #endif
148 return DRM_ERR(EBUSY);
149 }
150
151 static int r128_do_wait_for_idle(drm_r128_private_t * dev_priv)
152 {
153 int i, ret;
154
155 ret = r128_do_wait_for_fifo(dev_priv, 64);
156 if (ret)
157 return ret;
158
159 for (i = 0; i < dev_priv->usec_timeout; i++) {
160 if (!(R128_READ(R128_GUI_STAT) & R128_GUI_ACTIVE)) {
161 r128_do_pixcache_flush(dev_priv);
162 return 0;
163 }
164 DRM_UDELAY(1);
165 }
166
167 #if R128_FIFO_DEBUG
168 DRM_ERROR("failed!\n");
169 #endif
170 return DRM_ERR(EBUSY);
171 }
172
173 /* ================================================================
174 * CCE control, initialization
175 */
176
177 /* Load the microcode for the CCE */
178 static void r128_cce_load_microcode(drm_r128_private_t * dev_priv)
179 {
180 int i;
181
182 DRM_DEBUG("\n");
183
184 r128_do_wait_for_idle(dev_priv);
185
186 R128_WRITE(R128_PM4_MICROCODE_ADDR, 0);
187 for (i = 0; i < 256; i++) {
188 R128_WRITE(R128_PM4_MICROCODE_DATAH, r128_cce_microcode[i * 2]);
189 R128_WRITE(R128_PM4_MICROCODE_DATAL,
190 r128_cce_microcode[i * 2 + 1]);
191 }
192 }
193
194 /* Flush any pending commands to the CCE. This should only be used just
195 * prior to a wait for idle, as it informs the engine that the command
196 * stream is ending.
197 */
198 static void r128_do_cce_flush(drm_r128_private_t * dev_priv)
199 {
200 u32 tmp;
201
202 tmp = R128_READ(R128_PM4_BUFFER_DL_WPTR) | R128_PM4_BUFFER_DL_DONE;
203 R128_WRITE(R128_PM4_BUFFER_DL_WPTR, tmp);
204 }
205
206 /* Wait for the CCE to go idle.
207 */
208 int r128_do_cce_idle(drm_r128_private_t * dev_priv)
209 {
210 int i;
211
212 for (i = 0; i < dev_priv->usec_timeout; i++) {
213 if (GET_RING_HEAD(dev_priv) == dev_priv->ring.tail) {
214 int pm4stat = R128_READ(R128_PM4_STAT);
215 if (((pm4stat & R128_PM4_FIFOCNT_MASK) >=
216 dev_priv->cce_fifo_size) &&
217 !(pm4stat & (R128_PM4_BUSY |
218 R128_PM4_GUI_ACTIVE))) {
219 return r128_do_pixcache_flush(dev_priv);
220 }
221 }
222 DRM_UDELAY(1);
223 }
224
225 #if R128_FIFO_DEBUG
226 DRM_ERROR("failed!\n");
227 r128_status(dev_priv);
228 #endif
229 return DRM_ERR(EBUSY);
230 }
231
232 /* Start the Concurrent Command Engine.
233 */
234 static void r128_do_cce_start(drm_r128_private_t * dev_priv)
235 {
236 r128_do_wait_for_idle(dev_priv);
237
238 R128_WRITE(R128_PM4_BUFFER_CNTL,
239 dev_priv->cce_mode | dev_priv->ring.size_l2qw
240 | R128_PM4_BUFFER_CNTL_NOUPDATE);
241 R128_READ(R128_PM4_BUFFER_ADDR); /* as per the sample code */
242 R128_WRITE(R128_PM4_MICRO_CNTL, R128_PM4_MICRO_FREERUN);
243
244 dev_priv->cce_running = 1;
245 }
246
247 /* Reset the Concurrent Command Engine. This will not flush any pending
248 * commands, so you must wait for the CCE command stream to complete
249 * before calling this routine.
250 */
251 static void r128_do_cce_reset(drm_r128_private_t * dev_priv)
252 {
253 R128_WRITE(R128_PM4_BUFFER_DL_WPTR, 0);
254 R128_WRITE(R128_PM4_BUFFER_DL_RPTR, 0);
255 dev_priv->ring.tail = 0;
256 }
257
258 /* Stop the Concurrent Command Engine. This will not flush any pending
259 * commands, so you must flush the command stream and wait for the CCE
260 * to go idle before calling this routine.
261 */
262 static void r128_do_cce_stop(drm_r128_private_t * dev_priv)
263 {
264 R128_WRITE(R128_PM4_MICRO_CNTL, 0);
265 R128_WRITE(R128_PM4_BUFFER_CNTL,
266 R128_PM4_NONPM4 | R128_PM4_BUFFER_CNTL_NOUPDATE);
267
268 dev_priv->cce_running = 0;
269 }
270
271 /* Reset the engine. This will stop the CCE if it is running.
272 */
273 static int r128_do_engine_reset(drm_device_t * dev)
274 {
275 drm_r128_private_t *dev_priv = dev->dev_private;
276 u32 clock_cntl_index, mclk_cntl, gen_reset_cntl;
277
278 r128_do_pixcache_flush(dev_priv);
279
280 clock_cntl_index = R128_READ(R128_CLOCK_CNTL_INDEX);
281 mclk_cntl = R128_READ_PLL(dev, R128_MCLK_CNTL);
282
283 R128_WRITE_PLL(R128_MCLK_CNTL,
284 mclk_cntl | R128_FORCE_GCP | R128_FORCE_PIPE3D_CP);
285
286 gen_reset_cntl = R128_READ(R128_GEN_RESET_CNTL);
287
288 /* Taken from the sample code - do not change */
289 R128_WRITE(R128_GEN_RESET_CNTL, gen_reset_cntl | R128_SOFT_RESET_GUI);
290 R128_READ(R128_GEN_RESET_CNTL);
291 R128_WRITE(R128_GEN_RESET_CNTL, gen_reset_cntl & ~R128_SOFT_RESET_GUI);
292 R128_READ(R128_GEN_RESET_CNTL);
293
294 R128_WRITE_PLL(R128_MCLK_CNTL, mclk_cntl);
295 R128_WRITE(R128_CLOCK_CNTL_INDEX, clock_cntl_index);
296 R128_WRITE(R128_GEN_RESET_CNTL, gen_reset_cntl);
297
298 /* Reset the CCE ring */
299 r128_do_cce_reset(dev_priv);
300
301 /* The CCE is no longer running after an engine reset */
302 dev_priv->cce_running = 0;
303
304 /* Reset any pending vertex, indirect buffers */
305 r128_freelist_reset(dev);
306
307 return 0;
308 }
309
310 static void r128_cce_init_ring_buffer(drm_device_t * dev,
311 drm_r128_private_t * dev_priv)
312 {
313 u32 ring_start;
314 u32 tmp;
315
316 DRM_DEBUG("\n");
317
318 /* The manual (p. 2) says this address is in "VM space". This
319 * means it's an offset from the start of AGP space.
320 */
321 #if __OS_HAS_AGP
322 if (!dev_priv->is_pci)
323 ring_start = dev_priv->cce_ring->offset - dev->agp->base;
324 else
325 #endif
326 ring_start = dev_priv->cce_ring->offset -
327 (unsigned long)dev->sg->virtual;
328
329 R128_WRITE(R128_PM4_BUFFER_OFFSET, ring_start | R128_AGP_OFFSET);
330
331 R128_WRITE(R128_PM4_BUFFER_DL_WPTR, 0);
332 R128_WRITE(R128_PM4_BUFFER_DL_RPTR, 0);
333
334 /* Set watermark control */
335 R128_WRITE(R128_PM4_BUFFER_WM_CNTL,
336 ((R128_WATERMARK_L / 4) << R128_WMA_SHIFT)
337 | ((R128_WATERMARK_M / 4) << R128_WMB_SHIFT)
338 | ((R128_WATERMARK_N / 4) << R128_WMC_SHIFT)
339 | ((R128_WATERMARK_K / 64) << R128_WB_WM_SHIFT));
340
341 /* Force read. Why? Because it's in the examples... */
342 R128_READ(R128_PM4_BUFFER_ADDR);
343
344 /* Turn on bus mastering */
345 tmp = R128_READ(R128_BUS_CNTL) & ~R128_BUS_MASTER_DIS;
346 R128_WRITE(R128_BUS_CNTL, tmp);
347 }
348
349 static int r128_do_init_cce(drm_device_t * dev, drm_r128_init_t * init)
350 {
351 drm_r128_private_t *dev_priv;
352
353 DRM_DEBUG("\n");
354
355 dev_priv = drm_alloc(sizeof(drm_r128_private_t), DRM_MEM_DRIVER);
356 if (dev_priv == NULL)
357 return DRM_ERR(ENOMEM);
358
359 memset(dev_priv, 0, sizeof(drm_r128_private_t));
360
361 dev_priv->is_pci = init->is_pci;
362
363 if (dev_priv->is_pci && !dev->sg) {
364 DRM_ERROR("PCI GART memory not allocated!\n");
365 dev->dev_private = (void *)dev_priv;
366 r128_do_cleanup_cce(dev);
367 return DRM_ERR(EINVAL);
368 }
369
370 dev_priv->usec_timeout = init->usec_timeout;
371 if (dev_priv->usec_timeout < 1 ||
372 dev_priv->usec_timeout > R128_MAX_USEC_TIMEOUT) {
373 DRM_DEBUG("TIMEOUT problem!\n");
374 dev->dev_private = (void *)dev_priv;
375 r128_do_cleanup_cce(dev);
376 return DRM_ERR(EINVAL);
377 }
378
379 dev_priv->cce_mode = init->cce_mode;
380
381 /* GH: Simple idle check.
382 */
383 atomic_set(&dev_priv->idle_count, 0);
384
385 /* We don't support anything other than bus-mastering ring mode,
386 * but the ring can be in either AGP or PCI space for the ring
387 * read pointer.
388 */
389 if ((init->cce_mode != R128_PM4_192BM) &&
390 (init->cce_mode != R128_PM4_128BM_64INDBM) &&
391 (init->cce_mode != R128_PM4_64BM_128INDBM) &&
392 (init->cce_mode != R128_PM4_64BM_64VCBM_64INDBM)) {
393 DRM_DEBUG("Bad cce_mode!\n");
394 dev->dev_private = (void *)dev_priv;
395 r128_do_cleanup_cce(dev);
396 return DRM_ERR(EINVAL);
397 }
398
399 switch (init->cce_mode) {
400 case R128_PM4_NONPM4:
401 dev_priv->cce_fifo_size = 0;
402 break;
403 case R128_PM4_192PIO:
404 case R128_PM4_192BM:
405 dev_priv->cce_fifo_size = 192;
406 break;
407 case R128_PM4_128PIO_64INDBM:
408 case R128_PM4_128BM_64INDBM:
409 dev_priv->cce_fifo_size = 128;
410 break;
411 case R128_PM4_64PIO_128INDBM:
412 case R128_PM4_64BM_128INDBM:
413 case R128_PM4_64PIO_64VCBM_64INDBM:
414 case R128_PM4_64BM_64VCBM_64INDBM:
415 case R128_PM4_64PIO_64VCPIO_64INDPIO:
416 dev_priv->cce_fifo_size = 64;
417 break;
418 }
419
420 switch (init->fb_bpp) {
421 case 16:
422 dev_priv->color_fmt = R128_DATATYPE_RGB565;
423 break;
424 case 32:
425 default:
426 dev_priv->color_fmt = R128_DATATYPE_ARGB8888;
427 break;
428 }
429 dev_priv->front_offset = init->front_offset;
430 dev_priv->front_pitch = init->front_pitch;
431 dev_priv->back_offset = init->back_offset;
432 dev_priv->back_pitch = init->back_pitch;
433
434 switch (init->depth_bpp) {
435 case 16:
436 dev_priv->depth_fmt = R128_DATATYPE_RGB565;
437 break;
438 case 24:
439 case 32:
440 default:
441 dev_priv->depth_fmt = R128_DATATYPE_ARGB8888;
442 break;
443 }
444 dev_priv->depth_offset = init->depth_offset;
445 dev_priv->depth_pitch = init->depth_pitch;
446 dev_priv->span_offset = init->span_offset;
447
448 dev_priv->front_pitch_offset_c = (((dev_priv->front_pitch / 8) << 21) |
449 (dev_priv->front_offset >> 5));
450 dev_priv->back_pitch_offset_c = (((dev_priv->back_pitch / 8) << 21) |
451 (dev_priv->back_offset >> 5));
452 dev_priv->depth_pitch_offset_c = (((dev_priv->depth_pitch / 8) << 21) |
453 (dev_priv->depth_offset >> 5) |
454 R128_DST_TILE);
455 dev_priv->span_pitch_offset_c = (((dev_priv->depth_pitch / 8) << 21) |
456 (dev_priv->span_offset >> 5));
457
458 DRM_GETSAREA();
459
460 if (!dev_priv->sarea) {
461 DRM_ERROR("could not find sarea!\n");
462 dev->dev_private = (void *)dev_priv;
463 r128_do_cleanup_cce(dev);
464 return DRM_ERR(EINVAL);
465 }
466
467 dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset);
468 if (!dev_priv->mmio) {
469 DRM_ERROR("could not find mmio region!\n");
470 dev->dev_private = (void *)dev_priv;
471 r128_do_cleanup_cce(dev);
472 return DRM_ERR(EINVAL);
473 }
474 dev_priv->cce_ring = drm_core_findmap(dev, init->ring_offset);
475 if (!dev_priv->cce_ring) {
476 DRM_ERROR("could not find cce ring region!\n");
477 dev->dev_private = (void *)dev_priv;
478 r128_do_cleanup_cce(dev);
479 return DRM_ERR(EINVAL);
480 }
481 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
482 if (!dev_priv->ring_rptr) {
483 DRM_ERROR("could not find ring read pointer!\n");
484 dev->dev_private = (void *)dev_priv;
485 r128_do_cleanup_cce(dev);
486 return DRM_ERR(EINVAL);
487 }
488 dev->agp_buffer_token = init->buffers_offset;
489 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
490 if (!dev->agp_buffer_map) {
491 DRM_ERROR("could not find dma buffer region!\n");
492 dev->dev_private = (void *)dev_priv;
493 r128_do_cleanup_cce(dev);
494 return DRM_ERR(EINVAL);
495 }
496
497 if (!dev_priv->is_pci) {
498 dev_priv->agp_textures =
499 drm_core_findmap(dev, init->agp_textures_offset);
500 if (!dev_priv->agp_textures) {
501 DRM_ERROR("could not find agp texture region!\n");
502 dev->dev_private = (void *)dev_priv;
503 r128_do_cleanup_cce(dev);
504 return DRM_ERR(EINVAL);
505 }
506 }
507
508 dev_priv->sarea_priv =
509 (drm_r128_sarea_t *) ((u8 *) dev_priv->sarea->handle +
510 init->sarea_priv_offset);
511
512 #if __OS_HAS_AGP
513 if (!dev_priv->is_pci) {
514 drm_core_ioremap(dev_priv->cce_ring, dev);
515 drm_core_ioremap(dev_priv->ring_rptr, dev);
516 drm_core_ioremap(dev->agp_buffer_map, dev);
517 if (!dev_priv->cce_ring->handle ||
518 !dev_priv->ring_rptr->handle ||
519 !dev->agp_buffer_map->handle) {
520 DRM_ERROR("Could not ioremap agp regions!\n");
521 dev->dev_private = (void *)dev_priv;
522 r128_do_cleanup_cce(dev);
523 return DRM_ERR(ENOMEM);
524 }
525 } else
526 #endif
527 {
528 dev_priv->cce_ring->handle = (void *)dev_priv->cce_ring->offset;
529 dev_priv->ring_rptr->handle =
530 (void *)dev_priv->ring_rptr->offset;
531 dev->agp_buffer_map->handle =
532 (void *)dev->agp_buffer_map->offset;
533 }
534
535 #if __OS_HAS_AGP
536 if (!dev_priv->is_pci)
537 dev_priv->cce_buffers_offset = dev->agp->base;
538 else
539 #endif
540 dev_priv->cce_buffers_offset = (unsigned long)dev->sg->virtual;
541
542 dev_priv->ring.start = (u32 *) dev_priv->cce_ring->handle;
543 dev_priv->ring.end = ((u32 *) dev_priv->cce_ring->handle
544 + init->ring_size / sizeof(u32));
545 dev_priv->ring.size = init->ring_size;
546 dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
547
548 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
549
550 dev_priv->ring.high_mark = 128;
551
552 dev_priv->sarea_priv->last_frame = 0;
553 R128_WRITE(R128_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);
554
555 dev_priv->sarea_priv->last_dispatch = 0;
556 R128_WRITE(R128_LAST_DISPATCH_REG, dev_priv->sarea_priv->last_dispatch);
557
558 #if __OS_HAS_AGP
559 if (dev_priv->is_pci) {
560 #endif
561 dev_priv->gart_info.gart_table_location = DRM_ATI_GART_MAIN;
562 dev_priv->gart_info.addr = dev_priv->gart_info.bus_addr = 0;
563 dev_priv->gart_info.is_pcie = 0;
564 if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) {
565 DRM_ERROR("failed to init PCI GART!\n");
566 dev->dev_private = (void *)dev_priv;
567 r128_do_cleanup_cce(dev);
568 return DRM_ERR(ENOMEM);
569 }
570 R128_WRITE(R128_PCI_GART_PAGE, dev_priv->gart_info.bus_addr);
571 #if __OS_HAS_AGP
572 }
573 #endif
574
575 r128_cce_init_ring_buffer(dev, dev_priv);
576 r128_cce_load_microcode(dev_priv);
577
578 dev->dev_private = (void *)dev_priv;
579
580 r128_do_engine_reset(dev);
581
582 return 0;
583 }
584
585 int r128_do_cleanup_cce(drm_device_t * dev)
586 {
587
588 /* Make sure interrupts are disabled here because the uninstall ioctl
589 * may not have been called from userspace and after dev_private
590 * is freed, it's too late.
591 */
592 if (dev->irq_enabled)
593 drm_irq_uninstall(dev);
594
595 if (dev->dev_private) {
596 drm_r128_private_t *dev_priv = dev->dev_private;
597
598 #if __OS_HAS_AGP
599 if (!dev_priv->is_pci) {
600 if (dev_priv->cce_ring != NULL)
601 drm_core_ioremapfree(dev_priv->cce_ring, dev);
602 if (dev_priv->ring_rptr != NULL)
603 drm_core_ioremapfree(dev_priv->ring_rptr, dev);
604 if (dev->agp_buffer_map != NULL)
605 drm_core_ioremapfree(dev->agp_buffer_map, dev);
606 } else
607 #endif
608 {
609 if (dev_priv->gart_info.bus_addr)
610 if (!drm_ati_pcigart_cleanup(dev,
611 &dev_priv->
612 gart_info))
613 DRM_ERROR
614 ("failed to cleanup PCI GART!\n");
615 }
616
617 drm_free(dev->dev_private, sizeof(drm_r128_private_t),
618 DRM_MEM_DRIVER);
619 dev->dev_private = NULL;
620 }
621
622 return 0;
623 }
624
625 int r128_cce_init(DRM_IOCTL_ARGS)
626 {
627 DRM_DEVICE;
628 drm_r128_init_t init;
629
630 DRM_DEBUG("\n");
631
632 LOCK_TEST_WITH_RETURN(dev, filp);
633
634 DRM_COPY_FROM_USER_IOCTL(init, (drm_r128_init_t __user *) data,
635 sizeof(init));
636
637 switch (init.func) {
638 case R128_INIT_CCE:
639 return r128_do_init_cce(dev, &init);
640 case R128_CLEANUP_CCE:
641 return r128_do_cleanup_cce(dev);
642 }
643
644 return DRM_ERR(EINVAL);
645 }
646
647 int r128_cce_start(DRM_IOCTL_ARGS)
648 {
649 DRM_DEVICE;
650 drm_r128_private_t *dev_priv = dev->dev_private;
651 DRM_DEBUG("\n");
652
653 LOCK_TEST_WITH_RETURN(dev, filp);
654
655 if (dev_priv->cce_running || dev_priv->cce_mode == R128_PM4_NONPM4) {
656 DRM_DEBUG("%s while CCE running\n", __FUNCTION__);
657 return 0;
658 }
659
660 r128_do_cce_start(dev_priv);
661
662 return 0;
663 }
664
665 /* Stop the CCE. The engine must have been idled before calling this
666 * routine.
667 */
668 int r128_cce_stop(DRM_IOCTL_ARGS)
669 {
670 DRM_DEVICE;
671 drm_r128_private_t *dev_priv = dev->dev_private;
672 drm_r128_cce_stop_t stop;
673 int ret;
674 DRM_DEBUG("\n");
675
676 LOCK_TEST_WITH_RETURN(dev, filp);
677
678 DRM_COPY_FROM_USER_IOCTL(stop, (drm_r128_cce_stop_t __user *) data,
679 sizeof(stop));
680
681 /* Flush any pending CCE commands. This ensures any outstanding
682 * commands are exectuted by the engine before we turn it off.
683 */
684 if (stop.flush) {
685 r128_do_cce_flush(dev_priv);
686 }
687
688 /* If we fail to make the engine go idle, we return an error
689 * code so that the DRM ioctl wrapper can try again.
690 */
691 if (stop.idle) {
692 ret = r128_do_cce_idle(dev_priv);
693 if (ret)
694 return ret;
695 }
696
697 /* Finally, we can turn off the CCE. If the engine isn't idle,
698 * we will get some dropped triangles as they won't be fully
699 * rendered before the CCE is shut down.
700 */
701 r128_do_cce_stop(dev_priv);
702
703 /* Reset the engine */
704 r128_do_engine_reset(dev);
705
706 return 0;
707 }
708
709 /* Just reset the CCE ring. Called as part of an X Server engine reset.
710 */
711 int r128_cce_reset(DRM_IOCTL_ARGS)
712 {
713 DRM_DEVICE;
714 drm_r128_private_t *dev_priv = dev->dev_private;
715 DRM_DEBUG("\n");
716
717 LOCK_TEST_WITH_RETURN(dev, filp);
718
719 if (!dev_priv) {
720 DRM_DEBUG("%s called before init done\n", __FUNCTION__);
721 return DRM_ERR(EINVAL);
722 }
723
724 r128_do_cce_reset(dev_priv);
725
726 /* The CCE is no longer running after an engine reset */
727 dev_priv->cce_running = 0;
728
729 return 0;
730 }
731
732 int r128_cce_idle(DRM_IOCTL_ARGS)
733 {
734 DRM_DEVICE;
735 drm_r128_private_t *dev_priv = dev->dev_private;
736 DRM_DEBUG("\n");
737
738 LOCK_TEST_WITH_RETURN(dev, filp);
739
740 if (dev_priv->cce_running) {
741 r128_do_cce_flush(dev_priv);
742 }
743
744 return r128_do_cce_idle(dev_priv);
745 }
746
747 int r128_engine_reset(DRM_IOCTL_ARGS)
748 {
749 DRM_DEVICE;
750 DRM_DEBUG("\n");
751
752 LOCK_TEST_WITH_RETURN(dev, filp);
753
754 return r128_do_engine_reset(dev);
755 }
756
757 int r128_fullscreen(DRM_IOCTL_ARGS)
758 {
759 return DRM_ERR(EINVAL);
760 }
761
762 /* ================================================================
763 * Freelist management
764 */
765 #define R128_BUFFER_USED 0xffffffff
766 #define R128_BUFFER_FREE 0
767
768 #if 0
769 static int r128_freelist_init(drm_device_t * dev)
770 {
771 drm_device_dma_t *dma = dev->dma;
772 drm_r128_private_t *dev_priv = dev->dev_private;
773 drm_buf_t *buf;
774 drm_r128_buf_priv_t *buf_priv;
775 drm_r128_freelist_t *entry;
776 int i;
777
778 dev_priv->head = drm_alloc(sizeof(drm_r128_freelist_t), DRM_MEM_DRIVER);
779 if (dev_priv->head == NULL)
780 return DRM_ERR(ENOMEM);
781
782 memset(dev_priv->head, 0, sizeof(drm_r128_freelist_t));
783 dev_priv->head->age = R128_BUFFER_USED;
784
785 for (i = 0; i < dma->buf_count; i++) {
786 buf = dma->buflist[i];
787 buf_priv = buf->dev_private;
788
789 entry = drm_alloc(sizeof(drm_r128_freelist_t), DRM_MEM_DRIVER);
790 if (!entry)
791 return DRM_ERR(ENOMEM);
792
793 entry->age = R128_BUFFER_FREE;
794 entry->buf = buf;
795 entry->prev = dev_priv->head;
796 entry->next = dev_priv->head->next;
797 if (!entry->next)
798 dev_priv->tail = entry;
799
800 buf_priv->discard = 0;
801 buf_priv->dispatched = 0;
802 buf_priv->list_entry = entry;
803
804 dev_priv->head->next = entry;
805
806 if (dev_priv->head->next)
807 dev_priv->head->next->prev = entry;
808 }
809
810 return 0;
811
812 }
813 #endif
814
815 static drm_buf_t *r128_freelist_get(drm_device_t * dev)
816 {
817 drm_device_dma_t *dma = dev->dma;
818 drm_r128_private_t *dev_priv = dev->dev_private;
819 drm_r128_buf_priv_t *buf_priv;
820 drm_buf_t *buf;
821 int i, t;
822
823 /* FIXME: Optimize -- use freelist code */
824
825 for (i = 0; i < dma->buf_count; i++) {
826 buf = dma->buflist[i];
827 buf_priv = buf->dev_private;
828 if (buf->filp == 0)
829 return buf;
830 }
831
832 for (t = 0; t < dev_priv->usec_timeout; t++) {
833 u32 done_age = R128_READ(R128_LAST_DISPATCH_REG);
834
835 for (i = 0; i < dma->buf_count; i++) {
836 buf = dma->buflist[i];
837 buf_priv = buf->dev_private;
838 if (buf->pending && buf_priv->age <= done_age) {
839 /* The buffer has been processed, so it
840 * can now be used.
841 */
842 buf->pending = 0;
843 return buf;
844 }
845 }
846 DRM_UDELAY(1);
847 }
848
849 DRM_DEBUG("returning NULL!\n");
850 return NULL;
851 }
852
853 void r128_freelist_reset(drm_device_t * dev)
854 {
855 drm_device_dma_t *dma = dev->dma;
856 int i;
857
858 for (i = 0; i < dma->buf_count; i++) {
859 drm_buf_t *buf = dma->buflist[i];
860 drm_r128_buf_priv_t *buf_priv = buf->dev_private;
861 buf_priv->age = 0;
862 }
863 }
864
865 /* ================================================================
866 * CCE command submission
867 */
868
869 int r128_wait_ring(drm_r128_private_t * dev_priv, int n)
870 {
871 drm_r128_ring_buffer_t *ring = &dev_priv->ring;
872 int i;
873
874 for (i = 0; i < dev_priv->usec_timeout; i++) {
875 r128_update_ring_snapshot(dev_priv);
876 if (ring->space >= n)
877 return 0;
878 DRM_UDELAY(1);
879 }
880
881 /* FIXME: This is being ignored... */
882 DRM_ERROR("failed!\n");
883 return DRM_ERR(EBUSY);
884 }
885
886 static int r128_cce_get_buffers(DRMFILE filp, drm_device_t * dev, drm_dma_t * d)
887 {
888 int i;
889 drm_buf_t *buf;
890
891 for (i = d->granted_count; i < d->request_count; i++) {
892 buf = r128_freelist_get(dev);
893 if (!buf)
894 return DRM_ERR(EAGAIN);
895
896 buf->filp = filp;
897
898 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
899 sizeof(buf->idx)))
900 return DRM_ERR(EFAULT);
901 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
902 sizeof(buf->total)))
903 return DRM_ERR(EFAULT);
904
905 d->granted_count++;
906 }
907 return 0;
908 }
909
910 int r128_cce_buffers(DRM_IOCTL_ARGS)
911 {
912 DRM_DEVICE;
913 drm_device_dma_t *dma = dev->dma;
914 int ret = 0;
915 drm_dma_t __user *argp = (void __user *)data;
916 drm_dma_t d;
917
918 LOCK_TEST_WITH_RETURN(dev, filp);
919
920 DRM_COPY_FROM_USER_IOCTL(d, argp, sizeof(d));
921
922 /* Please don't send us buffers.
923 */
924 if (d.send_count != 0) {
925 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
926 DRM_CURRENTPID, d.send_count);
927 return DRM_ERR(EINVAL);
928 }
929
930 /* We'll send you buffers.
931 */
932 if (d.request_count < 0 || d.request_count > dma->buf_count) {
933 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
934 DRM_CURRENTPID, d.request_count, dma->buf_count);
935 return DRM_ERR(EINVAL);
936 }
937
938 d.granted_count = 0;
939
940 if (d.request_count) {
941 ret = r128_cce_get_buffers(filp, dev, &d);
942 }
943
944 DRM_COPY_TO_USER_IOCTL(argp, d, sizeof(d));
945
946 return ret;
947 }
Verdex Pro support