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[ALSA] hda-intel - Fix a compile error with CONFIG_SND_DEBUG_DETECT=y
[linux-2.6/verdex.git] / sound / pci / hda / hda_intel.c
blobf3242e1a7315fb9465301fe87a34df8cd6daa428
1 /*
2 *
3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
37 #include <asm/io.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/kernel.h>
41 #include <linux/module.h>
42 #include <linux/moduleparam.h>
43 #include <linux/init.h>
44 #include <linux/slab.h>
45 #include <linux/pci.h>
46 #include <linux/mutex.h>
47 #include <sound/core.h>
48 #include <sound/initval.h>
49 #include "hda_codec.h"
50
51
52 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
53 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
54 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
55 static char *model[SNDRV_CARDS];
56 static int position_fix[SNDRV_CARDS];
57 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
58 static int single_cmd;
59 static int enable_msi;
60
61 module_param_array(index, int, NULL, 0444);
62 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
63 module_param_array(id, charp, NULL, 0444);
64 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
65 module_param_array(enable, bool, NULL, 0444);
66 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
67 module_param_array(model, charp, NULL, 0444);
68 MODULE_PARM_DESC(model, "Use the given board model.");
69 module_param_array(position_fix, int, NULL, 0444);
70 MODULE_PARM_DESC(position_fix, "Fix DMA pointer "
71 "(0 = auto, 1 = none, 2 = POSBUF, 3 = FIFO size).");
72 module_param_array(probe_mask, int, NULL, 0444);
73 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
74 module_param(single_cmd, bool, 0444);
75 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
76 "(for debugging only).");
77 module_param(enable_msi, int, 0444);
78 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
79
80 #ifdef CONFIG_SND_HDA_POWER_SAVE
81 /* power_save option is defined in hda_codec.c */
82
83 /* reset the HD-audio controller in power save mode.
84 * this may give more power-saving, but will take longer time to
85 * wake up.
86 */
87 static int power_save_controller = 1;
88 module_param(power_save_controller, bool, 0644);
89 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
90 #endif
91
92 MODULE_LICENSE("GPL");
93 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
94 "{Intel, ICH6M},"
95 "{Intel, ICH7},"
96 "{Intel, ESB2},"
97 "{Intel, ICH8},"
98 "{Intel, ICH9},"
99 "{Intel, ICH10},"
100 "{Intel, SCH},"
101 "{ATI, SB450},"
102 "{ATI, SB600},"
103 "{ATI, RS600},"
104 "{ATI, RS690},"
105 "{ATI, RS780},"
106 "{ATI, R600},"
107 "{ATI, RV630},"
108 "{ATI, RV610},"
109 "{ATI, RV670},"
110 "{ATI, RV635},"
111 "{ATI, RV620},"
112 "{ATI, RV770},"
113 "{VIA, VT8251},"
114 "{VIA, VT8237A},"
115 "{SiS, SIS966},"
116 "{ULI, M5461}}");
117 MODULE_DESCRIPTION("Intel HDA driver");
118
119 #define SFX "hda-intel: "
120
121
122 /*
123 * registers
124 */
125 #define ICH6_REG_GCAP 0x00
126 #define ICH6_REG_VMIN 0x02
127 #define ICH6_REG_VMAJ 0x03
128 #define ICH6_REG_OUTPAY 0x04
129 #define ICH6_REG_INPAY 0x06
130 #define ICH6_REG_GCTL 0x08
131 #define ICH6_REG_WAKEEN 0x0c
132 #define ICH6_REG_STATESTS 0x0e
133 #define ICH6_REG_GSTS 0x10
134 #define ICH6_REG_INTCTL 0x20
135 #define ICH6_REG_INTSTS 0x24
136 #define ICH6_REG_WALCLK 0x30
137 #define ICH6_REG_SYNC 0x34
138 #define ICH6_REG_CORBLBASE 0x40
139 #define ICH6_REG_CORBUBASE 0x44
140 #define ICH6_REG_CORBWP 0x48
141 #define ICH6_REG_CORBRP 0x4A
142 #define ICH6_REG_CORBCTL 0x4c
143 #define ICH6_REG_CORBSTS 0x4d
144 #define ICH6_REG_CORBSIZE 0x4e
145
146 #define ICH6_REG_RIRBLBASE 0x50
147 #define ICH6_REG_RIRBUBASE 0x54
148 #define ICH6_REG_RIRBWP 0x58
149 #define ICH6_REG_RINTCNT 0x5a
150 #define ICH6_REG_RIRBCTL 0x5c
151 #define ICH6_REG_RIRBSTS 0x5d
152 #define ICH6_REG_RIRBSIZE 0x5e
153
154 #define ICH6_REG_IC 0x60
155 #define ICH6_REG_IR 0x64
156 #define ICH6_REG_IRS 0x68
157 #define ICH6_IRS_VALID (1<<1)
158 #define ICH6_IRS_BUSY (1<<0)
159
160 #define ICH6_REG_DPLBASE 0x70
161 #define ICH6_REG_DPUBASE 0x74
162 #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
163
164 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
165 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
166
167 /* stream register offsets from stream base */
168 #define ICH6_REG_SD_CTL 0x00
169 #define ICH6_REG_SD_STS 0x03
170 #define ICH6_REG_SD_LPIB 0x04
171 #define ICH6_REG_SD_CBL 0x08
172 #define ICH6_REG_SD_LVI 0x0c
173 #define ICH6_REG_SD_FIFOW 0x0e
174 #define ICH6_REG_SD_FIFOSIZE 0x10
175 #define ICH6_REG_SD_FORMAT 0x12
176 #define ICH6_REG_SD_BDLPL 0x18
177 #define ICH6_REG_SD_BDLPU 0x1c
178
179 /* PCI space */
180 #define ICH6_PCIREG_TCSEL 0x44
181
182 /*
183 * other constants
184 */
185
186 /* max number of SDs */
187 /* ICH, ATI and VIA have 4 playback and 4 capture */
188 #define ICH6_CAPTURE_INDEX 0
189 #define ICH6_NUM_CAPTURE 4
190 #define ICH6_PLAYBACK_INDEX 4
191 #define ICH6_NUM_PLAYBACK 4
192
193 /* ULI has 6 playback and 5 capture */
194 #define ULI_CAPTURE_INDEX 0
195 #define ULI_NUM_CAPTURE 5
196 #define ULI_PLAYBACK_INDEX 5
197 #define ULI_NUM_PLAYBACK 6
198
199 /* ATI HDMI has 1 playback and 0 capture */
200 #define ATIHDMI_CAPTURE_INDEX 0
201 #define ATIHDMI_NUM_CAPTURE 0
202 #define ATIHDMI_PLAYBACK_INDEX 0
203 #define ATIHDMI_NUM_PLAYBACK 1
204
205 /* this number is statically defined for simplicity */
206 #define MAX_AZX_DEV 16
207
208 /* max number of fragments - we may use more if allocating more pages for BDL */
209 #define BDL_SIZE 4096
210 #define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
211 #define AZX_MAX_FRAG 32
212 /* max buffer size - no h/w limit, you can increase as you like */
213 #define AZX_MAX_BUF_SIZE (1024*1024*1024)
214 /* max number of PCM devics per card */
215 #define AZX_MAX_PCMS 8
216
217 /* RIRB int mask: overrun[2], response[0] */
218 #define RIRB_INT_RESPONSE 0x01
219 #define RIRB_INT_OVERRUN 0x04
220 #define RIRB_INT_MASK 0x05
221
222 /* STATESTS int mask: SD2,SD1,SD0 */
223 #define AZX_MAX_CODECS 3
224 #define STATESTS_INT_MASK 0x07
225
226 /* SD_CTL bits */
227 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
228 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
229 #define SD_CTL_STREAM_TAG_MASK (0xf << 20)
230 #define SD_CTL_STREAM_TAG_SHIFT 20
231
232 /* SD_CTL and SD_STS */
233 #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
234 #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
235 #define SD_INT_COMPLETE 0x04 /* completion interrupt */
236 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
237 SD_INT_COMPLETE)
238
239 /* SD_STS */
240 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */
241
242 /* INTCTL and INTSTS */
243 #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
244 #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
245 #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
246
247 /* GCTL unsolicited response enable bit */
248 #define ICH6_GCTL_UREN (1<<8)
249
250 /* GCTL reset bit */
251 #define ICH6_GCTL_RESET (1<<0)
252
253 /* CORB/RIRB control, read/write pointer */
254 #define ICH6_RBCTL_DMA_EN 0x02 /* enable DMA */
255 #define ICH6_RBCTL_IRQ_EN 0x01 /* enable IRQ */
256 #define ICH6_RBRWP_CLR 0x8000 /* read/write pointer clear */
257 /* below are so far hardcoded - should read registers in future */
258 #define ICH6_MAX_CORB_ENTRIES 256
259 #define ICH6_MAX_RIRB_ENTRIES 256
260
261 /* position fix mode */
262 enum {
263 POS_FIX_AUTO,
264 POS_FIX_NONE,
265 POS_FIX_POSBUF,
266 POS_FIX_FIFO,
267 };
268
269 /* Defines for ATI HD Audio support in SB450 south bridge */
270 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
271 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
272
273 /* Defines for Nvidia HDA support */
274 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
275 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
276
277 /* Defines for Intel SCH HDA snoop control */
278 #define INTEL_SCH_HDA_DEVC 0x78
279 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
280
281
282 /*
283 */
284
285 struct azx_dev {
286 struct snd_dma_buffer bdl; /* BDL buffer */
287 u32 *posbuf; /* position buffer pointer */
288
289 unsigned int bufsize; /* size of the play buffer in bytes */
290 unsigned int frags; /* number for period in the play buffer */
291 unsigned int fifo_size; /* FIFO size */
292
293 void __iomem *sd_addr; /* stream descriptor pointer */
294
295 u32 sd_int_sta_mask; /* stream int status mask */
296
297 /* pcm support */
298 struct snd_pcm_substream *substream; /* assigned substream,
299 * set in PCM open
300 */
301 unsigned int format_val; /* format value to be set in the
302 * controller and the codec
303 */
304 unsigned char stream_tag; /* assigned stream */
305 unsigned char index; /* stream index */
306 /* for sanity check of position buffer */
307 unsigned int period_intr;
308
309 unsigned int opened :1;
310 unsigned int running :1;
311 };
312
313 /* CORB/RIRB */
314 struct azx_rb {
315 u32 *buf; /* CORB/RIRB buffer
316 * Each CORB entry is 4byte, RIRB is 8byte
317 */
318 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
319 /* for RIRB */
320 unsigned short rp, wp; /* read/write pointers */
321 int cmds; /* number of pending requests */
322 u32 res; /* last read value */
323 };
324
325 struct azx {
326 struct snd_card *card;
327 struct pci_dev *pci;
328
329 /* chip type specific */
330 int driver_type;
331 int playback_streams;
332 int playback_index_offset;
333 int capture_streams;
334 int capture_index_offset;
335 int num_streams;
336
337 /* pci resources */
338 unsigned long addr;
339 void __iomem *remap_addr;
340 int irq;
341
342 /* locks */
343 spinlock_t reg_lock;
344 struct mutex open_mutex;
345
346 /* streams (x num_streams) */
347 struct azx_dev *azx_dev;
348
349 /* PCM */
350 struct snd_pcm *pcm[AZX_MAX_PCMS];
351
352 /* HD codec */
353 unsigned short codec_mask;
354 struct hda_bus *bus;
355
356 /* CORB/RIRB */
357 struct azx_rb corb;
358 struct azx_rb rirb;
359
360 /* CORB/RIRB and position buffers */
361 struct snd_dma_buffer rb;
362 struct snd_dma_buffer posbuf;
363
364 /* flags */
365 int position_fix;
366 unsigned int running :1;
367 unsigned int initialized :1;
368 unsigned int single_cmd :1;
369 unsigned int polling_mode :1;
370 unsigned int msi :1;
371
372 /* for debugging */
373 unsigned int last_cmd; /* last issued command (to sync) */
374 };
375
376 /* driver types */
377 enum {
378 AZX_DRIVER_ICH,
379 AZX_DRIVER_SCH,
380 AZX_DRIVER_ATI,
381 AZX_DRIVER_ATIHDMI,
382 AZX_DRIVER_VIA,
383 AZX_DRIVER_SIS,
384 AZX_DRIVER_ULI,
385 AZX_DRIVER_NVIDIA,
386 };
387
388 static char *driver_short_names[] __devinitdata = {
389 [AZX_DRIVER_ICH] = "HDA Intel",
390 [AZX_DRIVER_SCH] = "HDA Intel MID",
391 [AZX_DRIVER_ATI] = "HDA ATI SB",
392 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
393 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
394 [AZX_DRIVER_SIS] = "HDA SIS966",
395 [AZX_DRIVER_ULI] = "HDA ULI M5461",
396 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
397 };
398
399 /*
400 * macros for easy use
401 */
402 #define azx_writel(chip,reg,value) \
403 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
404 #define azx_readl(chip,reg) \
405 readl((chip)->remap_addr + ICH6_REG_##reg)
406 #define azx_writew(chip,reg,value) \
407 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
408 #define azx_readw(chip,reg) \
409 readw((chip)->remap_addr + ICH6_REG_##reg)
410 #define azx_writeb(chip,reg,value) \
411 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
412 #define azx_readb(chip,reg) \
413 readb((chip)->remap_addr + ICH6_REG_##reg)
414
415 #define azx_sd_writel(dev,reg,value) \
416 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
417 #define azx_sd_readl(dev,reg) \
418 readl((dev)->sd_addr + ICH6_REG_##reg)
419 #define azx_sd_writew(dev,reg,value) \
420 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
421 #define azx_sd_readw(dev,reg) \
422 readw((dev)->sd_addr + ICH6_REG_##reg)
423 #define azx_sd_writeb(dev,reg,value) \
424 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
425 #define azx_sd_readb(dev,reg) \
426 readb((dev)->sd_addr + ICH6_REG_##reg)
427
428 /* for pcm support */
429 #define get_azx_dev(substream) (substream->runtime->private_data)
430
431 /* Get the upper 32bit of the given dma_addr_t
432 * Compiler should optimize and eliminate the code if dma_addr_t is 32bit
433 */
434 #define upper_32bit(addr) (sizeof(addr) > 4 ? (u32)((addr) >> 32) : (u32)0)
435
436 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
437
438 /*
439 * Interface for HD codec
440 */
441
442 /*
443 * CORB / RIRB interface
444 */
445 static int azx_alloc_cmd_io(struct azx *chip)
446 {
447 int err;
448
449 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
450 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
451 snd_dma_pci_data(chip->pci),
452 PAGE_SIZE, &chip->rb);
453 if (err < 0) {
454 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
455 return err;
456 }
457 return 0;
458 }
459
460 static void azx_init_cmd_io(struct azx *chip)
461 {
462 /* CORB set up */
463 chip->corb.addr = chip->rb.addr;
464 chip->corb.buf = (u32 *)chip->rb.area;
465 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
466 azx_writel(chip, CORBUBASE, upper_32bit(chip->corb.addr));
467
468 /* set the corb size to 256 entries (ULI requires explicitly) */
469 azx_writeb(chip, CORBSIZE, 0x02);
470 /* set the corb write pointer to 0 */
471 azx_writew(chip, CORBWP, 0);
472 /* reset the corb hw read pointer */
473 azx_writew(chip, CORBRP, ICH6_RBRWP_CLR);
474 /* enable corb dma */
475 azx_writeb(chip, CORBCTL, ICH6_RBCTL_DMA_EN);
476
477 /* RIRB set up */
478 chip->rirb.addr = chip->rb.addr + 2048;
479 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
480 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
481 azx_writel(chip, RIRBUBASE, upper_32bit(chip->rirb.addr));
482
483 /* set the rirb size to 256 entries (ULI requires explicitly) */
484 azx_writeb(chip, RIRBSIZE, 0x02);
485 /* reset the rirb hw write pointer */
486 azx_writew(chip, RIRBWP, ICH6_RBRWP_CLR);
487 /* set N=1, get RIRB response interrupt for new entry */
488 azx_writew(chip, RINTCNT, 1);
489 /* enable rirb dma and response irq */
490 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
491 chip->rirb.rp = chip->rirb.cmds = 0;
492 }
493
494 static void azx_free_cmd_io(struct azx *chip)
495 {
496 /* disable ringbuffer DMAs */
497 azx_writeb(chip, RIRBCTL, 0);
498 azx_writeb(chip, CORBCTL, 0);
499 }
500
501 /* send a command */
502 static int azx_corb_send_cmd(struct hda_codec *codec, u32 val)
503 {
504 struct azx *chip = codec->bus->private_data;
505 unsigned int wp;
506
507 /* add command to corb */
508 wp = azx_readb(chip, CORBWP);
509 wp++;
510 wp %= ICH6_MAX_CORB_ENTRIES;
511
512 spin_lock_irq(&chip->reg_lock);
513 chip->rirb.cmds++;
514 chip->corb.buf[wp] = cpu_to_le32(val);
515 azx_writel(chip, CORBWP, wp);
516 spin_unlock_irq(&chip->reg_lock);
517
518 return 0;
519 }
520
521 #define ICH6_RIRB_EX_UNSOL_EV (1<<4)
522
523 /* retrieve RIRB entry - called from interrupt handler */
524 static void azx_update_rirb(struct azx *chip)
525 {
526 unsigned int rp, wp;
527 u32 res, res_ex;
528
529 wp = azx_readb(chip, RIRBWP);
530 if (wp == chip->rirb.wp)
531 return;
532 chip->rirb.wp = wp;
533
534 while (chip->rirb.rp != wp) {
535 chip->rirb.rp++;
536 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
537
538 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
539 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
540 res = le32_to_cpu(chip->rirb.buf[rp]);
541 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
542 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
543 else if (chip->rirb.cmds) {
544 chip->rirb.cmds--;
545 chip->rirb.res = res;
546 }
547 }
548 }
549
550 /* receive a response */
551 static unsigned int azx_rirb_get_response(struct hda_codec *codec)
552 {
553 struct azx *chip = codec->bus->private_data;
554 unsigned long timeout;
555
556 again:
557 timeout = jiffies + msecs_to_jiffies(1000);
558 for (;;) {
559 if (chip->polling_mode) {
560 spin_lock_irq(&chip->reg_lock);
561 azx_update_rirb(chip);
562 spin_unlock_irq(&chip->reg_lock);
563 }
564 if (!chip->rirb.cmds)
565 return chip->rirb.res; /* the last value */
566 if (time_after(jiffies, timeout))
567 break;
568 if (codec->bus->needs_damn_long_delay)
569 msleep(2); /* temporary workaround */
570 else {
571 udelay(10);
572 cond_resched();
573 }
574 }
575
576 if (chip->msi) {
577 snd_printk(KERN_WARNING "hda_intel: No response from codec, "
578 "disabling MSI: last cmd=0x%08x\n", chip->last_cmd);
579 free_irq(chip->irq, chip);
580 chip->irq = -1;
581 pci_disable_msi(chip->pci);
582 chip->msi = 0;
583 if (azx_acquire_irq(chip, 1) < 0)
584 return -1;
585 goto again;
586 }
587
588 if (!chip->polling_mode) {
589 snd_printk(KERN_WARNING "hda_intel: azx_get_response timeout, "
590 "switching to polling mode: last cmd=0x%08x\n",
591 chip->last_cmd);
592 chip->polling_mode = 1;
593 goto again;
594 }
595
596 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
597 "switching to single_cmd mode: last cmd=0x%08x\n",
598 chip->last_cmd);
599 chip->rirb.rp = azx_readb(chip, RIRBWP);
600 chip->rirb.cmds = 0;
601 /* switch to single_cmd mode */
602 chip->single_cmd = 1;
603 azx_free_cmd_io(chip);
604 return -1;
605 }
606
607 /*
608 * Use the single immediate command instead of CORB/RIRB for simplicity
609 *
610 * Note: according to Intel, this is not preferred use. The command was
611 * intended for the BIOS only, and may get confused with unsolicited
612 * responses. So, we shouldn't use it for normal operation from the
613 * driver.
614 * I left the codes, however, for debugging/testing purposes.
615 */
616
617 /* send a command */
618 static int azx_single_send_cmd(struct hda_codec *codec, u32 val)
619 {
620 struct azx *chip = codec->bus->private_data;
621 int timeout = 50;
622
623 while (timeout--) {
624 /* check ICB busy bit */
625 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
626 /* Clear IRV valid bit */
627 azx_writew(chip, IRS, azx_readw(chip, IRS) |
628 ICH6_IRS_VALID);
629 azx_writel(chip, IC, val);
630 azx_writew(chip, IRS, azx_readw(chip, IRS) |
631 ICH6_IRS_BUSY);
632 return 0;
633 }
634 udelay(1);
635 }
636 if (printk_ratelimit())
637 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
638 azx_readw(chip, IRS), val);
639 return -EIO;
640 }
641
642 /* receive a response */
643 static unsigned int azx_single_get_response(struct hda_codec *codec)
644 {
645 struct azx *chip = codec->bus->private_data;
646 int timeout = 50;
647
648 while (timeout--) {
649 /* check IRV busy bit */
650 if (azx_readw(chip, IRS) & ICH6_IRS_VALID)
651 return azx_readl(chip, IR);
652 udelay(1);
653 }
654 if (printk_ratelimit())
655 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
656 azx_readw(chip, IRS));
657 return (unsigned int)-1;
658 }
659
660 /*
661 * The below are the main callbacks from hda_codec.
662 *
663 * They are just the skeleton to call sub-callbacks according to the
664 * current setting of chip->single_cmd.
665 */
666
667 /* send a command */
668 static int azx_send_cmd(struct hda_codec *codec, hda_nid_t nid,
669 int direct, unsigned int verb,
670 unsigned int para)
671 {
672 struct azx *chip = codec->bus->private_data;
673 u32 val;
674
675 val = (u32)(codec->addr & 0x0f) << 28;
676 val |= (u32)direct << 27;
677 val |= (u32)nid << 20;
678 val |= verb << 8;
679 val |= para;
680 chip->last_cmd = val;
681
682 if (chip->single_cmd)
683 return azx_single_send_cmd(codec, val);
684 else
685 return azx_corb_send_cmd(codec, val);
686 }
687
688 /* get a response */
689 static unsigned int azx_get_response(struct hda_codec *codec)
690 {
691 struct azx *chip = codec->bus->private_data;
692 if (chip->single_cmd)
693 return azx_single_get_response(codec);
694 else
695 return azx_rirb_get_response(codec);
696 }
697
698 #ifdef CONFIG_SND_HDA_POWER_SAVE
699 static void azx_power_notify(struct hda_codec *codec);
700 #endif
701
702 /* reset codec link */
703 static int azx_reset(struct azx *chip)
704 {
705 int count;
706
707 /* clear STATESTS */
708 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
709
710 /* reset controller */
711 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
712
713 count = 50;
714 while (azx_readb(chip, GCTL) && --count)
715 msleep(1);
716
717 /* delay for >= 100us for codec PLL to settle per spec
718 * Rev 0.9 section 5.5.1
719 */
720 msleep(1);
721
722 /* Bring controller out of reset */
723 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
724
725 count = 50;
726 while (!azx_readb(chip, GCTL) && --count)
727 msleep(1);
728
729 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
730 msleep(1);
731
732 /* check to see if controller is ready */
733 if (!azx_readb(chip, GCTL)) {
734 snd_printd("azx_reset: controller not ready!\n");
735 return -EBUSY;
736 }
737
738 /* Accept unsolicited responses */
739 azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UREN);
740
741 /* detect codecs */
742 if (!chip->codec_mask) {
743 chip->codec_mask = azx_readw(chip, STATESTS);
744 snd_printdd("codec_mask = 0x%x\n", chip->codec_mask);
745 }
746
747 return 0;
748 }
749
750
751 /*
752 * Lowlevel interface
753 */
754
755 /* enable interrupts */
756 static void azx_int_enable(struct azx *chip)
757 {
758 /* enable controller CIE and GIE */
759 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
760 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
761 }
762
763 /* disable interrupts */
764 static void azx_int_disable(struct azx *chip)
765 {
766 int i;
767
768 /* disable interrupts in stream descriptor */
769 for (i = 0; i < chip->num_streams; i++) {
770 struct azx_dev *azx_dev = &chip->azx_dev[i];
771 azx_sd_writeb(azx_dev, SD_CTL,
772 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
773 }
774
775 /* disable SIE for all streams */
776 azx_writeb(chip, INTCTL, 0);
777
778 /* disable controller CIE and GIE */
779 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
780 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
781 }
782
783 /* clear interrupts */
784 static void azx_int_clear(struct azx *chip)
785 {
786 int i;
787
788 /* clear stream status */
789 for (i = 0; i < chip->num_streams; i++) {
790 struct azx_dev *azx_dev = &chip->azx_dev[i];
791 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
792 }
793
794 /* clear STATESTS */
795 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
796
797 /* clear rirb status */
798 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
799
800 /* clear int status */
801 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
802 }
803
804 /* start a stream */
805 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
806 {
807 /* enable SIE */
808 azx_writeb(chip, INTCTL,
809 azx_readb(chip, INTCTL) | (1 << azx_dev->index));
810 /* set DMA start and interrupt mask */
811 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
812 SD_CTL_DMA_START | SD_INT_MASK);
813 }
814
815 /* stop a stream */
816 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
817 {
818 /* stop DMA */
819 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
820 ~(SD_CTL_DMA_START | SD_INT_MASK));
821 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
822 /* disable SIE */
823 azx_writeb(chip, INTCTL,
824 azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
825 }
826
827
828 /*
829 * reset and start the controller registers
830 */
831 static void azx_init_chip(struct azx *chip)
832 {
833 if (chip->initialized)
834 return;
835
836 /* reset controller */
837 azx_reset(chip);
838
839 /* initialize interrupts */
840 azx_int_clear(chip);
841 azx_int_enable(chip);
842
843 /* initialize the codec command I/O */
844 if (!chip->single_cmd)
845 azx_init_cmd_io(chip);
846
847 /* program the position buffer */
848 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
849 azx_writel(chip, DPUBASE, upper_32bit(chip->posbuf.addr));
850
851 chip->initialized = 1;
852 }
853
854 /*
855 * initialize the PCI registers
856 */
857 /* update bits in a PCI register byte */
858 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
859 unsigned char mask, unsigned char val)
860 {
861 unsigned char data;
862
863 pci_read_config_byte(pci, reg, &data);
864 data &= ~mask;
865 data |= (val & mask);
866 pci_write_config_byte(pci, reg, data);
867 }
868
869 static void azx_init_pci(struct azx *chip)
870 {
871 unsigned short snoop;
872
873 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
874 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
875 * Ensuring these bits are 0 clears playback static on some HD Audio
876 * codecs
877 */
878 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
879
880 switch (chip->driver_type) {
881 case AZX_DRIVER_ATI:
882 /* For ATI SB450 azalia HD audio, we need to enable snoop */
883 update_pci_byte(chip->pci,
884 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
885 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
886 break;
887 case AZX_DRIVER_NVIDIA:
888 /* For NVIDIA HDA, enable snoop */
889 update_pci_byte(chip->pci,
890 NVIDIA_HDA_TRANSREG_ADDR,
891 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
892 break;
893 case AZX_DRIVER_SCH:
894 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
895 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) {
896 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, \
897 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP));
898 pci_read_config_word(chip->pci,
899 INTEL_SCH_HDA_DEVC, &snoop);
900 snd_printdd("HDA snoop disabled, enabling ... %s\n",\
901 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) \
902 ? "Failed" : "OK");
903 }
904 break;
905
906 }
907 }
908
909
910 /*
911 * interrupt handler
912 */
913 static irqreturn_t azx_interrupt(int irq, void *dev_id)
914 {
915 struct azx *chip = dev_id;
916 struct azx_dev *azx_dev;
917 u32 status;
918 int i;
919
920 spin_lock(&chip->reg_lock);
921
922 status = azx_readl(chip, INTSTS);
923 if (status == 0) {
924 spin_unlock(&chip->reg_lock);
925 return IRQ_NONE;
926 }
927
928 for (i = 0; i < chip->num_streams; i++) {
929 azx_dev = &chip->azx_dev[i];
930 if (status & azx_dev->sd_int_sta_mask) {
931 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
932 if (azx_dev->substream && azx_dev->running) {
933 azx_dev->period_intr++;
934 spin_unlock(&chip->reg_lock);
935 snd_pcm_period_elapsed(azx_dev->substream);
936 spin_lock(&chip->reg_lock);
937 }
938 }
939 }
940
941 /* clear rirb int */
942 status = azx_readb(chip, RIRBSTS);
943 if (status & RIRB_INT_MASK) {
944 if (!chip->single_cmd && (status & RIRB_INT_RESPONSE))
945 azx_update_rirb(chip);
946 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
947 }
948
949 #if 0
950 /* clear state status int */
951 if (azx_readb(chip, STATESTS) & 0x04)
952 azx_writeb(chip, STATESTS, 0x04);
953 #endif
954 spin_unlock(&chip->reg_lock);
955
956 return IRQ_HANDLED;
957 }
958
959
960 /*
961 * set up BDL entries
962 */
963 static int azx_setup_periods(struct snd_pcm_substream *substream,
964 struct azx_dev *azx_dev)
965 {
966 struct snd_sg_buf *sgbuf = snd_pcm_substream_sgbuf(substream);
967 u32 *bdl;
968 int i, ofs, periods, period_bytes;
969
970 /* reset BDL address */
971 azx_sd_writel(azx_dev, SD_BDLPL, 0);
972 azx_sd_writel(azx_dev, SD_BDLPU, 0);
973
974 period_bytes = snd_pcm_lib_period_bytes(substream);
975 periods = azx_dev->bufsize / period_bytes;
976
977 /* program the initial BDL entries */
978 bdl = (u32 *)azx_dev->bdl.area;
979 ofs = 0;
980 azx_dev->frags = 0;
981 for (i = 0; i < periods; i++) {
982 int size, rest;
983 if (i >= AZX_MAX_BDL_ENTRIES) {
984 snd_printk(KERN_ERR "Too many BDL entries: "
985 "buffer=%d, period=%d\n",
986 azx_dev->bufsize, period_bytes);
987 /* reset */
988 azx_sd_writel(azx_dev, SD_BDLPL, 0);
989 azx_sd_writel(azx_dev, SD_BDLPU, 0);
990 return -EINVAL;
991 }
992 rest = period_bytes;
993 do {
994 dma_addr_t addr = snd_pcm_sgbuf_get_addr(sgbuf, ofs);
995 /* program the address field of the BDL entry */
996 bdl[0] = cpu_to_le32((u32)addr);
997 bdl[1] = cpu_to_le32(upper_32bit(addr));
998 /* program the size field of the BDL entry */
999 size = PAGE_SIZE - (ofs % PAGE_SIZE);
1000 if (rest < size)
1001 size = rest;
1002 bdl[2] = cpu_to_le32(size);
1003 /* program the IOC to enable interrupt
1004 * only when the whole fragment is processed
1005 */
1006 rest -= size;
1007 bdl[3] = rest ? 0 : cpu_to_le32(0x01);
1008 bdl += 4;
1009 azx_dev->frags++;
1010 ofs += size;
1011 } while (rest > 0);
1012 }
1013 return 0;
1014 }
1015
1016 /*
1017 * set up the SD for streaming
1018 */
1019 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1020 {
1021 unsigned char val;
1022 int timeout;
1023
1024 /* make sure the run bit is zero for SD */
1025 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1026 ~SD_CTL_DMA_START);
1027 /* reset stream */
1028 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1029 SD_CTL_STREAM_RESET);
1030 udelay(3);
1031 timeout = 300;
1032 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1033 --timeout)
1034 ;
1035 val &= ~SD_CTL_STREAM_RESET;
1036 azx_sd_writeb(azx_dev, SD_CTL, val);
1037 udelay(3);
1038
1039 timeout = 300;
1040 /* waiting for hardware to report that the stream is out of reset */
1041 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1042 --timeout)
1043 ;
1044
1045 /* program the stream_tag */
1046 azx_sd_writel(azx_dev, SD_CTL,
1047 (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
1048 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1049
1050 /* program the length of samples in cyclic buffer */
1051 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1052
1053 /* program the stream format */
1054 /* this value needs to be the same as the one programmed */
1055 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1056
1057 /* program the stream LVI (last valid index) of the BDL */
1058 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1059
1060 /* program the BDL address */
1061 /* lower BDL address */
1062 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1063 /* upper BDL address */
1064 azx_sd_writel(azx_dev, SD_BDLPU, upper_32bit(azx_dev->bdl.addr));
1065
1066 /* enable the position buffer */
1067 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1068 azx_writel(chip, DPLBASE,
1069 (u32)chip->posbuf.addr |ICH6_DPLBASE_ENABLE);
1070
1071 /* set the interrupt enable bits in the descriptor control register */
1072 azx_sd_writel(azx_dev, SD_CTL,
1073 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1074
1075 return 0;
1076 }
1077
1078
1079 /*
1080 * Codec initialization
1081 */
1082
1083 static unsigned int azx_max_codecs[] __devinitdata = {
1084 [AZX_DRIVER_ICH] = 3,
1085 [AZX_DRIVER_SCH] = 3,
1086 [AZX_DRIVER_ATI] = 4,
1087 [AZX_DRIVER_ATIHDMI] = 4,
1088 [AZX_DRIVER_VIA] = 3, /* FIXME: correct? */
1089 [AZX_DRIVER_SIS] = 3, /* FIXME: correct? */
1090 [AZX_DRIVER_ULI] = 3, /* FIXME: correct? */
1091 [AZX_DRIVER_NVIDIA] = 3, /* FIXME: correct? */
1092 };
1093
1094 static int __devinit azx_codec_create(struct azx *chip, const char *model,
1095 unsigned int codec_probe_mask)
1096 {
1097 struct hda_bus_template bus_temp;
1098 int c, codecs, audio_codecs, err;
1099
1100 memset(&bus_temp, 0, sizeof(bus_temp));
1101 bus_temp.private_data = chip;
1102 bus_temp.modelname = model;
1103 bus_temp.pci = chip->pci;
1104 bus_temp.ops.command = azx_send_cmd;
1105 bus_temp.ops.get_response = azx_get_response;
1106 #ifdef CONFIG_SND_HDA_POWER_SAVE
1107 bus_temp.ops.pm_notify = azx_power_notify;
1108 #endif
1109
1110 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1111 if (err < 0)
1112 return err;
1113
1114 codecs = audio_codecs = 0;
1115 for (c = 0; c < AZX_MAX_CODECS; c++) {
1116 if ((chip->codec_mask & (1 << c)) & codec_probe_mask) {
1117 struct hda_codec *codec;
1118 err = snd_hda_codec_new(chip->bus, c, &codec);
1119 if (err < 0)
1120 continue;
1121 codecs++;
1122 if (codec->afg)
1123 audio_codecs++;
1124 }
1125 }
1126 if (!audio_codecs) {
1127 /* probe additional slots if no codec is found */
1128 for (; c < azx_max_codecs[chip->driver_type]; c++) {
1129 if ((chip->codec_mask & (1 << c)) & codec_probe_mask) {
1130 err = snd_hda_codec_new(chip->bus, c, NULL);
1131 if (err < 0)
1132 continue;
1133 codecs++;
1134 }
1135 }
1136 }
1137 if (!codecs) {
1138 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1139 return -ENXIO;
1140 }
1141
1142 return 0;
1143 }
1144
1145
1146 /*
1147 * PCM support
1148 */
1149
1150 /* assign a stream for the PCM */
1151 static inline struct azx_dev *azx_assign_device(struct azx *chip, int stream)
1152 {
1153 int dev, i, nums;
1154 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1155 dev = chip->playback_index_offset;
1156 nums = chip->playback_streams;
1157 } else {
1158 dev = chip->capture_index_offset;
1159 nums = chip->capture_streams;
1160 }
1161 for (i = 0; i < nums; i++, dev++)
1162 if (!chip->azx_dev[dev].opened) {
1163 chip->azx_dev[dev].opened = 1;
1164 return &chip->azx_dev[dev];
1165 }
1166 return NULL;
1167 }
1168
1169 /* release the assigned stream */
1170 static inline void azx_release_device(struct azx_dev *azx_dev)
1171 {
1172 azx_dev->opened = 0;
1173 }
1174
1175 static struct snd_pcm_hardware azx_pcm_hw = {
1176 .info = (SNDRV_PCM_INFO_MMAP |
1177 SNDRV_PCM_INFO_INTERLEAVED |
1178 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1179 SNDRV_PCM_INFO_MMAP_VALID |
1180 /* No full-resume yet implemented */
1181 /* SNDRV_PCM_INFO_RESUME |*/
1182 SNDRV_PCM_INFO_PAUSE),
1183 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1184 .rates = SNDRV_PCM_RATE_48000,
1185 .rate_min = 48000,
1186 .rate_max = 48000,
1187 .channels_min = 2,
1188 .channels_max = 2,
1189 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1190 .period_bytes_min = 128,
1191 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1192 .periods_min = 2,
1193 .periods_max = AZX_MAX_FRAG,
1194 .fifo_size = 0,
1195 };
1196
1197 struct azx_pcm {
1198 struct azx *chip;
1199 struct hda_codec *codec;
1200 struct hda_pcm_stream *hinfo[2];
1201 };
1202
1203 static int azx_pcm_open(struct snd_pcm_substream *substream)
1204 {
1205 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1206 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1207 struct azx *chip = apcm->chip;
1208 struct azx_dev *azx_dev;
1209 struct snd_pcm_runtime *runtime = substream->runtime;
1210 unsigned long flags;
1211 int err;
1212
1213 mutex_lock(&chip->open_mutex);
1214 azx_dev = azx_assign_device(chip, substream->stream);
1215 if (azx_dev == NULL) {
1216 mutex_unlock(&chip->open_mutex);
1217 return -EBUSY;
1218 }
1219 runtime->hw = azx_pcm_hw;
1220 runtime->hw.channels_min = hinfo->channels_min;
1221 runtime->hw.channels_max = hinfo->channels_max;
1222 runtime->hw.formats = hinfo->formats;
1223 runtime->hw.rates = hinfo->rates;
1224 snd_pcm_limit_hw_rates(runtime);
1225 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1226 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1227 128);
1228 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1229 128);
1230 snd_hda_power_up(apcm->codec);
1231 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1232 if (err < 0) {
1233 azx_release_device(azx_dev);
1234 snd_hda_power_down(apcm->codec);
1235 mutex_unlock(&chip->open_mutex);
1236 return err;
1237 }
1238 spin_lock_irqsave(&chip->reg_lock, flags);
1239 azx_dev->substream = substream;
1240 azx_dev->running = 0;
1241 spin_unlock_irqrestore(&chip->reg_lock, flags);
1242
1243 runtime->private_data = azx_dev;
1244 mutex_unlock(&chip->open_mutex);
1245 return 0;
1246 }
1247
1248 static int azx_pcm_close(struct snd_pcm_substream *substream)
1249 {
1250 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1251 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1252 struct azx *chip = apcm->chip;
1253 struct azx_dev *azx_dev = get_azx_dev(substream);
1254 unsigned long flags;
1255
1256 mutex_lock(&chip->open_mutex);
1257 spin_lock_irqsave(&chip->reg_lock, flags);
1258 azx_dev->substream = NULL;
1259 azx_dev->running = 0;
1260 spin_unlock_irqrestore(&chip->reg_lock, flags);
1261 azx_release_device(azx_dev);
1262 hinfo->ops.close(hinfo, apcm->codec, substream);
1263 snd_hda_power_down(apcm->codec);
1264 mutex_unlock(&chip->open_mutex);
1265 return 0;
1266 }
1267
1268 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1269 struct snd_pcm_hw_params *hw_params)
1270 {
1271 return snd_pcm_lib_malloc_pages(substream,
1272 params_buffer_bytes(hw_params));
1273 }
1274
1275 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1276 {
1277 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1278 struct azx_dev *azx_dev = get_azx_dev(substream);
1279 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1280
1281 /* reset BDL address */
1282 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1283 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1284 azx_sd_writel(azx_dev, SD_CTL, 0);
1285
1286 hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1287
1288 return snd_pcm_lib_free_pages(substream);
1289 }
1290
1291 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1292 {
1293 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1294 struct azx *chip = apcm->chip;
1295 struct azx_dev *azx_dev = get_azx_dev(substream);
1296 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1297 struct snd_pcm_runtime *runtime = substream->runtime;
1298
1299 azx_dev->bufsize = snd_pcm_lib_buffer_bytes(substream);
1300 azx_dev->format_val = snd_hda_calc_stream_format(runtime->rate,
1301 runtime->channels,
1302 runtime->format,
1303 hinfo->maxbps);
1304 if (!azx_dev->format_val) {
1305 snd_printk(KERN_ERR SFX
1306 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1307 runtime->rate, runtime->channels, runtime->format);
1308 return -EINVAL;
1309 }
1310
1311 snd_printdd("azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1312 azx_dev->bufsize, azx_dev->format_val);
1313 if (azx_setup_periods(substream, azx_dev) < 0)
1314 return -EINVAL;
1315 azx_setup_controller(chip, azx_dev);
1316 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1317 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1318 else
1319 azx_dev->fifo_size = 0;
1320
1321 return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1322 azx_dev->format_val, substream);
1323 }
1324
1325 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1326 {
1327 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1328 struct azx_dev *azx_dev = get_azx_dev(substream);
1329 struct azx *chip = apcm->chip;
1330 int err = 0;
1331
1332 spin_lock(&chip->reg_lock);
1333 switch (cmd) {
1334 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1335 case SNDRV_PCM_TRIGGER_RESUME:
1336 case SNDRV_PCM_TRIGGER_START:
1337 azx_stream_start(chip, azx_dev);
1338 azx_dev->running = 1;
1339 break;
1340 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1341 case SNDRV_PCM_TRIGGER_SUSPEND:
1342 case SNDRV_PCM_TRIGGER_STOP:
1343 azx_stream_stop(chip, azx_dev);
1344 azx_dev->running = 0;
1345 break;
1346 default:
1347 err = -EINVAL;
1348 }
1349 spin_unlock(&chip->reg_lock);
1350 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH ||
1351 cmd == SNDRV_PCM_TRIGGER_SUSPEND ||
1352 cmd == SNDRV_PCM_TRIGGER_STOP) {
1353 int timeout = 5000;
1354 while ((azx_sd_readb(azx_dev, SD_CTL) & SD_CTL_DMA_START) &&
1355 --timeout)
1356 ;
1357 }
1358 return err;
1359 }
1360
1361 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1362 {
1363 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1364 struct azx *chip = apcm->chip;
1365 struct azx_dev *azx_dev = get_azx_dev(substream);
1366 unsigned int pos;
1367
1368 if (chip->position_fix == POS_FIX_POSBUF ||
1369 chip->position_fix == POS_FIX_AUTO) {
1370 /* use the position buffer */
1371 pos = le32_to_cpu(*azx_dev->posbuf);
1372 if (chip->position_fix == POS_FIX_AUTO &&
1373 azx_dev->period_intr == 1 && !pos) {
1374 printk(KERN_WARNING
1375 "hda-intel: Invalid position buffer, "
1376 "using LPIB read method instead.\n");
1377 chip->position_fix = POS_FIX_NONE;
1378 goto read_lpib;
1379 }
1380 } else {
1381 read_lpib:
1382 /* read LPIB */
1383 pos = azx_sd_readl(azx_dev, SD_LPIB);
1384 if (chip->position_fix == POS_FIX_FIFO)
1385 pos += azx_dev->fifo_size;
1386 }
1387 if (pos >= azx_dev->bufsize)
1388 pos = 0;
1389 return bytes_to_frames(substream->runtime, pos);
1390 }
1391
1392 static struct snd_pcm_ops azx_pcm_ops = {
1393 .open = azx_pcm_open,
1394 .close = azx_pcm_close,
1395 .ioctl = snd_pcm_lib_ioctl,
1396 .hw_params = azx_pcm_hw_params,
1397 .hw_free = azx_pcm_hw_free,
1398 .prepare = azx_pcm_prepare,
1399 .trigger = azx_pcm_trigger,
1400 .pointer = azx_pcm_pointer,
1401 .page = snd_pcm_sgbuf_ops_page,
1402 };
1403
1404 static void azx_pcm_free(struct snd_pcm *pcm)
1405 {
1406 kfree(pcm->private_data);
1407 }
1408
1409 static int __devinit create_codec_pcm(struct azx *chip, struct hda_codec *codec,
1410 struct hda_pcm *cpcm)
1411 {
1412 int err;
1413 struct snd_pcm *pcm;
1414 struct azx_pcm *apcm;
1415
1416 /* if no substreams are defined for both playback and capture,
1417 * it's just a placeholder. ignore it.
1418 */
1419 if (!cpcm->stream[0].substreams && !cpcm->stream[1].substreams)
1420 return 0;
1421
1422 snd_assert(cpcm->name, return -EINVAL);
1423
1424 err = snd_pcm_new(chip->card, cpcm->name, cpcm->device,
1425 cpcm->stream[0].substreams,
1426 cpcm->stream[1].substreams,
1427 &pcm);
1428 if (err < 0)
1429 return err;
1430 strcpy(pcm->name, cpcm->name);
1431 apcm = kmalloc(sizeof(*apcm), GFP_KERNEL);
1432 if (apcm == NULL)
1433 return -ENOMEM;
1434 apcm->chip = chip;
1435 apcm->codec = codec;
1436 apcm->hinfo[0] = &cpcm->stream[0];
1437 apcm->hinfo[1] = &cpcm->stream[1];
1438 pcm->private_data = apcm;
1439 pcm->private_free = azx_pcm_free;
1440 if (cpcm->stream[0].substreams)
1441 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &azx_pcm_ops);
1442 if (cpcm->stream[1].substreams)
1443 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &azx_pcm_ops);
1444 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
1445 snd_dma_pci_data(chip->pci),
1446 1024 * 64, 1024 * 1024);
1447 chip->pcm[cpcm->device] = pcm;
1448 return 0;
1449 }
1450
1451 static int __devinit azx_pcm_create(struct azx *chip)
1452 {
1453 static const char *dev_name[HDA_PCM_NTYPES] = {
1454 "Audio", "SPDIF", "HDMI", "Modem"
1455 };
1456 /* starting device index for each PCM type */
1457 static int dev_idx[HDA_PCM_NTYPES] = {
1458 [HDA_PCM_TYPE_AUDIO] = 0,
1459 [HDA_PCM_TYPE_SPDIF] = 1,
1460 [HDA_PCM_TYPE_HDMI] = 3,
1461 [HDA_PCM_TYPE_MODEM] = 6
1462 };
1463 /* normal audio device indices; not linear to keep compatibility */
1464 static int audio_idx[4] = { 0, 2, 4, 5 };
1465 struct hda_codec *codec;
1466 int c, err;
1467 int num_devs[HDA_PCM_NTYPES];
1468
1469 err = snd_hda_build_pcms(chip->bus);
1470 if (err < 0)
1471 return err;
1472
1473 /* create audio PCMs */
1474 memset(num_devs, 0, sizeof(num_devs));
1475 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1476 for (c = 0; c < codec->num_pcms; c++) {
1477 struct hda_pcm *cpcm = &codec->pcm_info[c];
1478 int type = cpcm->pcm_type;
1479 switch (type) {
1480 case HDA_PCM_TYPE_AUDIO:
1481 if (num_devs[type] >= ARRAY_SIZE(audio_idx)) {
1482 snd_printk(KERN_WARNING
1483 "Too many audio devices\n");
1484 continue;
1485 }
1486 cpcm->device = audio_idx[num_devs[type]];
1487 break;
1488 case HDA_PCM_TYPE_SPDIF:
1489 case HDA_PCM_TYPE_HDMI:
1490 case HDA_PCM_TYPE_MODEM:
1491 if (num_devs[type]) {
1492 snd_printk(KERN_WARNING
1493 "%s already defined\n",
1494 dev_name[type]);
1495 continue;
1496 }
1497 cpcm->device = dev_idx[type];
1498 break;
1499 default:
1500 snd_printk(KERN_WARNING
1501 "Invalid PCM type %d\n", type);
1502 continue;
1503 }
1504 num_devs[type]++;
1505 err = create_codec_pcm(chip, codec, cpcm);
1506 if (err < 0)
1507 return err;
1508 }
1509 }
1510 return 0;
1511 }
1512
1513 /*
1514 * mixer creation - all stuff is implemented in hda module
1515 */
1516 static int __devinit azx_mixer_create(struct azx *chip)
1517 {
1518 return snd_hda_build_controls(chip->bus);
1519 }
1520
1521
1522 /*
1523 * initialize SD streams
1524 */
1525 static int __devinit azx_init_stream(struct azx *chip)
1526 {
1527 int i;
1528
1529 /* initialize each stream (aka device)
1530 * assign the starting bdl address to each stream (device)
1531 * and initialize
1532 */
1533 for (i = 0; i < chip->num_streams; i++) {
1534 struct azx_dev *azx_dev = &chip->azx_dev[i];
1535 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1536 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1537 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
1538 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1539 azx_dev->sd_int_sta_mask = 1 << i;
1540 /* stream tag: must be non-zero and unique */
1541 azx_dev->index = i;
1542 azx_dev->stream_tag = i + 1;
1543 }
1544
1545 return 0;
1546 }
1547
1548 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
1549 {
1550 if (request_irq(chip->pci->irq, azx_interrupt,
1551 chip->msi ? 0 : IRQF_SHARED,
1552 "HDA Intel", chip)) {
1553 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
1554 "disabling device\n", chip->pci->irq);
1555 if (do_disconnect)
1556 snd_card_disconnect(chip->card);
1557 return -1;
1558 }
1559 chip->irq = chip->pci->irq;
1560 pci_intx(chip->pci, !chip->msi);
1561 return 0;
1562 }
1563
1564
1565 static void azx_stop_chip(struct azx *chip)
1566 {
1567 if (!chip->initialized)
1568 return;
1569
1570 /* disable interrupts */
1571 azx_int_disable(chip);
1572 azx_int_clear(chip);
1573
1574 /* disable CORB/RIRB */
1575 azx_free_cmd_io(chip);
1576
1577 /* disable position buffer */
1578 azx_writel(chip, DPLBASE, 0);
1579 azx_writel(chip, DPUBASE, 0);
1580
1581 chip->initialized = 0;
1582 }
1583
1584 #ifdef CONFIG_SND_HDA_POWER_SAVE
1585 /* power-up/down the controller */
1586 static void azx_power_notify(struct hda_codec *codec)
1587 {
1588 struct azx *chip = codec->bus->private_data;
1589 struct hda_codec *c;
1590 int power_on = 0;
1591
1592 list_for_each_entry(c, &codec->bus->codec_list, list) {
1593 if (c->power_on) {
1594 power_on = 1;
1595 break;
1596 }
1597 }
1598 if (power_on)
1599 azx_init_chip(chip);
1600 else if (chip->running && power_save_controller)
1601 azx_stop_chip(chip);
1602 }
1603 #endif /* CONFIG_SND_HDA_POWER_SAVE */
1604
1605 #ifdef CONFIG_PM
1606 /*
1607 * power management
1608 */
1609 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
1610 {
1611 struct snd_card *card = pci_get_drvdata(pci);
1612 struct azx *chip = card->private_data;
1613 int i;
1614
1615 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1616 for (i = 0; i < AZX_MAX_PCMS; i++)
1617 snd_pcm_suspend_all(chip->pcm[i]);
1618 if (chip->initialized)
1619 snd_hda_suspend(chip->bus, state);
1620 azx_stop_chip(chip);
1621 if (chip->irq >= 0) {
1622 synchronize_irq(chip->irq);
1623 free_irq(chip->irq, chip);
1624 chip->irq = -1;
1625 }
1626 if (chip->msi)
1627 pci_disable_msi(chip->pci);
1628 pci_disable_device(pci);
1629 pci_save_state(pci);
1630 pci_set_power_state(pci, pci_choose_state(pci, state));
1631 return 0;
1632 }
1633
1634 static int azx_resume(struct pci_dev *pci)
1635 {
1636 struct snd_card *card = pci_get_drvdata(pci);
1637 struct azx *chip = card->private_data;
1638
1639 pci_set_power_state(pci, PCI_D0);
1640 pci_restore_state(pci);
1641 if (pci_enable_device(pci) < 0) {
1642 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
1643 "disabling device\n");
1644 snd_card_disconnect(card);
1645 return -EIO;
1646 }
1647 pci_set_master(pci);
1648 if (chip->msi)
1649 if (pci_enable_msi(pci) < 0)
1650 chip->msi = 0;
1651 if (azx_acquire_irq(chip, 1) < 0)
1652 return -EIO;
1653 azx_init_pci(chip);
1654
1655 if (snd_hda_codecs_inuse(chip->bus))
1656 azx_init_chip(chip);
1657
1658 snd_hda_resume(chip->bus);
1659 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1660 return 0;
1661 }
1662 #endif /* CONFIG_PM */
1663
1664
1665 /*
1666 * destructor
1667 */
1668 static int azx_free(struct azx *chip)
1669 {
1670 int i;
1671
1672 if (chip->initialized) {
1673 for (i = 0; i < chip->num_streams; i++)
1674 azx_stream_stop(chip, &chip->azx_dev[i]);
1675 azx_stop_chip(chip);
1676 }
1677
1678 if (chip->irq >= 0) {
1679 synchronize_irq(chip->irq);
1680 free_irq(chip->irq, (void*)chip);
1681 }
1682 if (chip->msi)
1683 pci_disable_msi(chip->pci);
1684 if (chip->remap_addr)
1685 iounmap(chip->remap_addr);
1686
1687 if (chip->azx_dev) {
1688 for (i = 0; i < chip->num_streams; i++)
1689 if (chip->azx_dev[i].bdl.area)
1690 snd_dma_free_pages(&chip->azx_dev[i].bdl);
1691 }
1692 if (chip->rb.area)
1693 snd_dma_free_pages(&chip->rb);
1694 if (chip->posbuf.area)
1695 snd_dma_free_pages(&chip->posbuf);
1696 pci_release_regions(chip->pci);
1697 pci_disable_device(chip->pci);
1698 kfree(chip->azx_dev);
1699 kfree(chip);
1700
1701 return 0;
1702 }
1703
1704 static int azx_dev_free(struct snd_device *device)
1705 {
1706 return azx_free(device->device_data);
1707 }
1708
1709 /*
1710 * white/black-listing for position_fix
1711 */
1712 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
1713 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_NONE),
1714 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_NONE),
1715 {}
1716 };
1717
1718 static int __devinit check_position_fix(struct azx *chip, int fix)
1719 {
1720 const struct snd_pci_quirk *q;
1721
1722 if (fix == POS_FIX_AUTO) {
1723 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1724 if (q) {
1725 printk(KERN_INFO
1726 "hda_intel: position_fix set to %d "
1727 "for device %04x:%04x\n",
1728 q->value, q->subvendor, q->subdevice);
1729 return q->value;
1730 }
1731 }
1732 return fix;
1733 }
1734
1735 /*
1736 * black-lists for probe_mask
1737 */
1738 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
1739 /* Thinkpad often breaks the controller communication when accessing
1740 * to the non-working (or non-existing) modem codec slot.
1741 */
1742 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1743 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1744 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1745 {}
1746 };
1747
1748 static void __devinit check_probe_mask(struct azx *chip, int dev)
1749 {
1750 const struct snd_pci_quirk *q;
1751
1752 if (probe_mask[dev] == -1) {
1753 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1754 if (q) {
1755 printk(KERN_INFO
1756 "hda_intel: probe_mask set to 0x%x "
1757 "for device %04x:%04x\n",
1758 q->value, q->subvendor, q->subdevice);
1759 probe_mask[dev] = q->value;
1760 }
1761 }
1762 }
1763
1764
1765 /*
1766 * constructor
1767 */
1768 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
1769 int dev, int driver_type,
1770 struct azx **rchip)
1771 {
1772 struct azx *chip;
1773 int i, err;
1774 unsigned short gcap;
1775 static struct snd_device_ops ops = {
1776 .dev_free = azx_dev_free,
1777 };
1778
1779 *rchip = NULL;
1780
1781 err = pci_enable_device(pci);
1782 if (err < 0)
1783 return err;
1784
1785 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1786 if (!chip) {
1787 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
1788 pci_disable_device(pci);
1789 return -ENOMEM;
1790 }
1791
1792 spin_lock_init(&chip->reg_lock);
1793 mutex_init(&chip->open_mutex);
1794 chip->card = card;
1795 chip->pci = pci;
1796 chip->irq = -1;
1797 chip->driver_type = driver_type;
1798 chip->msi = enable_msi;
1799
1800 chip->position_fix = check_position_fix(chip, position_fix[dev]);
1801 check_probe_mask(chip, dev);
1802
1803 chip->single_cmd = single_cmd;
1804
1805 #if BITS_PER_LONG != 64
1806 /* Fix up base address on ULI M5461 */
1807 if (chip->driver_type == AZX_DRIVER_ULI) {
1808 u16 tmp3;
1809 pci_read_config_word(pci, 0x40, &tmp3);
1810 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1811 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1812 }
1813 #endif
1814
1815 err = pci_request_regions(pci, "ICH HD audio");
1816 if (err < 0) {
1817 kfree(chip);
1818 pci_disable_device(pci);
1819 return err;
1820 }
1821
1822 chip->addr = pci_resource_start(pci, 0);
1823 chip->remap_addr = ioremap_nocache(chip->addr, pci_resource_len(pci,0));
1824 if (chip->remap_addr == NULL) {
1825 snd_printk(KERN_ERR SFX "ioremap error\n");
1826 err = -ENXIO;
1827 goto errout;
1828 }
1829
1830 if (chip->msi)
1831 if (pci_enable_msi(pci) < 0)
1832 chip->msi = 0;
1833
1834 if (azx_acquire_irq(chip, 0) < 0) {
1835 err = -EBUSY;
1836 goto errout;
1837 }
1838
1839 pci_set_master(pci);
1840 synchronize_irq(chip->irq);
1841
1842 gcap = azx_readw(chip, GCAP);
1843 snd_printdd("chipset global capabilities = 0x%x\n", gcap);
1844
1845 /* allow 64bit DMA address if supported by H/W */
1846 if ((gcap & 0x01) && !pci_set_dma_mask(pci, DMA_64BIT_MASK))
1847 pci_set_consistent_dma_mask(pci, DMA_64BIT_MASK);
1848
1849 if (gcap) {
1850 /* read number of streams from GCAP register instead of using
1851 * hardcoded value
1852 */
1853 chip->playback_streams = (gcap & (0xF << 12)) >> 12;
1854 chip->capture_streams = (gcap & (0xF << 8)) >> 8;
1855 chip->playback_index_offset = chip->capture_streams;
1856 chip->capture_index_offset = 0;
1857 } else {
1858 /* gcap didn't give any info, switching to old method */
1859
1860 switch (chip->driver_type) {
1861 case AZX_DRIVER_ULI:
1862 chip->playback_streams = ULI_NUM_PLAYBACK;
1863 chip->capture_streams = ULI_NUM_CAPTURE;
1864 chip->playback_index_offset = ULI_PLAYBACK_INDEX;
1865 chip->capture_index_offset = ULI_CAPTURE_INDEX;
1866 break;
1867 case AZX_DRIVER_ATIHDMI:
1868 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1869 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1870 chip->playback_index_offset = ATIHDMI_PLAYBACK_INDEX;
1871 chip->capture_index_offset = ATIHDMI_CAPTURE_INDEX;
1872 break;
1873 default:
1874 chip->playback_streams = ICH6_NUM_PLAYBACK;
1875 chip->capture_streams = ICH6_NUM_CAPTURE;
1876 chip->playback_index_offset = ICH6_PLAYBACK_INDEX;
1877 chip->capture_index_offset = ICH6_CAPTURE_INDEX;
1878 break;
1879 }
1880 }
1881 chip->num_streams = chip->playback_streams + chip->capture_streams;
1882 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
1883 GFP_KERNEL);
1884 if (!chip->azx_dev) {
1885 snd_printk(KERN_ERR "cannot malloc azx_dev\n");
1886 goto errout;
1887 }
1888
1889 for (i = 0; i < chip->num_streams; i++) {
1890 /* allocate memory for the BDL for each stream */
1891 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
1892 snd_dma_pci_data(chip->pci),
1893 BDL_SIZE, &chip->azx_dev[i].bdl);
1894 if (err < 0) {
1895 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
1896 goto errout;
1897 }
1898 }
1899 /* allocate memory for the position buffer */
1900 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
1901 snd_dma_pci_data(chip->pci),
1902 chip->num_streams * 8, &chip->posbuf);
1903 if (err < 0) {
1904 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
1905 goto errout;
1906 }
1907 /* allocate CORB/RIRB */
1908 if (!chip->single_cmd) {
1909 err = azx_alloc_cmd_io(chip);
1910 if (err < 0)
1911 goto errout;
1912 }
1913
1914 /* initialize streams */
1915 azx_init_stream(chip);
1916
1917 /* initialize chip */
1918 azx_init_pci(chip);
1919 azx_init_chip(chip);
1920
1921 /* codec detection */
1922 if (!chip->codec_mask) {
1923 snd_printk(KERN_ERR SFX "no codecs found!\n");
1924 err = -ENODEV;
1925 goto errout;
1926 }
1927
1928 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1929 if (err <0) {
1930 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
1931 goto errout;
1932 }
1933
1934 strcpy(card->driver, "HDA-Intel");
1935 strcpy(card->shortname, driver_short_names[chip->driver_type]);
1936 sprintf(card->longname, "%s at 0x%lx irq %i",
1937 card->shortname, chip->addr, chip->irq);
1938
1939 *rchip = chip;
1940 return 0;
1941
1942 errout:
1943 azx_free(chip);
1944 return err;
1945 }
1946
1947 static void power_down_all_codecs(struct azx *chip)
1948 {
1949 #ifdef CONFIG_SND_HDA_POWER_SAVE
1950 /* The codecs were powered up in snd_hda_codec_new().
1951 * Now all initialization done, so turn them down if possible
1952 */
1953 struct hda_codec *codec;
1954 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1955 snd_hda_power_down(codec);
1956 }
1957 #endif
1958 }
1959
1960 static int __devinit azx_probe(struct pci_dev *pci,
1961 const struct pci_device_id *pci_id)
1962 {
1963 static int dev;
1964 struct snd_card *card;
1965 struct azx *chip;
1966 int err;
1967
1968 if (dev >= SNDRV_CARDS)
1969 return -ENODEV;
1970 if (!enable[dev]) {
1971 dev++;
1972 return -ENOENT;
1973 }
1974
1975 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
1976 if (!card) {
1977 snd_printk(KERN_ERR SFX "Error creating card!\n");
1978 return -ENOMEM;
1979 }
1980
1981 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
1982 if (err < 0) {
1983 snd_card_free(card);
1984 return err;
1985 }
1986 card->private_data = chip;
1987
1988 /* create codec instances */
1989 err = azx_codec_create(chip, model[dev], probe_mask[dev]);
1990 if (err < 0) {
1991 snd_card_free(card);
1992 return err;
1993 }
1994
1995 /* create PCM streams */
1996 err = azx_pcm_create(chip);
1997 if (err < 0) {
1998 snd_card_free(card);
1999 return err;
2000 }
2001
2002 /* create mixer controls */
2003 err = azx_mixer_create(chip);
2004 if (err < 0) {
2005 snd_card_free(card);
2006 return err;
2007 }
2008
2009 snd_card_set_dev(card, &pci->dev);
2010
2011 err = snd_card_register(card);
2012 if (err < 0) {
2013 snd_card_free(card);
2014 return err;
2015 }
2016
2017 pci_set_drvdata(pci, card);
2018 chip->running = 1;
2019 power_down_all_codecs(chip);
2020
2021 dev++;
2022 return err;
2023 }
2024
2025 static void __devexit azx_remove(struct pci_dev *pci)
2026 {
2027 snd_card_free(pci_get_drvdata(pci));
2028 pci_set_drvdata(pci, NULL);
2029 }
2030
2031 /* PCI IDs */
2032 static struct pci_device_id azx_ids[] = {
2033 { 0x8086, 0x2668, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH6 */
2034 { 0x8086, 0x27d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH7 */
2035 { 0x8086, 0x269a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ESB2 */
2036 { 0x8086, 0x284b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH8 */
2037 { 0x8086, 0x293e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH9 */
2038 { 0x8086, 0x293f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH9 */
2039 { 0x8086, 0x3a3e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH10 */
2040 { 0x8086, 0x3a6e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH10 */
2041 { 0x8086, 0x811b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_SCH }, /* SCH*/
2042 { 0x1002, 0x437b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATI }, /* ATI SB450 */
2043 { 0x1002, 0x4383, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATI }, /* ATI SB600 */
2044 { 0x1002, 0x793b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RS600 HDMI */
2045 { 0x1002, 0x7919, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RS690 HDMI */
2046 { 0x1002, 0x960f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RS780 HDMI */
2047 { 0x1002, 0xaa00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI R600 HDMI */
2048 { 0x1002, 0xaa08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RV630 HDMI */
2049 { 0x1002, 0xaa10, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RV610 HDMI */
2050 { 0x1002, 0xaa18, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RV670 HDMI */
2051 { 0x1002, 0xaa20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RV635 HDMI */
2052 { 0x1002, 0xaa28, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RV620 HDMI */
2053 { 0x1002, 0xaa30, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RV770 HDMI */
2054 { 0x1106, 0x3288, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_VIA }, /* VIA VT8251/VT8237A */
2055 { 0x1039, 0x7502, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_SIS }, /* SIS966 */
2056 { 0x10b9, 0x5461, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ULI }, /* ULI M5461 */
2057 { 0x10de, 0x026c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP51 */
2058 { 0x10de, 0x0371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP55 */
2059 { 0x10de, 0x03e4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP61 */
2060 { 0x10de, 0x03f0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP61 */
2061 { 0x10de, 0x044a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP65 */
2062 { 0x10de, 0x044b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP65 */
2063 { 0x10de, 0x055c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP67 */
2064 { 0x10de, 0x055d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP67 */
2065 { 0x10de, 0x07fc, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP73 */
2066 { 0x10de, 0x07fd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP73 */
2067 { 0x10de, 0x0774, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP77 */
2068 { 0x10de, 0x0775, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP77 */
2069 { 0x10de, 0x0776, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP77 */
2070 { 0x10de, 0x0777, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP77 */
2071 { 0x10de, 0x0ac0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP79 */
2072 { 0x10de, 0x0ac1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP79 */
2073 { 0x10de, 0x0ac2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP79 */
2074 { 0x10de, 0x0ac3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP79 */
2075 { 0, }
2076 };
2077 MODULE_DEVICE_TABLE(pci, azx_ids);
2078
2079 /* pci_driver definition */
2080 static struct pci_driver driver = {
2081 .name = "HDA Intel",
2082 .id_table = azx_ids,
2083 .probe = azx_probe,
2084 .remove = __devexit_p(azx_remove),
2085 #ifdef CONFIG_PM
2086 .suspend = azx_suspend,
2087 .resume = azx_resume,
2088 #endif
2089 };
2090
2091 static int __init alsa_card_azx_init(void)
2092 {
2093 return pci_register_driver(&driver);
2094 }
2095
2096 static void __exit alsa_card_azx_exit(void)
2097 {
2098 pci_unregister_driver(&driver);
2099 }
2100
2101 module_init(alsa_card_azx_init)
2102 module_exit(alsa_card_azx_exit)
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