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iwlwifi: move spectrum measurement code to iwl-spectrum.c file
[linux-2.6/verdex.git] / drivers / net / jme.c
blob0430ffb62364b1e272b7bdb8a064a401adb7f66b
1 /*
2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3 *
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
6 *
7 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 */
23
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/pci.h>
27 #include <linux/netdevice.h>
28 #include <linux/etherdevice.h>
29 #include <linux/ethtool.h>
30 #include <linux/mii.h>
31 #include <linux/crc32.h>
32 #include <linux/delay.h>
33 #include <linux/spinlock.h>
34 #include <linux/in.h>
35 #include <linux/ip.h>
36 #include <linux/ipv6.h>
37 #include <linux/tcp.h>
38 #include <linux/udp.h>
39 #include <linux/if_vlan.h>
40 #include <net/ip6_checksum.h>
41 #include "jme.h"
42
43 static int force_pseudohp = -1;
44 static int no_pseudohp = -1;
45 static int no_extplug = -1;
46 module_param(force_pseudohp, int, 0);
47 MODULE_PARM_DESC(force_pseudohp,
48 "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
49 module_param(no_pseudohp, int, 0);
50 MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
51 module_param(no_extplug, int, 0);
52 MODULE_PARM_DESC(no_extplug,
53 "Do not use external plug signal for pseudo hot-plug.");
54
55 static int
56 jme_mdio_read(struct net_device *netdev, int phy, int reg)
57 {
58 struct jme_adapter *jme = netdev_priv(netdev);
59 int i, val, again = (reg == MII_BMSR) ? 1 : 0;
60
61 read_again:
62 jwrite32(jme, JME_SMI, SMI_OP_REQ |
63 smi_phy_addr(phy) |
64 smi_reg_addr(reg));
65
66 wmb();
67 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
68 udelay(20);
69 val = jread32(jme, JME_SMI);
70 if ((val & SMI_OP_REQ) == 0)
71 break;
72 }
73
74 if (i == 0) {
75 jeprintk(jme->pdev, "phy(%d) read timeout : %d\n", phy, reg);
76 return 0;
77 }
78
79 if (again--)
80 goto read_again;
81
82 return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
83 }
84
85 static void
86 jme_mdio_write(struct net_device *netdev,
87 int phy, int reg, int val)
88 {
89 struct jme_adapter *jme = netdev_priv(netdev);
90 int i;
91
92 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
93 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
94 smi_phy_addr(phy) | smi_reg_addr(reg));
95
96 wmb();
97 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
98 udelay(20);
99 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
100 break;
101 }
102
103 if (i == 0)
104 jeprintk(jme->pdev, "phy(%d) write timeout : %d\n", phy, reg);
105
106 return;
107 }
108
109 static inline void
110 jme_reset_phy_processor(struct jme_adapter *jme)
111 {
112 u32 val;
113
114 jme_mdio_write(jme->dev,
115 jme->mii_if.phy_id,
116 MII_ADVERTISE, ADVERTISE_ALL |
117 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
118
119 if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
120 jme_mdio_write(jme->dev,
121 jme->mii_if.phy_id,
122 MII_CTRL1000,
123 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
124
125 val = jme_mdio_read(jme->dev,
126 jme->mii_if.phy_id,
127 MII_BMCR);
128
129 jme_mdio_write(jme->dev,
130 jme->mii_if.phy_id,
131 MII_BMCR, val | BMCR_RESET);
132
133 return;
134 }
135
136 static void
137 jme_setup_wakeup_frame(struct jme_adapter *jme,
138 u32 *mask, u32 crc, int fnr)
139 {
140 int i;
141
142 /*
143 * Setup CRC pattern
144 */
145 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
146 wmb();
147 jwrite32(jme, JME_WFODP, crc);
148 wmb();
149
150 /*
151 * Setup Mask
152 */
153 for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
154 jwrite32(jme, JME_WFOI,
155 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
156 (fnr & WFOI_FRAME_SEL));
157 wmb();
158 jwrite32(jme, JME_WFODP, mask[i]);
159 wmb();
160 }
161 }
162
163 static inline void
164 jme_reset_mac_processor(struct jme_adapter *jme)
165 {
166 u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
167 u32 crc = 0xCDCDCDCD;
168 u32 gpreg0;
169 int i;
170
171 jwrite32(jme, JME_GHC, jme->reg_ghc | GHC_SWRST);
172 udelay(2);
173 jwrite32(jme, JME_GHC, jme->reg_ghc);
174
175 jwrite32(jme, JME_RXDBA_LO, 0x00000000);
176 jwrite32(jme, JME_RXDBA_HI, 0x00000000);
177 jwrite32(jme, JME_RXQDC, 0x00000000);
178 jwrite32(jme, JME_RXNDA, 0x00000000);
179 jwrite32(jme, JME_TXDBA_LO, 0x00000000);
180 jwrite32(jme, JME_TXDBA_HI, 0x00000000);
181 jwrite32(jme, JME_TXQDC, 0x00000000);
182 jwrite32(jme, JME_TXNDA, 0x00000000);
183
184 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
185 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
186 for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
187 jme_setup_wakeup_frame(jme, mask, crc, i);
188 if (jme->fpgaver)
189 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
190 else
191 gpreg0 = GPREG0_DEFAULT;
192 jwrite32(jme, JME_GPREG0, gpreg0);
193 jwrite32(jme, JME_GPREG1, GPREG1_DEFAULT);
194 }
195
196 static inline void
197 jme_reset_ghc_speed(struct jme_adapter *jme)
198 {
199 jme->reg_ghc &= ~(GHC_SPEED_1000M | GHC_DPX);
200 jwrite32(jme, JME_GHC, jme->reg_ghc);
201 }
202
203 static inline void
204 jme_clear_pm(struct jme_adapter *jme)
205 {
206 jwrite32(jme, JME_PMCS, 0xFFFF0000 | jme->reg_pmcs);
207 pci_set_power_state(jme->pdev, PCI_D0);
208 pci_enable_wake(jme->pdev, PCI_D0, false);
209 }
210
211 static int
212 jme_reload_eeprom(struct jme_adapter *jme)
213 {
214 u32 val;
215 int i;
216
217 val = jread32(jme, JME_SMBCSR);
218
219 if (val & SMBCSR_EEPROMD) {
220 val |= SMBCSR_CNACK;
221 jwrite32(jme, JME_SMBCSR, val);
222 val |= SMBCSR_RELOAD;
223 jwrite32(jme, JME_SMBCSR, val);
224 mdelay(12);
225
226 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
227 mdelay(1);
228 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
229 break;
230 }
231
232 if (i == 0) {
233 jeprintk(jme->pdev, "eeprom reload timeout\n");
234 return -EIO;
235 }
236 }
237
238 return 0;
239 }
240
241 static void
242 jme_load_macaddr(struct net_device *netdev)
243 {
244 struct jme_adapter *jme = netdev_priv(netdev);
245 unsigned char macaddr[6];
246 u32 val;
247
248 spin_lock_bh(&jme->macaddr_lock);
249 val = jread32(jme, JME_RXUMA_LO);
250 macaddr[0] = (val >> 0) & 0xFF;
251 macaddr[1] = (val >> 8) & 0xFF;
252 macaddr[2] = (val >> 16) & 0xFF;
253 macaddr[3] = (val >> 24) & 0xFF;
254 val = jread32(jme, JME_RXUMA_HI);
255 macaddr[4] = (val >> 0) & 0xFF;
256 macaddr[5] = (val >> 8) & 0xFF;
257 memcpy(netdev->dev_addr, macaddr, 6);
258 spin_unlock_bh(&jme->macaddr_lock);
259 }
260
261 static inline void
262 jme_set_rx_pcc(struct jme_adapter *jme, int p)
263 {
264 switch (p) {
265 case PCC_OFF:
266 jwrite32(jme, JME_PCCRX0,
267 ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
268 ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
269 break;
270 case PCC_P1:
271 jwrite32(jme, JME_PCCRX0,
272 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
273 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
274 break;
275 case PCC_P2:
276 jwrite32(jme, JME_PCCRX0,
277 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
278 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
279 break;
280 case PCC_P3:
281 jwrite32(jme, JME_PCCRX0,
282 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
283 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
284 break;
285 default:
286 break;
287 }
288 wmb();
289
290 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
291 msg_rx_status(jme, "Switched to PCC_P%d\n", p);
292 }
293
294 static void
295 jme_start_irq(struct jme_adapter *jme)
296 {
297 register struct dynpcc_info *dpi = &(jme->dpi);
298
299 jme_set_rx_pcc(jme, PCC_P1);
300 dpi->cur = PCC_P1;
301 dpi->attempt = PCC_P1;
302 dpi->cnt = 0;
303
304 jwrite32(jme, JME_PCCTX,
305 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
306 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
307 PCCTXQ0_EN
308 );
309
310 /*
311 * Enable Interrupts
312 */
313 jwrite32(jme, JME_IENS, INTR_ENABLE);
314 }
315
316 static inline void
317 jme_stop_irq(struct jme_adapter *jme)
318 {
319 /*
320 * Disable Interrupts
321 */
322 jwrite32f(jme, JME_IENC, INTR_ENABLE);
323 }
324
325 static inline void
326 jme_enable_shadow(struct jme_adapter *jme)
327 {
328 jwrite32(jme,
329 JME_SHBA_LO,
330 ((u32)jme->shadow_dma & ~((u32)0x1F)) | SHBA_POSTEN);
331 }
332
333 static inline void
334 jme_disable_shadow(struct jme_adapter *jme)
335 {
336 jwrite32(jme, JME_SHBA_LO, 0x0);
337 }
338
339 static u32
340 jme_linkstat_from_phy(struct jme_adapter *jme)
341 {
342 u32 phylink, bmsr;
343
344 phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
345 bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
346 if (bmsr & BMSR_ANCOMP)
347 phylink |= PHY_LINK_AUTONEG_COMPLETE;
348
349 return phylink;
350 }
351
352 static inline void
353 jme_set_phyfifoa(struct jme_adapter *jme)
354 {
355 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
356 }
357
358 static inline void
359 jme_set_phyfifob(struct jme_adapter *jme)
360 {
361 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
362 }
363
364 static int
365 jme_check_link(struct net_device *netdev, int testonly)
366 {
367 struct jme_adapter *jme = netdev_priv(netdev);
368 u32 phylink, ghc, cnt = JME_SPDRSV_TIMEOUT, bmcr, gpreg1;
369 char linkmsg[64];
370 int rc = 0;
371
372 linkmsg[0] = '\0';
373
374 if (jme->fpgaver)
375 phylink = jme_linkstat_from_phy(jme);
376 else
377 phylink = jread32(jme, JME_PHY_LINK);
378
379 if (phylink & PHY_LINK_UP) {
380 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
381 /*
382 * If we did not enable AN
383 * Speed/Duplex Info should be obtained from SMI
384 */
385 phylink = PHY_LINK_UP;
386
387 bmcr = jme_mdio_read(jme->dev,
388 jme->mii_if.phy_id,
389 MII_BMCR);
390
391 phylink |= ((bmcr & BMCR_SPEED1000) &&
392 (bmcr & BMCR_SPEED100) == 0) ?
393 PHY_LINK_SPEED_1000M :
394 (bmcr & BMCR_SPEED100) ?
395 PHY_LINK_SPEED_100M :
396 PHY_LINK_SPEED_10M;
397
398 phylink |= (bmcr & BMCR_FULLDPLX) ?
399 PHY_LINK_DUPLEX : 0;
400
401 strcat(linkmsg, "Forced: ");
402 } else {
403 /*
404 * Keep polling for speed/duplex resolve complete
405 */
406 while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
407 --cnt) {
408
409 udelay(1);
410
411 if (jme->fpgaver)
412 phylink = jme_linkstat_from_phy(jme);
413 else
414 phylink = jread32(jme, JME_PHY_LINK);
415 }
416 if (!cnt)
417 jeprintk(jme->pdev,
418 "Waiting speed resolve timeout.\n");
419
420 strcat(linkmsg, "ANed: ");
421 }
422
423 if (jme->phylink == phylink) {
424 rc = 1;
425 goto out;
426 }
427 if (testonly)
428 goto out;
429
430 jme->phylink = phylink;
431
432 ghc = jme->reg_ghc & ~(GHC_SPEED_10M |
433 GHC_SPEED_100M |
434 GHC_SPEED_1000M |
435 GHC_DPX);
436 switch (phylink & PHY_LINK_SPEED_MASK) {
437 case PHY_LINK_SPEED_10M:
438 ghc |= GHC_SPEED_10M;
439 strcat(linkmsg, "10 Mbps, ");
440 break;
441 case PHY_LINK_SPEED_100M:
442 ghc |= GHC_SPEED_100M;
443 strcat(linkmsg, "100 Mbps, ");
444 break;
445 case PHY_LINK_SPEED_1000M:
446 ghc |= GHC_SPEED_1000M;
447 strcat(linkmsg, "1000 Mbps, ");
448 break;
449 default:
450 break;
451 }
452
453 if (phylink & PHY_LINK_DUPLEX) {
454 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
455 ghc |= GHC_DPX;
456 } else {
457 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
458 TXMCS_BACKOFF |
459 TXMCS_CARRIERSENSE |
460 TXMCS_COLLISION);
461 jwrite32(jme, JME_TXTRHD, TXTRHD_TXPEN |
462 ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) |
463 TXTRHD_TXREN |
464 ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL));
465 }
466 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
467 "Full-Duplex, " :
468 "Half-Duplex, ");
469
470 if (phylink & PHY_LINK_MDI_STAT)
471 strcat(linkmsg, "MDI-X");
472 else
473 strcat(linkmsg, "MDI");
474
475 gpreg1 = GPREG1_DEFAULT;
476 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
477 if (!(phylink & PHY_LINK_DUPLEX))
478 gpreg1 |= GPREG1_HALFMODEPATCH;
479 switch (phylink & PHY_LINK_SPEED_MASK) {
480 case PHY_LINK_SPEED_10M:
481 jme_set_phyfifoa(jme);
482 gpreg1 |= GPREG1_RSSPATCH;
483 break;
484 case PHY_LINK_SPEED_100M:
485 jme_set_phyfifob(jme);
486 gpreg1 |= GPREG1_RSSPATCH;
487 break;
488 case PHY_LINK_SPEED_1000M:
489 jme_set_phyfifoa(jme);
490 break;
491 default:
492 break;
493 }
494 }
495 jwrite32(jme, JME_GPREG1, gpreg1);
496
497 jme->reg_ghc = ghc;
498 jwrite32(jme, JME_GHC, ghc);
499
500 msg_link(jme, "Link is up at %s.\n", linkmsg);
501 netif_carrier_on(netdev);
502 } else {
503 if (testonly)
504 goto out;
505
506 msg_link(jme, "Link is down.\n");
507 jme->phylink = 0;
508 netif_carrier_off(netdev);
509 }
510
511 out:
512 return rc;
513 }
514
515 static int
516 jme_setup_tx_resources(struct jme_adapter *jme)
517 {
518 struct jme_ring *txring = &(jme->txring[0]);
519
520 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
521 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
522 &(txring->dmaalloc),
523 GFP_ATOMIC);
524
525 if (!txring->alloc) {
526 txring->desc = NULL;
527 txring->dmaalloc = 0;
528 txring->dma = 0;
529 return -ENOMEM;
530 }
531
532 /*
533 * 16 Bytes align
534 */
535 txring->desc = (void *)ALIGN((unsigned long)(txring->alloc),
536 RING_DESC_ALIGN);
537 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
538 txring->next_to_use = 0;
539 atomic_set(&txring->next_to_clean, 0);
540 atomic_set(&txring->nr_free, jme->tx_ring_size);
541
542 /*
543 * Initialize Transmit Descriptors
544 */
545 memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
546 memset(txring->bufinf, 0,
547 sizeof(struct jme_buffer_info) * jme->tx_ring_size);
548
549 return 0;
550 }
551
552 static void
553 jme_free_tx_resources(struct jme_adapter *jme)
554 {
555 int i;
556 struct jme_ring *txring = &(jme->txring[0]);
557 struct jme_buffer_info *txbi = txring->bufinf;
558
559 if (txring->alloc) {
560 for (i = 0 ; i < jme->tx_ring_size ; ++i) {
561 txbi = txring->bufinf + i;
562 if (txbi->skb) {
563 dev_kfree_skb(txbi->skb);
564 txbi->skb = NULL;
565 }
566 txbi->mapping = 0;
567 txbi->len = 0;
568 txbi->nr_desc = 0;
569 txbi->start_xmit = 0;
570 }
571
572 dma_free_coherent(&(jme->pdev->dev),
573 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
574 txring->alloc,
575 txring->dmaalloc);
576
577 txring->alloc = NULL;
578 txring->desc = NULL;
579 txring->dmaalloc = 0;
580 txring->dma = 0;
581 }
582 txring->next_to_use = 0;
583 atomic_set(&txring->next_to_clean, 0);
584 atomic_set(&txring->nr_free, 0);
585
586 }
587
588 static inline void
589 jme_enable_tx_engine(struct jme_adapter *jme)
590 {
591 /*
592 * Select Queue 0
593 */
594 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
595 wmb();
596
597 /*
598 * Setup TX Queue 0 DMA Bass Address
599 */
600 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
601 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
602 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
603
604 /*
605 * Setup TX Descptor Count
606 */
607 jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
608
609 /*
610 * Enable TX Engine
611 */
612 wmb();
613 jwrite32(jme, JME_TXCS, jme->reg_txcs |
614 TXCS_SELECT_QUEUE0 |
615 TXCS_ENABLE);
616
617 }
618
619 static inline void
620 jme_restart_tx_engine(struct jme_adapter *jme)
621 {
622 /*
623 * Restart TX Engine
624 */
625 jwrite32(jme, JME_TXCS, jme->reg_txcs |
626 TXCS_SELECT_QUEUE0 |
627 TXCS_ENABLE);
628 }
629
630 static inline void
631 jme_disable_tx_engine(struct jme_adapter *jme)
632 {
633 int i;
634 u32 val;
635
636 /*
637 * Disable TX Engine
638 */
639 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
640 wmb();
641
642 val = jread32(jme, JME_TXCS);
643 for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
644 mdelay(1);
645 val = jread32(jme, JME_TXCS);
646 rmb();
647 }
648
649 if (!i)
650 jeprintk(jme->pdev, "Disable TX engine timeout.\n");
651 }
652
653 static void
654 jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
655 {
656 struct jme_ring *rxring = jme->rxring;
657 register struct rxdesc *rxdesc = rxring->desc;
658 struct jme_buffer_info *rxbi = rxring->bufinf;
659 rxdesc += i;
660 rxbi += i;
661
662 rxdesc->dw[0] = 0;
663 rxdesc->dw[1] = 0;
664 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
665 rxdesc->desc1.bufaddrl = cpu_to_le32(
666 (__u64)rxbi->mapping & 0xFFFFFFFFUL);
667 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
668 if (jme->dev->features & NETIF_F_HIGHDMA)
669 rxdesc->desc1.flags = RXFLAG_64BIT;
670 wmb();
671 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
672 }
673
674 static int
675 jme_make_new_rx_buf(struct jme_adapter *jme, int i)
676 {
677 struct jme_ring *rxring = &(jme->rxring[0]);
678 struct jme_buffer_info *rxbi = rxring->bufinf + i;
679 struct sk_buff *skb;
680
681 skb = netdev_alloc_skb(jme->dev,
682 jme->dev->mtu + RX_EXTRA_LEN);
683 if (unlikely(!skb))
684 return -ENOMEM;
685
686 rxbi->skb = skb;
687 rxbi->len = skb_tailroom(skb);
688 rxbi->mapping = pci_map_page(jme->pdev,
689 virt_to_page(skb->data),
690 offset_in_page(skb->data),
691 rxbi->len,
692 PCI_DMA_FROMDEVICE);
693
694 return 0;
695 }
696
697 static void
698 jme_free_rx_buf(struct jme_adapter *jme, int i)
699 {
700 struct jme_ring *rxring = &(jme->rxring[0]);
701 struct jme_buffer_info *rxbi = rxring->bufinf;
702 rxbi += i;
703
704 if (rxbi->skb) {
705 pci_unmap_page(jme->pdev,
706 rxbi->mapping,
707 rxbi->len,
708 PCI_DMA_FROMDEVICE);
709 dev_kfree_skb(rxbi->skb);
710 rxbi->skb = NULL;
711 rxbi->mapping = 0;
712 rxbi->len = 0;
713 }
714 }
715
716 static void
717 jme_free_rx_resources(struct jme_adapter *jme)
718 {
719 int i;
720 struct jme_ring *rxring = &(jme->rxring[0]);
721
722 if (rxring->alloc) {
723 for (i = 0 ; i < jme->rx_ring_size ; ++i)
724 jme_free_rx_buf(jme, i);
725
726 dma_free_coherent(&(jme->pdev->dev),
727 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
728 rxring->alloc,
729 rxring->dmaalloc);
730 rxring->alloc = NULL;
731 rxring->desc = NULL;
732 rxring->dmaalloc = 0;
733 rxring->dma = 0;
734 }
735 rxring->next_to_use = 0;
736 atomic_set(&rxring->next_to_clean, 0);
737 }
738
739 static int
740 jme_setup_rx_resources(struct jme_adapter *jme)
741 {
742 int i;
743 struct jme_ring *rxring = &(jme->rxring[0]);
744
745 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
746 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
747 &(rxring->dmaalloc),
748 GFP_ATOMIC);
749 if (!rxring->alloc) {
750 rxring->desc = NULL;
751 rxring->dmaalloc = 0;
752 rxring->dma = 0;
753 return -ENOMEM;
754 }
755
756 /*
757 * 16 Bytes align
758 */
759 rxring->desc = (void *)ALIGN((unsigned long)(rxring->alloc),
760 RING_DESC_ALIGN);
761 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
762 rxring->next_to_use = 0;
763 atomic_set(&rxring->next_to_clean, 0);
764
765 /*
766 * Initiallize Receive Descriptors
767 */
768 for (i = 0 ; i < jme->rx_ring_size ; ++i) {
769 if (unlikely(jme_make_new_rx_buf(jme, i))) {
770 jme_free_rx_resources(jme);
771 return -ENOMEM;
772 }
773
774 jme_set_clean_rxdesc(jme, i);
775 }
776
777 return 0;
778 }
779
780 static inline void
781 jme_enable_rx_engine(struct jme_adapter *jme)
782 {
783 /*
784 * Select Queue 0
785 */
786 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
787 RXCS_QUEUESEL_Q0);
788 wmb();
789
790 /*
791 * Setup RX DMA Bass Address
792 */
793 jwrite32(jme, JME_RXDBA_LO, (__u64)jme->rxring[0].dma & 0xFFFFFFFFUL);
794 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
795 jwrite32(jme, JME_RXNDA, (__u64)jme->rxring[0].dma & 0xFFFFFFFFUL);
796
797 /*
798 * Setup RX Descriptor Count
799 */
800 jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
801
802 /*
803 * Setup Unicast Filter
804 */
805 jme_set_multi(jme->dev);
806
807 /*
808 * Enable RX Engine
809 */
810 wmb();
811 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
812 RXCS_QUEUESEL_Q0 |
813 RXCS_ENABLE |
814 RXCS_QST);
815 }
816
817 static inline void
818 jme_restart_rx_engine(struct jme_adapter *jme)
819 {
820 /*
821 * Start RX Engine
822 */
823 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
824 RXCS_QUEUESEL_Q0 |
825 RXCS_ENABLE |
826 RXCS_QST);
827 }
828
829 static inline void
830 jme_disable_rx_engine(struct jme_adapter *jme)
831 {
832 int i;
833 u32 val;
834
835 /*
836 * Disable RX Engine
837 */
838 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
839 wmb();
840
841 val = jread32(jme, JME_RXCS);
842 for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
843 mdelay(1);
844 val = jread32(jme, JME_RXCS);
845 rmb();
846 }
847
848 if (!i)
849 jeprintk(jme->pdev, "Disable RX engine timeout.\n");
850
851 }
852
853 static int
854 jme_rxsum_ok(struct jme_adapter *jme, u16 flags)
855 {
856 if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
857 return false;
858
859 if (unlikely(!(flags & RXWBFLAG_MF) &&
860 (flags & RXWBFLAG_TCPON) && !(flags & RXWBFLAG_TCPCS))) {
861 msg_rx_err(jme, "TCP Checksum error.\n");
862 goto out_sumerr;
863 }
864
865 if (unlikely(!(flags & RXWBFLAG_MF) &&
866 (flags & RXWBFLAG_UDPON) && !(flags & RXWBFLAG_UDPCS))) {
867 msg_rx_err(jme, "UDP Checksum error.\n");
868 goto out_sumerr;
869 }
870
871 if (unlikely((flags & RXWBFLAG_IPV4) && !(flags & RXWBFLAG_IPCS))) {
872 msg_rx_err(jme, "IPv4 Checksum error.\n");
873 goto out_sumerr;
874 }
875
876 return true;
877
878 out_sumerr:
879 return false;
880 }
881
882 static void
883 jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
884 {
885 struct jme_ring *rxring = &(jme->rxring[0]);
886 struct rxdesc *rxdesc = rxring->desc;
887 struct jme_buffer_info *rxbi = rxring->bufinf;
888 struct sk_buff *skb;
889 int framesize;
890
891 rxdesc += idx;
892 rxbi += idx;
893
894 skb = rxbi->skb;
895 pci_dma_sync_single_for_cpu(jme->pdev,
896 rxbi->mapping,
897 rxbi->len,
898 PCI_DMA_FROMDEVICE);
899
900 if (unlikely(jme_make_new_rx_buf(jme, idx))) {
901 pci_dma_sync_single_for_device(jme->pdev,
902 rxbi->mapping,
903 rxbi->len,
904 PCI_DMA_FROMDEVICE);
905
906 ++(NET_STAT(jme).rx_dropped);
907 } else {
908 framesize = le16_to_cpu(rxdesc->descwb.framesize)
909 - RX_PREPAD_SIZE;
910
911 skb_reserve(skb, RX_PREPAD_SIZE);
912 skb_put(skb, framesize);
913 skb->protocol = eth_type_trans(skb, jme->dev);
914
915 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags)))
916 skb->ip_summed = CHECKSUM_UNNECESSARY;
917 else
918 skb->ip_summed = CHECKSUM_NONE;
919
920 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
921 if (jme->vlgrp) {
922 jme->jme_vlan_rx(skb, jme->vlgrp,
923 le16_to_cpu(rxdesc->descwb.vlan));
924 NET_STAT(jme).rx_bytes += 4;
925 }
926 } else {
927 jme->jme_rx(skb);
928 }
929
930 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) ==
931 cpu_to_le16(RXWBFLAG_DEST_MUL))
932 ++(NET_STAT(jme).multicast);
933
934 NET_STAT(jme).rx_bytes += framesize;
935 ++(NET_STAT(jme).rx_packets);
936 }
937
938 jme_set_clean_rxdesc(jme, idx);
939
940 }
941
942 static int
943 jme_process_receive(struct jme_adapter *jme, int limit)
944 {
945 struct jme_ring *rxring = &(jme->rxring[0]);
946 struct rxdesc *rxdesc = rxring->desc;
947 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
948
949 if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
950 goto out_inc;
951
952 if (unlikely(atomic_read(&jme->link_changing) != 1))
953 goto out_inc;
954
955 if (unlikely(!netif_carrier_ok(jme->dev)))
956 goto out_inc;
957
958 i = atomic_read(&rxring->next_to_clean);
959 while (limit-- > 0) {
960 rxdesc = rxring->desc;
961 rxdesc += i;
962
963 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) ||
964 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
965 goto out;
966
967 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
968
969 if (unlikely(desccnt > 1 ||
970 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
971
972 if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
973 ++(NET_STAT(jme).rx_crc_errors);
974 else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
975 ++(NET_STAT(jme).rx_fifo_errors);
976 else
977 ++(NET_STAT(jme).rx_errors);
978
979 if (desccnt > 1)
980 limit -= desccnt - 1;
981
982 for (j = i, ccnt = desccnt ; ccnt-- ; ) {
983 jme_set_clean_rxdesc(jme, j);
984 j = (j + 1) & (mask);
985 }
986
987 } else {
988 jme_alloc_and_feed_skb(jme, i);
989 }
990
991 i = (i + desccnt) & (mask);
992 }
993
994 out:
995 atomic_set(&rxring->next_to_clean, i);
996
997 out_inc:
998 atomic_inc(&jme->rx_cleaning);
999
1000 return limit > 0 ? limit : 0;
1001
1002 }
1003
1004 static void
1005 jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1006 {
1007 if (likely(atmp == dpi->cur)) {
1008 dpi->cnt = 0;
1009 return;
1010 }
1011
1012 if (dpi->attempt == atmp) {
1013 ++(dpi->cnt);
1014 } else {
1015 dpi->attempt = atmp;
1016 dpi->cnt = 0;
1017 }
1018
1019 }
1020
1021 static void
1022 jme_dynamic_pcc(struct jme_adapter *jme)
1023 {
1024 register struct dynpcc_info *dpi = &(jme->dpi);
1025
1026 if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
1027 jme_attempt_pcc(dpi, PCC_P3);
1028 else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD
1029 || dpi->intr_cnt > PCC_INTR_THRESHOLD)
1030 jme_attempt_pcc(dpi, PCC_P2);
1031 else
1032 jme_attempt_pcc(dpi, PCC_P1);
1033
1034 if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1035 if (dpi->attempt < dpi->cur)
1036 tasklet_schedule(&jme->rxclean_task);
1037 jme_set_rx_pcc(jme, dpi->attempt);
1038 dpi->cur = dpi->attempt;
1039 dpi->cnt = 0;
1040 }
1041 }
1042
1043 static void
1044 jme_start_pcc_timer(struct jme_adapter *jme)
1045 {
1046 struct dynpcc_info *dpi = &(jme->dpi);
1047 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1048 dpi->last_pkts = NET_STAT(jme).rx_packets;
1049 dpi->intr_cnt = 0;
1050 jwrite32(jme, JME_TMCSR,
1051 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1052 }
1053
1054 static inline void
1055 jme_stop_pcc_timer(struct jme_adapter *jme)
1056 {
1057 jwrite32(jme, JME_TMCSR, 0);
1058 }
1059
1060 static void
1061 jme_shutdown_nic(struct jme_adapter *jme)
1062 {
1063 u32 phylink;
1064
1065 phylink = jme_linkstat_from_phy(jme);
1066
1067 if (!(phylink & PHY_LINK_UP)) {
1068 /*
1069 * Disable all interrupt before issue timer
1070 */
1071 jme_stop_irq(jme);
1072 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1073 }
1074 }
1075
1076 static void
1077 jme_pcc_tasklet(unsigned long arg)
1078 {
1079 struct jme_adapter *jme = (struct jme_adapter *)arg;
1080 struct net_device *netdev = jme->dev;
1081
1082 if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1083 jme_shutdown_nic(jme);
1084 return;
1085 }
1086
1087 if (unlikely(!netif_carrier_ok(netdev) ||
1088 (atomic_read(&jme->link_changing) != 1)
1089 )) {
1090 jme_stop_pcc_timer(jme);
1091 return;
1092 }
1093
1094 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
1095 jme_dynamic_pcc(jme);
1096
1097 jme_start_pcc_timer(jme);
1098 }
1099
1100 static inline void
1101 jme_polling_mode(struct jme_adapter *jme)
1102 {
1103 jme_set_rx_pcc(jme, PCC_OFF);
1104 }
1105
1106 static inline void
1107 jme_interrupt_mode(struct jme_adapter *jme)
1108 {
1109 jme_set_rx_pcc(jme, PCC_P1);
1110 }
1111
1112 static inline int
1113 jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1114 {
1115 u32 apmc;
1116 apmc = jread32(jme, JME_APMC);
1117 return apmc & JME_APMC_PSEUDO_HP_EN;
1118 }
1119
1120 static void
1121 jme_start_shutdown_timer(struct jme_adapter *jme)
1122 {
1123 u32 apmc;
1124
1125 apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1126 apmc &= ~JME_APMC_EPIEN_CTRL;
1127 if (!no_extplug) {
1128 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1129 wmb();
1130 }
1131 jwrite32f(jme, JME_APMC, apmc);
1132
1133 jwrite32f(jme, JME_TIMER2, 0);
1134 set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1135 jwrite32(jme, JME_TMCSR,
1136 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1137 }
1138
1139 static void
1140 jme_stop_shutdown_timer(struct jme_adapter *jme)
1141 {
1142 u32 apmc;
1143
1144 jwrite32f(jme, JME_TMCSR, 0);
1145 jwrite32f(jme, JME_TIMER2, 0);
1146 clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1147
1148 apmc = jread32(jme, JME_APMC);
1149 apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1150 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1151 wmb();
1152 jwrite32f(jme, JME_APMC, apmc);
1153 }
1154
1155 static void
1156 jme_link_change_tasklet(unsigned long arg)
1157 {
1158 struct jme_adapter *jme = (struct jme_adapter *)arg;
1159 struct net_device *netdev = jme->dev;
1160 int rc;
1161
1162 while (!atomic_dec_and_test(&jme->link_changing)) {
1163 atomic_inc(&jme->link_changing);
1164 msg_intr(jme, "Get link change lock failed.\n");
1165 while (atomic_read(&jme->link_changing) != 1)
1166 msg_intr(jme, "Waiting link change lock.\n");
1167 }
1168
1169 if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
1170 goto out;
1171
1172 jme->old_mtu = netdev->mtu;
1173 netif_stop_queue(netdev);
1174 if (jme_pseudo_hotplug_enabled(jme))
1175 jme_stop_shutdown_timer(jme);
1176
1177 jme_stop_pcc_timer(jme);
1178 tasklet_disable(&jme->txclean_task);
1179 tasklet_disable(&jme->rxclean_task);
1180 tasklet_disable(&jme->rxempty_task);
1181
1182 if (netif_carrier_ok(netdev)) {
1183 jme_reset_ghc_speed(jme);
1184 jme_disable_rx_engine(jme);
1185 jme_disable_tx_engine(jme);
1186 jme_reset_mac_processor(jme);
1187 jme_free_rx_resources(jme);
1188 jme_free_tx_resources(jme);
1189
1190 if (test_bit(JME_FLAG_POLL, &jme->flags))
1191 jme_polling_mode(jme);
1192
1193 netif_carrier_off(netdev);
1194 }
1195
1196 jme_check_link(netdev, 0);
1197 if (netif_carrier_ok(netdev)) {
1198 rc = jme_setup_rx_resources(jme);
1199 if (rc) {
1200 jeprintk(jme->pdev, "Allocating resources for RX error"
1201 ", Device STOPPED!\n");
1202 goto out_enable_tasklet;
1203 }
1204
1205 rc = jme_setup_tx_resources(jme);
1206 if (rc) {
1207 jeprintk(jme->pdev, "Allocating resources for TX error"
1208 ", Device STOPPED!\n");
1209 goto err_out_free_rx_resources;
1210 }
1211
1212 jme_enable_rx_engine(jme);
1213 jme_enable_tx_engine(jme);
1214
1215 netif_start_queue(netdev);
1216
1217 if (test_bit(JME_FLAG_POLL, &jme->flags))
1218 jme_interrupt_mode(jme);
1219
1220 jme_start_pcc_timer(jme);
1221 } else if (jme_pseudo_hotplug_enabled(jme)) {
1222 jme_start_shutdown_timer(jme);
1223 }
1224
1225 goto out_enable_tasklet;
1226
1227 err_out_free_rx_resources:
1228 jme_free_rx_resources(jme);
1229 out_enable_tasklet:
1230 tasklet_enable(&jme->txclean_task);
1231 tasklet_hi_enable(&jme->rxclean_task);
1232 tasklet_hi_enable(&jme->rxempty_task);
1233 out:
1234 atomic_inc(&jme->link_changing);
1235 }
1236
1237 static void
1238 jme_rx_clean_tasklet(unsigned long arg)
1239 {
1240 struct jme_adapter *jme = (struct jme_adapter *)arg;
1241 struct dynpcc_info *dpi = &(jme->dpi);
1242
1243 jme_process_receive(jme, jme->rx_ring_size);
1244 ++(dpi->intr_cnt);
1245
1246 }
1247
1248 static int
1249 jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
1250 {
1251 struct jme_adapter *jme = jme_napi_priv(holder);
1252 struct net_device *netdev = jme->dev;
1253 int rest;
1254
1255 rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
1256
1257 while (atomic_read(&jme->rx_empty) > 0) {
1258 atomic_dec(&jme->rx_empty);
1259 ++(NET_STAT(jme).rx_dropped);
1260 jme_restart_rx_engine(jme);
1261 }
1262 atomic_inc(&jme->rx_empty);
1263
1264 if (rest) {
1265 JME_RX_COMPLETE(netdev, holder);
1266 jme_interrupt_mode(jme);
1267 }
1268
1269 JME_NAPI_WEIGHT_SET(budget, rest);
1270 return JME_NAPI_WEIGHT_VAL(budget) - rest;
1271 }
1272
1273 static void
1274 jme_rx_empty_tasklet(unsigned long arg)
1275 {
1276 struct jme_adapter *jme = (struct jme_adapter *)arg;
1277
1278 if (unlikely(atomic_read(&jme->link_changing) != 1))
1279 return;
1280
1281 if (unlikely(!netif_carrier_ok(jme->dev)))
1282 return;
1283
1284 msg_rx_status(jme, "RX Queue Full!\n");
1285
1286 jme_rx_clean_tasklet(arg);
1287
1288 while (atomic_read(&jme->rx_empty) > 0) {
1289 atomic_dec(&jme->rx_empty);
1290 ++(NET_STAT(jme).rx_dropped);
1291 jme_restart_rx_engine(jme);
1292 }
1293 atomic_inc(&jme->rx_empty);
1294 }
1295
1296 static void
1297 jme_wake_queue_if_stopped(struct jme_adapter *jme)
1298 {
1299 struct jme_ring *txring = jme->txring;
1300
1301 smp_wmb();
1302 if (unlikely(netif_queue_stopped(jme->dev) &&
1303 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
1304 msg_tx_done(jme, "TX Queue Waked.\n");
1305 netif_wake_queue(jme->dev);
1306 }
1307
1308 }
1309
1310 static void
1311 jme_tx_clean_tasklet(unsigned long arg)
1312 {
1313 struct jme_adapter *jme = (struct jme_adapter *)arg;
1314 struct jme_ring *txring = &(jme->txring[0]);
1315 struct txdesc *txdesc = txring->desc;
1316 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
1317 int i, j, cnt = 0, max, err, mask;
1318
1319 tx_dbg(jme, "Into txclean.\n");
1320
1321 if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
1322 goto out;
1323
1324 if (unlikely(atomic_read(&jme->link_changing) != 1))
1325 goto out;
1326
1327 if (unlikely(!netif_carrier_ok(jme->dev)))
1328 goto out;
1329
1330 max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1331 mask = jme->tx_ring_mask;
1332
1333 for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
1334
1335 ctxbi = txbi + i;
1336
1337 if (likely(ctxbi->skb &&
1338 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
1339
1340 tx_dbg(jme, "txclean: %d+%d@%lu\n",
1341 i, ctxbi->nr_desc, jiffies);
1342
1343 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
1344
1345 for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
1346 ttxbi = txbi + ((i + j) & (mask));
1347 txdesc[(i + j) & (mask)].dw[0] = 0;
1348
1349 pci_unmap_page(jme->pdev,
1350 ttxbi->mapping,
1351 ttxbi->len,
1352 PCI_DMA_TODEVICE);
1353
1354 ttxbi->mapping = 0;
1355 ttxbi->len = 0;
1356 }
1357
1358 dev_kfree_skb(ctxbi->skb);
1359
1360 cnt += ctxbi->nr_desc;
1361
1362 if (unlikely(err)) {
1363 ++(NET_STAT(jme).tx_carrier_errors);
1364 } else {
1365 ++(NET_STAT(jme).tx_packets);
1366 NET_STAT(jme).tx_bytes += ctxbi->len;
1367 }
1368
1369 ctxbi->skb = NULL;
1370 ctxbi->len = 0;
1371 ctxbi->start_xmit = 0;
1372
1373 } else {
1374 break;
1375 }
1376
1377 i = (i + ctxbi->nr_desc) & mask;
1378
1379 ctxbi->nr_desc = 0;
1380 }
1381
1382 tx_dbg(jme, "txclean: done %d@%lu.\n", i, jiffies);
1383 atomic_set(&txring->next_to_clean, i);
1384 atomic_add(cnt, &txring->nr_free);
1385
1386 jme_wake_queue_if_stopped(jme);
1387
1388 out:
1389 atomic_inc(&jme->tx_cleaning);
1390 }
1391
1392 static void
1393 jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
1394 {
1395 /*
1396 * Disable interrupt
1397 */
1398 jwrite32f(jme, JME_IENC, INTR_ENABLE);
1399
1400 if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
1401 /*
1402 * Link change event is critical
1403 * all other events are ignored
1404 */
1405 jwrite32(jme, JME_IEVE, intrstat);
1406 tasklet_schedule(&jme->linkch_task);
1407 goto out_reenable;
1408 }
1409
1410 if (intrstat & INTR_TMINTR) {
1411 jwrite32(jme, JME_IEVE, INTR_TMINTR);
1412 tasklet_schedule(&jme->pcc_task);
1413 }
1414
1415 if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
1416 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
1417 tasklet_schedule(&jme->txclean_task);
1418 }
1419
1420 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1421 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1422 INTR_PCCRX0 |
1423 INTR_RX0EMP)) |
1424 INTR_RX0);
1425 }
1426
1427 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1428 if (intrstat & INTR_RX0EMP)
1429 atomic_inc(&jme->rx_empty);
1430
1431 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1432 if (likely(JME_RX_SCHEDULE_PREP(jme))) {
1433 jme_polling_mode(jme);
1434 JME_RX_SCHEDULE(jme);
1435 }
1436 }
1437 } else {
1438 if (intrstat & INTR_RX0EMP) {
1439 atomic_inc(&jme->rx_empty);
1440 tasklet_hi_schedule(&jme->rxempty_task);
1441 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1442 tasklet_hi_schedule(&jme->rxclean_task);
1443 }
1444 }
1445
1446 out_reenable:
1447 /*
1448 * Re-enable interrupt
1449 */
1450 jwrite32f(jme, JME_IENS, INTR_ENABLE);
1451 }
1452
1453 static irqreturn_t
1454 jme_intr(int irq, void *dev_id)
1455 {
1456 struct net_device *netdev = dev_id;
1457 struct jme_adapter *jme = netdev_priv(netdev);
1458 u32 intrstat;
1459
1460 intrstat = jread32(jme, JME_IEVE);
1461
1462 /*
1463 * Check if it's really an interrupt for us
1464 */
1465 if (unlikely((intrstat & INTR_ENABLE) == 0))
1466 return IRQ_NONE;
1467
1468 /*
1469 * Check if the device still exist
1470 */
1471 if (unlikely(intrstat == ~((typeof(intrstat))0)))
1472 return IRQ_NONE;
1473
1474 jme_intr_msi(jme, intrstat);
1475
1476 return IRQ_HANDLED;
1477 }
1478
1479 static irqreturn_t
1480 jme_msi(int irq, void *dev_id)
1481 {
1482 struct net_device *netdev = dev_id;
1483 struct jme_adapter *jme = netdev_priv(netdev);
1484 u32 intrstat;
1485
1486 pci_dma_sync_single_for_cpu(jme->pdev,
1487 jme->shadow_dma,
1488 sizeof(u32) * SHADOW_REG_NR,
1489 PCI_DMA_FROMDEVICE);
1490 intrstat = jme->shadow_regs[SHADOW_IEVE];
1491 jme->shadow_regs[SHADOW_IEVE] = 0;
1492
1493 jme_intr_msi(jme, intrstat);
1494
1495 return IRQ_HANDLED;
1496 }
1497
1498 static void
1499 jme_reset_link(struct jme_adapter *jme)
1500 {
1501 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1502 }
1503
1504 static void
1505 jme_restart_an(struct jme_adapter *jme)
1506 {
1507 u32 bmcr;
1508
1509 spin_lock_bh(&jme->phy_lock);
1510 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1511 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1512 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1513 spin_unlock_bh(&jme->phy_lock);
1514 }
1515
1516 static int
1517 jme_request_irq(struct jme_adapter *jme)
1518 {
1519 int rc;
1520 struct net_device *netdev = jme->dev;
1521 irq_handler_t handler = jme_intr;
1522 int irq_flags = IRQF_SHARED;
1523
1524 if (!pci_enable_msi(jme->pdev)) {
1525 set_bit(JME_FLAG_MSI, &jme->flags);
1526 handler = jme_msi;
1527 irq_flags = 0;
1528 }
1529
1530 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1531 netdev);
1532 if (rc) {
1533 jeprintk(jme->pdev,
1534 "Unable to request %s interrupt (return: %d)\n",
1535 test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1536 rc);
1537
1538 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1539 pci_disable_msi(jme->pdev);
1540 clear_bit(JME_FLAG_MSI, &jme->flags);
1541 }
1542 } else {
1543 netdev->irq = jme->pdev->irq;
1544 }
1545
1546 return rc;
1547 }
1548
1549 static void
1550 jme_free_irq(struct jme_adapter *jme)
1551 {
1552 free_irq(jme->pdev->irq, jme->dev);
1553 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1554 pci_disable_msi(jme->pdev);
1555 clear_bit(JME_FLAG_MSI, &jme->flags);
1556 jme->dev->irq = jme->pdev->irq;
1557 }
1558 }
1559
1560 static int
1561 jme_open(struct net_device *netdev)
1562 {
1563 struct jme_adapter *jme = netdev_priv(netdev);
1564 int rc;
1565
1566 jme_clear_pm(jme);
1567 JME_NAPI_ENABLE(jme);
1568
1569 tasklet_enable(&jme->txclean_task);
1570 tasklet_hi_enable(&jme->rxclean_task);
1571 tasklet_hi_enable(&jme->rxempty_task);
1572
1573 rc = jme_request_irq(jme);
1574 if (rc)
1575 goto err_out;
1576
1577 jme_enable_shadow(jme);
1578 jme_start_irq(jme);
1579
1580 if (test_bit(JME_FLAG_SSET, &jme->flags))
1581 jme_set_settings(netdev, &jme->old_ecmd);
1582 else
1583 jme_reset_phy_processor(jme);
1584
1585 jme_reset_link(jme);
1586
1587 return 0;
1588
1589 err_out:
1590 netif_stop_queue(netdev);
1591 netif_carrier_off(netdev);
1592 return rc;
1593 }
1594
1595 #ifdef CONFIG_PM
1596 static void
1597 jme_set_100m_half(struct jme_adapter *jme)
1598 {
1599 u32 bmcr, tmp;
1600
1601 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1602 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1603 BMCR_SPEED1000 | BMCR_FULLDPLX);
1604 tmp |= BMCR_SPEED100;
1605
1606 if (bmcr != tmp)
1607 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1608
1609 if (jme->fpgaver)
1610 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1611 else
1612 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
1613 }
1614
1615 #define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1616 static void
1617 jme_wait_link(struct jme_adapter *jme)
1618 {
1619 u32 phylink, to = JME_WAIT_LINK_TIME;
1620
1621 mdelay(1000);
1622 phylink = jme_linkstat_from_phy(jme);
1623 while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
1624 mdelay(10);
1625 phylink = jme_linkstat_from_phy(jme);
1626 }
1627 }
1628 #endif
1629
1630 static inline void
1631 jme_phy_off(struct jme_adapter *jme)
1632 {
1633 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, BMCR_PDOWN);
1634 }
1635
1636 static int
1637 jme_close(struct net_device *netdev)
1638 {
1639 struct jme_adapter *jme = netdev_priv(netdev);
1640
1641 netif_stop_queue(netdev);
1642 netif_carrier_off(netdev);
1643
1644 jme_stop_irq(jme);
1645 jme_disable_shadow(jme);
1646 jme_free_irq(jme);
1647
1648 JME_NAPI_DISABLE(jme);
1649
1650 tasklet_kill(&jme->linkch_task);
1651 tasklet_kill(&jme->txclean_task);
1652 tasklet_kill(&jme->rxclean_task);
1653 tasklet_kill(&jme->rxempty_task);
1654
1655 jme_reset_ghc_speed(jme);
1656 jme_disable_rx_engine(jme);
1657 jme_disable_tx_engine(jme);
1658 jme_reset_mac_processor(jme);
1659 jme_free_rx_resources(jme);
1660 jme_free_tx_resources(jme);
1661 jme->phylink = 0;
1662 jme_phy_off(jme);
1663
1664 return 0;
1665 }
1666
1667 static int
1668 jme_alloc_txdesc(struct jme_adapter *jme,
1669 struct sk_buff *skb)
1670 {
1671 struct jme_ring *txring = jme->txring;
1672 int idx, nr_alloc, mask = jme->tx_ring_mask;
1673
1674 idx = txring->next_to_use;
1675 nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1676
1677 if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
1678 return -1;
1679
1680 atomic_sub(nr_alloc, &txring->nr_free);
1681
1682 txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1683
1684 return idx;
1685 }
1686
1687 static void
1688 jme_fill_tx_map(struct pci_dev *pdev,
1689 struct txdesc *txdesc,
1690 struct jme_buffer_info *txbi,
1691 struct page *page,
1692 u32 page_offset,
1693 u32 len,
1694 u8 hidma)
1695 {
1696 dma_addr_t dmaaddr;
1697
1698 dmaaddr = pci_map_page(pdev,
1699 page,
1700 page_offset,
1701 len,
1702 PCI_DMA_TODEVICE);
1703
1704 pci_dma_sync_single_for_device(pdev,
1705 dmaaddr,
1706 len,
1707 PCI_DMA_TODEVICE);
1708
1709 txdesc->dw[0] = 0;
1710 txdesc->dw[1] = 0;
1711 txdesc->desc2.flags = TXFLAG_OWN;
1712 txdesc->desc2.flags |= (hidma) ? TXFLAG_64BIT : 0;
1713 txdesc->desc2.datalen = cpu_to_le16(len);
1714 txdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
1715 txdesc->desc2.bufaddrl = cpu_to_le32(
1716 (__u64)dmaaddr & 0xFFFFFFFFUL);
1717
1718 txbi->mapping = dmaaddr;
1719 txbi->len = len;
1720 }
1721
1722 static void
1723 jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1724 {
1725 struct jme_ring *txring = jme->txring;
1726 struct txdesc *txdesc = txring->desc, *ctxdesc;
1727 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
1728 u8 hidma = jme->dev->features & NETIF_F_HIGHDMA;
1729 int i, nr_frags = skb_shinfo(skb)->nr_frags;
1730 int mask = jme->tx_ring_mask;
1731 struct skb_frag_struct *frag;
1732 u32 len;
1733
1734 for (i = 0 ; i < nr_frags ; ++i) {
1735 frag = &skb_shinfo(skb)->frags[i];
1736 ctxdesc = txdesc + ((idx + i + 2) & (mask));
1737 ctxbi = txbi + ((idx + i + 2) & (mask));
1738
1739 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, frag->page,
1740 frag->page_offset, frag->size, hidma);
1741 }
1742
1743 len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
1744 ctxdesc = txdesc + ((idx + 1) & (mask));
1745 ctxbi = txbi + ((idx + 1) & (mask));
1746 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
1747 offset_in_page(skb->data), len, hidma);
1748
1749 }
1750
1751 static int
1752 jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb)
1753 {
1754 if (unlikely(skb_shinfo(skb)->gso_size &&
1755 skb_header_cloned(skb) &&
1756 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))) {
1757 dev_kfree_skb(skb);
1758 return -1;
1759 }
1760
1761 return 0;
1762 }
1763
1764 static int
1765 jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags)
1766 {
1767 *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT);
1768 if (*mss) {
1769 *flags |= TXFLAG_LSEN;
1770
1771 if (skb->protocol == htons(ETH_P_IP)) {
1772 struct iphdr *iph = ip_hdr(skb);
1773
1774 iph->check = 0;
1775 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
1776 iph->daddr, 0,
1777 IPPROTO_TCP,
1778 0);
1779 } else {
1780 struct ipv6hdr *ip6h = ipv6_hdr(skb);
1781
1782 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
1783 &ip6h->daddr, 0,
1784 IPPROTO_TCP,
1785 0);
1786 }
1787
1788 return 0;
1789 }
1790
1791 return 1;
1792 }
1793
1794 static void
1795 jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
1796 {
1797 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1798 u8 ip_proto;
1799
1800 switch (skb->protocol) {
1801 case htons(ETH_P_IP):
1802 ip_proto = ip_hdr(skb)->protocol;
1803 break;
1804 case htons(ETH_P_IPV6):
1805 ip_proto = ipv6_hdr(skb)->nexthdr;
1806 break;
1807 default:
1808 ip_proto = 0;
1809 break;
1810 }
1811
1812 switch (ip_proto) {
1813 case IPPROTO_TCP:
1814 *flags |= TXFLAG_TCPCS;
1815 break;
1816 case IPPROTO_UDP:
1817 *flags |= TXFLAG_UDPCS;
1818 break;
1819 default:
1820 msg_tx_err(jme, "Error upper layer protocol.\n");
1821 break;
1822 }
1823 }
1824 }
1825
1826 static inline void
1827 jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags)
1828 {
1829 if (vlan_tx_tag_present(skb)) {
1830 *flags |= TXFLAG_TAGON;
1831 *vlan = cpu_to_le16(vlan_tx_tag_get(skb));
1832 }
1833 }
1834
1835 static int
1836 jme_fill_first_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1837 {
1838 struct jme_ring *txring = jme->txring;
1839 struct txdesc *txdesc;
1840 struct jme_buffer_info *txbi;
1841 u8 flags;
1842
1843 txdesc = (struct txdesc *)txring->desc + idx;
1844 txbi = txring->bufinf + idx;
1845
1846 txdesc->dw[0] = 0;
1847 txdesc->dw[1] = 0;
1848 txdesc->dw[2] = 0;
1849 txdesc->dw[3] = 0;
1850 txdesc->desc1.pktsize = cpu_to_le16(skb->len);
1851 /*
1852 * Set OWN bit at final.
1853 * When kernel transmit faster than NIC.
1854 * And NIC trying to send this descriptor before we tell
1855 * it to start sending this TX queue.
1856 * Other fields are already filled correctly.
1857 */
1858 wmb();
1859 flags = TXFLAG_OWN | TXFLAG_INT;
1860 /*
1861 * Set checksum flags while not tso
1862 */
1863 if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
1864 jme_tx_csum(jme, skb, &flags);
1865 jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
1866 txdesc->desc1.flags = flags;
1867 /*
1868 * Set tx buffer info after telling NIC to send
1869 * For better tx_clean timing
1870 */
1871 wmb();
1872 txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
1873 txbi->skb = skb;
1874 txbi->len = skb->len;
1875 txbi->start_xmit = jiffies;
1876 if (!txbi->start_xmit)
1877 txbi->start_xmit = (0UL-1);
1878
1879 return 0;
1880 }
1881
1882 static void
1883 jme_stop_queue_if_full(struct jme_adapter *jme)
1884 {
1885 struct jme_ring *txring = jme->txring;
1886 struct jme_buffer_info *txbi = txring->bufinf;
1887 int idx = atomic_read(&txring->next_to_clean);
1888
1889 txbi += idx;
1890
1891 smp_wmb();
1892 if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
1893 netif_stop_queue(jme->dev);
1894 msg_tx_queued(jme, "TX Queue Paused.\n");
1895 smp_wmb();
1896 if (atomic_read(&txring->nr_free)
1897 >= (jme->tx_wake_threshold)) {
1898 netif_wake_queue(jme->dev);
1899 msg_tx_queued(jme, "TX Queue Fast Waked.\n");
1900 }
1901 }
1902
1903 if (unlikely(txbi->start_xmit &&
1904 (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
1905 txbi->skb)) {
1906 netif_stop_queue(jme->dev);
1907 msg_tx_queued(jme, "TX Queue Stopped %d@%lu.\n", idx, jiffies);
1908 }
1909 }
1910
1911 /*
1912 * This function is already protected by netif_tx_lock()
1913 */
1914
1915 static int
1916 jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
1917 {
1918 struct jme_adapter *jme = netdev_priv(netdev);
1919 int idx;
1920
1921 if (unlikely(jme_expand_header(jme, skb))) {
1922 ++(NET_STAT(jme).tx_dropped);
1923 return NETDEV_TX_OK;
1924 }
1925
1926 idx = jme_alloc_txdesc(jme, skb);
1927
1928 if (unlikely(idx < 0)) {
1929 netif_stop_queue(netdev);
1930 msg_tx_err(jme, "BUG! Tx ring full when queue awake!\n");
1931
1932 return NETDEV_TX_BUSY;
1933 }
1934
1935 jme_map_tx_skb(jme, skb, idx);
1936 jme_fill_first_tx_desc(jme, skb, idx);
1937
1938 jwrite32(jme, JME_TXCS, jme->reg_txcs |
1939 TXCS_SELECT_QUEUE0 |
1940 TXCS_QUEUE0S |
1941 TXCS_ENABLE);
1942 netdev->trans_start = jiffies;
1943
1944 tx_dbg(jme, "xmit: %d+%d@%lu\n", idx,
1945 skb_shinfo(skb)->nr_frags + 2,
1946 jiffies);
1947 jme_stop_queue_if_full(jme);
1948
1949 return NETDEV_TX_OK;
1950 }
1951
1952 static int
1953 jme_set_macaddr(struct net_device *netdev, void *p)
1954 {
1955 struct jme_adapter *jme = netdev_priv(netdev);
1956 struct sockaddr *addr = p;
1957 u32 val;
1958
1959 if (netif_running(netdev))
1960 return -EBUSY;
1961
1962 spin_lock_bh(&jme->macaddr_lock);
1963 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1964
1965 val = (addr->sa_data[3] & 0xff) << 24 |
1966 (addr->sa_data[2] & 0xff) << 16 |
1967 (addr->sa_data[1] & 0xff) << 8 |
1968 (addr->sa_data[0] & 0xff);
1969 jwrite32(jme, JME_RXUMA_LO, val);
1970 val = (addr->sa_data[5] & 0xff) << 8 |
1971 (addr->sa_data[4] & 0xff);
1972 jwrite32(jme, JME_RXUMA_HI, val);
1973 spin_unlock_bh(&jme->macaddr_lock);
1974
1975 return 0;
1976 }
1977
1978 static void
1979 jme_set_multi(struct net_device *netdev)
1980 {
1981 struct jme_adapter *jme = netdev_priv(netdev);
1982 u32 mc_hash[2] = {};
1983 int i;
1984
1985 spin_lock_bh(&jme->rxmcs_lock);
1986
1987 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
1988
1989 if (netdev->flags & IFF_PROMISC) {
1990 jme->reg_rxmcs |= RXMCS_ALLFRAME;
1991 } else if (netdev->flags & IFF_ALLMULTI) {
1992 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
1993 } else if (netdev->flags & IFF_MULTICAST) {
1994 struct dev_mc_list *mclist;
1995 int bit_nr;
1996
1997 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
1998 for (i = 0, mclist = netdev->mc_list;
1999 mclist && i < netdev->mc_count;
2000 ++i, mclist = mclist->next) {
2001
2002 bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x3F;
2003 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
2004 }
2005
2006 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2007 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
2008 }
2009
2010 wmb();
2011 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2012
2013 spin_unlock_bh(&jme->rxmcs_lock);
2014 }
2015
2016 static int
2017 jme_change_mtu(struct net_device *netdev, int new_mtu)
2018 {
2019 struct jme_adapter *jme = netdev_priv(netdev);
2020
2021 if (new_mtu == jme->old_mtu)
2022 return 0;
2023
2024 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
2025 ((new_mtu) < IPV6_MIN_MTU))
2026 return -EINVAL;
2027
2028 if (new_mtu > 4000) {
2029 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2030 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
2031 jme_restart_rx_engine(jme);
2032 } else {
2033 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2034 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
2035 jme_restart_rx_engine(jme);
2036 }
2037
2038 if (new_mtu > 1900) {
2039 netdev->features &= ~(NETIF_F_HW_CSUM |
2040 NETIF_F_TSO |
2041 NETIF_F_TSO6);
2042 } else {
2043 if (test_bit(JME_FLAG_TXCSUM, &jme->flags))
2044 netdev->features |= NETIF_F_HW_CSUM;
2045 if (test_bit(JME_FLAG_TSO, &jme->flags))
2046 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2047 }
2048
2049 netdev->mtu = new_mtu;
2050 jme_reset_link(jme);
2051
2052 return 0;
2053 }
2054
2055 static void
2056 jme_tx_timeout(struct net_device *netdev)
2057 {
2058 struct jme_adapter *jme = netdev_priv(netdev);
2059
2060 jme->phylink = 0;
2061 jme_reset_phy_processor(jme);
2062 if (test_bit(JME_FLAG_SSET, &jme->flags))
2063 jme_set_settings(netdev, &jme->old_ecmd);
2064
2065 /*
2066 * Force to Reset the link again
2067 */
2068 jme_reset_link(jme);
2069 }
2070
2071 static void
2072 jme_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2073 {
2074 struct jme_adapter *jme = netdev_priv(netdev);
2075
2076 jme->vlgrp = grp;
2077 }
2078
2079 static void
2080 jme_get_drvinfo(struct net_device *netdev,
2081 struct ethtool_drvinfo *info)
2082 {
2083 struct jme_adapter *jme = netdev_priv(netdev);
2084
2085 strcpy(info->driver, DRV_NAME);
2086 strcpy(info->version, DRV_VERSION);
2087 strcpy(info->bus_info, pci_name(jme->pdev));
2088 }
2089
2090 static int
2091 jme_get_regs_len(struct net_device *netdev)
2092 {
2093 return JME_REG_LEN;
2094 }
2095
2096 static void
2097 mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
2098 {
2099 int i;
2100
2101 for (i = 0 ; i < len ; i += 4)
2102 p[i >> 2] = jread32(jme, reg + i);
2103 }
2104
2105 static void
2106 mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
2107 {
2108 int i;
2109 u16 *p16 = (u16 *)p;
2110
2111 for (i = 0 ; i < reg_nr ; ++i)
2112 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
2113 }
2114
2115 static void
2116 jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2117 {
2118 struct jme_adapter *jme = netdev_priv(netdev);
2119 u32 *p32 = (u32 *)p;
2120
2121 memset(p, 0xFF, JME_REG_LEN);
2122
2123 regs->version = 1;
2124 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2125
2126 p32 += 0x100 >> 2;
2127 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2128
2129 p32 += 0x100 >> 2;
2130 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2131
2132 p32 += 0x100 >> 2;
2133 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2134
2135 p32 += 0x100 >> 2;
2136 mdio_memcpy(jme, p32, JME_PHY_REG_NR);
2137 }
2138
2139 static int
2140 jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2141 {
2142 struct jme_adapter *jme = netdev_priv(netdev);
2143
2144 ecmd->tx_coalesce_usecs = PCC_TX_TO;
2145 ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2146
2147 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2148 ecmd->use_adaptive_rx_coalesce = false;
2149 ecmd->rx_coalesce_usecs = 0;
2150 ecmd->rx_max_coalesced_frames = 0;
2151 return 0;
2152 }
2153
2154 ecmd->use_adaptive_rx_coalesce = true;
2155
2156 switch (jme->dpi.cur) {
2157 case PCC_P1:
2158 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2159 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2160 break;
2161 case PCC_P2:
2162 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2163 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2164 break;
2165 case PCC_P3:
2166 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2167 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2168 break;
2169 default:
2170 break;
2171 }
2172
2173 return 0;
2174 }
2175
2176 static int
2177 jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2178 {
2179 struct jme_adapter *jme = netdev_priv(netdev);
2180 struct dynpcc_info *dpi = &(jme->dpi);
2181
2182 if (netif_running(netdev))
2183 return -EBUSY;
2184
2185 if (ecmd->use_adaptive_rx_coalesce
2186 && test_bit(JME_FLAG_POLL, &jme->flags)) {
2187 clear_bit(JME_FLAG_POLL, &jme->flags);
2188 jme->jme_rx = netif_rx;
2189 jme->jme_vlan_rx = vlan_hwaccel_rx;
2190 dpi->cur = PCC_P1;
2191 dpi->attempt = PCC_P1;
2192 dpi->cnt = 0;
2193 jme_set_rx_pcc(jme, PCC_P1);
2194 jme_interrupt_mode(jme);
2195 } else if (!(ecmd->use_adaptive_rx_coalesce)
2196 && !(test_bit(JME_FLAG_POLL, &jme->flags))) {
2197 set_bit(JME_FLAG_POLL, &jme->flags);
2198 jme->jme_rx = netif_receive_skb;
2199 jme->jme_vlan_rx = vlan_hwaccel_receive_skb;
2200 jme_interrupt_mode(jme);
2201 }
2202
2203 return 0;
2204 }
2205
2206 static void
2207 jme_get_pauseparam(struct net_device *netdev,
2208 struct ethtool_pauseparam *ecmd)
2209 {
2210 struct jme_adapter *jme = netdev_priv(netdev);
2211 u32 val;
2212
2213 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2214 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2215
2216 spin_lock_bh(&jme->phy_lock);
2217 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2218 spin_unlock_bh(&jme->phy_lock);
2219
2220 ecmd->autoneg =
2221 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
2222 }
2223
2224 static int
2225 jme_set_pauseparam(struct net_device *netdev,
2226 struct ethtool_pauseparam *ecmd)
2227 {
2228 struct jme_adapter *jme = netdev_priv(netdev);
2229 u32 val;
2230
2231 if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
2232 (ecmd->tx_pause != 0)) {
2233
2234 if (ecmd->tx_pause)
2235 jme->reg_txpfc |= TXPFC_PF_EN;
2236 else
2237 jme->reg_txpfc &= ~TXPFC_PF_EN;
2238
2239 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2240 }
2241
2242 spin_lock_bh(&jme->rxmcs_lock);
2243 if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
2244 (ecmd->rx_pause != 0)) {
2245
2246 if (ecmd->rx_pause)
2247 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2248 else
2249 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2250
2251 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2252 }
2253 spin_unlock_bh(&jme->rxmcs_lock);
2254
2255 spin_lock_bh(&jme->phy_lock);
2256 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2257 if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
2258 (ecmd->autoneg != 0)) {
2259
2260 if (ecmd->autoneg)
2261 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2262 else
2263 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2264
2265 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2266 MII_ADVERTISE, val);
2267 }
2268 spin_unlock_bh(&jme->phy_lock);
2269
2270 return 0;
2271 }
2272
2273 static void
2274 jme_get_wol(struct net_device *netdev,
2275 struct ethtool_wolinfo *wol)
2276 {
2277 struct jme_adapter *jme = netdev_priv(netdev);
2278
2279 wol->supported = WAKE_MAGIC | WAKE_PHY;
2280
2281 wol->wolopts = 0;
2282
2283 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2284 wol->wolopts |= WAKE_PHY;
2285
2286 if (jme->reg_pmcs & PMCS_MFEN)
2287 wol->wolopts |= WAKE_MAGIC;
2288
2289 }
2290
2291 static int
2292 jme_set_wol(struct net_device *netdev,
2293 struct ethtool_wolinfo *wol)
2294 {
2295 struct jme_adapter *jme = netdev_priv(netdev);
2296
2297 if (wol->wolopts & (WAKE_MAGICSECURE |
2298 WAKE_UCAST |
2299 WAKE_MCAST |
2300 WAKE_BCAST |
2301 WAKE_ARP))
2302 return -EOPNOTSUPP;
2303
2304 jme->reg_pmcs = 0;
2305
2306 if (wol->wolopts & WAKE_PHY)
2307 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2308
2309 if (wol->wolopts & WAKE_MAGIC)
2310 jme->reg_pmcs |= PMCS_MFEN;
2311
2312 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
2313
2314 return 0;
2315 }
2316
2317 static int
2318 jme_get_settings(struct net_device *netdev,
2319 struct ethtool_cmd *ecmd)
2320 {
2321 struct jme_adapter *jme = netdev_priv(netdev);
2322 int rc;
2323
2324 spin_lock_bh(&jme->phy_lock);
2325 rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
2326 spin_unlock_bh(&jme->phy_lock);
2327 return rc;
2328 }
2329
2330 static int
2331 jme_set_settings(struct net_device *netdev,
2332 struct ethtool_cmd *ecmd)
2333 {
2334 struct jme_adapter *jme = netdev_priv(netdev);
2335 int rc, fdc = 0;
2336
2337 if (ecmd->speed == SPEED_1000 && ecmd->autoneg != AUTONEG_ENABLE)
2338 return -EINVAL;
2339
2340 if (jme->mii_if.force_media &&
2341 ecmd->autoneg != AUTONEG_ENABLE &&
2342 (jme->mii_if.full_duplex != ecmd->duplex))
2343 fdc = 1;
2344
2345 spin_lock_bh(&jme->phy_lock);
2346 rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
2347 spin_unlock_bh(&jme->phy_lock);
2348
2349 if (!rc && fdc)
2350 jme_reset_link(jme);
2351
2352 if (!rc) {
2353 set_bit(JME_FLAG_SSET, &jme->flags);
2354 jme->old_ecmd = *ecmd;
2355 }
2356
2357 return rc;
2358 }
2359
2360 static u32
2361 jme_get_link(struct net_device *netdev)
2362 {
2363 struct jme_adapter *jme = netdev_priv(netdev);
2364 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2365 }
2366
2367 static u32
2368 jme_get_msglevel(struct net_device *netdev)
2369 {
2370 struct jme_adapter *jme = netdev_priv(netdev);
2371 return jme->msg_enable;
2372 }
2373
2374 static void
2375 jme_set_msglevel(struct net_device *netdev, u32 value)
2376 {
2377 struct jme_adapter *jme = netdev_priv(netdev);
2378 jme->msg_enable = value;
2379 }
2380
2381 static u32
2382 jme_get_rx_csum(struct net_device *netdev)
2383 {
2384 struct jme_adapter *jme = netdev_priv(netdev);
2385 return jme->reg_rxmcs & RXMCS_CHECKSUM;
2386 }
2387
2388 static int
2389 jme_set_rx_csum(struct net_device *netdev, u32 on)
2390 {
2391 struct jme_adapter *jme = netdev_priv(netdev);
2392
2393 spin_lock_bh(&jme->rxmcs_lock);
2394 if (on)
2395 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2396 else
2397 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2398 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2399 spin_unlock_bh(&jme->rxmcs_lock);
2400
2401 return 0;
2402 }
2403
2404 static int
2405 jme_set_tx_csum(struct net_device *netdev, u32 on)
2406 {
2407 struct jme_adapter *jme = netdev_priv(netdev);
2408
2409 if (on) {
2410 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2411 if (netdev->mtu <= 1900)
2412 netdev->features |= NETIF_F_HW_CSUM;
2413 } else {
2414 clear_bit(JME_FLAG_TXCSUM, &jme->flags);
2415 netdev->features &= ~NETIF_F_HW_CSUM;
2416 }
2417
2418 return 0;
2419 }
2420
2421 static int
2422 jme_set_tso(struct net_device *netdev, u32 on)
2423 {
2424 struct jme_adapter *jme = netdev_priv(netdev);
2425
2426 if (on) {
2427 set_bit(JME_FLAG_TSO, &jme->flags);
2428 if (netdev->mtu <= 1900)
2429 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2430 } else {
2431 clear_bit(JME_FLAG_TSO, &jme->flags);
2432 netdev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
2433 }
2434
2435 return 0;
2436 }
2437
2438 static int
2439 jme_nway_reset(struct net_device *netdev)
2440 {
2441 struct jme_adapter *jme = netdev_priv(netdev);
2442 jme_restart_an(jme);
2443 return 0;
2444 }
2445
2446 static u8
2447 jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2448 {
2449 u32 val;
2450 int to;
2451
2452 val = jread32(jme, JME_SMBCSR);
2453 to = JME_SMB_BUSY_TIMEOUT;
2454 while ((val & SMBCSR_BUSY) && --to) {
2455 msleep(1);
2456 val = jread32(jme, JME_SMBCSR);
2457 }
2458 if (!to) {
2459 msg_hw(jme, "SMB Bus Busy.\n");
2460 return 0xFF;
2461 }
2462
2463 jwrite32(jme, JME_SMBINTF,
2464 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2465 SMBINTF_HWRWN_READ |
2466 SMBINTF_HWCMD);
2467
2468 val = jread32(jme, JME_SMBINTF);
2469 to = JME_SMB_BUSY_TIMEOUT;
2470 while ((val & SMBINTF_HWCMD) && --to) {
2471 msleep(1);
2472 val = jread32(jme, JME_SMBINTF);
2473 }
2474 if (!to) {
2475 msg_hw(jme, "SMB Bus Busy.\n");
2476 return 0xFF;
2477 }
2478
2479 return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2480 }
2481
2482 static void
2483 jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
2484 {
2485 u32 val;
2486 int to;
2487
2488 val = jread32(jme, JME_SMBCSR);
2489 to = JME_SMB_BUSY_TIMEOUT;
2490 while ((val & SMBCSR_BUSY) && --to) {
2491 msleep(1);
2492 val = jread32(jme, JME_SMBCSR);
2493 }
2494 if (!to) {
2495 msg_hw(jme, "SMB Bus Busy.\n");
2496 return;
2497 }
2498
2499 jwrite32(jme, JME_SMBINTF,
2500 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2501 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2502 SMBINTF_HWRWN_WRITE |
2503 SMBINTF_HWCMD);
2504
2505 val = jread32(jme, JME_SMBINTF);
2506 to = JME_SMB_BUSY_TIMEOUT;
2507 while ((val & SMBINTF_HWCMD) && --to) {
2508 msleep(1);
2509 val = jread32(jme, JME_SMBINTF);
2510 }
2511 if (!to) {
2512 msg_hw(jme, "SMB Bus Busy.\n");
2513 return;
2514 }
2515
2516 mdelay(2);
2517 }
2518
2519 static int
2520 jme_get_eeprom_len(struct net_device *netdev)
2521 {
2522 struct jme_adapter *jme = netdev_priv(netdev);
2523 u32 val;
2524 val = jread32(jme, JME_SMBCSR);
2525 return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
2526 }
2527
2528 static int
2529 jme_get_eeprom(struct net_device *netdev,
2530 struct ethtool_eeprom *eeprom, u8 *data)
2531 {
2532 struct jme_adapter *jme = netdev_priv(netdev);
2533 int i, offset = eeprom->offset, len = eeprom->len;
2534
2535 /*
2536 * ethtool will check the boundary for us
2537 */
2538 eeprom->magic = JME_EEPROM_MAGIC;
2539 for (i = 0 ; i < len ; ++i)
2540 data[i] = jme_smb_read(jme, i + offset);
2541
2542 return 0;
2543 }
2544
2545 static int
2546 jme_set_eeprom(struct net_device *netdev,
2547 struct ethtool_eeprom *eeprom, u8 *data)
2548 {
2549 struct jme_adapter *jme = netdev_priv(netdev);
2550 int i, offset = eeprom->offset, len = eeprom->len;
2551
2552 if (eeprom->magic != JME_EEPROM_MAGIC)
2553 return -EINVAL;
2554
2555 /*
2556 * ethtool will check the boundary for us
2557 */
2558 for (i = 0 ; i < len ; ++i)
2559 jme_smb_write(jme, i + offset, data[i]);
2560
2561 return 0;
2562 }
2563
2564 static const struct ethtool_ops jme_ethtool_ops = {
2565 .get_drvinfo = jme_get_drvinfo,
2566 .get_regs_len = jme_get_regs_len,
2567 .get_regs = jme_get_regs,
2568 .get_coalesce = jme_get_coalesce,
2569 .set_coalesce = jme_set_coalesce,
2570 .get_pauseparam = jme_get_pauseparam,
2571 .set_pauseparam = jme_set_pauseparam,
2572 .get_wol = jme_get_wol,
2573 .set_wol = jme_set_wol,
2574 .get_settings = jme_get_settings,
2575 .set_settings = jme_set_settings,
2576 .get_link = jme_get_link,
2577 .get_msglevel = jme_get_msglevel,
2578 .set_msglevel = jme_set_msglevel,
2579 .get_rx_csum = jme_get_rx_csum,
2580 .set_rx_csum = jme_set_rx_csum,
2581 .set_tx_csum = jme_set_tx_csum,
2582 .set_tso = jme_set_tso,
2583 .set_sg = ethtool_op_set_sg,
2584 .nway_reset = jme_nway_reset,
2585 .get_eeprom_len = jme_get_eeprom_len,
2586 .get_eeprom = jme_get_eeprom,
2587 .set_eeprom = jme_set_eeprom,
2588 };
2589
2590 static int
2591 jme_pci_dma64(struct pci_dev *pdev)
2592 {
2593 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK))
2594 if (!pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))
2595 return 1;
2596
2597 if (!pci_set_dma_mask(pdev, DMA_40BIT_MASK))
2598 if (!pci_set_consistent_dma_mask(pdev, DMA_40BIT_MASK))
2599 return 1;
2600
2601 if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK))
2602 if (!pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK))
2603 return 0;
2604
2605 return -1;
2606 }
2607
2608 static inline void
2609 jme_phy_init(struct jme_adapter *jme)
2610 {
2611 u16 reg26;
2612
2613 reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
2614 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
2615 }
2616
2617 static inline void
2618 jme_check_hw_ver(struct jme_adapter *jme)
2619 {
2620 u32 chipmode;
2621
2622 chipmode = jread32(jme, JME_CHIPMODE);
2623
2624 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
2625 jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
2626 }
2627
2628 static int __devinit
2629 jme_init_one(struct pci_dev *pdev,
2630 const struct pci_device_id *ent)
2631 {
2632 int rc = 0, using_dac, i;
2633 struct net_device *netdev;
2634 struct jme_adapter *jme;
2635 u16 bmcr, bmsr;
2636 u32 apmc;
2637
2638 /*
2639 * set up PCI device basics
2640 */
2641 rc = pci_enable_device(pdev);
2642 if (rc) {
2643 jeprintk(pdev, "Cannot enable PCI device.\n");
2644 goto err_out;
2645 }
2646
2647 using_dac = jme_pci_dma64(pdev);
2648 if (using_dac < 0) {
2649 jeprintk(pdev, "Cannot set PCI DMA Mask.\n");
2650 rc = -EIO;
2651 goto err_out_disable_pdev;
2652 }
2653
2654 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2655 jeprintk(pdev, "No PCI resource region found.\n");
2656 rc = -ENOMEM;
2657 goto err_out_disable_pdev;
2658 }
2659
2660 rc = pci_request_regions(pdev, DRV_NAME);
2661 if (rc) {
2662 jeprintk(pdev, "Cannot obtain PCI resource region.\n");
2663 goto err_out_disable_pdev;
2664 }
2665
2666 pci_set_master(pdev);
2667
2668 /*
2669 * alloc and init net device
2670 */
2671 netdev = alloc_etherdev(sizeof(*jme));
2672 if (!netdev) {
2673 jeprintk(pdev, "Cannot allocate netdev structure.\n");
2674 rc = -ENOMEM;
2675 goto err_out_release_regions;
2676 }
2677 netdev->open = jme_open;
2678 netdev->stop = jme_close;
2679 netdev->hard_start_xmit = jme_start_xmit;
2680 netdev->set_mac_address = jme_set_macaddr;
2681 netdev->set_multicast_list = jme_set_multi;
2682 netdev->change_mtu = jme_change_mtu;
2683 netdev->ethtool_ops = &jme_ethtool_ops;
2684 netdev->tx_timeout = jme_tx_timeout;
2685 netdev->watchdog_timeo = TX_TIMEOUT;
2686 netdev->vlan_rx_register = jme_vlan_rx_register;
2687 NETDEV_GET_STATS(netdev, &jme_get_stats);
2688 netdev->features = NETIF_F_HW_CSUM |
2689 NETIF_F_SG |
2690 NETIF_F_TSO |
2691 NETIF_F_TSO6 |
2692 NETIF_F_HW_VLAN_TX |
2693 NETIF_F_HW_VLAN_RX;
2694 if (using_dac)
2695 netdev->features |= NETIF_F_HIGHDMA;
2696
2697 SET_NETDEV_DEV(netdev, &pdev->dev);
2698 pci_set_drvdata(pdev, netdev);
2699
2700 /*
2701 * init adapter info
2702 */
2703 jme = netdev_priv(netdev);
2704 jme->pdev = pdev;
2705 jme->dev = netdev;
2706 jme->jme_rx = netif_rx;
2707 jme->jme_vlan_rx = vlan_hwaccel_rx;
2708 jme->old_mtu = netdev->mtu = 1500;
2709 jme->phylink = 0;
2710 jme->tx_ring_size = 1 << 10;
2711 jme->tx_ring_mask = jme->tx_ring_size - 1;
2712 jme->tx_wake_threshold = 1 << 9;
2713 jme->rx_ring_size = 1 << 9;
2714 jme->rx_ring_mask = jme->rx_ring_size - 1;
2715 jme->msg_enable = JME_DEF_MSG_ENABLE;
2716 jme->regs = ioremap(pci_resource_start(pdev, 0),
2717 pci_resource_len(pdev, 0));
2718 if (!(jme->regs)) {
2719 jeprintk(pdev, "Mapping PCI resource region error.\n");
2720 rc = -ENOMEM;
2721 goto err_out_free_netdev;
2722 }
2723 jme->shadow_regs = pci_alloc_consistent(pdev,
2724 sizeof(u32) * SHADOW_REG_NR,
2725 &(jme->shadow_dma));
2726 if (!(jme->shadow_regs)) {
2727 jeprintk(pdev, "Allocating shadow register mapping error.\n");
2728 rc = -ENOMEM;
2729 goto err_out_unmap;
2730 }
2731
2732 if (no_pseudohp) {
2733 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
2734 jwrite32(jme, JME_APMC, apmc);
2735 } else if (force_pseudohp) {
2736 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
2737 jwrite32(jme, JME_APMC, apmc);
2738 }
2739
2740 NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, jme->rx_ring_size >> 2)
2741
2742 spin_lock_init(&jme->phy_lock);
2743 spin_lock_init(&jme->macaddr_lock);
2744 spin_lock_init(&jme->rxmcs_lock);
2745
2746 atomic_set(&jme->link_changing, 1);
2747 atomic_set(&jme->rx_cleaning, 1);
2748 atomic_set(&jme->tx_cleaning, 1);
2749 atomic_set(&jme->rx_empty, 1);
2750
2751 tasklet_init(&jme->pcc_task,
2752 &jme_pcc_tasklet,
2753 (unsigned long) jme);
2754 tasklet_init(&jme->linkch_task,
2755 &jme_link_change_tasklet,
2756 (unsigned long) jme);
2757 tasklet_init(&jme->txclean_task,
2758 &jme_tx_clean_tasklet,
2759 (unsigned long) jme);
2760 tasklet_init(&jme->rxclean_task,
2761 &jme_rx_clean_tasklet,
2762 (unsigned long) jme);
2763 tasklet_init(&jme->rxempty_task,
2764 &jme_rx_empty_tasklet,
2765 (unsigned long) jme);
2766 tasklet_disable_nosync(&jme->txclean_task);
2767 tasklet_disable_nosync(&jme->rxclean_task);
2768 tasklet_disable_nosync(&jme->rxempty_task);
2769 jme->dpi.cur = PCC_P1;
2770
2771 jme->reg_ghc = 0;
2772 jme->reg_rxcs = RXCS_DEFAULT;
2773 jme->reg_rxmcs = RXMCS_DEFAULT;
2774 jme->reg_txpfc = 0;
2775 jme->reg_pmcs = PMCS_MFEN;
2776 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2777 set_bit(JME_FLAG_TSO, &jme->flags);
2778
2779 /*
2780 * Get Max Read Req Size from PCI Config Space
2781 */
2782 pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
2783 jme->mrrs &= PCI_DCSR_MRRS_MASK;
2784 switch (jme->mrrs) {
2785 case MRRS_128B:
2786 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
2787 break;
2788 case MRRS_256B:
2789 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
2790 break;
2791 default:
2792 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
2793 break;
2794 };
2795
2796 /*
2797 * Must check before reset_mac_processor
2798 */
2799 jme_check_hw_ver(jme);
2800 jme->mii_if.dev = netdev;
2801 if (jme->fpgaver) {
2802 jme->mii_if.phy_id = 0;
2803 for (i = 1 ; i < 32 ; ++i) {
2804 bmcr = jme_mdio_read(netdev, i, MII_BMCR);
2805 bmsr = jme_mdio_read(netdev, i, MII_BMSR);
2806 if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
2807 jme->mii_if.phy_id = i;
2808 break;
2809 }
2810 }
2811
2812 if (!jme->mii_if.phy_id) {
2813 rc = -EIO;
2814 jeprintk(pdev, "Can not find phy_id.\n");
2815 goto err_out_free_shadow;
2816 }
2817
2818 jme->reg_ghc |= GHC_LINK_POLL;
2819 } else {
2820 jme->mii_if.phy_id = 1;
2821 }
2822 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
2823 jme->mii_if.supports_gmii = true;
2824 else
2825 jme->mii_if.supports_gmii = false;
2826 jme->mii_if.mdio_read = jme_mdio_read;
2827 jme->mii_if.mdio_write = jme_mdio_write;
2828
2829 jme_clear_pm(jme);
2830 jme_set_phyfifoa(jme);
2831 pci_read_config_byte(pdev, PCI_REVISION_ID, &jme->rev);
2832 if (!jme->fpgaver)
2833 jme_phy_init(jme);
2834 jme_phy_off(jme);
2835
2836 /*
2837 * Reset MAC processor and reload EEPROM for MAC Address
2838 */
2839 jme_reset_mac_processor(jme);
2840 rc = jme_reload_eeprom(jme);
2841 if (rc) {
2842 jeprintk(pdev,
2843 "Reload eeprom for reading MAC Address error.\n");
2844 goto err_out_free_shadow;
2845 }
2846 jme_load_macaddr(netdev);
2847
2848 /*
2849 * Tell stack that we are not ready to work until open()
2850 */
2851 netif_carrier_off(netdev);
2852 netif_stop_queue(netdev);
2853
2854 /*
2855 * Register netdev
2856 */
2857 rc = register_netdev(netdev);
2858 if (rc) {
2859 jeprintk(pdev, "Cannot register net device.\n");
2860 goto err_out_free_shadow;
2861 }
2862
2863 msg_probe(jme, "JMC250 gigabit%s ver:%x rev:%x macaddr:%pM\n",
2864 (jme->fpgaver != 0) ? " (FPGA)" : "",
2865 (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
2866 jme->rev, netdev->dev_addr);
2867
2868 return 0;
2869
2870 err_out_free_shadow:
2871 pci_free_consistent(pdev,
2872 sizeof(u32) * SHADOW_REG_NR,
2873 jme->shadow_regs,
2874 jme->shadow_dma);
2875 err_out_unmap:
2876 iounmap(jme->regs);
2877 err_out_free_netdev:
2878 pci_set_drvdata(pdev, NULL);
2879 free_netdev(netdev);
2880 err_out_release_regions:
2881 pci_release_regions(pdev);
2882 err_out_disable_pdev:
2883 pci_disable_device(pdev);
2884 err_out:
2885 return rc;
2886 }
2887
2888 static void __devexit
2889 jme_remove_one(struct pci_dev *pdev)
2890 {
2891 struct net_device *netdev = pci_get_drvdata(pdev);
2892 struct jme_adapter *jme = netdev_priv(netdev);
2893
2894 unregister_netdev(netdev);
2895 pci_free_consistent(pdev,
2896 sizeof(u32) * SHADOW_REG_NR,
2897 jme->shadow_regs,
2898 jme->shadow_dma);
2899 iounmap(jme->regs);
2900 pci_set_drvdata(pdev, NULL);
2901 free_netdev(netdev);
2902 pci_release_regions(pdev);
2903 pci_disable_device(pdev);
2904
2905 }
2906
2907 #ifdef CONFIG_PM
2908 static int
2909 jme_suspend(struct pci_dev *pdev, pm_message_t state)
2910 {
2911 struct net_device *netdev = pci_get_drvdata(pdev);
2912 struct jme_adapter *jme = netdev_priv(netdev);
2913
2914 atomic_dec(&jme->link_changing);
2915
2916 netif_device_detach(netdev);
2917 netif_stop_queue(netdev);
2918 jme_stop_irq(jme);
2919
2920 tasklet_disable(&jme->txclean_task);
2921 tasklet_disable(&jme->rxclean_task);
2922 tasklet_disable(&jme->rxempty_task);
2923
2924 jme_disable_shadow(jme);
2925
2926 if (netif_carrier_ok(netdev)) {
2927 if (test_bit(JME_FLAG_POLL, &jme->flags))
2928 jme_polling_mode(jme);
2929
2930 jme_stop_pcc_timer(jme);
2931 jme_reset_ghc_speed(jme);
2932 jme_disable_rx_engine(jme);
2933 jme_disable_tx_engine(jme);
2934 jme_reset_mac_processor(jme);
2935 jme_free_rx_resources(jme);
2936 jme_free_tx_resources(jme);
2937 netif_carrier_off(netdev);
2938 jme->phylink = 0;
2939 }
2940
2941 tasklet_enable(&jme->txclean_task);
2942 tasklet_hi_enable(&jme->rxclean_task);
2943 tasklet_hi_enable(&jme->rxempty_task);
2944
2945 pci_save_state(pdev);
2946 if (jme->reg_pmcs) {
2947 jme_set_100m_half(jme);
2948
2949 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2950 jme_wait_link(jme);
2951
2952 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
2953
2954 pci_enable_wake(pdev, PCI_D3cold, true);
2955 } else {
2956 jme_phy_off(jme);
2957 }
2958 pci_set_power_state(pdev, PCI_D3cold);
2959
2960 return 0;
2961 }
2962
2963 static int
2964 jme_resume(struct pci_dev *pdev)
2965 {
2966 struct net_device *netdev = pci_get_drvdata(pdev);
2967 struct jme_adapter *jme = netdev_priv(netdev);
2968
2969 jme_clear_pm(jme);
2970 pci_restore_state(pdev);
2971
2972 if (test_bit(JME_FLAG_SSET, &jme->flags))
2973 jme_set_settings(netdev, &jme->old_ecmd);
2974 else
2975 jme_reset_phy_processor(jme);
2976
2977 jme_enable_shadow(jme);
2978 jme_start_irq(jme);
2979 netif_device_attach(netdev);
2980
2981 atomic_inc(&jme->link_changing);
2982
2983 jme_reset_link(jme);
2984
2985 return 0;
2986 }
2987 #endif
2988
2989 static struct pci_device_id jme_pci_tbl[] = {
2990 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
2991 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
2992 { }
2993 };
2994
2995 static struct pci_driver jme_driver = {
2996 .name = DRV_NAME,
2997 .id_table = jme_pci_tbl,
2998 .probe = jme_init_one,
2999 .remove = __devexit_p(jme_remove_one),
3000 #ifdef CONFIG_PM
3001 .suspend = jme_suspend,
3002 .resume = jme_resume,
3003 #endif /* CONFIG_PM */
3004 };
3005
3006 static int __init
3007 jme_init_module(void)
3008 {
3009 printk(KERN_INFO PFX "JMicron JMC250 gigabit ethernet "
3010 "driver version %s\n", DRV_VERSION);
3011 return pci_register_driver(&jme_driver);
3012 }
3013
3014 static void __exit
3015 jme_cleanup_module(void)
3016 {
3017 pci_unregister_driver(&jme_driver);
3018 }
3019
3020 module_init(jme_init_module);
3021 module_exit(jme_cleanup_module);
3022
3023 MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
3024 MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3025 MODULE_LICENSE("GPL");
3026 MODULE_VERSION(DRV_VERSION);
3027 MODULE_DEVICE_TABLE(pci, jme_pci_tbl);
3028
Verdex Pro support