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iwlwifi: move spectrum measurement code to iwl-spectrum.c file
[linux-2.6/verdex.git] / drivers / net / dl2k.c
blob9ec9785a9fc3424ebf72ced7e5a94c02ff87a77c
1 /* D-Link DL2000-based Gigabit Ethernet Adapter Linux driver */
2 /*
3 Copyright (c) 2001, 2002 by D-Link Corporation
4 Written by Edward Peng.<edward_peng@dlink.com.tw>
5 Created 03-May-2001, base on Linux' sundance.c.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11 */
12
13 #define DRV_NAME "DL2000/TC902x-based linux driver"
14 #define DRV_VERSION "v1.19"
15 #define DRV_RELDATE "2007/08/12"
16 #include "dl2k.h"
17 #include <linux/dma-mapping.h>
18
19 static char version[] __devinitdata =
20 KERN_INFO DRV_NAME " " DRV_VERSION " " DRV_RELDATE "\n";
21 #define MAX_UNITS 8
22 static int mtu[MAX_UNITS];
23 static int vlan[MAX_UNITS];
24 static int jumbo[MAX_UNITS];
25 static char *media[MAX_UNITS];
26 static int tx_flow=-1;
27 static int rx_flow=-1;
28 static int copy_thresh;
29 static int rx_coalesce=10; /* Rx frame count each interrupt */
30 static int rx_timeout=200; /* Rx DMA wait time in 640ns increments */
31 static int tx_coalesce=16; /* HW xmit count each TxDMAComplete */
32
33
34 MODULE_AUTHOR ("Edward Peng");
35 MODULE_DESCRIPTION ("D-Link DL2000-based Gigabit Ethernet Adapter");
36 MODULE_LICENSE("GPL");
37 module_param_array(mtu, int, NULL, 0);
38 module_param_array(media, charp, NULL, 0);
39 module_param_array(vlan, int, NULL, 0);
40 module_param_array(jumbo, int, NULL, 0);
41 module_param(tx_flow, int, 0);
42 module_param(rx_flow, int, 0);
43 module_param(copy_thresh, int, 0);
44 module_param(rx_coalesce, int, 0); /* Rx frame count each interrupt */
45 module_param(rx_timeout, int, 0); /* Rx DMA wait time in 64ns increments */
46 module_param(tx_coalesce, int, 0); /* HW xmit count each TxDMAComplete */
47
48
49 /* Enable the default interrupts */
50 #define DEFAULT_INTR (RxDMAComplete | HostError | IntRequested | TxDMAComplete| \
51 UpdateStats | LinkEvent)
52 #define EnableInt() \
53 writew(DEFAULT_INTR, ioaddr + IntEnable)
54
55 static const int max_intrloop = 50;
56 static const int multicast_filter_limit = 0x40;
57
58 static int rio_open (struct net_device *dev);
59 static void rio_timer (unsigned long data);
60 static void rio_tx_timeout (struct net_device *dev);
61 static void alloc_list (struct net_device *dev);
62 static int start_xmit (struct sk_buff *skb, struct net_device *dev);
63 static irqreturn_t rio_interrupt (int irq, void *dev_instance);
64 static void rio_free_tx (struct net_device *dev, int irq);
65 static void tx_error (struct net_device *dev, int tx_status);
66 static int receive_packet (struct net_device *dev);
67 static void rio_error (struct net_device *dev, int int_status);
68 static int change_mtu (struct net_device *dev, int new_mtu);
69 static void set_multicast (struct net_device *dev);
70 static struct net_device_stats *get_stats (struct net_device *dev);
71 static int clear_stats (struct net_device *dev);
72 static int rio_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
73 static int rio_close (struct net_device *dev);
74 static int find_miiphy (struct net_device *dev);
75 static int parse_eeprom (struct net_device *dev);
76 static int read_eeprom (long ioaddr, int eep_addr);
77 static int mii_wait_link (struct net_device *dev, int wait);
78 static int mii_set_media (struct net_device *dev);
79 static int mii_get_media (struct net_device *dev);
80 static int mii_set_media_pcs (struct net_device *dev);
81 static int mii_get_media_pcs (struct net_device *dev);
82 static int mii_read (struct net_device *dev, int phy_addr, int reg_num);
83 static int mii_write (struct net_device *dev, int phy_addr, int reg_num,
84 u16 data);
85
86 static const struct ethtool_ops ethtool_ops;
87
88 static int __devinit
89 rio_probe1 (struct pci_dev *pdev, const struct pci_device_id *ent)
90 {
91 struct net_device *dev;
92 struct netdev_private *np;
93 static int card_idx;
94 int chip_idx = ent->driver_data;
95 int err, irq;
96 long ioaddr;
97 static int version_printed;
98 void *ring_space;
99 dma_addr_t ring_dma;
100
101 if (!version_printed++)
102 printk ("%s", version);
103
104 err = pci_enable_device (pdev);
105 if (err)
106 return err;
107
108 irq = pdev->irq;
109 err = pci_request_regions (pdev, "dl2k");
110 if (err)
111 goto err_out_disable;
112
113 pci_set_master (pdev);
114 dev = alloc_etherdev (sizeof (*np));
115 if (!dev) {
116 err = -ENOMEM;
117 goto err_out_res;
118 }
119 SET_NETDEV_DEV(dev, &pdev->dev);
120
121 #ifdef MEM_MAPPING
122 ioaddr = pci_resource_start (pdev, 1);
123 ioaddr = (long) ioremap (ioaddr, RIO_IO_SIZE);
124 if (!ioaddr) {
125 err = -ENOMEM;
126 goto err_out_dev;
127 }
128 #else
129 ioaddr = pci_resource_start (pdev, 0);
130 #endif
131 dev->base_addr = ioaddr;
132 dev->irq = irq;
133 np = netdev_priv(dev);
134 np->chip_id = chip_idx;
135 np->pdev = pdev;
136 spin_lock_init (&np->tx_lock);
137 spin_lock_init (&np->rx_lock);
138
139 /* Parse manual configuration */
140 np->an_enable = 1;
141 np->tx_coalesce = 1;
142 if (card_idx < MAX_UNITS) {
143 if (media[card_idx] != NULL) {
144 np->an_enable = 0;
145 if (strcmp (media[card_idx], "auto") == 0 ||
146 strcmp (media[card_idx], "autosense") == 0 ||
147 strcmp (media[card_idx], "0") == 0 ) {
148 np->an_enable = 2;
149 } else if (strcmp (media[card_idx], "100mbps_fd") == 0 ||
150 strcmp (media[card_idx], "4") == 0) {
151 np->speed = 100;
152 np->full_duplex = 1;
153 } else if (strcmp (media[card_idx], "100mbps_hd") == 0
154 || strcmp (media[card_idx], "3") == 0) {
155 np->speed = 100;
156 np->full_duplex = 0;
157 } else if (strcmp (media[card_idx], "10mbps_fd") == 0 ||
158 strcmp (media[card_idx], "2") == 0) {
159 np->speed = 10;
160 np->full_duplex = 1;
161 } else if (strcmp (media[card_idx], "10mbps_hd") == 0 ||
162 strcmp (media[card_idx], "1") == 0) {
163 np->speed = 10;
164 np->full_duplex = 0;
165 } else if (strcmp (media[card_idx], "1000mbps_fd") == 0 ||
166 strcmp (media[card_idx], "6") == 0) {
167 np->speed=1000;
168 np->full_duplex=1;
169 } else if (strcmp (media[card_idx], "1000mbps_hd") == 0 ||
170 strcmp (media[card_idx], "5") == 0) {
171 np->speed = 1000;
172 np->full_duplex = 0;
173 } else {
174 np->an_enable = 1;
175 }
176 }
177 if (jumbo[card_idx] != 0) {
178 np->jumbo = 1;
179 dev->mtu = MAX_JUMBO;
180 } else {
181 np->jumbo = 0;
182 if (mtu[card_idx] > 0 && mtu[card_idx] < PACKET_SIZE)
183 dev->mtu = mtu[card_idx];
184 }
185 np->vlan = (vlan[card_idx] > 0 && vlan[card_idx] < 4096) ?
186 vlan[card_idx] : 0;
187 if (rx_coalesce > 0 && rx_timeout > 0) {
188 np->rx_coalesce = rx_coalesce;
189 np->rx_timeout = rx_timeout;
190 np->coalesce = 1;
191 }
192 np->tx_flow = (tx_flow == 0) ? 0 : 1;
193 np->rx_flow = (rx_flow == 0) ? 0 : 1;
194
195 if (tx_coalesce < 1)
196 tx_coalesce = 1;
197 else if (tx_coalesce > TX_RING_SIZE-1)
198 tx_coalesce = TX_RING_SIZE - 1;
199 }
200 dev->open = &rio_open;
201 dev->hard_start_xmit = &start_xmit;
202 dev->stop = &rio_close;
203 dev->get_stats = &get_stats;
204 dev->set_multicast_list = &set_multicast;
205 dev->do_ioctl = &rio_ioctl;
206 dev->tx_timeout = &rio_tx_timeout;
207 dev->watchdog_timeo = TX_TIMEOUT;
208 dev->change_mtu = &change_mtu;
209 SET_ETHTOOL_OPS(dev, &ethtool_ops);
210 #if 0
211 dev->features = NETIF_F_IP_CSUM;
212 #endif
213 pci_set_drvdata (pdev, dev);
214
215 ring_space = pci_alloc_consistent (pdev, TX_TOTAL_SIZE, &ring_dma);
216 if (!ring_space)
217 goto err_out_iounmap;
218 np->tx_ring = (struct netdev_desc *) ring_space;
219 np->tx_ring_dma = ring_dma;
220
221 ring_space = pci_alloc_consistent (pdev, RX_TOTAL_SIZE, &ring_dma);
222 if (!ring_space)
223 goto err_out_unmap_tx;
224 np->rx_ring = (struct netdev_desc *) ring_space;
225 np->rx_ring_dma = ring_dma;
226
227 /* Parse eeprom data */
228 parse_eeprom (dev);
229
230 /* Find PHY address */
231 err = find_miiphy (dev);
232 if (err)
233 goto err_out_unmap_rx;
234
235 /* Fiber device? */
236 np->phy_media = (readw(ioaddr + ASICCtrl) & PhyMedia) ? 1 : 0;
237 np->link_status = 0;
238 /* Set media and reset PHY */
239 if (np->phy_media) {
240 /* default Auto-Negotiation for fiber deivices */
241 if (np->an_enable == 2) {
242 np->an_enable = 1;
243 }
244 mii_set_media_pcs (dev);
245 } else {
246 /* Auto-Negotiation is mandatory for 1000BASE-T,
247 IEEE 802.3ab Annex 28D page 14 */
248 if (np->speed == 1000)
249 np->an_enable = 1;
250 mii_set_media (dev);
251 }
252
253 err = register_netdev (dev);
254 if (err)
255 goto err_out_unmap_rx;
256
257 card_idx++;
258
259 printk (KERN_INFO "%s: %s, %pM, IRQ %d\n",
260 dev->name, np->name, dev->dev_addr, irq);
261 if (tx_coalesce > 1)
262 printk(KERN_INFO "tx_coalesce:\t%d packets\n",
263 tx_coalesce);
264 if (np->coalesce)
265 printk(KERN_INFO "rx_coalesce:\t%d packets\n"
266 KERN_INFO "rx_timeout: \t%d ns\n",
267 np->rx_coalesce, np->rx_timeout*640);
268 if (np->vlan)
269 printk(KERN_INFO "vlan(id):\t%d\n", np->vlan);
270 return 0;
271
272 err_out_unmap_rx:
273 pci_free_consistent (pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma);
274 err_out_unmap_tx:
275 pci_free_consistent (pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma);
276 err_out_iounmap:
277 #ifdef MEM_MAPPING
278 iounmap ((void *) ioaddr);
279
280 err_out_dev:
281 #endif
282 free_netdev (dev);
283
284 err_out_res:
285 pci_release_regions (pdev);
286
287 err_out_disable:
288 pci_disable_device (pdev);
289 return err;
290 }
291
292 static int
293 find_miiphy (struct net_device *dev)
294 {
295 int i, phy_found = 0;
296 struct netdev_private *np;
297 long ioaddr;
298 np = netdev_priv(dev);
299 ioaddr = dev->base_addr;
300 np->phy_addr = 1;
301
302 for (i = 31; i >= 0; i--) {
303 int mii_status = mii_read (dev, i, 1);
304 if (mii_status != 0xffff && mii_status != 0x0000) {
305 np->phy_addr = i;
306 phy_found++;
307 }
308 }
309 if (!phy_found) {
310 printk (KERN_ERR "%s: No MII PHY found!\n", dev->name);
311 return -ENODEV;
312 }
313 return 0;
314 }
315
316 static int
317 parse_eeprom (struct net_device *dev)
318 {
319 int i, j;
320 long ioaddr = dev->base_addr;
321 u8 sromdata[256];
322 u8 *psib;
323 u32 crc;
324 PSROM_t psrom = (PSROM_t) sromdata;
325 struct netdev_private *np = netdev_priv(dev);
326
327 int cid, next;
328
329 #ifdef MEM_MAPPING
330 ioaddr = pci_resource_start (np->pdev, 0);
331 #endif
332 /* Read eeprom */
333 for (i = 0; i < 128; i++) {
334 ((__le16 *) sromdata)[i] = cpu_to_le16(read_eeprom (ioaddr, i));
335 }
336 #ifdef MEM_MAPPING
337 ioaddr = dev->base_addr;
338 #endif
339 if (np->pdev->vendor == PCI_VENDOR_ID_DLINK) { /* D-Link Only */
340 /* Check CRC */
341 crc = ~ether_crc_le (256 - 4, sromdata);
342 if (psrom->crc != crc) {
343 printk (KERN_ERR "%s: EEPROM data CRC error.\n",
344 dev->name);
345 return -1;
346 }
347 }
348
349 /* Set MAC address */
350 for (i = 0; i < 6; i++)
351 dev->dev_addr[i] = psrom->mac_addr[i];
352
353 if (np->pdev->vendor != PCI_VENDOR_ID_DLINK) {
354 return 0;
355 }
356
357 /* Parse Software Information Block */
358 i = 0x30;
359 psib = (u8 *) sromdata;
360 do {
361 cid = psib[i++];
362 next = psib[i++];
363 if ((cid == 0 && next == 0) || (cid == 0xff && next == 0xff)) {
364 printk (KERN_ERR "Cell data error\n");
365 return -1;
366 }
367 switch (cid) {
368 case 0: /* Format version */
369 break;
370 case 1: /* End of cell */
371 return 0;
372 case 2: /* Duplex Polarity */
373 np->duplex_polarity = psib[i];
374 writeb (readb (ioaddr + PhyCtrl) | psib[i],
375 ioaddr + PhyCtrl);
376 break;
377 case 3: /* Wake Polarity */
378 np->wake_polarity = psib[i];
379 break;
380 case 9: /* Adapter description */
381 j = (next - i > 255) ? 255 : next - i;
382 memcpy (np->name, &(psib[i]), j);
383 break;
384 case 4:
385 case 5:
386 case 6:
387 case 7:
388 case 8: /* Reversed */
389 break;
390 default: /* Unknown cell */
391 return -1;
392 }
393 i = next;
394 } while (1);
395
396 return 0;
397 }
398
399 static int
400 rio_open (struct net_device *dev)
401 {
402 struct netdev_private *np = netdev_priv(dev);
403 long ioaddr = dev->base_addr;
404 int i;
405 u16 macctrl;
406
407 i = request_irq (dev->irq, &rio_interrupt, IRQF_SHARED, dev->name, dev);
408 if (i)
409 return i;
410
411 /* Reset all logic functions */
412 writew (GlobalReset | DMAReset | FIFOReset | NetworkReset | HostReset,
413 ioaddr + ASICCtrl + 2);
414 mdelay(10);
415
416 /* DebugCtrl bit 4, 5, 9 must set */
417 writel (readl (ioaddr + DebugCtrl) | 0x0230, ioaddr + DebugCtrl);
418
419 /* Jumbo frame */
420 if (np->jumbo != 0)
421 writew (MAX_JUMBO+14, ioaddr + MaxFrameSize);
422
423 alloc_list (dev);
424
425 /* Get station address */
426 for (i = 0; i < 6; i++)
427 writeb (dev->dev_addr[i], ioaddr + StationAddr0 + i);
428
429 set_multicast (dev);
430 if (np->coalesce) {
431 writel (np->rx_coalesce | np->rx_timeout << 16,
432 ioaddr + RxDMAIntCtrl);
433 }
434 /* Set RIO to poll every N*320nsec. */
435 writeb (0x20, ioaddr + RxDMAPollPeriod);
436 writeb (0xff, ioaddr + TxDMAPollPeriod);
437 writeb (0x30, ioaddr + RxDMABurstThresh);
438 writeb (0x30, ioaddr + RxDMAUrgentThresh);
439 writel (0x0007ffff, ioaddr + RmonStatMask);
440 /* clear statistics */
441 clear_stats (dev);
442
443 /* VLAN supported */
444 if (np->vlan) {
445 /* priority field in RxDMAIntCtrl */
446 writel (readl(ioaddr + RxDMAIntCtrl) | 0x7 << 10,
447 ioaddr + RxDMAIntCtrl);
448 /* VLANId */
449 writew (np->vlan, ioaddr + VLANId);
450 /* Length/Type should be 0x8100 */
451 writel (0x8100 << 16 | np->vlan, ioaddr + VLANTag);
452 /* Enable AutoVLANuntagging, but disable AutoVLANtagging.
453 VLAN information tagged by TFC' VID, CFI fields. */
454 writel (readl (ioaddr + MACCtrl) | AutoVLANuntagging,
455 ioaddr + MACCtrl);
456 }
457
458 init_timer (&np->timer);
459 np->timer.expires = jiffies + 1*HZ;
460 np->timer.data = (unsigned long) dev;
461 np->timer.function = &rio_timer;
462 add_timer (&np->timer);
463
464 /* Start Tx/Rx */
465 writel (readl (ioaddr + MACCtrl) | StatsEnable | RxEnable | TxEnable,
466 ioaddr + MACCtrl);
467
468 macctrl = 0;
469 macctrl |= (np->vlan) ? AutoVLANuntagging : 0;
470 macctrl |= (np->full_duplex) ? DuplexSelect : 0;
471 macctrl |= (np->tx_flow) ? TxFlowControlEnable : 0;
472 macctrl |= (np->rx_flow) ? RxFlowControlEnable : 0;
473 writew(macctrl, ioaddr + MACCtrl);
474
475 netif_start_queue (dev);
476
477 /* Enable default interrupts */
478 EnableInt ();
479 return 0;
480 }
481
482 static void
483 rio_timer (unsigned long data)
484 {
485 struct net_device *dev = (struct net_device *)data;
486 struct netdev_private *np = netdev_priv(dev);
487 unsigned int entry;
488 int next_tick = 1*HZ;
489 unsigned long flags;
490
491 spin_lock_irqsave(&np->rx_lock, flags);
492 /* Recover rx ring exhausted error */
493 if (np->cur_rx - np->old_rx >= RX_RING_SIZE) {
494 printk(KERN_INFO "Try to recover rx ring exhausted...\n");
495 /* Re-allocate skbuffs to fill the descriptor ring */
496 for (; np->cur_rx - np->old_rx > 0; np->old_rx++) {
497 struct sk_buff *skb;
498 entry = np->old_rx % RX_RING_SIZE;
499 /* Dropped packets don't need to re-allocate */
500 if (np->rx_skbuff[entry] == NULL) {
501 skb = netdev_alloc_skb (dev, np->rx_buf_sz);
502 if (skb == NULL) {
503 np->rx_ring[entry].fraginfo = 0;
504 printk (KERN_INFO
505 "%s: Still unable to re-allocate Rx skbuff.#%d\n",
506 dev->name, entry);
507 break;
508 }
509 np->rx_skbuff[entry] = skb;
510 /* 16 byte align the IP header */
511 skb_reserve (skb, 2);
512 np->rx_ring[entry].fraginfo =
513 cpu_to_le64 (pci_map_single
514 (np->pdev, skb->data, np->rx_buf_sz,
515 PCI_DMA_FROMDEVICE));
516 }
517 np->rx_ring[entry].fraginfo |=
518 cpu_to_le64((u64)np->rx_buf_sz << 48);
519 np->rx_ring[entry].status = 0;
520 } /* end for */
521 } /* end if */
522 spin_unlock_irqrestore (&np->rx_lock, flags);
523 np->timer.expires = jiffies + next_tick;
524 add_timer(&np->timer);
525 }
526
527 static void
528 rio_tx_timeout (struct net_device *dev)
529 {
530 long ioaddr = dev->base_addr;
531
532 printk (KERN_INFO "%s: Tx timed out (%4.4x), is buffer full?\n",
533 dev->name, readl (ioaddr + TxStatus));
534 rio_free_tx(dev, 0);
535 dev->if_port = 0;
536 dev->trans_start = jiffies;
537 }
538
539 /* allocate and initialize Tx and Rx descriptors */
540 static void
541 alloc_list (struct net_device *dev)
542 {
543 struct netdev_private *np = netdev_priv(dev);
544 int i;
545
546 np->cur_rx = np->cur_tx = 0;
547 np->old_rx = np->old_tx = 0;
548 np->rx_buf_sz = (dev->mtu <= 1500 ? PACKET_SIZE : dev->mtu + 32);
549
550 /* Initialize Tx descriptors, TFDListPtr leaves in start_xmit(). */
551 for (i = 0; i < TX_RING_SIZE; i++) {
552 np->tx_skbuff[i] = NULL;
553 np->tx_ring[i].status = cpu_to_le64 (TFDDone);
554 np->tx_ring[i].next_desc = cpu_to_le64 (np->tx_ring_dma +
555 ((i+1)%TX_RING_SIZE) *
556 sizeof (struct netdev_desc));
557 }
558
559 /* Initialize Rx descriptors */
560 for (i = 0; i < RX_RING_SIZE; i++) {
561 np->rx_ring[i].next_desc = cpu_to_le64 (np->rx_ring_dma +
562 ((i + 1) % RX_RING_SIZE) *
563 sizeof (struct netdev_desc));
564 np->rx_ring[i].status = 0;
565 np->rx_ring[i].fraginfo = 0;
566 np->rx_skbuff[i] = NULL;
567 }
568
569 /* Allocate the rx buffers */
570 for (i = 0; i < RX_RING_SIZE; i++) {
571 /* Allocated fixed size of skbuff */
572 struct sk_buff *skb = netdev_alloc_skb (dev, np->rx_buf_sz);
573 np->rx_skbuff[i] = skb;
574 if (skb == NULL) {
575 printk (KERN_ERR
576 "%s: alloc_list: allocate Rx buffer error! ",
577 dev->name);
578 break;
579 }
580 skb_reserve (skb, 2); /* 16 byte align the IP header. */
581 /* Rubicon now supports 40 bits of addressing space. */
582 np->rx_ring[i].fraginfo =
583 cpu_to_le64 ( pci_map_single (
584 np->pdev, skb->data, np->rx_buf_sz,
585 PCI_DMA_FROMDEVICE));
586 np->rx_ring[i].fraginfo |= cpu_to_le64((u64)np->rx_buf_sz << 48);
587 }
588
589 /* Set RFDListPtr */
590 writel (np->rx_ring_dma, dev->base_addr + RFDListPtr0);
591 writel (0, dev->base_addr + RFDListPtr1);
592
593 return;
594 }
595
596 static int
597 start_xmit (struct sk_buff *skb, struct net_device *dev)
598 {
599 struct netdev_private *np = netdev_priv(dev);
600 struct netdev_desc *txdesc;
601 unsigned entry;
602 u32 ioaddr;
603 u64 tfc_vlan_tag = 0;
604
605 if (np->link_status == 0) { /* Link Down */
606 dev_kfree_skb(skb);
607 return 0;
608 }
609 ioaddr = dev->base_addr;
610 entry = np->cur_tx % TX_RING_SIZE;
611 np->tx_skbuff[entry] = skb;
612 txdesc = &np->tx_ring[entry];
613
614 #if 0
615 if (skb->ip_summed == CHECKSUM_PARTIAL) {
616 txdesc->status |=
617 cpu_to_le64 (TCPChecksumEnable | UDPChecksumEnable |
618 IPChecksumEnable);
619 }
620 #endif
621 if (np->vlan) {
622 tfc_vlan_tag = VLANTagInsert |
623 ((u64)np->vlan << 32) |
624 ((u64)skb->priority << 45);
625 }
626 txdesc->fraginfo = cpu_to_le64 (pci_map_single (np->pdev, skb->data,
627 skb->len,
628 PCI_DMA_TODEVICE));
629 txdesc->fraginfo |= cpu_to_le64((u64)skb->len << 48);
630
631 /* DL2K bug: DMA fails to get next descriptor ptr in 10Mbps mode
632 * Work around: Always use 1 descriptor in 10Mbps mode */
633 if (entry % np->tx_coalesce == 0 || np->speed == 10)
634 txdesc->status = cpu_to_le64 (entry | tfc_vlan_tag |
635 WordAlignDisable |
636 TxDMAIndicate |
637 (1 << FragCountShift));
638 else
639 txdesc->status = cpu_to_le64 (entry | tfc_vlan_tag |
640 WordAlignDisable |
641 (1 << FragCountShift));
642
643 /* TxDMAPollNow */
644 writel (readl (ioaddr + DMACtrl) | 0x00001000, ioaddr + DMACtrl);
645 /* Schedule ISR */
646 writel(10000, ioaddr + CountDown);
647 np->cur_tx = (np->cur_tx + 1) % TX_RING_SIZE;
648 if ((np->cur_tx - np->old_tx + TX_RING_SIZE) % TX_RING_SIZE
649 < TX_QUEUE_LEN - 1 && np->speed != 10) {
650 /* do nothing */
651 } else if (!netif_queue_stopped(dev)) {
652 netif_stop_queue (dev);
653 }
654
655 /* The first TFDListPtr */
656 if (readl (dev->base_addr + TFDListPtr0) == 0) {
657 writel (np->tx_ring_dma + entry * sizeof (struct netdev_desc),
658 dev->base_addr + TFDListPtr0);
659 writel (0, dev->base_addr + TFDListPtr1);
660 }
661
662 /* NETDEV WATCHDOG timer */
663 dev->trans_start = jiffies;
664 return 0;
665 }
666
667 static irqreturn_t
668 rio_interrupt (int irq, void *dev_instance)
669 {
670 struct net_device *dev = dev_instance;
671 struct netdev_private *np;
672 unsigned int_status;
673 long ioaddr;
674 int cnt = max_intrloop;
675 int handled = 0;
676
677 ioaddr = dev->base_addr;
678 np = netdev_priv(dev);
679 while (1) {
680 int_status = readw (ioaddr + IntStatus);
681 writew (int_status, ioaddr + IntStatus);
682 int_status &= DEFAULT_INTR;
683 if (int_status == 0 || --cnt < 0)
684 break;
685 handled = 1;
686 /* Processing received packets */
687 if (int_status & RxDMAComplete)
688 receive_packet (dev);
689 /* TxDMAComplete interrupt */
690 if ((int_status & (TxDMAComplete|IntRequested))) {
691 int tx_status;
692 tx_status = readl (ioaddr + TxStatus);
693 if (tx_status & 0x01)
694 tx_error (dev, tx_status);
695 /* Free used tx skbuffs */
696 rio_free_tx (dev, 1);
697 }
698
699 /* Handle uncommon events */
700 if (int_status &
701 (HostError | LinkEvent | UpdateStats))
702 rio_error (dev, int_status);
703 }
704 if (np->cur_tx != np->old_tx)
705 writel (100, ioaddr + CountDown);
706 return IRQ_RETVAL(handled);
707 }
708
709 static inline dma_addr_t desc_to_dma(struct netdev_desc *desc)
710 {
711 return le64_to_cpu(desc->fraginfo) & DMA_48BIT_MASK;
712 }
713
714 static void
715 rio_free_tx (struct net_device *dev, int irq)
716 {
717 struct netdev_private *np = netdev_priv(dev);
718 int entry = np->old_tx % TX_RING_SIZE;
719 int tx_use = 0;
720 unsigned long flag = 0;
721
722 if (irq)
723 spin_lock(&np->tx_lock);
724 else
725 spin_lock_irqsave(&np->tx_lock, flag);
726
727 /* Free used tx skbuffs */
728 while (entry != np->cur_tx) {
729 struct sk_buff *skb;
730
731 if (!(np->tx_ring[entry].status & cpu_to_le64(TFDDone)))
732 break;
733 skb = np->tx_skbuff[entry];
734 pci_unmap_single (np->pdev,
735 desc_to_dma(&np->tx_ring[entry]),
736 skb->len, PCI_DMA_TODEVICE);
737 if (irq)
738 dev_kfree_skb_irq (skb);
739 else
740 dev_kfree_skb (skb);
741
742 np->tx_skbuff[entry] = NULL;
743 entry = (entry + 1) % TX_RING_SIZE;
744 tx_use++;
745 }
746 if (irq)
747 spin_unlock(&np->tx_lock);
748 else
749 spin_unlock_irqrestore(&np->tx_lock, flag);
750 np->old_tx = entry;
751
752 /* If the ring is no longer full, clear tx_full and
753 call netif_wake_queue() */
754
755 if (netif_queue_stopped(dev) &&
756 ((np->cur_tx - np->old_tx + TX_RING_SIZE) % TX_RING_SIZE
757 < TX_QUEUE_LEN - 1 || np->speed == 10)) {
758 netif_wake_queue (dev);
759 }
760 }
761
762 static void
763 tx_error (struct net_device *dev, int tx_status)
764 {
765 struct netdev_private *np;
766 long ioaddr = dev->base_addr;
767 int frame_id;
768 int i;
769
770 np = netdev_priv(dev);
771
772 frame_id = (tx_status & 0xffff0000);
773 printk (KERN_ERR "%s: Transmit error, TxStatus %4.4x, FrameId %d.\n",
774 dev->name, tx_status, frame_id);
775 np->stats.tx_errors++;
776 /* Ttransmit Underrun */
777 if (tx_status & 0x10) {
778 np->stats.tx_fifo_errors++;
779 writew (readw (ioaddr + TxStartThresh) + 0x10,
780 ioaddr + TxStartThresh);
781 /* Transmit Underrun need to set TxReset, DMARest, FIFOReset */
782 writew (TxReset | DMAReset | FIFOReset | NetworkReset,
783 ioaddr + ASICCtrl + 2);
784 /* Wait for ResetBusy bit clear */
785 for (i = 50; i > 0; i--) {
786 if ((readw (ioaddr + ASICCtrl + 2) & ResetBusy) == 0)
787 break;
788 mdelay (1);
789 }
790 rio_free_tx (dev, 1);
791 /* Reset TFDListPtr */
792 writel (np->tx_ring_dma +
793 np->old_tx * sizeof (struct netdev_desc),
794 dev->base_addr + TFDListPtr0);
795 writel (0, dev->base_addr + TFDListPtr1);
796
797 /* Let TxStartThresh stay default value */
798 }
799 /* Late Collision */
800 if (tx_status & 0x04) {
801 np->stats.tx_fifo_errors++;
802 /* TxReset and clear FIFO */
803 writew (TxReset | FIFOReset, ioaddr + ASICCtrl + 2);
804 /* Wait reset done */
805 for (i = 50; i > 0; i--) {
806 if ((readw (ioaddr + ASICCtrl + 2) & ResetBusy) == 0)
807 break;
808 mdelay (1);
809 }
810 /* Let TxStartThresh stay default value */
811 }
812 /* Maximum Collisions */
813 #ifdef ETHER_STATS
814 if (tx_status & 0x08)
815 np->stats.collisions16++;
816 #else
817 if (tx_status & 0x08)
818 np->stats.collisions++;
819 #endif
820 /* Restart the Tx */
821 writel (readw (dev->base_addr + MACCtrl) | TxEnable, ioaddr + MACCtrl);
822 }
823
824 static int
825 receive_packet (struct net_device *dev)
826 {
827 struct netdev_private *np = netdev_priv(dev);
828 int entry = np->cur_rx % RX_RING_SIZE;
829 int cnt = 30;
830
831 /* If RFDDone, FrameStart and FrameEnd set, there is a new packet in. */
832 while (1) {
833 struct netdev_desc *desc = &np->rx_ring[entry];
834 int pkt_len;
835 u64 frame_status;
836
837 if (!(desc->status & cpu_to_le64(RFDDone)) ||
838 !(desc->status & cpu_to_le64(FrameStart)) ||
839 !(desc->status & cpu_to_le64(FrameEnd)))
840 break;
841
842 /* Chip omits the CRC. */
843 frame_status = le64_to_cpu(desc->status);
844 pkt_len = frame_status & 0xffff;
845 if (--cnt < 0)
846 break;
847 /* Update rx error statistics, drop packet. */
848 if (frame_status & RFS_Errors) {
849 np->stats.rx_errors++;
850 if (frame_status & (RxRuntFrame | RxLengthError))
851 np->stats.rx_length_errors++;
852 if (frame_status & RxFCSError)
853 np->stats.rx_crc_errors++;
854 if (frame_status & RxAlignmentError && np->speed != 1000)
855 np->stats.rx_frame_errors++;
856 if (frame_status & RxFIFOOverrun)
857 np->stats.rx_fifo_errors++;
858 } else {
859 struct sk_buff *skb;
860
861 /* Small skbuffs for short packets */
862 if (pkt_len > copy_thresh) {
863 pci_unmap_single (np->pdev,
864 desc_to_dma(desc),
865 np->rx_buf_sz,
866 PCI_DMA_FROMDEVICE);
867 skb_put (skb = np->rx_skbuff[entry], pkt_len);
868 np->rx_skbuff[entry] = NULL;
869 } else if ((skb = netdev_alloc_skb(dev, pkt_len + 2))) {
870 pci_dma_sync_single_for_cpu(np->pdev,
871 desc_to_dma(desc),
872 np->rx_buf_sz,
873 PCI_DMA_FROMDEVICE);
874 /* 16 byte align the IP header */
875 skb_reserve (skb, 2);
876 skb_copy_to_linear_data (skb,
877 np->rx_skbuff[entry]->data,
878 pkt_len);
879 skb_put (skb, pkt_len);
880 pci_dma_sync_single_for_device(np->pdev,
881 desc_to_dma(desc),
882 np->rx_buf_sz,
883 PCI_DMA_FROMDEVICE);
884 }
885 skb->protocol = eth_type_trans (skb, dev);
886 #if 0
887 /* Checksum done by hw, but csum value unavailable. */
888 if (np->pdev->pci_rev_id >= 0x0c &&
889 !(frame_status & (TCPError | UDPError | IPError))) {
890 skb->ip_summed = CHECKSUM_UNNECESSARY;
891 }
892 #endif
893 netif_rx (skb);
894 }
895 entry = (entry + 1) % RX_RING_SIZE;
896 }
897 spin_lock(&np->rx_lock);
898 np->cur_rx = entry;
899 /* Re-allocate skbuffs to fill the descriptor ring */
900 entry = np->old_rx;
901 while (entry != np->cur_rx) {
902 struct sk_buff *skb;
903 /* Dropped packets don't need to re-allocate */
904 if (np->rx_skbuff[entry] == NULL) {
905 skb = netdev_alloc_skb(dev, np->rx_buf_sz);
906 if (skb == NULL) {
907 np->rx_ring[entry].fraginfo = 0;
908 printk (KERN_INFO
909 "%s: receive_packet: "
910 "Unable to re-allocate Rx skbuff.#%d\n",
911 dev->name, entry);
912 break;
913 }
914 np->rx_skbuff[entry] = skb;
915 /* 16 byte align the IP header */
916 skb_reserve (skb, 2);
917 np->rx_ring[entry].fraginfo =
918 cpu_to_le64 (pci_map_single
919 (np->pdev, skb->data, np->rx_buf_sz,
920 PCI_DMA_FROMDEVICE));
921 }
922 np->rx_ring[entry].fraginfo |=
923 cpu_to_le64((u64)np->rx_buf_sz << 48);
924 np->rx_ring[entry].status = 0;
925 entry = (entry + 1) % RX_RING_SIZE;
926 }
927 np->old_rx = entry;
928 spin_unlock(&np->rx_lock);
929 return 0;
930 }
931
932 static void
933 rio_error (struct net_device *dev, int int_status)
934 {
935 long ioaddr = dev->base_addr;
936 struct netdev_private *np = netdev_priv(dev);
937 u16 macctrl;
938
939 /* Link change event */
940 if (int_status & LinkEvent) {
941 if (mii_wait_link (dev, 10) == 0) {
942 printk (KERN_INFO "%s: Link up\n", dev->name);
943 if (np->phy_media)
944 mii_get_media_pcs (dev);
945 else
946 mii_get_media (dev);
947 if (np->speed == 1000)
948 np->tx_coalesce = tx_coalesce;
949 else
950 np->tx_coalesce = 1;
951 macctrl = 0;
952 macctrl |= (np->vlan) ? AutoVLANuntagging : 0;
953 macctrl |= (np->full_duplex) ? DuplexSelect : 0;
954 macctrl |= (np->tx_flow) ?
955 TxFlowControlEnable : 0;
956 macctrl |= (np->rx_flow) ?
957 RxFlowControlEnable : 0;
958 writew(macctrl, ioaddr + MACCtrl);
959 np->link_status = 1;
960 netif_carrier_on(dev);
961 } else {
962 printk (KERN_INFO "%s: Link off\n", dev->name);
963 np->link_status = 0;
964 netif_carrier_off(dev);
965 }
966 }
967
968 /* UpdateStats statistics registers */
969 if (int_status & UpdateStats) {
970 get_stats (dev);
971 }
972
973 /* PCI Error, a catastronphic error related to the bus interface
974 occurs, set GlobalReset and HostReset to reset. */
975 if (int_status & HostError) {
976 printk (KERN_ERR "%s: HostError! IntStatus %4.4x.\n",
977 dev->name, int_status);
978 writew (GlobalReset | HostReset, ioaddr + ASICCtrl + 2);
979 mdelay (500);
980 }
981 }
982
983 static struct net_device_stats *
984 get_stats (struct net_device *dev)
985 {
986 long ioaddr = dev->base_addr;
987 struct netdev_private *np = netdev_priv(dev);
988 #ifdef MEM_MAPPING
989 int i;
990 #endif
991 unsigned int stat_reg;
992
993 /* All statistics registers need to be acknowledged,
994 else statistic overflow could cause problems */
995
996 np->stats.rx_packets += readl (ioaddr + FramesRcvOk);
997 np->stats.tx_packets += readl (ioaddr + FramesXmtOk);
998 np->stats.rx_bytes += readl (ioaddr + OctetRcvOk);
999 np->stats.tx_bytes += readl (ioaddr + OctetXmtOk);
1000
1001 np->stats.multicast = readl (ioaddr + McstFramesRcvdOk);
1002 np->stats.collisions += readl (ioaddr + SingleColFrames)
1003 + readl (ioaddr + MultiColFrames);
1004
1005 /* detailed tx errors */
1006 stat_reg = readw (ioaddr + FramesAbortXSColls);
1007 np->stats.tx_aborted_errors += stat_reg;
1008 np->stats.tx_errors += stat_reg;
1009
1010 stat_reg = readw (ioaddr + CarrierSenseErrors);
1011 np->stats.tx_carrier_errors += stat_reg;
1012 np->stats.tx_errors += stat_reg;
1013
1014 /* Clear all other statistic register. */
1015 readl (ioaddr + McstOctetXmtOk);
1016 readw (ioaddr + BcstFramesXmtdOk);
1017 readl (ioaddr + McstFramesXmtdOk);
1018 readw (ioaddr + BcstFramesRcvdOk);
1019 readw (ioaddr + MacControlFramesRcvd);
1020 readw (ioaddr + FrameTooLongErrors);
1021 readw (ioaddr + InRangeLengthErrors);
1022 readw (ioaddr + FramesCheckSeqErrors);
1023 readw (ioaddr + FramesLostRxErrors);
1024 readl (ioaddr + McstOctetXmtOk);
1025 readl (ioaddr + BcstOctetXmtOk);
1026 readl (ioaddr + McstFramesXmtdOk);
1027 readl (ioaddr + FramesWDeferredXmt);
1028 readl (ioaddr + LateCollisions);
1029 readw (ioaddr + BcstFramesXmtdOk);
1030 readw (ioaddr + MacControlFramesXmtd);
1031 readw (ioaddr + FramesWEXDeferal);
1032
1033 #ifdef MEM_MAPPING
1034 for (i = 0x100; i <= 0x150; i += 4)
1035 readl (ioaddr + i);
1036 #endif
1037 readw (ioaddr + TxJumboFrames);
1038 readw (ioaddr + RxJumboFrames);
1039 readw (ioaddr + TCPCheckSumErrors);
1040 readw (ioaddr + UDPCheckSumErrors);
1041 readw (ioaddr + IPCheckSumErrors);
1042 return &np->stats;
1043 }
1044
1045 static int
1046 clear_stats (struct net_device *dev)
1047 {
1048 long ioaddr = dev->base_addr;
1049 #ifdef MEM_MAPPING
1050 int i;
1051 #endif
1052
1053 /* All statistics registers need to be acknowledged,
1054 else statistic overflow could cause problems */
1055 readl (ioaddr + FramesRcvOk);
1056 readl (ioaddr + FramesXmtOk);
1057 readl (ioaddr + OctetRcvOk);
1058 readl (ioaddr + OctetXmtOk);
1059
1060 readl (ioaddr + McstFramesRcvdOk);
1061 readl (ioaddr + SingleColFrames);
1062 readl (ioaddr + MultiColFrames);
1063 readl (ioaddr + LateCollisions);
1064 /* detailed rx errors */
1065 readw (ioaddr + FrameTooLongErrors);
1066 readw (ioaddr + InRangeLengthErrors);
1067 readw (ioaddr + FramesCheckSeqErrors);
1068 readw (ioaddr + FramesLostRxErrors);
1069
1070 /* detailed tx errors */
1071 readw (ioaddr + FramesAbortXSColls);
1072 readw (ioaddr + CarrierSenseErrors);
1073
1074 /* Clear all other statistic register. */
1075 readl (ioaddr + McstOctetXmtOk);
1076 readw (ioaddr + BcstFramesXmtdOk);
1077 readl (ioaddr + McstFramesXmtdOk);
1078 readw (ioaddr + BcstFramesRcvdOk);
1079 readw (ioaddr + MacControlFramesRcvd);
1080 readl (ioaddr + McstOctetXmtOk);
1081 readl (ioaddr + BcstOctetXmtOk);
1082 readl (ioaddr + McstFramesXmtdOk);
1083 readl (ioaddr + FramesWDeferredXmt);
1084 readw (ioaddr + BcstFramesXmtdOk);
1085 readw (ioaddr + MacControlFramesXmtd);
1086 readw (ioaddr + FramesWEXDeferal);
1087 #ifdef MEM_MAPPING
1088 for (i = 0x100; i <= 0x150; i += 4)
1089 readl (ioaddr + i);
1090 #endif
1091 readw (ioaddr + TxJumboFrames);
1092 readw (ioaddr + RxJumboFrames);
1093 readw (ioaddr + TCPCheckSumErrors);
1094 readw (ioaddr + UDPCheckSumErrors);
1095 readw (ioaddr + IPCheckSumErrors);
1096 return 0;
1097 }
1098
1099
1100 static int
1101 change_mtu (struct net_device *dev, int new_mtu)
1102 {
1103 struct netdev_private *np = netdev_priv(dev);
1104 int max = (np->jumbo) ? MAX_JUMBO : 1536;
1105
1106 if ((new_mtu < 68) || (new_mtu > max)) {
1107 return -EINVAL;
1108 }
1109
1110 dev->mtu = new_mtu;
1111
1112 return 0;
1113 }
1114
1115 static void
1116 set_multicast (struct net_device *dev)
1117 {
1118 long ioaddr = dev->base_addr;
1119 u32 hash_table[2];
1120 u16 rx_mode = 0;
1121 struct netdev_private *np = netdev_priv(dev);
1122
1123 hash_table[0] = hash_table[1] = 0;
1124 /* RxFlowcontrol DA: 01-80-C2-00-00-01. Hash index=0x39 */
1125 hash_table[1] |= 0x02000000;
1126 if (dev->flags & IFF_PROMISC) {
1127 /* Receive all frames promiscuously. */
1128 rx_mode = ReceiveAllFrames;
1129 } else if ((dev->flags & IFF_ALLMULTI) ||
1130 (dev->mc_count > multicast_filter_limit)) {
1131 /* Receive broadcast and multicast frames */
1132 rx_mode = ReceiveBroadcast | ReceiveMulticast | ReceiveUnicast;
1133 } else if (dev->mc_count > 0) {
1134 int i;
1135 struct dev_mc_list *mclist;
1136 /* Receive broadcast frames and multicast frames filtering
1137 by Hashtable */
1138 rx_mode =
1139 ReceiveBroadcast | ReceiveMulticastHash | ReceiveUnicast;
1140 for (i=0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1141 i++, mclist=mclist->next)
1142 {
1143 int bit, index = 0;
1144 int crc = ether_crc_le (ETH_ALEN, mclist->dmi_addr);
1145 /* The inverted high significant 6 bits of CRC are
1146 used as an index to hashtable */
1147 for (bit = 0; bit < 6; bit++)
1148 if (crc & (1 << (31 - bit)))
1149 index |= (1 << bit);
1150 hash_table[index / 32] |= (1 << (index % 32));
1151 }
1152 } else {
1153 rx_mode = ReceiveBroadcast | ReceiveUnicast;
1154 }
1155 if (np->vlan) {
1156 /* ReceiveVLANMatch field in ReceiveMode */
1157 rx_mode |= ReceiveVLANMatch;
1158 }
1159
1160 writel (hash_table[0], ioaddr + HashTable0);
1161 writel (hash_table[1], ioaddr + HashTable1);
1162 writew (rx_mode, ioaddr + ReceiveMode);
1163 }
1164
1165 static void rio_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1166 {
1167 struct netdev_private *np = netdev_priv(dev);
1168 strcpy(info->driver, "dl2k");
1169 strcpy(info->version, DRV_VERSION);
1170 strcpy(info->bus_info, pci_name(np->pdev));
1171 }
1172
1173 static int rio_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1174 {
1175 struct netdev_private *np = netdev_priv(dev);
1176 if (np->phy_media) {
1177 /* fiber device */
1178 cmd->supported = SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1179 cmd->advertising= ADVERTISED_Autoneg | ADVERTISED_FIBRE;
1180 cmd->port = PORT_FIBRE;
1181 cmd->transceiver = XCVR_INTERNAL;
1182 } else {
1183 /* copper device */
1184 cmd->supported = SUPPORTED_10baseT_Half |
1185 SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Half
1186 | SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full |
1187 SUPPORTED_Autoneg | SUPPORTED_MII;
1188 cmd->advertising = ADVERTISED_10baseT_Half |
1189 ADVERTISED_10baseT_Full | ADVERTISED_100baseT_Half |
1190 ADVERTISED_100baseT_Full | ADVERTISED_1000baseT_Full|
1191 ADVERTISED_Autoneg | ADVERTISED_MII;
1192 cmd->port = PORT_MII;
1193 cmd->transceiver = XCVR_INTERNAL;
1194 }
1195 if ( np->link_status ) {
1196 cmd->speed = np->speed;
1197 cmd->duplex = np->full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
1198 } else {
1199 cmd->speed = -1;
1200 cmd->duplex = -1;
1201 }
1202 if ( np->an_enable)
1203 cmd->autoneg = AUTONEG_ENABLE;
1204 else
1205 cmd->autoneg = AUTONEG_DISABLE;
1206
1207 cmd->phy_address = np->phy_addr;
1208 return 0;
1209 }
1210
1211 static int rio_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1212 {
1213 struct netdev_private *np = netdev_priv(dev);
1214 netif_carrier_off(dev);
1215 if (cmd->autoneg == AUTONEG_ENABLE) {
1216 if (np->an_enable)
1217 return 0;
1218 else {
1219 np->an_enable = 1;
1220 mii_set_media(dev);
1221 return 0;
1222 }
1223 } else {
1224 np->an_enable = 0;
1225 if (np->speed == 1000) {
1226 cmd->speed = SPEED_100;
1227 cmd->duplex = DUPLEX_FULL;
1228 printk("Warning!! Can't disable Auto negotiation in 1000Mbps, change to Manual 100Mbps, Full duplex.\n");
1229 }
1230 switch(cmd->speed + cmd->duplex) {
1231
1232 case SPEED_10 + DUPLEX_HALF:
1233 np->speed = 10;
1234 np->full_duplex = 0;
1235 break;
1236
1237 case SPEED_10 + DUPLEX_FULL:
1238 np->speed = 10;
1239 np->full_duplex = 1;
1240 break;
1241 case SPEED_100 + DUPLEX_HALF:
1242 np->speed = 100;
1243 np->full_duplex = 0;
1244 break;
1245 case SPEED_100 + DUPLEX_FULL:
1246 np->speed = 100;
1247 np->full_duplex = 1;
1248 break;
1249 case SPEED_1000 + DUPLEX_HALF:/* not supported */
1250 case SPEED_1000 + DUPLEX_FULL:/* not supported */
1251 default:
1252 return -EINVAL;
1253 }
1254 mii_set_media(dev);
1255 }
1256 return 0;
1257 }
1258
1259 static u32 rio_get_link(struct net_device *dev)
1260 {
1261 struct netdev_private *np = netdev_priv(dev);
1262 return np->link_status;
1263 }
1264
1265 static const struct ethtool_ops ethtool_ops = {
1266 .get_drvinfo = rio_get_drvinfo,
1267 .get_settings = rio_get_settings,
1268 .set_settings = rio_set_settings,
1269 .get_link = rio_get_link,
1270 };
1271
1272 static int
1273 rio_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
1274 {
1275 int phy_addr;
1276 struct netdev_private *np = netdev_priv(dev);
1277 struct mii_data *miidata = (struct mii_data *) &rq->ifr_ifru;
1278
1279 struct netdev_desc *desc;
1280 int i;
1281
1282 phy_addr = np->phy_addr;
1283 switch (cmd) {
1284 case SIOCDEVPRIVATE:
1285 break;
1286
1287 case SIOCDEVPRIVATE + 1:
1288 miidata->out_value = mii_read (dev, phy_addr, miidata->reg_num);
1289 break;
1290 case SIOCDEVPRIVATE + 2:
1291 mii_write (dev, phy_addr, miidata->reg_num, miidata->in_value);
1292 break;
1293 case SIOCDEVPRIVATE + 3:
1294 break;
1295 case SIOCDEVPRIVATE + 4:
1296 break;
1297 case SIOCDEVPRIVATE + 5:
1298 netif_stop_queue (dev);
1299 break;
1300 case SIOCDEVPRIVATE + 6:
1301 netif_wake_queue (dev);
1302 break;
1303 case SIOCDEVPRIVATE + 7:
1304 printk
1305 ("tx_full=%x cur_tx=%lx old_tx=%lx cur_rx=%lx old_rx=%lx\n",
1306 netif_queue_stopped(dev), np->cur_tx, np->old_tx, np->cur_rx,
1307 np->old_rx);
1308 break;
1309 case SIOCDEVPRIVATE + 8:
1310 printk("TX ring:\n");
1311 for (i = 0; i < TX_RING_SIZE; i++) {
1312 desc = &np->tx_ring[i];
1313 printk
1314 ("%02x:cur:%08x next:%08x status:%08x frag1:%08x frag0:%08x",
1315 i,
1316 (u32) (np->tx_ring_dma + i * sizeof (*desc)),
1317 (u32)le64_to_cpu(desc->next_desc),
1318 (u32)le64_to_cpu(desc->status),
1319 (u32)(le64_to_cpu(desc->fraginfo) >> 32),
1320 (u32)le64_to_cpu(desc->fraginfo));
1321 printk ("\n");
1322 }
1323 printk ("\n");
1324 break;
1325
1326 default:
1327 return -EOPNOTSUPP;
1328 }
1329 return 0;
1330 }
1331
1332 #define EEP_READ 0x0200
1333 #define EEP_BUSY 0x8000
1334 /* Read the EEPROM word */
1335 /* We use I/O instruction to read/write eeprom to avoid fail on some machines */
1336 static int
1337 read_eeprom (long ioaddr, int eep_addr)
1338 {
1339 int i = 1000;
1340 outw (EEP_READ | (eep_addr & 0xff), ioaddr + EepromCtrl);
1341 while (i-- > 0) {
1342 if (!(inw (ioaddr + EepromCtrl) & EEP_BUSY)) {
1343 return inw (ioaddr + EepromData);
1344 }
1345 }
1346 return 0;
1347 }
1348
1349 enum phy_ctrl_bits {
1350 MII_READ = 0x00, MII_CLK = 0x01, MII_DATA1 = 0x02, MII_WRITE = 0x04,
1351 MII_DUPLEX = 0x08,
1352 };
1353
1354 #define mii_delay() readb(ioaddr)
1355 static void
1356 mii_sendbit (struct net_device *dev, u32 data)
1357 {
1358 long ioaddr = dev->base_addr + PhyCtrl;
1359 data = (data) ? MII_DATA1 : 0;
1360 data |= MII_WRITE;
1361 data |= (readb (ioaddr) & 0xf8) | MII_WRITE;
1362 writeb (data, ioaddr);
1363 mii_delay ();
1364 writeb (data | MII_CLK, ioaddr);
1365 mii_delay ();
1366 }
1367
1368 static int
1369 mii_getbit (struct net_device *dev)
1370 {
1371 long ioaddr = dev->base_addr + PhyCtrl;
1372 u8 data;
1373
1374 data = (readb (ioaddr) & 0xf8) | MII_READ;
1375 writeb (data, ioaddr);
1376 mii_delay ();
1377 writeb (data | MII_CLK, ioaddr);
1378 mii_delay ();
1379 return ((readb (ioaddr) >> 1) & 1);
1380 }
1381
1382 static void
1383 mii_send_bits (struct net_device *dev, u32 data, int len)
1384 {
1385 int i;
1386 for (i = len - 1; i >= 0; i--) {
1387 mii_sendbit (dev, data & (1 << i));
1388 }
1389 }
1390
1391 static int
1392 mii_read (struct net_device *dev, int phy_addr, int reg_num)
1393 {
1394 u32 cmd;
1395 int i;
1396 u32 retval = 0;
1397
1398 /* Preamble */
1399 mii_send_bits (dev, 0xffffffff, 32);
1400 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
1401 /* ST,OP = 0110'b for read operation */
1402 cmd = (0x06 << 10 | phy_addr << 5 | reg_num);
1403 mii_send_bits (dev, cmd, 14);
1404 /* Turnaround */
1405 if (mii_getbit (dev))
1406 goto err_out;
1407 /* Read data */
1408 for (i = 0; i < 16; i++) {
1409 retval |= mii_getbit (dev);
1410 retval <<= 1;
1411 }
1412 /* End cycle */
1413 mii_getbit (dev);
1414 return (retval >> 1) & 0xffff;
1415
1416 err_out:
1417 return 0;
1418 }
1419 static int
1420 mii_write (struct net_device *dev, int phy_addr, int reg_num, u16 data)
1421 {
1422 u32 cmd;
1423
1424 /* Preamble */
1425 mii_send_bits (dev, 0xffffffff, 32);
1426 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
1427 /* ST,OP,AAAAA,RRRRR,TA = 0101xxxxxxxxxx10'b = 0x5002 for write */
1428 cmd = (0x5002 << 16) | (phy_addr << 23) | (reg_num << 18) | data;
1429 mii_send_bits (dev, cmd, 32);
1430 /* End cycle */
1431 mii_getbit (dev);
1432 return 0;
1433 }
1434 static int
1435 mii_wait_link (struct net_device *dev, int wait)
1436 {
1437 __u16 bmsr;
1438 int phy_addr;
1439 struct netdev_private *np;
1440
1441 np = netdev_priv(dev);
1442 phy_addr = np->phy_addr;
1443
1444 do {
1445 bmsr = mii_read (dev, phy_addr, MII_BMSR);
1446 if (bmsr & MII_BMSR_LINK_STATUS)
1447 return 0;
1448 mdelay (1);
1449 } while (--wait > 0);
1450 return -1;
1451 }
1452 static int
1453 mii_get_media (struct net_device *dev)
1454 {
1455 __u16 negotiate;
1456 __u16 bmsr;
1457 __u16 mscr;
1458 __u16 mssr;
1459 int phy_addr;
1460 struct netdev_private *np;
1461
1462 np = netdev_priv(dev);
1463 phy_addr = np->phy_addr;
1464
1465 bmsr = mii_read (dev, phy_addr, MII_BMSR);
1466 if (np->an_enable) {
1467 if (!(bmsr & MII_BMSR_AN_COMPLETE)) {
1468 /* Auto-Negotiation not completed */
1469 return -1;
1470 }
1471 negotiate = mii_read (dev, phy_addr, MII_ANAR) &
1472 mii_read (dev, phy_addr, MII_ANLPAR);
1473 mscr = mii_read (dev, phy_addr, MII_MSCR);
1474 mssr = mii_read (dev, phy_addr, MII_MSSR);
1475 if (mscr & MII_MSCR_1000BT_FD && mssr & MII_MSSR_LP_1000BT_FD) {
1476 np->speed = 1000;
1477 np->full_duplex = 1;
1478 printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n");
1479 } else if (mscr & MII_MSCR_1000BT_HD && mssr & MII_MSSR_LP_1000BT_HD) {
1480 np->speed = 1000;
1481 np->full_duplex = 0;
1482 printk (KERN_INFO "Auto 1000 Mbps, Half duplex\n");
1483 } else if (negotiate & MII_ANAR_100BX_FD) {
1484 np->speed = 100;
1485 np->full_duplex = 1;
1486 printk (KERN_INFO "Auto 100 Mbps, Full duplex\n");
1487 } else if (negotiate & MII_ANAR_100BX_HD) {
1488 np->speed = 100;
1489 np->full_duplex = 0;
1490 printk (KERN_INFO "Auto 100 Mbps, Half duplex\n");
1491 } else if (negotiate & MII_ANAR_10BT_FD) {
1492 np->speed = 10;
1493 np->full_duplex = 1;
1494 printk (KERN_INFO "Auto 10 Mbps, Full duplex\n");
1495 } else if (negotiate & MII_ANAR_10BT_HD) {
1496 np->speed = 10;
1497 np->full_duplex = 0;
1498 printk (KERN_INFO "Auto 10 Mbps, Half duplex\n");
1499 }
1500 if (negotiate & MII_ANAR_PAUSE) {
1501 np->tx_flow &= 1;
1502 np->rx_flow &= 1;
1503 } else if (negotiate & MII_ANAR_ASYMMETRIC) {
1504 np->tx_flow = 0;
1505 np->rx_flow &= 1;
1506 }
1507 /* else tx_flow, rx_flow = user select */
1508 } else {
1509 __u16 bmcr = mii_read (dev, phy_addr, MII_BMCR);
1510 switch (bmcr & (MII_BMCR_SPEED_100 | MII_BMCR_SPEED_1000)) {
1511 case MII_BMCR_SPEED_1000:
1512 printk (KERN_INFO "Operating at 1000 Mbps, ");
1513 break;
1514 case MII_BMCR_SPEED_100:
1515 printk (KERN_INFO "Operating at 100 Mbps, ");
1516 break;
1517 case 0:
1518 printk (KERN_INFO "Operating at 10 Mbps, ");
1519 }
1520 if (bmcr & MII_BMCR_DUPLEX_MODE) {
1521 printk ("Full duplex\n");
1522 } else {
1523 printk ("Half duplex\n");
1524 }
1525 }
1526 if (np->tx_flow)
1527 printk(KERN_INFO "Enable Tx Flow Control\n");
1528 else
1529 printk(KERN_INFO "Disable Tx Flow Control\n");
1530 if (np->rx_flow)
1531 printk(KERN_INFO "Enable Rx Flow Control\n");
1532 else
1533 printk(KERN_INFO "Disable Rx Flow Control\n");
1534
1535 return 0;
1536 }
1537
1538 static int
1539 mii_set_media (struct net_device *dev)
1540 {
1541 __u16 pscr;
1542 __u16 bmcr;
1543 __u16 bmsr;
1544 __u16 anar;
1545 int phy_addr;
1546 struct netdev_private *np;
1547 np = netdev_priv(dev);
1548 phy_addr = np->phy_addr;
1549
1550 /* Does user set speed? */
1551 if (np->an_enable) {
1552 /* Advertise capabilities */
1553 bmsr = mii_read (dev, phy_addr, MII_BMSR);
1554 anar = mii_read (dev, phy_addr, MII_ANAR) &
1555 ~MII_ANAR_100BX_FD &
1556 ~MII_ANAR_100BX_HD &
1557 ~MII_ANAR_100BT4 &
1558 ~MII_ANAR_10BT_FD &
1559 ~MII_ANAR_10BT_HD;
1560 if (bmsr & MII_BMSR_100BX_FD)
1561 anar |= MII_ANAR_100BX_FD;
1562 if (bmsr & MII_BMSR_100BX_HD)
1563 anar |= MII_ANAR_100BX_HD;
1564 if (bmsr & MII_BMSR_100BT4)
1565 anar |= MII_ANAR_100BT4;
1566 if (bmsr & MII_BMSR_10BT_FD)
1567 anar |= MII_ANAR_10BT_FD;
1568 if (bmsr & MII_BMSR_10BT_HD)
1569 anar |= MII_ANAR_10BT_HD;
1570 anar |= MII_ANAR_PAUSE | MII_ANAR_ASYMMETRIC;
1571 mii_write (dev, phy_addr, MII_ANAR, anar);
1572
1573 /* Enable Auto crossover */
1574 pscr = mii_read (dev, phy_addr, MII_PHY_SCR);
1575 pscr |= 3 << 5; /* 11'b */
1576 mii_write (dev, phy_addr, MII_PHY_SCR, pscr);
1577
1578 /* Soft reset PHY */
1579 mii_write (dev, phy_addr, MII_BMCR, MII_BMCR_RESET);
1580 bmcr = MII_BMCR_AN_ENABLE | MII_BMCR_RESTART_AN | MII_BMCR_RESET;
1581 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1582 mdelay(1);
1583 } else {
1584 /* Force speed setting */
1585 /* 1) Disable Auto crossover */
1586 pscr = mii_read (dev, phy_addr, MII_PHY_SCR);
1587 pscr &= ~(3 << 5);
1588 mii_write (dev, phy_addr, MII_PHY_SCR, pscr);
1589
1590 /* 2) PHY Reset */
1591 bmcr = mii_read (dev, phy_addr, MII_BMCR);
1592 bmcr |= MII_BMCR_RESET;
1593 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1594
1595 /* 3) Power Down */
1596 bmcr = 0x1940; /* must be 0x1940 */
1597 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1598 mdelay (100); /* wait a certain time */
1599
1600 /* 4) Advertise nothing */
1601 mii_write (dev, phy_addr, MII_ANAR, 0);
1602
1603 /* 5) Set media and Power Up */
1604 bmcr = MII_BMCR_POWER_DOWN;
1605 if (np->speed == 100) {
1606 bmcr |= MII_BMCR_SPEED_100;
1607 printk (KERN_INFO "Manual 100 Mbps, ");
1608 } else if (np->speed == 10) {
1609 printk (KERN_INFO "Manual 10 Mbps, ");
1610 }
1611 if (np->full_duplex) {
1612 bmcr |= MII_BMCR_DUPLEX_MODE;
1613 printk ("Full duplex\n");
1614 } else {
1615 printk ("Half duplex\n");
1616 }
1617 #if 0
1618 /* Set 1000BaseT Master/Slave setting */
1619 mscr = mii_read (dev, phy_addr, MII_MSCR);
1620 mscr |= MII_MSCR_CFG_ENABLE;
1621 mscr &= ~MII_MSCR_CFG_VALUE = 0;
1622 #endif
1623 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1624 mdelay(10);
1625 }
1626 return 0;
1627 }
1628
1629 static int
1630 mii_get_media_pcs (struct net_device *dev)
1631 {
1632 __u16 negotiate;
1633 __u16 bmsr;
1634 int phy_addr;
1635 struct netdev_private *np;
1636
1637 np = netdev_priv(dev);
1638 phy_addr = np->phy_addr;
1639
1640 bmsr = mii_read (dev, phy_addr, PCS_BMSR);
1641 if (np->an_enable) {
1642 if (!(bmsr & MII_BMSR_AN_COMPLETE)) {
1643 /* Auto-Negotiation not completed */
1644 return -1;
1645 }
1646 negotiate = mii_read (dev, phy_addr, PCS_ANAR) &
1647 mii_read (dev, phy_addr, PCS_ANLPAR);
1648 np->speed = 1000;
1649 if (negotiate & PCS_ANAR_FULL_DUPLEX) {
1650 printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n");
1651 np->full_duplex = 1;
1652 } else {
1653 printk (KERN_INFO "Auto 1000 Mbps, half duplex\n");
1654 np->full_duplex = 0;
1655 }
1656 if (negotiate & PCS_ANAR_PAUSE) {
1657 np->tx_flow &= 1;
1658 np->rx_flow &= 1;
1659 } else if (negotiate & PCS_ANAR_ASYMMETRIC) {
1660 np->tx_flow = 0;
1661 np->rx_flow &= 1;
1662 }
1663 /* else tx_flow, rx_flow = user select */
1664 } else {
1665 __u16 bmcr = mii_read (dev, phy_addr, PCS_BMCR);
1666 printk (KERN_INFO "Operating at 1000 Mbps, ");
1667 if (bmcr & MII_BMCR_DUPLEX_MODE) {
1668 printk ("Full duplex\n");
1669 } else {
1670 printk ("Half duplex\n");
1671 }
1672 }
1673 if (np->tx_flow)
1674 printk(KERN_INFO "Enable Tx Flow Control\n");
1675 else
1676 printk(KERN_INFO "Disable Tx Flow Control\n");
1677 if (np->rx_flow)
1678 printk(KERN_INFO "Enable Rx Flow Control\n");
1679 else
1680 printk(KERN_INFO "Disable Rx Flow Control\n");
1681
1682 return 0;
1683 }
1684
1685 static int
1686 mii_set_media_pcs (struct net_device *dev)
1687 {
1688 __u16 bmcr;
1689 __u16 esr;
1690 __u16 anar;
1691 int phy_addr;
1692 struct netdev_private *np;
1693 np = netdev_priv(dev);
1694 phy_addr = np->phy_addr;
1695
1696 /* Auto-Negotiation? */
1697 if (np->an_enable) {
1698 /* Advertise capabilities */
1699 esr = mii_read (dev, phy_addr, PCS_ESR);
1700 anar = mii_read (dev, phy_addr, MII_ANAR) &
1701 ~PCS_ANAR_HALF_DUPLEX &
1702 ~PCS_ANAR_FULL_DUPLEX;
1703 if (esr & (MII_ESR_1000BT_HD | MII_ESR_1000BX_HD))
1704 anar |= PCS_ANAR_HALF_DUPLEX;
1705 if (esr & (MII_ESR_1000BT_FD | MII_ESR_1000BX_FD))
1706 anar |= PCS_ANAR_FULL_DUPLEX;
1707 anar |= PCS_ANAR_PAUSE | PCS_ANAR_ASYMMETRIC;
1708 mii_write (dev, phy_addr, MII_ANAR, anar);
1709
1710 /* Soft reset PHY */
1711 mii_write (dev, phy_addr, MII_BMCR, MII_BMCR_RESET);
1712 bmcr = MII_BMCR_AN_ENABLE | MII_BMCR_RESTART_AN |
1713 MII_BMCR_RESET;
1714 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1715 mdelay(1);
1716 } else {
1717 /* Force speed setting */
1718 /* PHY Reset */
1719 bmcr = MII_BMCR_RESET;
1720 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1721 mdelay(10);
1722 if (np->full_duplex) {
1723 bmcr = MII_BMCR_DUPLEX_MODE;
1724 printk (KERN_INFO "Manual full duplex\n");
1725 } else {
1726 bmcr = 0;
1727 printk (KERN_INFO "Manual half duplex\n");
1728 }
1729 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1730 mdelay(10);
1731
1732 /* Advertise nothing */
1733 mii_write (dev, phy_addr, MII_ANAR, 0);
1734 }
1735 return 0;
1736 }
1737
1738
1739 static int
1740 rio_close (struct net_device *dev)
1741 {
1742 long ioaddr = dev->base_addr;
1743 struct netdev_private *np = netdev_priv(dev);
1744 struct sk_buff *skb;
1745 int i;
1746
1747 netif_stop_queue (dev);
1748
1749 /* Disable interrupts */
1750 writew (0, ioaddr + IntEnable);
1751
1752 /* Stop Tx and Rx logics */
1753 writel (TxDisable | RxDisable | StatsDisable, ioaddr + MACCtrl);
1754
1755 free_irq (dev->irq, dev);
1756 del_timer_sync (&np->timer);
1757
1758 /* Free all the skbuffs in the queue. */
1759 for (i = 0; i < RX_RING_SIZE; i++) {
1760 np->rx_ring[i].status = 0;
1761 np->rx_ring[i].fraginfo = 0;
1762 skb = np->rx_skbuff[i];
1763 if (skb) {
1764 pci_unmap_single(np->pdev,
1765 desc_to_dma(&np->rx_ring[i]),
1766 skb->len, PCI_DMA_FROMDEVICE);
1767 dev_kfree_skb (skb);
1768 np->rx_skbuff[i] = NULL;
1769 }
1770 }
1771 for (i = 0; i < TX_RING_SIZE; i++) {
1772 skb = np->tx_skbuff[i];
1773 if (skb) {
1774 pci_unmap_single(np->pdev,
1775 desc_to_dma(&np->tx_ring[i]),
1776 skb->len, PCI_DMA_TODEVICE);
1777 dev_kfree_skb (skb);
1778 np->tx_skbuff[i] = NULL;
1779 }
1780 }
1781
1782 return 0;
1783 }
1784
1785 static void __devexit
1786 rio_remove1 (struct pci_dev *pdev)
1787 {
1788 struct net_device *dev = pci_get_drvdata (pdev);
1789
1790 if (dev) {
1791 struct netdev_private *np = netdev_priv(dev);
1792
1793 unregister_netdev (dev);
1794 pci_free_consistent (pdev, RX_TOTAL_SIZE, np->rx_ring,
1795 np->rx_ring_dma);
1796 pci_free_consistent (pdev, TX_TOTAL_SIZE, np->tx_ring,
1797 np->tx_ring_dma);
1798 #ifdef MEM_MAPPING
1799 iounmap ((char *) (dev->base_addr));
1800 #endif
1801 free_netdev (dev);
1802 pci_release_regions (pdev);
1803 pci_disable_device (pdev);
1804 }
1805 pci_set_drvdata (pdev, NULL);
1806 }
1807
1808 static struct pci_driver rio_driver = {
1809 .name = "dl2k",
1810 .id_table = rio_pci_tbl,
1811 .probe = rio_probe1,
1812 .remove = __devexit_p(rio_remove1),
1813 };
1814
1815 static int __init
1816 rio_init (void)
1817 {
1818 return pci_register_driver(&rio_driver);
1819 }
1820
1821 static void __exit
1822 rio_exit (void)
1823 {
1824 pci_unregister_driver (&rio_driver);
1825 }
1826
1827 module_init (rio_init);
1828 module_exit (rio_exit);
1829
1830 /*
1831
1832 Compile command:
1833
1834 gcc -D__KERNEL__ -DMODULE -I/usr/src/linux/include -Wall -Wstrict-prototypes -O2 -c dl2k.c
1835
1836 Read Documentation/networking/dl2k.txt for details.
1837
1838 */
1839
Verdex Pro support