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iwlwifi: move spectrum measurement code to iwl-spectrum.c file
[linux-2.6/verdex.git] / drivers / net / 8139too.c
blob445a479db79d4626ef18c1e6f31945ddfc838b2e
1 /*
2
3 8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux.
4
5 Maintained by Jeff Garzik <jgarzik@pobox.com>
6 Copyright 2000-2002 Jeff Garzik
7
8 Much code comes from Donald Becker's rtl8139.c driver,
9 versions 1.13 and older. This driver was originally based
10 on rtl8139.c version 1.07. Header of rtl8139.c version 1.13:
11
12 -----<snip>-----
13
14 Written 1997-2001 by Donald Becker.
15 This software may be used and distributed according to the
16 terms of the GNU General Public License (GPL), incorporated
17 herein by reference. Drivers based on or derived from this
18 code fall under the GPL and must retain the authorship,
19 copyright and license notice. This file is not a complete
20 program and may only be used when the entire operating
21 system is licensed under the GPL.
22
23 This driver is for boards based on the RTL8129 and RTL8139
24 PCI ethernet chips.
25
26 The author may be reached as becker@scyld.com, or C/O Scyld
27 Computing Corporation 410 Severn Ave., Suite 210 Annapolis
28 MD 21403
29
30 Support and updates available at
31 http://www.scyld.com/network/rtl8139.html
32
33 Twister-tuning table provided by Kinston
34 <shangh@realtek.com.tw>.
35
36 -----<snip>-----
37
38 This software may be used and distributed according to the terms
39 of the GNU General Public License, incorporated herein by reference.
40
41 Contributors:
42
43 Donald Becker - he wrote the original driver, kudos to him!
44 (but please don't e-mail him for support, this isn't his driver)
45
46 Tigran Aivazian - bug fixes, skbuff free cleanup
47
48 Martin Mares - suggestions for PCI cleanup
49
50 David S. Miller - PCI DMA and softnet updates
51
52 Ernst Gill - fixes ported from BSD driver
53
54 Daniel Kobras - identified specific locations of
55 posted MMIO write bugginess
56
57 Gerard Sharp - bug fix, testing and feedback
58
59 David Ford - Rx ring wrap fix
60
61 Dan DeMaggio - swapped RTL8139 cards with me, and allowed me
62 to find and fix a crucial bug on older chipsets.
63
64 Donald Becker/Chris Butterworth/Marcus Westergren -
65 Noticed various Rx packet size-related buglets.
66
67 Santiago Garcia Mantinan - testing and feedback
68
69 Jens David - 2.2.x kernel backports
70
71 Martin Dennett - incredibly helpful insight on undocumented
72 features of the 8139 chips
73
74 Jean-Jacques Michel - bug fix
75
76 Tobias Ringström - Rx interrupt status checking suggestion
77
78 Andrew Morton - Clear blocked signals, avoid
79 buffer overrun setting current->comm.
80
81 Kalle Olavi Niemitalo - Wake-on-LAN ioctls
82
83 Robert Kuebel - Save kernel thread from dying on any signal.
84
85 Submitting bug reports:
86
87 "rtl8139-diag -mmmaaavvveefN" output
88 enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log
89
90 */
91
92 #define DRV_NAME "8139too"
93 #define DRV_VERSION "0.9.28"
94
95
96 #include <linux/module.h>
97 #include <linux/kernel.h>
98 #include <linux/compiler.h>
99 #include <linux/pci.h>
100 #include <linux/init.h>
101 #include <linux/netdevice.h>
102 #include <linux/etherdevice.h>
103 #include <linux/rtnetlink.h>
104 #include <linux/delay.h>
105 #include <linux/ethtool.h>
106 #include <linux/mii.h>
107 #include <linux/completion.h>
108 #include <linux/crc32.h>
109 #include <linux/io.h>
110 #include <linux/uaccess.h>
111 #include <asm/irq.h>
112
113 #define RTL8139_DRIVER_NAME DRV_NAME " Fast Ethernet driver " DRV_VERSION
114 #define PFX DRV_NAME ": "
115
116 /* Default Message level */
117 #define RTL8139_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
118 NETIF_MSG_PROBE | \
119 NETIF_MSG_LINK)
120
121
122 /* define to 1, 2 or 3 to enable copious debugging info */
123 #define RTL8139_DEBUG 0
124
125 /* define to 1 to disable lightweight runtime debugging checks */
126 #undef RTL8139_NDEBUG
127
128
129 #if RTL8139_DEBUG
130 /* note: prints function name for you */
131 # define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __func__ , ## args)
132 #else
133 # define DPRINTK(fmt, args...)
134 #endif
135
136 #ifdef RTL8139_NDEBUG
137 # define assert(expr) do {} while (0)
138 #else
139 # define assert(expr) \
140 if(unlikely(!(expr))) { \
141 printk(KERN_ERR "Assertion failed! %s,%s,%s,line=%d\n", \
142 #expr, __FILE__, __func__, __LINE__); \
143 }
144 #endif
145
146
147 /* A few user-configurable values. */
148 /* media options */
149 #define MAX_UNITS 8
150 static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
151 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
152
153 /* Whether to use MMIO or PIO. Default to MMIO. */
154 #ifdef CONFIG_8139TOO_PIO
155 static int use_io = 1;
156 #else
157 static int use_io = 0;
158 #endif
159
160 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
161 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
162 static int multicast_filter_limit = 32;
163
164 /* bitmapped message enable number */
165 static int debug = -1;
166
167 /*
168 * Receive ring size
169 * Warning: 64K ring has hardware issues and may lock up.
170 */
171 #if defined(CONFIG_SH_DREAMCAST)
172 #define RX_BUF_IDX 0 /* 8K ring */
173 #else
174 #define RX_BUF_IDX 2 /* 32K ring */
175 #endif
176 #define RX_BUF_LEN (8192 << RX_BUF_IDX)
177 #define RX_BUF_PAD 16
178 #define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */
179
180 #if RX_BUF_LEN == 65536
181 #define RX_BUF_TOT_LEN RX_BUF_LEN
182 #else
183 #define RX_BUF_TOT_LEN (RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)
184 #endif
185
186 /* Number of Tx descriptor registers. */
187 #define NUM_TX_DESC 4
188
189 /* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/
190 #define MAX_ETH_FRAME_SIZE 1536
191
192 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
193 #define TX_BUF_SIZE MAX_ETH_FRAME_SIZE
194 #define TX_BUF_TOT_LEN (TX_BUF_SIZE * NUM_TX_DESC)
195
196 /* PCI Tuning Parameters
197 Threshold is bytes transferred to chip before transmission starts. */
198 #define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */
199
200 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
201 #define RX_FIFO_THRESH 7 /* Rx buffer level before first PCI xfer. */
202 #define RX_DMA_BURST 7 /* Maximum PCI burst, '6' is 1024 */
203 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
204 #define TX_RETRY 8 /* 0-15. retries = 16 + (TX_RETRY * 16) */
205
206 /* Operational parameters that usually are not changed. */
207 /* Time in jiffies before concluding the transmitter is hung. */
208 #define TX_TIMEOUT (6*HZ)
209
210
211 enum {
212 HAS_MII_XCVR = 0x010000,
213 HAS_CHIP_XCVR = 0x020000,
214 HAS_LNK_CHNG = 0x040000,
215 };
216
217 #define RTL_NUM_STATS 4 /* number of ETHTOOL_GSTATS u64's */
218 #define RTL_REGS_VER 1 /* version of reg. data in ETHTOOL_GREGS */
219 #define RTL_MIN_IO_SIZE 0x80
220 #define RTL8139B_IO_SIZE 256
221
222 #define RTL8129_CAPS HAS_MII_XCVR
223 #define RTL8139_CAPS (HAS_CHIP_XCVR|HAS_LNK_CHNG)
224
225 typedef enum {
226 RTL8139 = 0,
227 RTL8129,
228 } board_t;
229
230
231 /* indexed by board_t, above */
232 static const struct {
233 const char *name;
234 u32 hw_flags;
235 } board_info[] __devinitdata = {
236 { "RealTek RTL8139", RTL8139_CAPS },
237 { "RealTek RTL8129", RTL8129_CAPS },
238 };
239
240
241 static struct pci_device_id rtl8139_pci_tbl[] = {
242 {0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
243 {0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
244 {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
245 {0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
246 {0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
247 {0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
248 {0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
249 {0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
250 {0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
251 {0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
252 {0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
253 {0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
254 {0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
255 {0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
256 {0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
257 {0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
258 {0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
259 {0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
260 {0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
261
262 #ifdef CONFIG_SH_SECUREEDGE5410
263 /* Bogus 8139 silicon reports 8129 without external PROM :-( */
264 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
265 #endif
266 #ifdef CONFIG_8139TOO_8129
267 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },
268 #endif
269
270 /* some crazy cards report invalid vendor ids like
271 * 0x0001 here. The other ids are valid and constant,
272 * so we simply don't match on the main vendor id.
273 */
274 {PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 },
275 {PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 },
276 {PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 },
277
278 {0,}
279 };
280 MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl);
281
282 static struct {
283 const char str[ETH_GSTRING_LEN];
284 } ethtool_stats_keys[] = {
285 { "early_rx" },
286 { "tx_buf_mapped" },
287 { "tx_timeouts" },
288 { "rx_lost_in_ring" },
289 };
290
291 /* The rest of these values should never change. */
292
293 /* Symbolic offsets to registers. */
294 enum RTL8139_registers {
295 MAC0 = 0, /* Ethernet hardware address. */
296 MAR0 = 8, /* Multicast filter. */
297 TxStatus0 = 0x10, /* Transmit status (Four 32bit registers). */
298 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
299 RxBuf = 0x30,
300 ChipCmd = 0x37,
301 RxBufPtr = 0x38,
302 RxBufAddr = 0x3A,
303 IntrMask = 0x3C,
304 IntrStatus = 0x3E,
305 TxConfig = 0x40,
306 RxConfig = 0x44,
307 Timer = 0x48, /* A general-purpose counter. */
308 RxMissed = 0x4C, /* 24 bits valid, write clears. */
309 Cfg9346 = 0x50,
310 Config0 = 0x51,
311 Config1 = 0x52,
312 TimerInt = 0x54,
313 MediaStatus = 0x58,
314 Config3 = 0x59,
315 Config4 = 0x5A, /* absent on RTL-8139A */
316 HltClk = 0x5B,
317 MultiIntr = 0x5C,
318 TxSummary = 0x60,
319 BasicModeCtrl = 0x62,
320 BasicModeStatus = 0x64,
321 NWayAdvert = 0x66,
322 NWayLPAR = 0x68,
323 NWayExpansion = 0x6A,
324 /* Undocumented registers, but required for proper operation. */
325 FIFOTMS = 0x70, /* FIFO Control and test. */
326 CSCR = 0x74, /* Chip Status and Configuration Register. */
327 PARA78 = 0x78,
328 FlashReg = 0xD4, /* Communication with Flash ROM, four bytes. */
329 PARA7c = 0x7c, /* Magic transceiver parameter register. */
330 Config5 = 0xD8, /* absent on RTL-8139A */
331 };
332
333 enum ClearBitMasks {
334 MultiIntrClear = 0xF000,
335 ChipCmdClear = 0xE2,
336 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
337 };
338
339 enum ChipCmdBits {
340 CmdReset = 0x10,
341 CmdRxEnb = 0x08,
342 CmdTxEnb = 0x04,
343 RxBufEmpty = 0x01,
344 };
345
346 /* Interrupt register bits, using my own meaningful names. */
347 enum IntrStatusBits {
348 PCIErr = 0x8000,
349 PCSTimeout = 0x4000,
350 RxFIFOOver = 0x40,
351 RxUnderrun = 0x20,
352 RxOverflow = 0x10,
353 TxErr = 0x08,
354 TxOK = 0x04,
355 RxErr = 0x02,
356 RxOK = 0x01,
357
358 RxAckBits = RxFIFOOver | RxOverflow | RxOK,
359 };
360
361 enum TxStatusBits {
362 TxHostOwns = 0x2000,
363 TxUnderrun = 0x4000,
364 TxStatOK = 0x8000,
365 TxOutOfWindow = 0x20000000,
366 TxAborted = 0x40000000,
367 TxCarrierLost = 0x80000000,
368 };
369 enum RxStatusBits {
370 RxMulticast = 0x8000,
371 RxPhysical = 0x4000,
372 RxBroadcast = 0x2000,
373 RxBadSymbol = 0x0020,
374 RxRunt = 0x0010,
375 RxTooLong = 0x0008,
376 RxCRCErr = 0x0004,
377 RxBadAlign = 0x0002,
378 RxStatusOK = 0x0001,
379 };
380
381 /* Bits in RxConfig. */
382 enum rx_mode_bits {
383 AcceptErr = 0x20,
384 AcceptRunt = 0x10,
385 AcceptBroadcast = 0x08,
386 AcceptMulticast = 0x04,
387 AcceptMyPhys = 0x02,
388 AcceptAllPhys = 0x01,
389 };
390
391 /* Bits in TxConfig. */
392 enum tx_config_bits {
393 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
394 TxIFGShift = 24,
395 TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */
396 TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */
397 TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */
398 TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */
399
400 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
401 TxCRC = (1 << 16), /* DISABLE Tx pkt CRC append */
402 TxClearAbt = (1 << 0), /* Clear abort (WO) */
403 TxDMAShift = 8, /* DMA burst value (0-7) is shifted X many bits */
404 TxRetryShift = 4, /* TXRR value (0-15) is shifted X many bits */
405
406 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
407 };
408
409 /* Bits in Config1 */
410 enum Config1Bits {
411 Cfg1_PM_Enable = 0x01,
412 Cfg1_VPD_Enable = 0x02,
413 Cfg1_PIO = 0x04,
414 Cfg1_MMIO = 0x08,
415 LWAKE = 0x10, /* not on 8139, 8139A */
416 Cfg1_Driver_Load = 0x20,
417 Cfg1_LED0 = 0x40,
418 Cfg1_LED1 = 0x80,
419 SLEEP = (1 << 1), /* only on 8139, 8139A */
420 PWRDN = (1 << 0), /* only on 8139, 8139A */
421 };
422
423 /* Bits in Config3 */
424 enum Config3Bits {
425 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */
426 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */
427 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */
428 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */
429 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */
430 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */
431 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */
432 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
433 };
434
435 /* Bits in Config4 */
436 enum Config4Bits {
437 LWPTN = (1 << 2), /* not on 8139, 8139A */
438 };
439
440 /* Bits in Config5 */
441 enum Config5Bits {
442 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */
443 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */
444 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */
445 Cfg5_FIFOAddrPtr= (1 << 3), /* Realtek internal SRAM testing */
446 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */
447 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */
448 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */
449 };
450
451 enum RxConfigBits {
452 /* rx fifo threshold */
453 RxCfgFIFOShift = 13,
454 RxCfgFIFONone = (7 << RxCfgFIFOShift),
455
456 /* Max DMA burst */
457 RxCfgDMAShift = 8,
458 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
459
460 /* rx ring buffer length */
461 RxCfgRcv8K = 0,
462 RxCfgRcv16K = (1 << 11),
463 RxCfgRcv32K = (1 << 12),
464 RxCfgRcv64K = (1 << 11) | (1 << 12),
465
466 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
467 RxNoWrap = (1 << 7),
468 };
469
470 /* Twister tuning parameters from RealTek.
471 Completely undocumented, but required to tune bad links on some boards. */
472 enum CSCRBits {
473 CSCR_LinkOKBit = 0x0400,
474 CSCR_LinkChangeBit = 0x0800,
475 CSCR_LinkStatusBits = 0x0f000,
476 CSCR_LinkDownOffCmd = 0x003c0,
477 CSCR_LinkDownCmd = 0x0f3c0,
478 };
479
480 enum Cfg9346Bits {
481 Cfg9346_Lock = 0x00,
482 Cfg9346_Unlock = 0xC0,
483 };
484
485 typedef enum {
486 CH_8139 = 0,
487 CH_8139_K,
488 CH_8139A,
489 CH_8139A_G,
490 CH_8139B,
491 CH_8130,
492 CH_8139C,
493 CH_8100,
494 CH_8100B_8139D,
495 CH_8101,
496 } chip_t;
497
498 enum chip_flags {
499 HasHltClk = (1 << 0),
500 HasLWake = (1 << 1),
501 };
502
503 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
504 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)
505 #define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1)
506
507 /* directly indexed by chip_t, above */
508 static const struct {
509 const char *name;
510 u32 version; /* from RTL8139C/RTL8139D docs */
511 u32 flags;
512 } rtl_chip_info[] = {
513 { "RTL-8139",
514 HW_REVID(1, 0, 0, 0, 0, 0, 0),
515 HasHltClk,
516 },
517
518 { "RTL-8139 rev K",
519 HW_REVID(1, 1, 0, 0, 0, 0, 0),
520 HasHltClk,
521 },
522
523 { "RTL-8139A",
524 HW_REVID(1, 1, 1, 0, 0, 0, 0),
525 HasHltClk, /* XXX undocumented? */
526 },
527
528 { "RTL-8139A rev G",
529 HW_REVID(1, 1, 1, 0, 0, 1, 0),
530 HasHltClk, /* XXX undocumented? */
531 },
532
533 { "RTL-8139B",
534 HW_REVID(1, 1, 1, 1, 0, 0, 0),
535 HasLWake,
536 },
537
538 { "RTL-8130",
539 HW_REVID(1, 1, 1, 1, 1, 0, 0),
540 HasLWake,
541 },
542
543 { "RTL-8139C",
544 HW_REVID(1, 1, 1, 0, 1, 0, 0),
545 HasLWake,
546 },
547
548 { "RTL-8100",
549 HW_REVID(1, 1, 1, 1, 0, 1, 0),
550 HasLWake,
551 },
552
553 { "RTL-8100B/8139D",
554 HW_REVID(1, 1, 1, 0, 1, 0, 1),
555 HasHltClk /* XXX undocumented? */
556 | HasLWake,
557 },
558
559 { "RTL-8101",
560 HW_REVID(1, 1, 1, 0, 1, 1, 1),
561 HasLWake,
562 },
563 };
564
565 struct rtl_extra_stats {
566 unsigned long early_rx;
567 unsigned long tx_buf_mapped;
568 unsigned long tx_timeouts;
569 unsigned long rx_lost_in_ring;
570 };
571
572 struct rtl8139_private {
573 void __iomem *mmio_addr;
574 int drv_flags;
575 struct pci_dev *pci_dev;
576 u32 msg_enable;
577 struct napi_struct napi;
578 struct net_device *dev;
579
580 unsigned char *rx_ring;
581 unsigned int cur_rx; /* RX buf index of next pkt */
582 dma_addr_t rx_ring_dma;
583
584 unsigned int tx_flag;
585 unsigned long cur_tx;
586 unsigned long dirty_tx;
587 unsigned char *tx_buf[NUM_TX_DESC]; /* Tx bounce buffers */
588 unsigned char *tx_bufs; /* Tx bounce buffer region. */
589 dma_addr_t tx_bufs_dma;
590
591 signed char phys[4]; /* MII device addresses. */
592
593 /* Twister tune state. */
594 char twistie, twist_row, twist_col;
595
596 unsigned int watchdog_fired : 1;
597 unsigned int default_port : 4; /* Last dev->if_port value. */
598 unsigned int have_thread : 1;
599
600 spinlock_t lock;
601 spinlock_t rx_lock;
602
603 chip_t chipset;
604 u32 rx_config;
605 struct rtl_extra_stats xstats;
606
607 struct delayed_work thread;
608
609 struct mii_if_info mii;
610 unsigned int regs_len;
611 unsigned long fifo_copy_timeout;
612 };
613
614 MODULE_AUTHOR ("Jeff Garzik <jgarzik@pobox.com>");
615 MODULE_DESCRIPTION ("RealTek RTL-8139 Fast Ethernet driver");
616 MODULE_LICENSE("GPL");
617 MODULE_VERSION(DRV_VERSION);
618
619 module_param(use_io, int, 0);
620 MODULE_PARM_DESC(use_io, "Force use of I/O access mode. 0=MMIO 1=PIO");
621 module_param(multicast_filter_limit, int, 0);
622 module_param_array(media, int, NULL, 0);
623 module_param_array(full_duplex, int, NULL, 0);
624 module_param(debug, int, 0);
625 MODULE_PARM_DESC (debug, "8139too bitmapped message enable number");
626 MODULE_PARM_DESC (multicast_filter_limit, "8139too maximum number of filtered multicast addresses");
627 MODULE_PARM_DESC (media, "8139too: Bits 4+9: force full duplex, bit 5: 100Mbps");
628 MODULE_PARM_DESC (full_duplex, "8139too: Force full duplex for board(s) (1)");
629
630 static int read_eeprom (void __iomem *ioaddr, int location, int addr_len);
631 static int rtl8139_open (struct net_device *dev);
632 static int mdio_read (struct net_device *dev, int phy_id, int location);
633 static void mdio_write (struct net_device *dev, int phy_id, int location,
634 int val);
635 static void rtl8139_start_thread(struct rtl8139_private *tp);
636 static void rtl8139_tx_timeout (struct net_device *dev);
637 static void rtl8139_init_ring (struct net_device *dev);
638 static int rtl8139_start_xmit (struct sk_buff *skb,
639 struct net_device *dev);
640 #ifdef CONFIG_NET_POLL_CONTROLLER
641 static void rtl8139_poll_controller(struct net_device *dev);
642 #endif
643 static int rtl8139_poll(struct napi_struct *napi, int budget);
644 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance);
645 static int rtl8139_close (struct net_device *dev);
646 static int netdev_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
647 static struct net_device_stats *rtl8139_get_stats (struct net_device *dev);
648 static void rtl8139_set_rx_mode (struct net_device *dev);
649 static void __set_rx_mode (struct net_device *dev);
650 static void rtl8139_hw_start (struct net_device *dev);
651 static void rtl8139_thread (struct work_struct *work);
652 static void rtl8139_tx_timeout_task(struct work_struct *work);
653 static const struct ethtool_ops rtl8139_ethtool_ops;
654
655 /* write MMIO register, with flush */
656 /* Flush avoids rtl8139 bug w/ posted MMIO writes */
657 #define RTL_W8_F(reg, val8) do { iowrite8 ((val8), ioaddr + (reg)); ioread8 (ioaddr + (reg)); } while (0)
658 #define RTL_W16_F(reg, val16) do { iowrite16 ((val16), ioaddr + (reg)); ioread16 (ioaddr + (reg)); } while (0)
659 #define RTL_W32_F(reg, val32) do { iowrite32 ((val32), ioaddr + (reg)); ioread32 (ioaddr + (reg)); } while (0)
660
661 /* write MMIO register */
662 #define RTL_W8(reg, val8) iowrite8 ((val8), ioaddr + (reg))
663 #define RTL_W16(reg, val16) iowrite16 ((val16), ioaddr + (reg))
664 #define RTL_W32(reg, val32) iowrite32 ((val32), ioaddr + (reg))
665
666 /* read MMIO register */
667 #define RTL_R8(reg) ioread8 (ioaddr + (reg))
668 #define RTL_R16(reg) ioread16 (ioaddr + (reg))
669 #define RTL_R32(reg) ((unsigned long) ioread32 (ioaddr + (reg)))
670
671
672 static const u16 rtl8139_intr_mask =
673 PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver |
674 TxErr | TxOK | RxErr | RxOK;
675
676 static const u16 rtl8139_norx_intr_mask =
677 PCIErr | PCSTimeout | RxUnderrun |
678 TxErr | TxOK | RxErr ;
679
680 #if RX_BUF_IDX == 0
681 static const unsigned int rtl8139_rx_config =
682 RxCfgRcv8K | RxNoWrap |
683 (RX_FIFO_THRESH << RxCfgFIFOShift) |
684 (RX_DMA_BURST << RxCfgDMAShift);
685 #elif RX_BUF_IDX == 1
686 static const unsigned int rtl8139_rx_config =
687 RxCfgRcv16K | RxNoWrap |
688 (RX_FIFO_THRESH << RxCfgFIFOShift) |
689 (RX_DMA_BURST << RxCfgDMAShift);
690 #elif RX_BUF_IDX == 2
691 static const unsigned int rtl8139_rx_config =
692 RxCfgRcv32K | RxNoWrap |
693 (RX_FIFO_THRESH << RxCfgFIFOShift) |
694 (RX_DMA_BURST << RxCfgDMAShift);
695 #elif RX_BUF_IDX == 3
696 static const unsigned int rtl8139_rx_config =
697 RxCfgRcv64K |
698 (RX_FIFO_THRESH << RxCfgFIFOShift) |
699 (RX_DMA_BURST << RxCfgDMAShift);
700 #else
701 #error "Invalid configuration for 8139_RXBUF_IDX"
702 #endif
703
704 static const unsigned int rtl8139_tx_config =
705 TxIFG96 | (TX_DMA_BURST << TxDMAShift) | (TX_RETRY << TxRetryShift);
706
707 static void __rtl8139_cleanup_dev (struct net_device *dev)
708 {
709 struct rtl8139_private *tp = netdev_priv(dev);
710 struct pci_dev *pdev;
711
712 assert (dev != NULL);
713 assert (tp->pci_dev != NULL);
714 pdev = tp->pci_dev;
715
716 if (tp->mmio_addr)
717 pci_iounmap (pdev, tp->mmio_addr);
718
719 /* it's ok to call this even if we have no regions to free */
720 pci_release_regions (pdev);
721
722 free_netdev(dev);
723 pci_set_drvdata (pdev, NULL);
724 }
725
726
727 static void rtl8139_chip_reset (void __iomem *ioaddr)
728 {
729 int i;
730
731 /* Soft reset the chip. */
732 RTL_W8 (ChipCmd, CmdReset);
733
734 /* Check that the chip has finished the reset. */
735 for (i = 1000; i > 0; i--) {
736 barrier();
737 if ((RTL_R8 (ChipCmd) & CmdReset) == 0)
738 break;
739 udelay (10);
740 }
741 }
742
743
744 static int __devinit rtl8139_init_board (struct pci_dev *pdev,
745 struct net_device **dev_out)
746 {
747 void __iomem *ioaddr;
748 struct net_device *dev;
749 struct rtl8139_private *tp;
750 u8 tmp8;
751 int rc, disable_dev_on_err = 0;
752 unsigned int i;
753 unsigned long pio_start, pio_end, pio_flags, pio_len;
754 unsigned long mmio_start, mmio_end, mmio_flags, mmio_len;
755 u32 version;
756
757 assert (pdev != NULL);
758
759 *dev_out = NULL;
760
761 /* dev and priv zeroed in alloc_etherdev */
762 dev = alloc_etherdev (sizeof (*tp));
763 if (dev == NULL) {
764 dev_err(&pdev->dev, "Unable to alloc new net device\n");
765 return -ENOMEM;
766 }
767 SET_NETDEV_DEV(dev, &pdev->dev);
768
769 tp = netdev_priv(dev);
770 tp->pci_dev = pdev;
771
772 /* enable device (incl. PCI PM wakeup and hotplug setup) */
773 rc = pci_enable_device (pdev);
774 if (rc)
775 goto err_out;
776
777 pio_start = pci_resource_start (pdev, 0);
778 pio_end = pci_resource_end (pdev, 0);
779 pio_flags = pci_resource_flags (pdev, 0);
780 pio_len = pci_resource_len (pdev, 0);
781
782 mmio_start = pci_resource_start (pdev, 1);
783 mmio_end = pci_resource_end (pdev, 1);
784 mmio_flags = pci_resource_flags (pdev, 1);
785 mmio_len = pci_resource_len (pdev, 1);
786
787 /* set this immediately, we need to know before
788 * we talk to the chip directly */
789 DPRINTK("PIO region size == 0x%02X\n", pio_len);
790 DPRINTK("MMIO region size == 0x%02lX\n", mmio_len);
791
792 retry:
793 if (use_io) {
794 /* make sure PCI base addr 0 is PIO */
795 if (!(pio_flags & IORESOURCE_IO)) {
796 dev_err(&pdev->dev, "region #0 not a PIO resource, aborting\n");
797 rc = -ENODEV;
798 goto err_out;
799 }
800 /* check for weird/broken PCI region reporting */
801 if (pio_len < RTL_MIN_IO_SIZE) {
802 dev_err(&pdev->dev, "Invalid PCI I/O region size(s), aborting\n");
803 rc = -ENODEV;
804 goto err_out;
805 }
806 } else {
807 /* make sure PCI base addr 1 is MMIO */
808 if (!(mmio_flags & IORESOURCE_MEM)) {
809 dev_err(&pdev->dev, "region #1 not an MMIO resource, aborting\n");
810 rc = -ENODEV;
811 goto err_out;
812 }
813 if (mmio_len < RTL_MIN_IO_SIZE) {
814 dev_err(&pdev->dev, "Invalid PCI mem region size(s), aborting\n");
815 rc = -ENODEV;
816 goto err_out;
817 }
818 }
819
820 rc = pci_request_regions (pdev, DRV_NAME);
821 if (rc)
822 goto err_out;
823 disable_dev_on_err = 1;
824
825 /* enable PCI bus-mastering */
826 pci_set_master (pdev);
827
828 if (use_io) {
829 ioaddr = pci_iomap(pdev, 0, 0);
830 if (!ioaddr) {
831 dev_err(&pdev->dev, "cannot map PIO, aborting\n");
832 rc = -EIO;
833 goto err_out;
834 }
835 dev->base_addr = pio_start;
836 tp->regs_len = pio_len;
837 } else {
838 /* ioremap MMIO region */
839 ioaddr = pci_iomap(pdev, 1, 0);
840 if (ioaddr == NULL) {
841 dev_err(&pdev->dev, "cannot remap MMIO, trying PIO\n");
842 pci_release_regions(pdev);
843 use_io = 1;
844 goto retry;
845 }
846 dev->base_addr = (long) ioaddr;
847 tp->regs_len = mmio_len;
848 }
849 tp->mmio_addr = ioaddr;
850
851 /* Bring old chips out of low-power mode. */
852 RTL_W8 (HltClk, 'R');
853
854 /* check for missing/broken hardware */
855 if (RTL_R32 (TxConfig) == 0xFFFFFFFF) {
856 dev_err(&pdev->dev, "Chip not responding, ignoring board\n");
857 rc = -EIO;
858 goto err_out;
859 }
860
861 /* identify chip attached to board */
862 version = RTL_R32 (TxConfig) & HW_REVID_MASK;
863 for (i = 0; i < ARRAY_SIZE (rtl_chip_info); i++)
864 if (version == rtl_chip_info[i].version) {
865 tp->chipset = i;
866 goto match;
867 }
868
869 /* if unknown chip, assume array element #0, original RTL-8139 in this case */
870 dev_printk (KERN_DEBUG, &pdev->dev,
871 "unknown chip version, assuming RTL-8139\n");
872 dev_printk (KERN_DEBUG, &pdev->dev,
873 "TxConfig = 0x%lx\n", RTL_R32 (TxConfig));
874 tp->chipset = 0;
875
876 match:
877 DPRINTK ("chipset id (%d) == index %d, '%s'\n",
878 version, i, rtl_chip_info[i].name);
879
880 if (tp->chipset >= CH_8139B) {
881 u8 new_tmp8 = tmp8 = RTL_R8 (Config1);
882 DPRINTK("PCI PM wakeup\n");
883 if ((rtl_chip_info[tp->chipset].flags & HasLWake) &&
884 (tmp8 & LWAKE))
885 new_tmp8 &= ~LWAKE;
886 new_tmp8 |= Cfg1_PM_Enable;
887 if (new_tmp8 != tmp8) {
888 RTL_W8 (Cfg9346, Cfg9346_Unlock);
889 RTL_W8 (Config1, tmp8);
890 RTL_W8 (Cfg9346, Cfg9346_Lock);
891 }
892 if (rtl_chip_info[tp->chipset].flags & HasLWake) {
893 tmp8 = RTL_R8 (Config4);
894 if (tmp8 & LWPTN) {
895 RTL_W8 (Cfg9346, Cfg9346_Unlock);
896 RTL_W8 (Config4, tmp8 & ~LWPTN);
897 RTL_W8 (Cfg9346, Cfg9346_Lock);
898 }
899 }
900 } else {
901 DPRINTK("Old chip wakeup\n");
902 tmp8 = RTL_R8 (Config1);
903 tmp8 &= ~(SLEEP | PWRDN);
904 RTL_W8 (Config1, tmp8);
905 }
906
907 rtl8139_chip_reset (ioaddr);
908
909 *dev_out = dev;
910 return 0;
911
912 err_out:
913 __rtl8139_cleanup_dev (dev);
914 if (disable_dev_on_err)
915 pci_disable_device (pdev);
916 return rc;
917 }
918
919 static const struct net_device_ops rtl8139_netdev_ops = {
920 .ndo_open = rtl8139_open,
921 .ndo_stop = rtl8139_close,
922 .ndo_get_stats = rtl8139_get_stats,
923 .ndo_validate_addr = eth_validate_addr,
924 .ndo_start_xmit = rtl8139_start_xmit,
925 .ndo_set_multicast_list = rtl8139_set_rx_mode,
926 .ndo_do_ioctl = netdev_ioctl,
927 .ndo_tx_timeout = rtl8139_tx_timeout,
928 #ifdef CONFIG_NET_POLL_CONTROLLER
929 .ndo_poll_controller = rtl8139_poll_controller,
930 #endif
931
932 };
933
934 static int __devinit rtl8139_init_one (struct pci_dev *pdev,
935 const struct pci_device_id *ent)
936 {
937 struct net_device *dev = NULL;
938 struct rtl8139_private *tp;
939 int i, addr_len, option;
940 void __iomem *ioaddr;
941 static int board_idx = -1;
942
943 assert (pdev != NULL);
944 assert (ent != NULL);
945
946 board_idx++;
947
948 /* when we're built into the kernel, the driver version message
949 * is only printed if at least one 8139 board has been found
950 */
951 #ifndef MODULE
952 {
953 static int printed_version;
954 if (!printed_version++)
955 printk (KERN_INFO RTL8139_DRIVER_NAME "\n");
956 }
957 #endif
958
959 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
960 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pdev->revision >= 0x20) {
961 dev_info(&pdev->dev,
962 "This (id %04x:%04x rev %02x) is an enhanced 8139C+ chip, use 8139cp\n",
963 pdev->vendor, pdev->device, pdev->revision);
964 return -ENODEV;
965 }
966
967 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
968 pdev->device == PCI_DEVICE_ID_REALTEK_8139 &&
969 pdev->subsystem_vendor == PCI_VENDOR_ID_ATHEROS &&
970 pdev->subsystem_device == PCI_DEVICE_ID_REALTEK_8139) {
971 printk(KERN_INFO "8139too: OQO Model 2 detected. Forcing PIO\n");
972 use_io = 1;
973 }
974
975 i = rtl8139_init_board (pdev, &dev);
976 if (i < 0)
977 return i;
978
979 assert (dev != NULL);
980 tp = netdev_priv(dev);
981 tp->dev = dev;
982
983 ioaddr = tp->mmio_addr;
984 assert (ioaddr != NULL);
985
986 addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6;
987 for (i = 0; i < 3; i++)
988 ((__le16 *) (dev->dev_addr))[i] =
989 cpu_to_le16(read_eeprom (ioaddr, i + 7, addr_len));
990 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
991
992 /* The Rtl8139-specific entries in the device structure. */
993 dev->netdev_ops = &rtl8139_netdev_ops;
994 dev->ethtool_ops = &rtl8139_ethtool_ops;
995 dev->watchdog_timeo = TX_TIMEOUT;
996 netif_napi_add(dev, &tp->napi, rtl8139_poll, 64);
997
998 /* note: the hardware is not capable of sg/csum/highdma, however
999 * through the use of skb_copy_and_csum_dev we enable these
1000 * features
1001 */
1002 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA;
1003
1004 dev->irq = pdev->irq;
1005
1006 /* tp zeroed and aligned in alloc_etherdev */
1007 tp = netdev_priv(dev);
1008
1009 /* note: tp->chipset set in rtl8139_init_board */
1010 tp->drv_flags = board_info[ent->driver_data].hw_flags;
1011 tp->mmio_addr = ioaddr;
1012 tp->msg_enable =
1013 (debug < 0 ? RTL8139_DEF_MSG_ENABLE : ((1 << debug) - 1));
1014 spin_lock_init (&tp->lock);
1015 spin_lock_init (&tp->rx_lock);
1016 INIT_DELAYED_WORK(&tp->thread, rtl8139_thread);
1017 tp->mii.dev = dev;
1018 tp->mii.mdio_read = mdio_read;
1019 tp->mii.mdio_write = mdio_write;
1020 tp->mii.phy_id_mask = 0x3f;
1021 tp->mii.reg_num_mask = 0x1f;
1022
1023 /* dev is fully set up and ready to use now */
1024 DPRINTK("about to register device named %s (%p)...\n", dev->name, dev);
1025 i = register_netdev (dev);
1026 if (i) goto err_out;
1027
1028 pci_set_drvdata (pdev, dev);
1029
1030 printk (KERN_INFO "%s: %s at 0x%lx, "
1031 "%pM, IRQ %d\n",
1032 dev->name,
1033 board_info[ent->driver_data].name,
1034 dev->base_addr,
1035 dev->dev_addr,
1036 dev->irq);
1037
1038 printk (KERN_DEBUG "%s: Identified 8139 chip type '%s'\n",
1039 dev->name, rtl_chip_info[tp->chipset].name);
1040
1041 /* Find the connected MII xcvrs.
1042 Doing this in open() would allow detecting external xcvrs later, but
1043 takes too much time. */
1044 #ifdef CONFIG_8139TOO_8129
1045 if (tp->drv_flags & HAS_MII_XCVR) {
1046 int phy, phy_idx = 0;
1047 for (phy = 0; phy < 32 && phy_idx < sizeof(tp->phys); phy++) {
1048 int mii_status = mdio_read(dev, phy, 1);
1049 if (mii_status != 0xffff && mii_status != 0x0000) {
1050 u16 advertising = mdio_read(dev, phy, 4);
1051 tp->phys[phy_idx++] = phy;
1052 printk(KERN_INFO "%s: MII transceiver %d status 0x%4.4x "
1053 "advertising %4.4x.\n",
1054 dev->name, phy, mii_status, advertising);
1055 }
1056 }
1057 if (phy_idx == 0) {
1058 printk(KERN_INFO "%s: No MII transceivers found! Assuming SYM "
1059 "transceiver.\n",
1060 dev->name);
1061 tp->phys[0] = 32;
1062 }
1063 } else
1064 #endif
1065 tp->phys[0] = 32;
1066 tp->mii.phy_id = tp->phys[0];
1067
1068 /* The lower four bits are the media type. */
1069 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];
1070 if (option > 0) {
1071 tp->mii.full_duplex = (option & 0x210) ? 1 : 0;
1072 tp->default_port = option & 0xFF;
1073 if (tp->default_port)
1074 tp->mii.force_media = 1;
1075 }
1076 if (board_idx < MAX_UNITS && full_duplex[board_idx] > 0)
1077 tp->mii.full_duplex = full_duplex[board_idx];
1078 if (tp->mii.full_duplex) {
1079 printk(KERN_INFO "%s: Media type forced to Full Duplex.\n", dev->name);
1080 /* Changing the MII-advertised media because might prevent
1081 re-connection. */
1082 tp->mii.force_media = 1;
1083 }
1084 if (tp->default_port) {
1085 printk(KERN_INFO " Forcing %dMbps %s-duplex operation.\n",
1086 (option & 0x20 ? 100 : 10),
1087 (option & 0x10 ? "full" : "half"));
1088 mdio_write(dev, tp->phys[0], 0,
1089 ((option & 0x20) ? 0x2000 : 0) | /* 100Mbps? */
1090 ((option & 0x10) ? 0x0100 : 0)); /* Full duplex? */
1091 }
1092
1093 /* Put the chip into low-power mode. */
1094 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1095 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */
1096
1097 return 0;
1098
1099 err_out:
1100 __rtl8139_cleanup_dev (dev);
1101 pci_disable_device (pdev);
1102 return i;
1103 }
1104
1105
1106 static void __devexit rtl8139_remove_one (struct pci_dev *pdev)
1107 {
1108 struct net_device *dev = pci_get_drvdata (pdev);
1109
1110 assert (dev != NULL);
1111
1112 flush_scheduled_work();
1113
1114 unregister_netdev (dev);
1115
1116 __rtl8139_cleanup_dev (dev);
1117 pci_disable_device (pdev);
1118 }
1119
1120
1121 /* Serial EEPROM section. */
1122
1123 /* EEPROM_Ctrl bits. */
1124 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1125 #define EE_CS 0x08 /* EEPROM chip select. */
1126 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1127 #define EE_WRITE_0 0x00
1128 #define EE_WRITE_1 0x02
1129 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1130 #define EE_ENB (0x80 | EE_CS)
1131
1132 /* Delay between EEPROM clock transitions.
1133 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1134 */
1135
1136 #define eeprom_delay() (void)RTL_R32(Cfg9346)
1137
1138 /* The EEPROM commands include the alway-set leading bit. */
1139 #define EE_WRITE_CMD (5)
1140 #define EE_READ_CMD (6)
1141 #define EE_ERASE_CMD (7)
1142
1143 static int __devinit read_eeprom (void __iomem *ioaddr, int location, int addr_len)
1144 {
1145 int i;
1146 unsigned retval = 0;
1147 int read_cmd = location | (EE_READ_CMD << addr_len);
1148
1149 RTL_W8 (Cfg9346, EE_ENB & ~EE_CS);
1150 RTL_W8 (Cfg9346, EE_ENB);
1151 eeprom_delay ();
1152
1153 /* Shift the read command bits out. */
1154 for (i = 4 + addr_len; i >= 0; i--) {
1155 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1156 RTL_W8 (Cfg9346, EE_ENB | dataval);
1157 eeprom_delay ();
1158 RTL_W8 (Cfg9346, EE_ENB | dataval | EE_SHIFT_CLK);
1159 eeprom_delay ();
1160 }
1161 RTL_W8 (Cfg9346, EE_ENB);
1162 eeprom_delay ();
1163
1164 for (i = 16; i > 0; i--) {
1165 RTL_W8 (Cfg9346, EE_ENB | EE_SHIFT_CLK);
1166 eeprom_delay ();
1167 retval =
1168 (retval << 1) | ((RTL_R8 (Cfg9346) & EE_DATA_READ) ? 1 :
1169 0);
1170 RTL_W8 (Cfg9346, EE_ENB);
1171 eeprom_delay ();
1172 }
1173
1174 /* Terminate the EEPROM access. */
1175 RTL_W8 (Cfg9346, ~EE_CS);
1176 eeprom_delay ();
1177
1178 return retval;
1179 }
1180
1181 /* MII serial management: mostly bogus for now. */
1182 /* Read and write the MII management registers using software-generated
1183 serial MDIO protocol.
1184 The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
1185 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
1186 "overclocking" issues. */
1187 #define MDIO_DIR 0x80
1188 #define MDIO_DATA_OUT 0x04
1189 #define MDIO_DATA_IN 0x02
1190 #define MDIO_CLK 0x01
1191 #define MDIO_WRITE0 (MDIO_DIR)
1192 #define MDIO_WRITE1 (MDIO_DIR | MDIO_DATA_OUT)
1193
1194 #define mdio_delay() RTL_R8(Config4)
1195
1196
1197 static const char mii_2_8139_map[8] = {
1198 BasicModeCtrl,
1199 BasicModeStatus,
1200 0,
1201 0,
1202 NWayAdvert,
1203 NWayLPAR,
1204 NWayExpansion,
1205 0
1206 };
1207
1208
1209 #ifdef CONFIG_8139TOO_8129
1210 /* Syncronize the MII management interface by shifting 32 one bits out. */
1211 static void mdio_sync (void __iomem *ioaddr)
1212 {
1213 int i;
1214
1215 for (i = 32; i >= 0; i--) {
1216 RTL_W8 (Config4, MDIO_WRITE1);
1217 mdio_delay ();
1218 RTL_W8 (Config4, MDIO_WRITE1 | MDIO_CLK);
1219 mdio_delay ();
1220 }
1221 }
1222 #endif
1223
1224 static int mdio_read (struct net_device *dev, int phy_id, int location)
1225 {
1226 struct rtl8139_private *tp = netdev_priv(dev);
1227 int retval = 0;
1228 #ifdef CONFIG_8139TOO_8129
1229 void __iomem *ioaddr = tp->mmio_addr;
1230 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
1231 int i;
1232 #endif
1233
1234 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1235 void __iomem *ioaddr = tp->mmio_addr;
1236 return location < 8 && mii_2_8139_map[location] ?
1237 RTL_R16 (mii_2_8139_map[location]) : 0;
1238 }
1239
1240 #ifdef CONFIG_8139TOO_8129
1241 mdio_sync (ioaddr);
1242 /* Shift the read command bits out. */
1243 for (i = 15; i >= 0; i--) {
1244 int dataval = (mii_cmd & (1 << i)) ? MDIO_DATA_OUT : 0;
1245
1246 RTL_W8 (Config4, MDIO_DIR | dataval);
1247 mdio_delay ();
1248 RTL_W8 (Config4, MDIO_DIR | dataval | MDIO_CLK);
1249 mdio_delay ();
1250 }
1251
1252 /* Read the two transition, 16 data, and wire-idle bits. */
1253 for (i = 19; i > 0; i--) {
1254 RTL_W8 (Config4, 0);
1255 mdio_delay ();
1256 retval = (retval << 1) | ((RTL_R8 (Config4) & MDIO_DATA_IN) ? 1 : 0);
1257 RTL_W8 (Config4, MDIO_CLK);
1258 mdio_delay ();
1259 }
1260 #endif
1261
1262 return (retval >> 1) & 0xffff;
1263 }
1264
1265
1266 static void mdio_write (struct net_device *dev, int phy_id, int location,
1267 int value)
1268 {
1269 struct rtl8139_private *tp = netdev_priv(dev);
1270 #ifdef CONFIG_8139TOO_8129
1271 void __iomem *ioaddr = tp->mmio_addr;
1272 int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location << 18) | value;
1273 int i;
1274 #endif
1275
1276 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1277 void __iomem *ioaddr = tp->mmio_addr;
1278 if (location == 0) {
1279 RTL_W8 (Cfg9346, Cfg9346_Unlock);
1280 RTL_W16 (BasicModeCtrl, value);
1281 RTL_W8 (Cfg9346, Cfg9346_Lock);
1282 } else if (location < 8 && mii_2_8139_map[location])
1283 RTL_W16 (mii_2_8139_map[location], value);
1284 return;
1285 }
1286
1287 #ifdef CONFIG_8139TOO_8129
1288 mdio_sync (ioaddr);
1289
1290 /* Shift the command bits out. */
1291 for (i = 31; i >= 0; i--) {
1292 int dataval =
1293 (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
1294 RTL_W8 (Config4, dataval);
1295 mdio_delay ();
1296 RTL_W8 (Config4, dataval | MDIO_CLK);
1297 mdio_delay ();
1298 }
1299 /* Clear out extra bits. */
1300 for (i = 2; i > 0; i--) {
1301 RTL_W8 (Config4, 0);
1302 mdio_delay ();
1303 RTL_W8 (Config4, MDIO_CLK);
1304 mdio_delay ();
1305 }
1306 #endif
1307 }
1308
1309
1310 static int rtl8139_open (struct net_device *dev)
1311 {
1312 struct rtl8139_private *tp = netdev_priv(dev);
1313 int retval;
1314 void __iomem *ioaddr = tp->mmio_addr;
1315
1316 retval = request_irq (dev->irq, rtl8139_interrupt, IRQF_SHARED, dev->name, dev);
1317 if (retval)
1318 return retval;
1319
1320 tp->tx_bufs = dma_alloc_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN,
1321 &tp->tx_bufs_dma, GFP_KERNEL);
1322 tp->rx_ring = dma_alloc_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN,
1323 &tp->rx_ring_dma, GFP_KERNEL);
1324 if (tp->tx_bufs == NULL || tp->rx_ring == NULL) {
1325 free_irq(dev->irq, dev);
1326
1327 if (tp->tx_bufs)
1328 dma_free_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN,
1329 tp->tx_bufs, tp->tx_bufs_dma);
1330 if (tp->rx_ring)
1331 dma_free_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN,
1332 tp->rx_ring, tp->rx_ring_dma);
1333
1334 return -ENOMEM;
1335
1336 }
1337
1338 napi_enable(&tp->napi);
1339
1340 tp->mii.full_duplex = tp->mii.force_media;
1341 tp->tx_flag = (TX_FIFO_THRESH << 11) & 0x003f0000;
1342
1343 rtl8139_init_ring (dev);
1344 rtl8139_hw_start (dev);
1345 netif_start_queue (dev);
1346
1347 if (netif_msg_ifup(tp))
1348 printk(KERN_DEBUG "%s: rtl8139_open() ioaddr %#llx IRQ %d"
1349 " GP Pins %2.2x %s-duplex.\n", dev->name,
1350 (unsigned long long)pci_resource_start (tp->pci_dev, 1),
1351 dev->irq, RTL_R8 (MediaStatus),
1352 tp->mii.full_duplex ? "full" : "half");
1353
1354 rtl8139_start_thread(tp);
1355
1356 return 0;
1357 }
1358
1359
1360 static void rtl_check_media (struct net_device *dev, unsigned int init_media)
1361 {
1362 struct rtl8139_private *tp = netdev_priv(dev);
1363
1364 if (tp->phys[0] >= 0) {
1365 mii_check_media(&tp->mii, netif_msg_link(tp), init_media);
1366 }
1367 }
1368
1369 /* Start the hardware at open or resume. */
1370 static void rtl8139_hw_start (struct net_device *dev)
1371 {
1372 struct rtl8139_private *tp = netdev_priv(dev);
1373 void __iomem *ioaddr = tp->mmio_addr;
1374 u32 i;
1375 u8 tmp;
1376
1377 /* Bring old chips out of low-power mode. */
1378 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1379 RTL_W8 (HltClk, 'R');
1380
1381 rtl8139_chip_reset (ioaddr);
1382
1383 /* unlock Config[01234] and BMCR register writes */
1384 RTL_W8_F (Cfg9346, Cfg9346_Unlock);
1385 /* Restore our idea of the MAC address. */
1386 RTL_W32_F (MAC0 + 0, le32_to_cpu (*(__le32 *) (dev->dev_addr + 0)));
1387 RTL_W32_F (MAC0 + 4, le16_to_cpu (*(__le16 *) (dev->dev_addr + 4)));
1388
1389 /* Must enable Tx/Rx before setting transfer thresholds! */
1390 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1391
1392 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
1393 RTL_W32 (RxConfig, tp->rx_config);
1394 RTL_W32 (TxConfig, rtl8139_tx_config);
1395
1396 tp->cur_rx = 0;
1397
1398 rtl_check_media (dev, 1);
1399
1400 if (tp->chipset >= CH_8139B) {
1401 /* Disable magic packet scanning, which is enabled
1402 * when PM is enabled in Config1. It can be reenabled
1403 * via ETHTOOL_SWOL if desired. */
1404 RTL_W8 (Config3, RTL_R8 (Config3) & ~Cfg3_Magic);
1405 }
1406
1407 DPRINTK("init buffer addresses\n");
1408
1409 /* Lock Config[01234] and BMCR register writes */
1410 RTL_W8 (Cfg9346, Cfg9346_Lock);
1411
1412 /* init Rx ring buffer DMA address */
1413 RTL_W32_F (RxBuf, tp->rx_ring_dma);
1414
1415 /* init Tx buffer DMA addresses */
1416 for (i = 0; i < NUM_TX_DESC; i++)
1417 RTL_W32_F (TxAddr0 + (i * 4), tp->tx_bufs_dma + (tp->tx_buf[i] - tp->tx_bufs));
1418
1419 RTL_W32 (RxMissed, 0);
1420
1421 rtl8139_set_rx_mode (dev);
1422
1423 /* no early-rx interrupts */
1424 RTL_W16 (MultiIntr, RTL_R16 (MultiIntr) & MultiIntrClear);
1425
1426 /* make sure RxTx has started */
1427 tmp = RTL_R8 (ChipCmd);
1428 if ((!(tmp & CmdRxEnb)) || (!(tmp & CmdTxEnb)))
1429 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1430
1431 /* Enable all known interrupts by setting the interrupt mask. */
1432 RTL_W16 (IntrMask, rtl8139_intr_mask);
1433 }
1434
1435
1436 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1437 static void rtl8139_init_ring (struct net_device *dev)
1438 {
1439 struct rtl8139_private *tp = netdev_priv(dev);
1440 int i;
1441
1442 tp->cur_rx = 0;
1443 tp->cur_tx = 0;
1444 tp->dirty_tx = 0;
1445
1446 for (i = 0; i < NUM_TX_DESC; i++)
1447 tp->tx_buf[i] = &tp->tx_bufs[i * TX_BUF_SIZE];
1448 }
1449
1450
1451 /* This must be global for CONFIG_8139TOO_TUNE_TWISTER case */
1452 static int next_tick = 3 * HZ;
1453
1454 #ifndef CONFIG_8139TOO_TUNE_TWISTER
1455 static inline void rtl8139_tune_twister (struct net_device *dev,
1456 struct rtl8139_private *tp) {}
1457 #else
1458 enum TwisterParamVals {
1459 PARA78_default = 0x78fa8388,
1460 PARA7c_default = 0xcb38de43, /* param[0][3] */
1461 PARA7c_xxx = 0xcb38de43,
1462 };
1463
1464 static const unsigned long param[4][4] = {
1465 {0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43},
1466 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1467 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1468 {0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83}
1469 };
1470
1471 static void rtl8139_tune_twister (struct net_device *dev,
1472 struct rtl8139_private *tp)
1473 {
1474 int linkcase;
1475 void __iomem *ioaddr = tp->mmio_addr;
1476
1477 /* This is a complicated state machine to configure the "twister" for
1478 impedance/echos based on the cable length.
1479 All of this is magic and undocumented.
1480 */
1481 switch (tp->twistie) {
1482 case 1:
1483 if (RTL_R16 (CSCR) & CSCR_LinkOKBit) {
1484 /* We have link beat, let us tune the twister. */
1485 RTL_W16 (CSCR, CSCR_LinkDownOffCmd);
1486 tp->twistie = 2; /* Change to state 2. */
1487 next_tick = HZ / 10;
1488 } else {
1489 /* Just put in some reasonable defaults for when beat returns. */
1490 RTL_W16 (CSCR, CSCR_LinkDownCmd);
1491 RTL_W32 (FIFOTMS, 0x20); /* Turn on cable test mode. */
1492 RTL_W32 (PARA78, PARA78_default);
1493 RTL_W32 (PARA7c, PARA7c_default);
1494 tp->twistie = 0; /* Bail from future actions. */
1495 }
1496 break;
1497 case 2:
1498 /* Read how long it took to hear the echo. */
1499 linkcase = RTL_R16 (CSCR) & CSCR_LinkStatusBits;
1500 if (linkcase == 0x7000)
1501 tp->twist_row = 3;
1502 else if (linkcase == 0x3000)
1503 tp->twist_row = 2;
1504 else if (linkcase == 0x1000)
1505 tp->twist_row = 1;
1506 else
1507 tp->twist_row = 0;
1508 tp->twist_col = 0;
1509 tp->twistie = 3; /* Change to state 2. */
1510 next_tick = HZ / 10;
1511 break;
1512 case 3:
1513 /* Put out four tuning parameters, one per 100msec. */
1514 if (tp->twist_col == 0)
1515 RTL_W16 (FIFOTMS, 0);
1516 RTL_W32 (PARA7c, param[(int) tp->twist_row]
1517 [(int) tp->twist_col]);
1518 next_tick = HZ / 10;
1519 if (++tp->twist_col >= 4) {
1520 /* For short cables we are done.
1521 For long cables (row == 3) check for mistune. */
1522 tp->twistie =
1523 (tp->twist_row == 3) ? 4 : 0;
1524 }
1525 break;
1526 case 4:
1527 /* Special case for long cables: check for mistune. */
1528 if ((RTL_R16 (CSCR) &
1529 CSCR_LinkStatusBits) == 0x7000) {
1530 tp->twistie = 0;
1531 break;
1532 } else {
1533 RTL_W32 (PARA7c, 0xfb38de03);
1534 tp->twistie = 5;
1535 next_tick = HZ / 10;
1536 }
1537 break;
1538 case 5:
1539 /* Retune for shorter cable (column 2). */
1540 RTL_W32 (FIFOTMS, 0x20);
1541 RTL_W32 (PARA78, PARA78_default);
1542 RTL_W32 (PARA7c, PARA7c_default);
1543 RTL_W32 (FIFOTMS, 0x00);
1544 tp->twist_row = 2;
1545 tp->twist_col = 0;
1546 tp->twistie = 3;
1547 next_tick = HZ / 10;
1548 break;
1549
1550 default:
1551 /* do nothing */
1552 break;
1553 }
1554 }
1555 #endif /* CONFIG_8139TOO_TUNE_TWISTER */
1556
1557 static inline void rtl8139_thread_iter (struct net_device *dev,
1558 struct rtl8139_private *tp,
1559 void __iomem *ioaddr)
1560 {
1561 int mii_lpa;
1562
1563 mii_lpa = mdio_read (dev, tp->phys[0], MII_LPA);
1564
1565 if (!tp->mii.force_media && mii_lpa != 0xffff) {
1566 int duplex = (mii_lpa & LPA_100FULL)
1567 || (mii_lpa & 0x01C0) == 0x0040;
1568 if (tp->mii.full_duplex != duplex) {
1569 tp->mii.full_duplex = duplex;
1570
1571 if (mii_lpa) {
1572 printk (KERN_INFO
1573 "%s: Setting %s-duplex based on MII #%d link"
1574 " partner ability of %4.4x.\n",
1575 dev->name,
1576 tp->mii.full_duplex ? "full" : "half",
1577 tp->phys[0], mii_lpa);
1578 } else {
1579 printk(KERN_INFO"%s: media is unconnected, link down, or incompatible connection\n",
1580 dev->name);
1581 }
1582 #if 0
1583 RTL_W8 (Cfg9346, Cfg9346_Unlock);
1584 RTL_W8 (Config1, tp->mii.full_duplex ? 0x60 : 0x20);
1585 RTL_W8 (Cfg9346, Cfg9346_Lock);
1586 #endif
1587 }
1588 }
1589
1590 next_tick = HZ * 60;
1591
1592 rtl8139_tune_twister (dev, tp);
1593
1594 DPRINTK ("%s: Media selection tick, Link partner %4.4x.\n",
1595 dev->name, RTL_R16 (NWayLPAR));
1596 DPRINTK ("%s: Other registers are IntMask %4.4x IntStatus %4.4x\n",
1597 dev->name, RTL_R16 (IntrMask), RTL_R16 (IntrStatus));
1598 DPRINTK ("%s: Chip config %2.2x %2.2x.\n",
1599 dev->name, RTL_R8 (Config0),
1600 RTL_R8 (Config1));
1601 }
1602
1603 static void rtl8139_thread (struct work_struct *work)
1604 {
1605 struct rtl8139_private *tp =
1606 container_of(work, struct rtl8139_private, thread.work);
1607 struct net_device *dev = tp->mii.dev;
1608 unsigned long thr_delay = next_tick;
1609
1610 rtnl_lock();
1611
1612 if (!netif_running(dev))
1613 goto out_unlock;
1614
1615 if (tp->watchdog_fired) {
1616 tp->watchdog_fired = 0;
1617 rtl8139_tx_timeout_task(work);
1618 } else
1619 rtl8139_thread_iter(dev, tp, tp->mmio_addr);
1620
1621 if (tp->have_thread)
1622 schedule_delayed_work(&tp->thread, thr_delay);
1623 out_unlock:
1624 rtnl_unlock ();
1625 }
1626
1627 static void rtl8139_start_thread(struct rtl8139_private *tp)
1628 {
1629 tp->twistie = 0;
1630 if (tp->chipset == CH_8139_K)
1631 tp->twistie = 1;
1632 else if (tp->drv_flags & HAS_LNK_CHNG)
1633 return;
1634
1635 tp->have_thread = 1;
1636 tp->watchdog_fired = 0;
1637
1638 schedule_delayed_work(&tp->thread, next_tick);
1639 }
1640
1641 static inline void rtl8139_tx_clear (struct rtl8139_private *tp)
1642 {
1643 tp->cur_tx = 0;
1644 tp->dirty_tx = 0;
1645
1646 /* XXX account for unsent Tx packets in tp->stats.tx_dropped */
1647 }
1648
1649 static void rtl8139_tx_timeout_task (struct work_struct *work)
1650 {
1651 struct rtl8139_private *tp =
1652 container_of(work, struct rtl8139_private, thread.work);
1653 struct net_device *dev = tp->mii.dev;
1654 void __iomem *ioaddr = tp->mmio_addr;
1655 int i;
1656 u8 tmp8;
1657
1658 printk (KERN_DEBUG "%s: Transmit timeout, status %2.2x %4.4x %4.4x "
1659 "media %2.2x.\n", dev->name, RTL_R8 (ChipCmd),
1660 RTL_R16(IntrStatus), RTL_R16(IntrMask), RTL_R8(MediaStatus));
1661 /* Emit info to figure out what went wrong. */
1662 printk (KERN_DEBUG "%s: Tx queue start entry %ld dirty entry %ld.\n",
1663 dev->name, tp->cur_tx, tp->dirty_tx);
1664 for (i = 0; i < NUM_TX_DESC; i++)
1665 printk (KERN_DEBUG "%s: Tx descriptor %d is %8.8lx.%s\n",
1666 dev->name, i, RTL_R32 (TxStatus0 + (i * 4)),
1667 i == tp->dirty_tx % NUM_TX_DESC ?
1668 " (queue head)" : "");
1669
1670 tp->xstats.tx_timeouts++;
1671
1672 /* disable Tx ASAP, if not already */
1673 tmp8 = RTL_R8 (ChipCmd);
1674 if (tmp8 & CmdTxEnb)
1675 RTL_W8 (ChipCmd, CmdRxEnb);
1676
1677 spin_lock_bh(&tp->rx_lock);
1678 /* Disable interrupts by clearing the interrupt mask. */
1679 RTL_W16 (IntrMask, 0x0000);
1680
1681 /* Stop a shared interrupt from scavenging while we are. */
1682 spin_lock_irq(&tp->lock);
1683 rtl8139_tx_clear (tp);
1684 spin_unlock_irq(&tp->lock);
1685
1686 /* ...and finally, reset everything */
1687 if (netif_running(dev)) {
1688 rtl8139_hw_start (dev);
1689 netif_wake_queue (dev);
1690 }
1691 spin_unlock_bh(&tp->rx_lock);
1692 }
1693
1694 static void rtl8139_tx_timeout (struct net_device *dev)
1695 {
1696 struct rtl8139_private *tp = netdev_priv(dev);
1697
1698 tp->watchdog_fired = 1;
1699 if (!tp->have_thread) {
1700 INIT_DELAYED_WORK(&tp->thread, rtl8139_thread);
1701 schedule_delayed_work(&tp->thread, next_tick);
1702 }
1703 }
1704
1705 static int rtl8139_start_xmit (struct sk_buff *skb, struct net_device *dev)
1706 {
1707 struct rtl8139_private *tp = netdev_priv(dev);
1708 void __iomem *ioaddr = tp->mmio_addr;
1709 unsigned int entry;
1710 unsigned int len = skb->len;
1711 unsigned long flags;
1712
1713 /* Calculate the next Tx descriptor entry. */
1714 entry = tp->cur_tx % NUM_TX_DESC;
1715
1716 /* Note: the chip doesn't have auto-pad! */
1717 if (likely(len < TX_BUF_SIZE)) {
1718 if (len < ETH_ZLEN)
1719 memset(tp->tx_buf[entry], 0, ETH_ZLEN);
1720 skb_copy_and_csum_dev(skb, tp->tx_buf[entry]);
1721 dev_kfree_skb(skb);
1722 } else {
1723 dev_kfree_skb(skb);
1724 dev->stats.tx_dropped++;
1725 return 0;
1726 }
1727
1728 spin_lock_irqsave(&tp->lock, flags);
1729 /*
1730 * Writing to TxStatus triggers a DMA transfer of the data
1731 * copied to tp->tx_buf[entry] above. Use a memory barrier
1732 * to make sure that the device sees the updated data.
1733 */
1734 wmb();
1735 RTL_W32_F (TxStatus0 + (entry * sizeof (u32)),
1736 tp->tx_flag | max(len, (unsigned int)ETH_ZLEN));
1737
1738 dev->trans_start = jiffies;
1739
1740 tp->cur_tx++;
1741
1742 if ((tp->cur_tx - NUM_TX_DESC) == tp->dirty_tx)
1743 netif_stop_queue (dev);
1744 spin_unlock_irqrestore(&tp->lock, flags);
1745
1746 if (netif_msg_tx_queued(tp))
1747 printk (KERN_DEBUG "%s: Queued Tx packet size %u to slot %d.\n",
1748 dev->name, len, entry);
1749
1750 return 0;
1751 }
1752
1753
1754 static void rtl8139_tx_interrupt (struct net_device *dev,
1755 struct rtl8139_private *tp,
1756 void __iomem *ioaddr)
1757 {
1758 unsigned long dirty_tx, tx_left;
1759
1760 assert (dev != NULL);
1761 assert (ioaddr != NULL);
1762
1763 dirty_tx = tp->dirty_tx;
1764 tx_left = tp->cur_tx - dirty_tx;
1765 while (tx_left > 0) {
1766 int entry = dirty_tx % NUM_TX_DESC;
1767 int txstatus;
1768
1769 txstatus = RTL_R32 (TxStatus0 + (entry * sizeof (u32)));
1770
1771 if (!(txstatus & (TxStatOK | TxUnderrun | TxAborted)))
1772 break; /* It still hasn't been Txed */
1773
1774 /* Note: TxCarrierLost is always asserted at 100mbps. */
1775 if (txstatus & (TxOutOfWindow | TxAborted)) {
1776 /* There was an major error, log it. */
1777 if (netif_msg_tx_err(tp))
1778 printk(KERN_DEBUG "%s: Transmit error, Tx status %8.8x.\n",
1779 dev->name, txstatus);
1780 dev->stats.tx_errors++;
1781 if (txstatus & TxAborted) {
1782 dev->stats.tx_aborted_errors++;
1783 RTL_W32 (TxConfig, TxClearAbt);
1784 RTL_W16 (IntrStatus, TxErr);
1785 wmb();
1786 }
1787 if (txstatus & TxCarrierLost)
1788 dev->stats.tx_carrier_errors++;
1789 if (txstatus & TxOutOfWindow)
1790 dev->stats.tx_window_errors++;
1791 } else {
1792 if (txstatus & TxUnderrun) {
1793 /* Add 64 to the Tx FIFO threshold. */
1794 if (tp->tx_flag < 0x00300000)
1795 tp->tx_flag += 0x00020000;
1796 dev->stats.tx_fifo_errors++;
1797 }
1798 dev->stats.collisions += (txstatus >> 24) & 15;
1799 dev->stats.tx_bytes += txstatus & 0x7ff;
1800 dev->stats.tx_packets++;
1801 }
1802
1803 dirty_tx++;
1804 tx_left--;
1805 }
1806
1807 #ifndef RTL8139_NDEBUG
1808 if (tp->cur_tx - dirty_tx > NUM_TX_DESC) {
1809 printk (KERN_ERR "%s: Out-of-sync dirty pointer, %ld vs. %ld.\n",
1810 dev->name, dirty_tx, tp->cur_tx);
1811 dirty_tx += NUM_TX_DESC;
1812 }
1813 #endif /* RTL8139_NDEBUG */
1814
1815 /* only wake the queue if we did work, and the queue is stopped */
1816 if (tp->dirty_tx != dirty_tx) {
1817 tp->dirty_tx = dirty_tx;
1818 mb();
1819 netif_wake_queue (dev);
1820 }
1821 }
1822
1823
1824 /* TODO: clean this up! Rx reset need not be this intensive */
1825 static void rtl8139_rx_err (u32 rx_status, struct net_device *dev,
1826 struct rtl8139_private *tp, void __iomem *ioaddr)
1827 {
1828 u8 tmp8;
1829 #ifdef CONFIG_8139_OLD_RX_RESET
1830 int tmp_work;
1831 #endif
1832
1833 if (netif_msg_rx_err (tp))
1834 printk(KERN_DEBUG "%s: Ethernet frame had errors, status %8.8x.\n",
1835 dev->name, rx_status);
1836 dev->stats.rx_errors++;
1837 if (!(rx_status & RxStatusOK)) {
1838 if (rx_status & RxTooLong) {
1839 DPRINTK ("%s: Oversized Ethernet frame, status %4.4x!\n",
1840 dev->name, rx_status);
1841 /* A.C.: The chip hangs here. */
1842 }
1843 if (rx_status & (RxBadSymbol | RxBadAlign))
1844 dev->stats.rx_frame_errors++;
1845 if (rx_status & (RxRunt | RxTooLong))
1846 dev->stats.rx_length_errors++;
1847 if (rx_status & RxCRCErr)
1848 dev->stats.rx_crc_errors++;
1849 } else {
1850 tp->xstats.rx_lost_in_ring++;
1851 }
1852
1853 #ifndef CONFIG_8139_OLD_RX_RESET
1854 tmp8 = RTL_R8 (ChipCmd);
1855 RTL_W8 (ChipCmd, tmp8 & ~CmdRxEnb);
1856 RTL_W8 (ChipCmd, tmp8);
1857 RTL_W32 (RxConfig, tp->rx_config);
1858 tp->cur_rx = 0;
1859 #else
1860 /* Reset the receiver, based on RealTek recommendation. (Bug?) */
1861
1862 /* disable receive */
1863 RTL_W8_F (ChipCmd, CmdTxEnb);
1864 tmp_work = 200;
1865 while (--tmp_work > 0) {
1866 udelay(1);
1867 tmp8 = RTL_R8 (ChipCmd);
1868 if (!(tmp8 & CmdRxEnb))
1869 break;
1870 }
1871 if (tmp_work <= 0)
1872 printk (KERN_WARNING PFX "rx stop wait too long\n");
1873 /* restart receive */
1874 tmp_work = 200;
1875 while (--tmp_work > 0) {
1876 RTL_W8_F (ChipCmd, CmdRxEnb | CmdTxEnb);
1877 udelay(1);
1878 tmp8 = RTL_R8 (ChipCmd);
1879 if ((tmp8 & CmdRxEnb) && (tmp8 & CmdTxEnb))
1880 break;
1881 }
1882 if (tmp_work <= 0)
1883 printk (KERN_WARNING PFX "tx/rx enable wait too long\n");
1884
1885 /* and reinitialize all rx related registers */
1886 RTL_W8_F (Cfg9346, Cfg9346_Unlock);
1887 /* Must enable Tx/Rx before setting transfer thresholds! */
1888 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1889
1890 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
1891 RTL_W32 (RxConfig, tp->rx_config);
1892 tp->cur_rx = 0;
1893
1894 DPRINTK("init buffer addresses\n");
1895
1896 /* Lock Config[01234] and BMCR register writes */
1897 RTL_W8 (Cfg9346, Cfg9346_Lock);
1898
1899 /* init Rx ring buffer DMA address */
1900 RTL_W32_F (RxBuf, tp->rx_ring_dma);
1901
1902 /* A.C.: Reset the multicast list. */
1903 __set_rx_mode (dev);
1904 #endif
1905 }
1906
1907 #if RX_BUF_IDX == 3
1908 static inline void wrap_copy(struct sk_buff *skb, const unsigned char *ring,
1909 u32 offset, unsigned int size)
1910 {
1911 u32 left = RX_BUF_LEN - offset;
1912
1913 if (size > left) {
1914 skb_copy_to_linear_data(skb, ring + offset, left);
1915 skb_copy_to_linear_data_offset(skb, left, ring, size - left);
1916 } else
1917 skb_copy_to_linear_data(skb, ring + offset, size);
1918 }
1919 #endif
1920
1921 static void rtl8139_isr_ack(struct rtl8139_private *tp)
1922 {
1923 void __iomem *ioaddr = tp->mmio_addr;
1924 u16 status;
1925
1926 status = RTL_R16 (IntrStatus) & RxAckBits;
1927
1928 /* Clear out errors and receive interrupts */
1929 if (likely(status != 0)) {
1930 if (unlikely(status & (RxFIFOOver | RxOverflow))) {
1931 tp->dev->stats.rx_errors++;
1932 if (status & RxFIFOOver)
1933 tp->dev->stats.rx_fifo_errors++;
1934 }
1935 RTL_W16_F (IntrStatus, RxAckBits);
1936 }
1937 }
1938
1939 static int rtl8139_rx(struct net_device *dev, struct rtl8139_private *tp,
1940 int budget)
1941 {
1942 void __iomem *ioaddr = tp->mmio_addr;
1943 int received = 0;
1944 unsigned char *rx_ring = tp->rx_ring;
1945 unsigned int cur_rx = tp->cur_rx;
1946 unsigned int rx_size = 0;
1947
1948 DPRINTK ("%s: In rtl8139_rx(), current %4.4x BufAddr %4.4x,"
1949 " free to %4.4x, Cmd %2.2x.\n", dev->name, (u16)cur_rx,
1950 RTL_R16 (RxBufAddr),
1951 RTL_R16 (RxBufPtr), RTL_R8 (ChipCmd));
1952
1953 while (netif_running(dev) && received < budget
1954 && (RTL_R8 (ChipCmd) & RxBufEmpty) == 0) {
1955 u32 ring_offset = cur_rx % RX_BUF_LEN;
1956 u32 rx_status;
1957 unsigned int pkt_size;
1958 struct sk_buff *skb;
1959
1960 rmb();
1961
1962 /* read size+status of next frame from DMA ring buffer */
1963 rx_status = le32_to_cpu (*(__le32 *) (rx_ring + ring_offset));
1964 rx_size = rx_status >> 16;
1965 pkt_size = rx_size - 4;
1966
1967 if (netif_msg_rx_status(tp))
1968 printk(KERN_DEBUG "%s: rtl8139_rx() status %4.4x, size %4.4x,"
1969 " cur %4.4x.\n", dev->name, rx_status,
1970 rx_size, cur_rx);
1971 #if RTL8139_DEBUG > 2
1972 {
1973 int i;
1974 DPRINTK ("%s: Frame contents ", dev->name);
1975 for (i = 0; i < 70; i++)
1976 printk (" %2.2x",
1977 rx_ring[ring_offset + i]);
1978 printk (".\n");
1979 }
1980 #endif
1981
1982 /* Packet copy from FIFO still in progress.
1983 * Theoretically, this should never happen
1984 * since EarlyRx is disabled.
1985 */
1986 if (unlikely(rx_size == 0xfff0)) {
1987 if (!tp->fifo_copy_timeout)
1988 tp->fifo_copy_timeout = jiffies + 2;
1989 else if (time_after(jiffies, tp->fifo_copy_timeout)) {
1990 DPRINTK ("%s: hung FIFO. Reset.", dev->name);
1991 rx_size = 0;
1992 goto no_early_rx;
1993 }
1994 if (netif_msg_intr(tp)) {
1995 printk(KERN_DEBUG "%s: fifo copy in progress.",
1996 dev->name);
1997 }
1998 tp->xstats.early_rx++;
1999 break;
2000 }
2001
2002 no_early_rx:
2003 tp->fifo_copy_timeout = 0;
2004
2005 /* If Rx err or invalid rx_size/rx_status received
2006 * (which happens if we get lost in the ring),
2007 * Rx process gets reset, so we abort any further
2008 * Rx processing.
2009 */
2010 if (unlikely((rx_size > (MAX_ETH_FRAME_SIZE+4)) ||
2011 (rx_size < 8) ||
2012 (!(rx_status & RxStatusOK)))) {
2013 rtl8139_rx_err (rx_status, dev, tp, ioaddr);
2014 received = -1;
2015 goto out;
2016 }
2017
2018 /* Malloc up new buffer, compatible with net-2e. */
2019 /* Omit the four octet CRC from the length. */
2020
2021 skb = netdev_alloc_skb(dev, pkt_size + NET_IP_ALIGN);
2022 if (likely(skb)) {
2023 skb_reserve (skb, NET_IP_ALIGN); /* 16 byte align the IP fields. */
2024 #if RX_BUF_IDX == 3
2025 wrap_copy(skb, rx_ring, ring_offset+4, pkt_size);
2026 #else
2027 skb_copy_to_linear_data (skb, &rx_ring[ring_offset + 4], pkt_size);
2028 #endif
2029 skb_put (skb, pkt_size);
2030
2031 skb->protocol = eth_type_trans (skb, dev);
2032
2033 dev->stats.rx_bytes += pkt_size;
2034 dev->stats.rx_packets++;
2035
2036 netif_receive_skb (skb);
2037 } else {
2038 if (net_ratelimit())
2039 printk (KERN_WARNING
2040 "%s: Memory squeeze, dropping packet.\n",
2041 dev->name);
2042 dev->stats.rx_dropped++;
2043 }
2044 received++;
2045
2046 cur_rx = (cur_rx + rx_size + 4 + 3) & ~3;
2047 RTL_W16 (RxBufPtr, (u16) (cur_rx - 16));
2048
2049 rtl8139_isr_ack(tp);
2050 }
2051
2052 if (unlikely(!received || rx_size == 0xfff0))
2053 rtl8139_isr_ack(tp);
2054
2055 #if RTL8139_DEBUG > 1
2056 DPRINTK ("%s: Done rtl8139_rx(), current %4.4x BufAddr %4.4x,"
2057 " free to %4.4x, Cmd %2.2x.\n", dev->name, cur_rx,
2058 RTL_R16 (RxBufAddr),
2059 RTL_R16 (RxBufPtr), RTL_R8 (ChipCmd));
2060 #endif
2061
2062 tp->cur_rx = cur_rx;
2063
2064 /*
2065 * The receive buffer should be mostly empty.
2066 * Tell NAPI to reenable the Rx irq.
2067 */
2068 if (tp->fifo_copy_timeout)
2069 received = budget;
2070
2071 out:
2072 return received;
2073 }
2074
2075
2076 static void rtl8139_weird_interrupt (struct net_device *dev,
2077 struct rtl8139_private *tp,
2078 void __iomem *ioaddr,
2079 int status, int link_changed)
2080 {
2081 DPRINTK ("%s: Abnormal interrupt, status %8.8x.\n",
2082 dev->name, status);
2083
2084 assert (dev != NULL);
2085 assert (tp != NULL);
2086 assert (ioaddr != NULL);
2087
2088 /* Update the error count. */
2089 dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2090 RTL_W32 (RxMissed, 0);
2091
2092 if ((status & RxUnderrun) && link_changed &&
2093 (tp->drv_flags & HAS_LNK_CHNG)) {
2094 rtl_check_media(dev, 0);
2095 status &= ~RxUnderrun;
2096 }
2097
2098 if (status & (RxUnderrun | RxErr))
2099 dev->stats.rx_errors++;
2100
2101 if (status & PCSTimeout)
2102 dev->stats.rx_length_errors++;
2103 if (status & RxUnderrun)
2104 dev->stats.rx_fifo_errors++;
2105 if (status & PCIErr) {
2106 u16 pci_cmd_status;
2107 pci_read_config_word (tp->pci_dev, PCI_STATUS, &pci_cmd_status);
2108 pci_write_config_word (tp->pci_dev, PCI_STATUS, pci_cmd_status);
2109
2110 printk (KERN_ERR "%s: PCI Bus error %4.4x.\n",
2111 dev->name, pci_cmd_status);
2112 }
2113 }
2114
2115 static int rtl8139_poll(struct napi_struct *napi, int budget)
2116 {
2117 struct rtl8139_private *tp = container_of(napi, struct rtl8139_private, napi);
2118 struct net_device *dev = tp->dev;
2119 void __iomem *ioaddr = tp->mmio_addr;
2120 int work_done;
2121
2122 spin_lock(&tp->rx_lock);
2123 work_done = 0;
2124 if (likely(RTL_R16(IntrStatus) & RxAckBits))
2125 work_done += rtl8139_rx(dev, tp, budget);
2126
2127 if (work_done < budget) {
2128 unsigned long flags;
2129 /*
2130 * Order is important since data can get interrupted
2131 * again when we think we are done.
2132 */
2133 spin_lock_irqsave(&tp->lock, flags);
2134 RTL_W16_F(IntrMask, rtl8139_intr_mask);
2135 __netif_rx_complete(dev, napi);
2136 spin_unlock_irqrestore(&tp->lock, flags);
2137 }
2138 spin_unlock(&tp->rx_lock);
2139
2140 return work_done;
2141 }
2142
2143 /* The interrupt handler does all of the Rx thread work and cleans up
2144 after the Tx thread. */
2145 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance)
2146 {
2147 struct net_device *dev = (struct net_device *) dev_instance;
2148 struct rtl8139_private *tp = netdev_priv(dev);
2149 void __iomem *ioaddr = tp->mmio_addr;
2150 u16 status, ackstat;
2151 int link_changed = 0; /* avoid bogus "uninit" warning */
2152 int handled = 0;
2153
2154 spin_lock (&tp->lock);
2155 status = RTL_R16 (IntrStatus);
2156
2157 /* shared irq? */
2158 if (unlikely((status & rtl8139_intr_mask) == 0))
2159 goto out;
2160
2161 handled = 1;
2162
2163 /* h/w no longer present (hotplug?) or major error, bail */
2164 if (unlikely(status == 0xFFFF))
2165 goto out;
2166
2167 /* close possible race's with dev_close */
2168 if (unlikely(!netif_running(dev))) {
2169 RTL_W16 (IntrMask, 0);
2170 goto out;
2171 }
2172
2173 /* Acknowledge all of the current interrupt sources ASAP, but
2174 an first get an additional status bit from CSCR. */
2175 if (unlikely(status & RxUnderrun))
2176 link_changed = RTL_R16 (CSCR) & CSCR_LinkChangeBit;
2177
2178 ackstat = status & ~(RxAckBits | TxErr);
2179 if (ackstat)
2180 RTL_W16 (IntrStatus, ackstat);
2181
2182 /* Receive packets are processed by poll routine.
2183 If not running start it now. */
2184 if (status & RxAckBits){
2185 if (netif_rx_schedule_prep(dev, &tp->napi)) {
2186 RTL_W16_F (IntrMask, rtl8139_norx_intr_mask);
2187 __netif_rx_schedule(dev, &tp->napi);
2188 }
2189 }
2190
2191 /* Check uncommon events with one test. */
2192 if (unlikely(status & (PCIErr | PCSTimeout | RxUnderrun | RxErr)))
2193 rtl8139_weird_interrupt (dev, tp, ioaddr,
2194 status, link_changed);
2195
2196 if (status & (TxOK | TxErr)) {
2197 rtl8139_tx_interrupt (dev, tp, ioaddr);
2198 if (status & TxErr)
2199 RTL_W16 (IntrStatus, TxErr);
2200 }
2201 out:
2202 spin_unlock (&tp->lock);
2203
2204 DPRINTK ("%s: exiting interrupt, intr_status=%#4.4x.\n",
2205 dev->name, RTL_R16 (IntrStatus));
2206 return IRQ_RETVAL(handled);
2207 }
2208
2209 #ifdef CONFIG_NET_POLL_CONTROLLER
2210 /*
2211 * Polling receive - used by netconsole and other diagnostic tools
2212 * to allow network i/o with interrupts disabled.
2213 */
2214 static void rtl8139_poll_controller(struct net_device *dev)
2215 {
2216 disable_irq(dev->irq);
2217 rtl8139_interrupt(dev->irq, dev);
2218 enable_irq(dev->irq);
2219 }
2220 #endif
2221
2222 static int rtl8139_close (struct net_device *dev)
2223 {
2224 struct rtl8139_private *tp = netdev_priv(dev);
2225 void __iomem *ioaddr = tp->mmio_addr;
2226 unsigned long flags;
2227
2228 netif_stop_queue(dev);
2229 napi_disable(&tp->napi);
2230
2231 if (netif_msg_ifdown(tp))
2232 printk(KERN_DEBUG "%s: Shutting down ethercard, status was 0x%4.4x.\n",
2233 dev->name, RTL_R16 (IntrStatus));
2234
2235 spin_lock_irqsave (&tp->lock, flags);
2236
2237 /* Stop the chip's Tx and Rx DMA processes. */
2238 RTL_W8 (ChipCmd, 0);
2239
2240 /* Disable interrupts by clearing the interrupt mask. */
2241 RTL_W16 (IntrMask, 0);
2242
2243 /* Update the error counts. */
2244 dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2245 RTL_W32 (RxMissed, 0);
2246
2247 spin_unlock_irqrestore (&tp->lock, flags);
2248
2249 free_irq (dev->irq, dev);
2250
2251 rtl8139_tx_clear (tp);
2252
2253 dma_free_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN,
2254 tp->rx_ring, tp->rx_ring_dma);
2255 dma_free_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN,
2256 tp->tx_bufs, tp->tx_bufs_dma);
2257 tp->rx_ring = NULL;
2258 tp->tx_bufs = NULL;
2259
2260 /* Green! Put the chip in low-power mode. */
2261 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2262
2263 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
2264 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */
2265
2266 return 0;
2267 }
2268
2269
2270 /* Get the ethtool Wake-on-LAN settings. Assumes that wol points to
2271 kernel memory, *wol has been initialized as {ETHTOOL_GWOL}, and
2272 other threads or interrupts aren't messing with the 8139. */
2273 static void rtl8139_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2274 {
2275 struct rtl8139_private *np = netdev_priv(dev);
2276 void __iomem *ioaddr = np->mmio_addr;
2277
2278 spin_lock_irq(&np->lock);
2279 if (rtl_chip_info[np->chipset].flags & HasLWake) {
2280 u8 cfg3 = RTL_R8 (Config3);
2281 u8 cfg5 = RTL_R8 (Config5);
2282
2283 wol->supported = WAKE_PHY | WAKE_MAGIC
2284 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST;
2285
2286 wol->wolopts = 0;
2287 if (cfg3 & Cfg3_LinkUp)
2288 wol->wolopts |= WAKE_PHY;
2289 if (cfg3 & Cfg3_Magic)
2290 wol->wolopts |= WAKE_MAGIC;
2291 /* (KON)FIXME: See how netdev_set_wol() handles the
2292 following constants. */
2293 if (cfg5 & Cfg5_UWF)
2294 wol->wolopts |= WAKE_UCAST;
2295 if (cfg5 & Cfg5_MWF)
2296 wol->wolopts |= WAKE_MCAST;
2297 if (cfg5 & Cfg5_BWF)
2298 wol->wolopts |= WAKE_BCAST;
2299 }
2300 spin_unlock_irq(&np->lock);
2301 }
2302
2303
2304 /* Set the ethtool Wake-on-LAN settings. Return 0 or -errno. Assumes
2305 that wol points to kernel memory and other threads or interrupts
2306 aren't messing with the 8139. */
2307 static int rtl8139_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2308 {
2309 struct rtl8139_private *np = netdev_priv(dev);
2310 void __iomem *ioaddr = np->mmio_addr;
2311 u32 support;
2312 u8 cfg3, cfg5;
2313
2314 support = ((rtl_chip_info[np->chipset].flags & HasLWake)
2315 ? (WAKE_PHY | WAKE_MAGIC
2316 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST)
2317 : 0);
2318 if (wol->wolopts & ~support)
2319 return -EINVAL;
2320
2321 spin_lock_irq(&np->lock);
2322 cfg3 = RTL_R8 (Config3) & ~(Cfg3_LinkUp | Cfg3_Magic);
2323 if (wol->wolopts & WAKE_PHY)
2324 cfg3 |= Cfg3_LinkUp;
2325 if (wol->wolopts & WAKE_MAGIC)
2326 cfg3 |= Cfg3_Magic;
2327 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2328 RTL_W8 (Config3, cfg3);
2329 RTL_W8 (Cfg9346, Cfg9346_Lock);
2330
2331 cfg5 = RTL_R8 (Config5) & ~(Cfg5_UWF | Cfg5_MWF | Cfg5_BWF);
2332 /* (KON)FIXME: These are untested. We may have to set the
2333 CRC0, Wakeup0 and LSBCRC0 registers too, but I have no
2334 documentation. */
2335 if (wol->wolopts & WAKE_UCAST)
2336 cfg5 |= Cfg5_UWF;
2337 if (wol->wolopts & WAKE_MCAST)
2338 cfg5 |= Cfg5_MWF;
2339 if (wol->wolopts & WAKE_BCAST)
2340 cfg5 |= Cfg5_BWF;
2341 RTL_W8 (Config5, cfg5); /* need not unlock via Cfg9346 */
2342 spin_unlock_irq(&np->lock);
2343
2344 return 0;
2345 }
2346
2347 static void rtl8139_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2348 {
2349 struct rtl8139_private *np = netdev_priv(dev);
2350 strcpy(info->driver, DRV_NAME);
2351 strcpy(info->version, DRV_VERSION);
2352 strcpy(info->bus_info, pci_name(np->pci_dev));
2353 info->regdump_len = np->regs_len;
2354 }
2355
2356 static int rtl8139_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2357 {
2358 struct rtl8139_private *np = netdev_priv(dev);
2359 spin_lock_irq(&np->lock);
2360 mii_ethtool_gset(&np->mii, cmd);
2361 spin_unlock_irq(&np->lock);
2362 return 0;
2363 }
2364
2365 static int rtl8139_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2366 {
2367 struct rtl8139_private *np = netdev_priv(dev);
2368 int rc;
2369 spin_lock_irq(&np->lock);
2370 rc = mii_ethtool_sset(&np->mii, cmd);
2371 spin_unlock_irq(&np->lock);
2372 return rc;
2373 }
2374
2375 static int rtl8139_nway_reset(struct net_device *dev)
2376 {
2377 struct rtl8139_private *np = netdev_priv(dev);
2378 return mii_nway_restart(&np->mii);
2379 }
2380
2381 static u32 rtl8139_get_link(struct net_device *dev)
2382 {
2383 struct rtl8139_private *np = netdev_priv(dev);
2384 return mii_link_ok(&np->mii);
2385 }
2386
2387 static u32 rtl8139_get_msglevel(struct net_device *dev)
2388 {
2389 struct rtl8139_private *np = netdev_priv(dev);
2390 return np->msg_enable;
2391 }
2392
2393 static void rtl8139_set_msglevel(struct net_device *dev, u32 datum)
2394 {
2395 struct rtl8139_private *np = netdev_priv(dev);
2396 np->msg_enable = datum;
2397 }
2398
2399 static int rtl8139_get_regs_len(struct net_device *dev)
2400 {
2401 struct rtl8139_private *np;
2402 /* TODO: we are too slack to do reg dumping for pio, for now */
2403 if (use_io)
2404 return 0;
2405 np = netdev_priv(dev);
2406 return np->regs_len;
2407 }
2408
2409 static void rtl8139_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *regbuf)
2410 {
2411 struct rtl8139_private *np;
2412
2413 /* TODO: we are too slack to do reg dumping for pio, for now */
2414 if (use_io)
2415 return;
2416 np = netdev_priv(dev);
2417
2418 regs->version = RTL_REGS_VER;
2419
2420 spin_lock_irq(&np->lock);
2421 memcpy_fromio(regbuf, np->mmio_addr, regs->len);
2422 spin_unlock_irq(&np->lock);
2423 }
2424
2425 static int rtl8139_get_sset_count(struct net_device *dev, int sset)
2426 {
2427 switch (sset) {
2428 case ETH_SS_STATS:
2429 return RTL_NUM_STATS;
2430 default:
2431 return -EOPNOTSUPP;
2432 }
2433 }
2434
2435 static void rtl8139_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data)
2436 {
2437 struct rtl8139_private *np = netdev_priv(dev);
2438
2439 data[0] = np->xstats.early_rx;
2440 data[1] = np->xstats.tx_buf_mapped;
2441 data[2] = np->xstats.tx_timeouts;
2442 data[3] = np->xstats.rx_lost_in_ring;
2443 }
2444
2445 static void rtl8139_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2446 {
2447 memcpy(data, ethtool_stats_keys, sizeof(ethtool_stats_keys));
2448 }
2449
2450 static const struct ethtool_ops rtl8139_ethtool_ops = {
2451 .get_drvinfo = rtl8139_get_drvinfo,
2452 .get_settings = rtl8139_get_settings,
2453 .set_settings = rtl8139_set_settings,
2454 .get_regs_len = rtl8139_get_regs_len,
2455 .get_regs = rtl8139_get_regs,
2456 .nway_reset = rtl8139_nway_reset,
2457 .get_link = rtl8139_get_link,
2458 .get_msglevel = rtl8139_get_msglevel,
2459 .set_msglevel = rtl8139_set_msglevel,
2460 .get_wol = rtl8139_get_wol,
2461 .set_wol = rtl8139_set_wol,
2462 .get_strings = rtl8139_get_strings,
2463 .get_sset_count = rtl8139_get_sset_count,
2464 .get_ethtool_stats = rtl8139_get_ethtool_stats,
2465 };
2466
2467 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2468 {
2469 struct rtl8139_private *np = netdev_priv(dev);
2470 int rc;
2471
2472 if (!netif_running(dev))
2473 return -EINVAL;
2474
2475 spin_lock_irq(&np->lock);
2476 rc = generic_mii_ioctl(&np->mii, if_mii(rq), cmd, NULL);
2477 spin_unlock_irq(&np->lock);
2478
2479 return rc;
2480 }
2481
2482
2483 static struct net_device_stats *rtl8139_get_stats (struct net_device *dev)
2484 {
2485 struct rtl8139_private *tp = netdev_priv(dev);
2486 void __iomem *ioaddr = tp->mmio_addr;
2487 unsigned long flags;
2488
2489 if (netif_running(dev)) {
2490 spin_lock_irqsave (&tp->lock, flags);
2491 dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2492 RTL_W32 (RxMissed, 0);
2493 spin_unlock_irqrestore (&tp->lock, flags);
2494 }
2495
2496 return &dev->stats;
2497 }
2498
2499 /* Set or clear the multicast filter for this adaptor.
2500 This routine is not state sensitive and need not be SMP locked. */
2501
2502 static void __set_rx_mode (struct net_device *dev)
2503 {
2504 struct rtl8139_private *tp = netdev_priv(dev);
2505 void __iomem *ioaddr = tp->mmio_addr;
2506 u32 mc_filter[2]; /* Multicast hash filter */
2507 int i, rx_mode;
2508 u32 tmp;
2509
2510 DPRINTK ("%s: rtl8139_set_rx_mode(%4.4x) done -- Rx config %8.8lx.\n",
2511 dev->name, dev->flags, RTL_R32 (RxConfig));
2512
2513 /* Note: do not reorder, GCC is clever about common statements. */
2514 if (dev->flags & IFF_PROMISC) {
2515 rx_mode =
2516 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
2517 AcceptAllPhys;
2518 mc_filter[1] = mc_filter[0] = 0xffffffff;
2519 } else if ((dev->mc_count > multicast_filter_limit)
2520 || (dev->flags & IFF_ALLMULTI)) {
2521 /* Too many to filter perfectly -- accept all multicasts. */
2522 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
2523 mc_filter[1] = mc_filter[0] = 0xffffffff;
2524 } else {
2525 struct dev_mc_list *mclist;
2526 rx_mode = AcceptBroadcast | AcceptMyPhys;
2527 mc_filter[1] = mc_filter[0] = 0;
2528 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2529 i++, mclist = mclist->next) {
2530 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
2531
2532 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2533 rx_mode |= AcceptMulticast;
2534 }
2535 }
2536
2537 /* We can safely update without stopping the chip. */
2538 tmp = rtl8139_rx_config | rx_mode;
2539 if (tp->rx_config != tmp) {
2540 RTL_W32_F (RxConfig, tmp);
2541 tp->rx_config = tmp;
2542 }
2543 RTL_W32_F (MAR0 + 0, mc_filter[0]);
2544 RTL_W32_F (MAR0 + 4, mc_filter[1]);
2545 }
2546
2547 static void rtl8139_set_rx_mode (struct net_device *dev)
2548 {
2549 unsigned long flags;
2550 struct rtl8139_private *tp = netdev_priv(dev);
2551
2552 spin_lock_irqsave (&tp->lock, flags);
2553 __set_rx_mode(dev);
2554 spin_unlock_irqrestore (&tp->lock, flags);
2555 }
2556
2557 #ifdef CONFIG_PM
2558
2559 static int rtl8139_suspend (struct pci_dev *pdev, pm_message_t state)
2560 {
2561 struct net_device *dev = pci_get_drvdata (pdev);
2562 struct rtl8139_private *tp = netdev_priv(dev);
2563 void __iomem *ioaddr = tp->mmio_addr;
2564 unsigned long flags;
2565
2566 pci_save_state (pdev);
2567
2568 if (!netif_running (dev))
2569 return 0;
2570
2571 netif_device_detach (dev);
2572
2573 spin_lock_irqsave (&tp->lock, flags);
2574
2575 /* Disable interrupts, stop Tx and Rx. */
2576 RTL_W16 (IntrMask, 0);
2577 RTL_W8 (ChipCmd, 0);
2578
2579 /* Update the error counts. */
2580 dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2581 RTL_W32 (RxMissed, 0);
2582
2583 spin_unlock_irqrestore (&tp->lock, flags);
2584
2585 pci_set_power_state (pdev, PCI_D3hot);
2586
2587 return 0;
2588 }
2589
2590
2591 static int rtl8139_resume (struct pci_dev *pdev)
2592 {
2593 struct net_device *dev = pci_get_drvdata (pdev);
2594
2595 pci_restore_state (pdev);
2596 if (!netif_running (dev))
2597 return 0;
2598 pci_set_power_state (pdev, PCI_D0);
2599 rtl8139_init_ring (dev);
2600 rtl8139_hw_start (dev);
2601 netif_device_attach (dev);
2602 return 0;
2603 }
2604
2605 #endif /* CONFIG_PM */
2606
2607
2608 static struct pci_driver rtl8139_pci_driver = {
2609 .name = DRV_NAME,
2610 .id_table = rtl8139_pci_tbl,
2611 .probe = rtl8139_init_one,
2612 .remove = __devexit_p(rtl8139_remove_one),
2613 #ifdef CONFIG_PM
2614 .suspend = rtl8139_suspend,
2615 .resume = rtl8139_resume,
2616 #endif /* CONFIG_PM */
2617 };
2618
2619
2620 static int __init rtl8139_init_module (void)
2621 {
2622 /* when we're a module, we always print a version message,
2623 * even if no 8139 board is found.
2624 */
2625 #ifdef MODULE
2626 printk (KERN_INFO RTL8139_DRIVER_NAME "\n");
2627 #endif
2628
2629 return pci_register_driver(&rtl8139_pci_driver);
2630 }
2631
2632
2633 static void __exit rtl8139_cleanup_module (void)
2634 {
2635 pci_unregister_driver (&rtl8139_pci_driver);
2636 }
2637
2638
2639 module_init(rtl8139_init_module);
2640 module_exit(rtl8139_cleanup_module);
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