2 * Copyright (C) 2001 Allan Trautman, IBM Corporation
4 * iSeries specific routines for PCI.
6 * Based on code from pci.c and iSeries_pci.c 32bit
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 #include <linux/kernel.h>
23 #include <linux/list.h>
24 #include <linux/string.h>
25 #include <linux/init.h>
26 #include <linux/module.h>
27 #include <linux/ide.h>
28 #include <linux/pci.h>
33 #include <asm/machdep.h>
34 #include <asm/pci-bridge.h>
35 #include <asm/ppcdebug.h>
36 #include <asm/iommu.h>
37 #include <asm/abs_addr.h>
39 #include <asm/iSeries/HvCallPci.h>
40 #include <asm/iSeries/HvCallXm.h>
41 #include <asm/iSeries/mf.h>
43 #include <asm/ppc-pci.h>
48 extern unsigned long io_page_mask
;
51 * Forward declares of prototypes.
53 static struct device_node
*find_Device_Node(int bus
, int devfn
);
54 static void scan_PHB_slots(struct pci_controller
*Phb
);
55 static void scan_EADS_bridge(HvBusNumber Bus
, HvSubBusNumber SubBus
, int IdSel
);
56 static int scan_bridge_slot(HvBusNumber Bus
, struct HvCallPci_BridgeInfo
*Info
);
58 LIST_HEAD(iSeries_Global_Device_List
);
60 static int DeviceCount
;
62 /* Counters and control flags. */
63 static long Pci_Io_Read_Count
;
64 static long Pci_Io_Write_Count
;
66 static long Pci_Cfg_Read_Count
;
67 static long Pci_Cfg_Write_Count
;
69 static long Pci_Error_Count
;
71 static int Pci_Retry_Max
= 3; /* Only retry 3 times */
72 static int Pci_Error_Flag
= 1; /* Set Retry Error on. */
74 static struct pci_ops iSeries_pci_ops
;
78 * Each Entry size is 4 MB * 1024 Entries = 4GB I/O address space.
80 #define IOMM_TABLE_MAX_ENTRIES 1024
81 #define IOMM_TABLE_ENTRY_SIZE 0x0000000000400000UL
82 #define BASE_IO_MEMORY 0xE000000000000000UL
84 static unsigned long max_io_memory
= 0xE000000000000000UL
;
85 static long current_iomm_table_entry
;
90 static struct device_node
**iomm_table
;
91 static u8
*iobar_table
;
94 * Static and Global variables
96 static char *pci_io_text
= "iSeries PCI I/O";
97 static DEFINE_SPINLOCK(iomm_table_lock
);
100 * iomm_table_initialize
102 * Allocates and initalizes the Address Translation Table and Bar
103 * Tables to get them ready for use. Must be called before any
104 * I/O space is handed out to the device BARs.
106 static void iomm_table_initialize(void)
108 spin_lock(&iomm_table_lock
);
109 iomm_table
= kmalloc(sizeof(*iomm_table
) * IOMM_TABLE_MAX_ENTRIES
,
111 iobar_table
= kmalloc(sizeof(*iobar_table
) * IOMM_TABLE_MAX_ENTRIES
,
113 spin_unlock(&iomm_table_lock
);
114 if ((iomm_table
== NULL
) || (iobar_table
== NULL
))
115 panic("PCI: I/O tables allocation failed.\n");
119 * iomm_table_allocate_entry
121 * Adds pci_dev entry in address translation table
123 * - Allocates the number of entries required in table base on BAR
125 * - Allocates starting at BASE_IO_MEMORY and increases.
126 * - The size is round up to be a multiple of entry size.
127 * - CurrentIndex is incremented to keep track of the last entry.
128 * - Builds the resource entry for allocated BARs.
130 static void iomm_table_allocate_entry(struct pci_dev
*dev
, int bar_num
)
132 struct resource
*bar_res
= &dev
->resource
[bar_num
];
133 long bar_size
= pci_resource_len(dev
, bar_num
);
136 * No space to allocate, quick exit, skip Allocation.
141 * Set Resource values.
143 spin_lock(&iomm_table_lock
);
144 bar_res
->name
= pci_io_text
;
146 IOMM_TABLE_ENTRY_SIZE
* current_iomm_table_entry
;
147 bar_res
->start
+= BASE_IO_MEMORY
;
148 bar_res
->end
= bar_res
->start
+ bar_size
- 1;
150 * Allocate the number of table entries needed for BAR.
152 while (bar_size
> 0 ) {
153 iomm_table
[current_iomm_table_entry
] = dev
->sysdata
;
154 iobar_table
[current_iomm_table_entry
] = bar_num
;
155 bar_size
-= IOMM_TABLE_ENTRY_SIZE
;
156 ++current_iomm_table_entry
;
158 max_io_memory
= BASE_IO_MEMORY
+
159 (IOMM_TABLE_ENTRY_SIZE
* current_iomm_table_entry
);
160 spin_unlock(&iomm_table_lock
);
164 * allocate_device_bars
166 * - Allocates ALL pci_dev BAR's and updates the resources with the
167 * BAR value. BARS with zero length will have the resources
168 * The HvCallPci_getBarParms is used to get the size of the BAR
169 * space. It calls iomm_table_allocate_entry to allocate
171 * - Loops through The Bar resources(0 - 5) including the ROM
174 static void allocate_device_bars(struct pci_dev
*dev
)
176 struct resource
*bar_res
;
179 for (bar_num
= 0; bar_num
<= PCI_ROM_RESOURCE
; ++bar_num
) {
180 bar_res
= &dev
->resource
[bar_num
];
181 iomm_table_allocate_entry(dev
, bar_num
);
186 * Log error information to system console.
187 * Filter out the device not there errors.
188 * PCI: EADs Connect Failed 0x18.58.10 Rc: 0x00xx
189 * PCI: Read Vendor Failed 0x18.58.10 Rc: 0x00xx
190 * PCI: Connect Bus Unit Failed 0x18.58.10 Rc: 0x00xx
192 static void pci_Log_Error(char *Error_Text
, int Bus
, int SubBus
,
193 int AgentId
, int HvRc
)
197 printk(KERN_ERR
"PCI: %s Failed: 0x%02X.%02X.%02X Rc: 0x%04X",
198 Error_Text
, Bus
, SubBus
, AgentId
, HvRc
);
202 * build_device_node(u16 Bus, int SubBus, u8 DevFn)
204 static struct device_node
*build_device_node(HvBusNumber Bus
,
205 HvSubBusNumber SubBus
, int AgentId
, int Function
)
207 struct device_node
*node
;
210 PPCDBG(PPCDBG_BUSWALK
,
211 "-build_device_node 0x%02X.%02X.%02X Function: %02X\n",
212 Bus
, SubBus
, AgentId
, Function
);
214 node
= kmalloc(sizeof(struct device_node
), GFP_KERNEL
);
217 memset(node
, 0, sizeof(struct device_node
));
218 pdn
= kzalloc(sizeof(*pdn
), GFP_KERNEL
);
225 list_add_tail(&pdn
->Device_List
, &iSeries_Global_Device_List
);
227 pdn
->bussubno
= SubBus
;
228 pdn
->devfn
= PCI_DEVFN(ISERIES_ENCODE_DEVICE(AgentId
), Function
);
233 * unsigned long __init find_and_init_phbs(void)
236 * This function checks for all possible system PCI host bridges that connect
237 * PCI buses. The system hypervisor is queried as to the guest partition
238 * ownership status. A pci_controller is built for any bus which is partially
239 * owned or fully owned by this guest partition.
241 unsigned long __init
find_and_init_phbs(void)
243 struct pci_controller
*phb
;
246 PPCDBG(PPCDBG_BUSWALK
, "find_and_init_phbs Entry\n");
248 /* Check all possible buses. */
249 for (bus
= 0; bus
< 256; bus
++) {
250 int ret
= HvCallXm_testBus(bus
);
252 printk("bus %d appears to exist\n", bus
);
254 phb
= (struct pci_controller
*)kmalloc(sizeof(struct pci_controller
), GFP_KERNEL
);
257 pci_setup_pci_controller(phb
);
259 phb
->pci_mem_offset
= phb
->local_number
= bus
;
260 phb
->first_busno
= bus
;
261 phb
->last_busno
= bus
;
262 phb
->ops
= &iSeries_pci_ops
;
264 PPCDBG(PPCDBG_BUSWALK
, "PCI:Create iSeries pci_controller(%p), Bus: %04X\n",
267 /* Find and connect the devices. */
271 * Check for Unexpected Return code, a clue that something
274 else if (ret
!= 0x0301)
275 printk(KERN_ERR
"Unexpected Return on Probe(0x%04X): 0x%04X",
282 * iSeries_pcibios_init
284 * Chance to initialize and structures or variable before PCI Bus walk.
286 void iSeries_pcibios_init(void)
288 PPCDBG(PPCDBG_BUSWALK
, "iSeries_pcibios_init Entry.\n");
289 iomm_table_initialize();
290 find_and_init_phbs();
292 PPCDBG(PPCDBG_BUSWALK
, "iSeries_pcibios_init Exit.\n");
296 * iSeries_pci_final_fixup(void)
298 void __init
iSeries_pci_final_fixup(void)
300 struct pci_dev
*pdev
= NULL
;
301 struct device_node
*node
;
304 PPCDBG(PPCDBG_BUSWALK
, "iSeries_pcibios_fixup Entry.\n");
306 /* Fix up at the device node and pci_dev relationship */
307 mf_display_src(0xC9000100);
309 printk("pcibios_final_fixup\n");
310 for_each_pci_dev(pdev
) {
311 node
= find_Device_Node(pdev
->bus
->number
, pdev
->devfn
);
312 printk("pci dev %p (%x.%x), node %p\n", pdev
,
313 pdev
->bus
->number
, pdev
->devfn
, node
);
317 pdev
->sysdata
= (void *)node
;
318 PCI_DN(node
)->pcidev
= pdev
;
319 PPCDBG(PPCDBG_BUSWALK
,
320 "pdev 0x%p <==> DevNode 0x%p\n",
322 allocate_device_bars(pdev
);
323 iSeries_Device_Information(pdev
, DeviceCount
);
324 iommu_devnode_init_iSeries(node
);
326 printk("PCI: Device Tree not found for 0x%016lX\n",
327 (unsigned long)pdev
);
328 pdev
->irq
= PCI_DN(node
)->Irq
;
330 iSeries_activate_IRQs();
331 mf_display_src(0xC9000200);
334 void pcibios_fixup_bus(struct pci_bus
*PciBus
)
336 PPCDBG(PPCDBG_BUSWALK
, "iSeries_pcibios_fixup_bus(0x%04X) Entry.\n",
340 void pcibios_fixup_resources(struct pci_dev
*pdev
)
342 PPCDBG(PPCDBG_BUSWALK
, "fixup_resources pdev %p\n", pdev
);
346 * Loop through each node function to find usable EADs bridges.
348 static void scan_PHB_slots(struct pci_controller
*Phb
)
350 struct HvCallPci_DeviceInfo
*DevInfo
;
351 HvBusNumber bus
= Phb
->local_number
; /* System Bus */
352 const HvSubBusNumber SubBus
= 0; /* EADs is always 0. */
355 const int MaxAgents
= 8;
357 DevInfo
= (struct HvCallPci_DeviceInfo
*)
358 kmalloc(sizeof(struct HvCallPci_DeviceInfo
), GFP_KERNEL
);
363 * Probe for EADs Bridges
365 for (IdSel
= 1; IdSel
< MaxAgents
; ++IdSel
) {
366 HvRc
= HvCallPci_getDeviceInfo(bus
, SubBus
, IdSel
,
367 iseries_hv_addr(DevInfo
),
368 sizeof(struct HvCallPci_DeviceInfo
));
370 if (DevInfo
->deviceType
== HvCallPci_NodeDevice
)
371 scan_EADS_bridge(bus
, SubBus
, IdSel
);
373 printk("PCI: Invalid System Configuration(0x%02X)"
374 " for bus 0x%02x id 0x%02x.\n",
375 DevInfo
->deviceType
, bus
, IdSel
);
378 pci_Log_Error("getDeviceInfo", bus
, SubBus
, IdSel
, HvRc
);
383 static void scan_EADS_bridge(HvBusNumber bus
, HvSubBusNumber SubBus
,
386 struct HvCallPci_BridgeInfo
*BridgeInfo
;
391 BridgeInfo
= (struct HvCallPci_BridgeInfo
*)
392 kmalloc(sizeof(struct HvCallPci_BridgeInfo
), GFP_KERNEL
);
393 if (BridgeInfo
== NULL
)
396 /* Note: hvSubBus and irq is always be 0 at this level! */
397 for (Function
= 0; Function
< 8; ++Function
) {
398 AgentId
= ISERIES_PCI_AGENTID(IdSel
, Function
);
399 HvRc
= HvCallXm_connectBusUnit(bus
, SubBus
, AgentId
, 0);
401 printk("found device at bus %d idsel %d func %d (AgentId %x)\n",
402 bus
, IdSel
, Function
, AgentId
);
403 /* Connect EADs: 0x18.00.12 = 0x00 */
404 PPCDBG(PPCDBG_BUSWALK
,
405 "PCI:Connect EADs: 0x%02X.%02X.%02X\n",
406 bus
, SubBus
, AgentId
);
407 HvRc
= HvCallPci_getBusUnitInfo(bus
, SubBus
, AgentId
,
408 iseries_hv_addr(BridgeInfo
),
409 sizeof(struct HvCallPci_BridgeInfo
));
411 printk("bridge info: type %x subbus %x maxAgents %x maxsubbus %x logslot %x\n",
412 BridgeInfo
->busUnitInfo
.deviceType
,
413 BridgeInfo
->subBusNumber
,
414 BridgeInfo
->maxAgents
,
415 BridgeInfo
->maxSubBusNumber
,
416 BridgeInfo
->logicalSlotNumber
);
417 PPCDBG(PPCDBG_BUSWALK
,
418 "PCI: BridgeInfo, Type:0x%02X, SubBus:0x%02X, MaxAgents:0x%02X, MaxSubBus: 0x%02X, LSlot: 0x%02X\n",
419 BridgeInfo
->busUnitInfo
.deviceType
,
420 BridgeInfo
->subBusNumber
,
421 BridgeInfo
->maxAgents
,
422 BridgeInfo
->maxSubBusNumber
,
423 BridgeInfo
->logicalSlotNumber
);
425 if (BridgeInfo
->busUnitInfo
.deviceType
==
426 HvCallPci_BridgeDevice
) {
427 /* Scan_Bridge_Slot...: 0x18.00.12 */
428 scan_bridge_slot(bus
, BridgeInfo
);
430 printk("PCI: Invalid Bridge Configuration(0x%02X)",
431 BridgeInfo
->busUnitInfo
.deviceType
);
433 } else if (HvRc
!= 0x000B)
434 pci_Log_Error("EADs Connect",
435 bus
, SubBus
, AgentId
, HvRc
);
441 * This assumes that the node slot is always on the primary bus!
443 static int scan_bridge_slot(HvBusNumber Bus
,
444 struct HvCallPci_BridgeInfo
*BridgeInfo
)
446 struct device_node
*node
;
447 HvSubBusNumber SubBus
= BridgeInfo
->subBusNumber
;
451 int IdSel
= ISERIES_GET_DEVICE_FROM_SUBBUS(SubBus
);
452 int Function
= ISERIES_GET_FUNCTION_FROM_SUBBUS(SubBus
);
453 HvAgentId EADsIdSel
= ISERIES_PCI_AGENTID(IdSel
, Function
);
455 /* iSeries_allocate_IRQ.: 0x18.00.12(0xA3) */
456 Irq
= iSeries_allocate_IRQ(Bus
, 0, EADsIdSel
);
457 PPCDBG(PPCDBG_BUSWALK
,
458 "PCI:- allocate and assign IRQ 0x%02X.%02X.%02X = 0x%02X\n",
459 Bus
, 0, EADsIdSel
, Irq
);
462 * Connect all functions of any device found.
464 for (IdSel
= 1; IdSel
<= BridgeInfo
->maxAgents
; ++IdSel
) {
465 for (Function
= 0; Function
< 8; ++Function
) {
466 HvAgentId AgentId
= ISERIES_PCI_AGENTID(IdSel
, Function
);
467 HvRc
= HvCallXm_connectBusUnit(Bus
, SubBus
,
470 pci_Log_Error("Connect Bus Unit",
471 Bus
, SubBus
, AgentId
, HvRc
);
475 HvRc
= HvCallPci_configLoad16(Bus
, SubBus
, AgentId
,
476 PCI_VENDOR_ID
, &VendorId
);
478 pci_Log_Error("Read Vendor",
479 Bus
, SubBus
, AgentId
, HvRc
);
482 printk("read vendor ID: %x\n", VendorId
);
484 /* FoundDevice: 0x18.28.10 = 0x12AE */
485 PPCDBG(PPCDBG_BUSWALK
,
486 "PCI:- FoundDevice: 0x%02X.%02X.%02X = 0x%04X, irq %d\n",
487 Bus
, SubBus
, AgentId
, VendorId
, Irq
);
488 HvRc
= HvCallPci_configStore8(Bus
, SubBus
, AgentId
,
489 PCI_INTERRUPT_LINE
, Irq
);
491 pci_Log_Error("PciCfgStore Irq Failed!",
492 Bus
, SubBus
, AgentId
, HvRc
);
495 node
= build_device_node(Bus
, SubBus
, EADsIdSel
, Function
);
496 PCI_DN(node
)->Irq
= Irq
;
497 PCI_DN(node
)->LogicalSlot
= BridgeInfo
->logicalSlotNumber
;
499 } /* for (Function = 0; Function < 8; ++Function) */
500 } /* for (IdSel = 1; IdSel <= MaxAgents; ++IdSel) */
505 * I/0 Memory copy MUST use mmio commands on iSeries
506 * To do; For performance, include the hv call directly
508 void iSeries_memset_io(volatile void __iomem
*dest
, char c
, size_t Count
)
511 long NumberOfBytes
= Count
;
513 while (NumberOfBytes
> 0) {
514 iSeries_Write_Byte(ByteValue
, dest
++);
518 EXPORT_SYMBOL(iSeries_memset_io
);
520 void iSeries_memcpy_toio(volatile void __iomem
*dest
, void *source
, size_t count
)
523 long NumberOfBytes
= count
;
525 while (NumberOfBytes
> 0) {
526 iSeries_Write_Byte(*src
++, dest
++);
530 EXPORT_SYMBOL(iSeries_memcpy_toio
);
532 void iSeries_memcpy_fromio(void *dest
, const volatile void __iomem
*src
, size_t count
)
535 long NumberOfBytes
= count
;
537 while (NumberOfBytes
> 0) {
538 *dst
++ = iSeries_Read_Byte(src
++);
542 EXPORT_SYMBOL(iSeries_memcpy_fromio
);
545 * Look down the chain to find the matching Device Device
547 static struct device_node
*find_Device_Node(int bus
, int devfn
)
551 list_for_each_entry(pdn
, &iSeries_Global_Device_List
, Device_List
) {
552 if ((bus
== pdn
->busno
) && (devfn
== pdn
->devfn
))
560 * Returns the device node for the passed pci_dev
561 * Sanity Check Node PciDev to passed pci_dev
562 * If none is found, returns a NULL which the client must handle.
564 static struct device_node
*get_Device_Node(struct pci_dev
*pdev
)
566 struct device_node
*node
;
568 node
= pdev
->sysdata
;
569 if (node
== NULL
|| PCI_DN(node
)->pcidev
!= pdev
)
570 node
= find_Device_Node(pdev
->bus
->number
, pdev
->devfn
);
576 * Config space read and write functions.
577 * For now at least, we look for the device node for the bus and devfn
578 * that we are asked to access. It may be possible to translate the devfn
579 * to a subbus and deviceid more directly.
581 static u64 hv_cfg_read_func
[4] = {
582 HvCallPciConfigLoad8
, HvCallPciConfigLoad16
,
583 HvCallPciConfigLoad32
, HvCallPciConfigLoad32
586 static u64 hv_cfg_write_func
[4] = {
587 HvCallPciConfigStore8
, HvCallPciConfigStore16
,
588 HvCallPciConfigStore32
, HvCallPciConfigStore32
592 * Read PCI config space
594 static int iSeries_pci_read_config(struct pci_bus
*bus
, unsigned int devfn
,
595 int offset
, int size
, u32
*val
)
597 struct device_node
*node
= find_Device_Node(bus
->number
, devfn
);
599 struct HvCallPci_LoadReturn ret
;
602 return PCIBIOS_DEVICE_NOT_FOUND
;
605 return PCIBIOS_BAD_REGISTER_NUMBER
;
608 fn
= hv_cfg_read_func
[(size
- 1) & 3];
609 HvCall3Ret16(fn
, &ret
, iseries_ds_addr(node
), offset
, 0);
613 return PCIBIOS_DEVICE_NOT_FOUND
; /* or something */
621 * Write PCI config space
624 static int iSeries_pci_write_config(struct pci_bus
*bus
, unsigned int devfn
,
625 int offset
, int size
, u32 val
)
627 struct device_node
*node
= find_Device_Node(bus
->number
, devfn
);
632 return PCIBIOS_DEVICE_NOT_FOUND
;
634 return PCIBIOS_BAD_REGISTER_NUMBER
;
636 fn
= hv_cfg_write_func
[(size
- 1) & 3];
637 ret
= HvCall4(fn
, iseries_ds_addr(node
), offset
, val
, 0);
640 return PCIBIOS_DEVICE_NOT_FOUND
;
645 static struct pci_ops iSeries_pci_ops
= {
646 .read
= iSeries_pci_read_config
,
647 .write
= iSeries_pci_write_config
652 * -> On Failure, print and log information.
653 * Increment Retry Count, if exceeds max, panic partition.
655 * PCI: Device 23.90 ReadL I/O Error( 0): 0x1234
656 * PCI: Device 23.90 ReadL Retry( 1)
657 * PCI: Device 23.90 ReadL Retry Successful(1)
659 static int CheckReturnCode(char *TextHdr
, struct device_node
*DevNode
,
663 struct pci_dn
*pdn
= PCI_DN(DevNode
);
667 printk("PCI: %s: Device 0x%04X:%02X I/O Error(%2d): 0x%04X\n",
668 TextHdr
, pdn
->busno
, pdn
->devfn
,
671 * Bump the retry and check for retry count exceeded.
672 * If, Exceeded, panic the system.
674 if (((*retry
) > Pci_Retry_Max
) &&
675 (Pci_Error_Flag
> 0)) {
676 mf_display_src(0xB6000103);
678 panic("PCI: Hardware I/O Error, SRC B6000103, "
679 "Automatic Reboot Disabled.\n");
681 return -1; /* Retry Try */
687 * Translate the I/O Address into a device node, bar, and bar offset.
688 * Note: Make sure the passed variable end up on the stack to avoid
689 * the exposure of being device global.
691 static inline struct device_node
*xlate_iomm_address(
692 const volatile void __iomem
*IoAddress
,
693 u64
*dsaptr
, u64
*BarOffsetPtr
)
695 unsigned long OrigIoAddr
;
696 unsigned long BaseIoAddr
;
697 unsigned long TableIndex
;
698 struct device_node
*DevNode
;
700 OrigIoAddr
= (unsigned long __force
)IoAddress
;
701 if ((OrigIoAddr
< BASE_IO_MEMORY
) || (OrigIoAddr
>= max_io_memory
))
703 BaseIoAddr
= OrigIoAddr
- BASE_IO_MEMORY
;
704 TableIndex
= BaseIoAddr
/ IOMM_TABLE_ENTRY_SIZE
;
705 DevNode
= iomm_table
[TableIndex
];
707 if (DevNode
!= NULL
) {
708 int barnum
= iobar_table
[TableIndex
];
709 *dsaptr
= iseries_ds_addr(DevNode
) | (barnum
<< 24);
710 *BarOffsetPtr
= BaseIoAddr
% IOMM_TABLE_ENTRY_SIZE
;
712 panic("PCI: Invalid PCI IoAddress detected!\n");
717 * Read MM I/O Instructions for the iSeries
718 * On MM I/O error, all ones are returned and iSeries_pci_IoError is cal
719 * else, data is returned in big Endian format.
721 * iSeries_Read_Byte = Read Byte ( 8 bit)
722 * iSeries_Read_Word = Read Word (16 bit)
723 * iSeries_Read_Long = Read Long (32 bit)
725 u8
iSeries_Read_Byte(const volatile void __iomem
*IoAddress
)
730 struct HvCallPci_LoadReturn ret
;
731 struct device_node
*DevNode
=
732 xlate_iomm_address(IoAddress
, &dsa
, &BarOffset
);
734 if (DevNode
== NULL
) {
735 static unsigned long last_jiffies
;
736 static int num_printed
;
738 if ((jiffies
- last_jiffies
) > 60 * HZ
) {
739 last_jiffies
= jiffies
;
742 if (num_printed
++ < 10)
743 printk(KERN_ERR
"iSeries_Read_Byte: invalid access at IO address %p\n", IoAddress
);
748 HvCall3Ret16(HvCallPciBarLoad8
, &ret
, dsa
, BarOffset
, 0);
749 } while (CheckReturnCode("RDB", DevNode
, &retry
, ret
.rc
) != 0);
751 return (u8
)ret
.value
;
753 EXPORT_SYMBOL(iSeries_Read_Byte
);
755 u16
iSeries_Read_Word(const volatile void __iomem
*IoAddress
)
760 struct HvCallPci_LoadReturn ret
;
761 struct device_node
*DevNode
=
762 xlate_iomm_address(IoAddress
, &dsa
, &BarOffset
);
764 if (DevNode
== NULL
) {
765 static unsigned long last_jiffies
;
766 static int num_printed
;
768 if ((jiffies
- last_jiffies
) > 60 * HZ
) {
769 last_jiffies
= jiffies
;
772 if (num_printed
++ < 10)
773 printk(KERN_ERR
"iSeries_Read_Word: invalid access at IO address %p\n", IoAddress
);
778 HvCall3Ret16(HvCallPciBarLoad16
, &ret
, dsa
,
780 } while (CheckReturnCode("RDW", DevNode
, &retry
, ret
.rc
) != 0);
782 return swab16((u16
)ret
.value
);
784 EXPORT_SYMBOL(iSeries_Read_Word
);
786 u32
iSeries_Read_Long(const volatile void __iomem
*IoAddress
)
791 struct HvCallPci_LoadReturn ret
;
792 struct device_node
*DevNode
=
793 xlate_iomm_address(IoAddress
, &dsa
, &BarOffset
);
795 if (DevNode
== NULL
) {
796 static unsigned long last_jiffies
;
797 static int num_printed
;
799 if ((jiffies
- last_jiffies
) > 60 * HZ
) {
800 last_jiffies
= jiffies
;
803 if (num_printed
++ < 10)
804 printk(KERN_ERR
"iSeries_Read_Long: invalid access at IO address %p\n", IoAddress
);
809 HvCall3Ret16(HvCallPciBarLoad32
, &ret
, dsa
,
811 } while (CheckReturnCode("RDL", DevNode
, &retry
, ret
.rc
) != 0);
813 return swab32((u32
)ret
.value
);
815 EXPORT_SYMBOL(iSeries_Read_Long
);
818 * Write MM I/O Instructions for the iSeries
820 * iSeries_Write_Byte = Write Byte (8 bit)
821 * iSeries_Write_Word = Write Word(16 bit)
822 * iSeries_Write_Long = Write Long(32 bit)
824 void iSeries_Write_Byte(u8 data
, volatile void __iomem
*IoAddress
)
830 struct device_node
*DevNode
=
831 xlate_iomm_address(IoAddress
, &dsa
, &BarOffset
);
833 if (DevNode
== NULL
) {
834 static unsigned long last_jiffies
;
835 static int num_printed
;
837 if ((jiffies
- last_jiffies
) > 60 * HZ
) {
838 last_jiffies
= jiffies
;
841 if (num_printed
++ < 10)
842 printk(KERN_ERR
"iSeries_Write_Byte: invalid access at IO address %p\n", IoAddress
);
846 ++Pci_Io_Write_Count
;
847 rc
= HvCall4(HvCallPciBarStore8
, dsa
, BarOffset
, data
, 0);
848 } while (CheckReturnCode("WWB", DevNode
, &retry
, rc
) != 0);
850 EXPORT_SYMBOL(iSeries_Write_Byte
);
852 void iSeries_Write_Word(u16 data
, volatile void __iomem
*IoAddress
)
858 struct device_node
*DevNode
=
859 xlate_iomm_address(IoAddress
, &dsa
, &BarOffset
);
861 if (DevNode
== NULL
) {
862 static unsigned long last_jiffies
;
863 static int num_printed
;
865 if ((jiffies
- last_jiffies
) > 60 * HZ
) {
866 last_jiffies
= jiffies
;
869 if (num_printed
++ < 10)
870 printk(KERN_ERR
"iSeries_Write_Word: invalid access at IO address %p\n", IoAddress
);
874 ++Pci_Io_Write_Count
;
875 rc
= HvCall4(HvCallPciBarStore16
, dsa
, BarOffset
, swab16(data
), 0);
876 } while (CheckReturnCode("WWW", DevNode
, &retry
, rc
) != 0);
878 EXPORT_SYMBOL(iSeries_Write_Word
);
880 void iSeries_Write_Long(u32 data
, volatile void __iomem
*IoAddress
)
886 struct device_node
*DevNode
=
887 xlate_iomm_address(IoAddress
, &dsa
, &BarOffset
);
889 if (DevNode
== NULL
) {
890 static unsigned long last_jiffies
;
891 static int num_printed
;
893 if ((jiffies
- last_jiffies
) > 60 * HZ
) {
894 last_jiffies
= jiffies
;
897 if (num_printed
++ < 10)
898 printk(KERN_ERR
"iSeries_Write_Long: invalid access at IO address %p\n", IoAddress
);
902 ++Pci_Io_Write_Count
;
903 rc
= HvCall4(HvCallPciBarStore32
, dsa
, BarOffset
, swab32(data
), 0);
904 } while (CheckReturnCode("WWL", DevNode
, &retry
, rc
) != 0);
906 EXPORT_SYMBOL(iSeries_Write_Long
);