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[MIPS] Kill duplicated setup_irq() for cp0 timer
[linux-2.6/verdex.git] / drivers / video / aty / radeon_base.c
blob1e32b3d13f2e7123bc86d9be742d747111f763d2
1 /*
2 * drivers/video/aty/radeon_base.c
3 *
4 * framebuffer driver for ATI Radeon chipset video boards
5 *
6 * Copyright 2003 Ben. Herrenschmidt <benh@kernel.crashing.org>
7 * Copyright 2000 Ani Joshi <ajoshi@kernel.crashing.org>
8 *
9 * i2c bits from Luca Tettamanti <kronos@kronoz.cjb.net>
10 *
11 * Special thanks to ATI DevRel team for their hardware donations.
12 *
13 * ...Insert GPL boilerplate here...
14 *
15 * Significant portions of this driver apdated from XFree86 Radeon
16 * driver which has the following copyright notice:
17 *
18 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
19 * VA Linux Systems Inc., Fremont, California.
20 *
21 * All Rights Reserved.
22 *
23 * Permission is hereby granted, free of charge, to any person obtaining
24 * a copy of this software and associated documentation files (the
25 * "Software"), to deal in the Software without restriction, including
26 * without limitation on the rights to use, copy, modify, merge,
27 * publish, distribute, sublicense, and/or sell copies of the Software,
28 * and to permit persons to whom the Software is furnished to do so,
29 * subject to the following conditions:
30 *
31 * The above copyright notice and this permission notice (including the
32 * next paragraph) shall be included in all copies or substantial
33 * portions of the Software.
34 *
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
37 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
39 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
41 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
42 * DEALINGS IN THE SOFTWARE.
43 *
44 * XFree86 driver authors:
45 *
46 * Kevin E. Martin <martin@xfree86.org>
47 * Rickard E. Faith <faith@valinux.com>
48 * Alan Hourihane <alanh@fairlite.demon.co.uk>
49 *
50 */
51
52
53 #define RADEON_VERSION "0.2.0"
54
55 #include <linux/module.h>
56 #include <linux/moduleparam.h>
57 #include <linux/kernel.h>
58 #include <linux/errno.h>
59 #include <linux/string.h>
60 #include <linux/mm.h>
61 #include <linux/slab.h>
62 #include <linux/delay.h>
63 #include <linux/time.h>
64 #include <linux/fb.h>
65 #include <linux/ioport.h>
66 #include <linux/init.h>
67 #include <linux/pci.h>
68 #include <linux/vmalloc.h>
69 #include <linux/device.h>
70
71 #include <asm/io.h>
72 #include <linux/uaccess.h>
73
74 #ifdef CONFIG_PPC_OF
75
76 #include <asm/pci-bridge.h>
77 #include "../macmodes.h"
78
79 #ifdef CONFIG_BOOTX_TEXT
80 #include <asm/btext.h>
81 #endif
82
83 #endif /* CONFIG_PPC_OF */
84
85 #ifdef CONFIG_MTRR
86 #include <asm/mtrr.h>
87 #endif
88
89 #include <video/radeon.h>
90 #include <linux/radeonfb.h>
91
92 #include "../edid.h" // MOVE THAT TO include/video
93 #include "ati_ids.h"
94 #include "radeonfb.h"
95
96 #define MAX_MAPPED_VRAM (2048*2048*4)
97 #define MIN_MAPPED_VRAM (1024*768*1)
98
99 #define CHIP_DEF(id, family, flags) \
100 { PCI_VENDOR_ID_ATI, id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (flags) | (CHIP_FAMILY_##family) }
101
102 static struct pci_device_id radeonfb_pci_table[] = {
103 /* Radeon Xpress 200m */
104 CHIP_DEF(PCI_CHIP_RS480_5955, RS480, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
105 CHIP_DEF(PCI_CHIP_RS482_5975, RS480, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
106 /* Mobility M6 */
107 CHIP_DEF(PCI_CHIP_RADEON_LY, RV100, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
108 CHIP_DEF(PCI_CHIP_RADEON_LZ, RV100, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
109 /* Radeon VE/7000 */
110 CHIP_DEF(PCI_CHIP_RV100_QY, RV100, CHIP_HAS_CRTC2),
111 CHIP_DEF(PCI_CHIP_RV100_QZ, RV100, CHIP_HAS_CRTC2),
112 CHIP_DEF(PCI_CHIP_RN50, RV100, CHIP_HAS_CRTC2),
113 /* Radeon IGP320M (U1) */
114 CHIP_DEF(PCI_CHIP_RS100_4336, RS100, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
115 /* Radeon IGP320 (A3) */
116 CHIP_DEF(PCI_CHIP_RS100_4136, RS100, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
117 /* IGP330M/340M/350M (U2) */
118 CHIP_DEF(PCI_CHIP_RS200_4337, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
119 /* IGP330/340/350 (A4) */
120 CHIP_DEF(PCI_CHIP_RS200_4137, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
121 /* Mobility 7000 IGP */
122 CHIP_DEF(PCI_CHIP_RS250_4437, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
123 /* 7000 IGP (A4+) */
124 CHIP_DEF(PCI_CHIP_RS250_4237, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
125 /* 8500 AIW */
126 CHIP_DEF(PCI_CHIP_R200_BB, R200, CHIP_HAS_CRTC2),
127 CHIP_DEF(PCI_CHIP_R200_BC, R200, CHIP_HAS_CRTC2),
128 /* 8700/8800 */
129 CHIP_DEF(PCI_CHIP_R200_QH, R200, CHIP_HAS_CRTC2),
130 /* 8500 */
131 CHIP_DEF(PCI_CHIP_R200_QL, R200, CHIP_HAS_CRTC2),
132 /* 9100 */
133 CHIP_DEF(PCI_CHIP_R200_QM, R200, CHIP_HAS_CRTC2),
134 /* Mobility M7 */
135 CHIP_DEF(PCI_CHIP_RADEON_LW, RV200, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
136 CHIP_DEF(PCI_CHIP_RADEON_LX, RV200, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
137 /* 7500 */
138 CHIP_DEF(PCI_CHIP_RV200_QW, RV200, CHIP_HAS_CRTC2),
139 CHIP_DEF(PCI_CHIP_RV200_QX, RV200, CHIP_HAS_CRTC2),
140 /* Mobility M9 */
141 CHIP_DEF(PCI_CHIP_RV250_Ld, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
142 CHIP_DEF(PCI_CHIP_RV250_Le, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
143 CHIP_DEF(PCI_CHIP_RV250_Lf, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
144 CHIP_DEF(PCI_CHIP_RV250_Lg, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
145 /* 9000/Pro */
146 CHIP_DEF(PCI_CHIP_RV250_If, RV250, CHIP_HAS_CRTC2),
147 CHIP_DEF(PCI_CHIP_RV250_Ig, RV250, CHIP_HAS_CRTC2),
148
149 CHIP_DEF(PCI_CHIP_RC410_5A62, RC410, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
150 /* Mobility 9100 IGP (U3) */
151 CHIP_DEF(PCI_CHIP_RS300_5835, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
152 CHIP_DEF(PCI_CHIP_RS350_7835, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
153 /* 9100 IGP (A5) */
154 CHIP_DEF(PCI_CHIP_RS300_5834, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
155 CHIP_DEF(PCI_CHIP_RS350_7834, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
156 /* Mobility 9200 (M9+) */
157 CHIP_DEF(PCI_CHIP_RV280_5C61, RV280, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
158 CHIP_DEF(PCI_CHIP_RV280_5C63, RV280, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
159 /* 9200 */
160 CHIP_DEF(PCI_CHIP_RV280_5960, RV280, CHIP_HAS_CRTC2),
161 CHIP_DEF(PCI_CHIP_RV280_5961, RV280, CHIP_HAS_CRTC2),
162 CHIP_DEF(PCI_CHIP_RV280_5962, RV280, CHIP_HAS_CRTC2),
163 CHIP_DEF(PCI_CHIP_RV280_5964, RV280, CHIP_HAS_CRTC2),
164 /* 9500 */
165 CHIP_DEF(PCI_CHIP_R300_AD, R300, CHIP_HAS_CRTC2),
166 CHIP_DEF(PCI_CHIP_R300_AE, R300, CHIP_HAS_CRTC2),
167 /* 9600TX / FireGL Z1 */
168 CHIP_DEF(PCI_CHIP_R300_AF, R300, CHIP_HAS_CRTC2),
169 CHIP_DEF(PCI_CHIP_R300_AG, R300, CHIP_HAS_CRTC2),
170 /* 9700/9500/Pro/FireGL X1 */
171 CHIP_DEF(PCI_CHIP_R300_ND, R300, CHIP_HAS_CRTC2),
172 CHIP_DEF(PCI_CHIP_R300_NE, R300, CHIP_HAS_CRTC2),
173 CHIP_DEF(PCI_CHIP_R300_NF, R300, CHIP_HAS_CRTC2),
174 CHIP_DEF(PCI_CHIP_R300_NG, R300, CHIP_HAS_CRTC2),
175 /* Mobility M10/M11 */
176 CHIP_DEF(PCI_CHIP_RV350_NP, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
177 CHIP_DEF(PCI_CHIP_RV350_NQ, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
178 CHIP_DEF(PCI_CHIP_RV350_NR, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
179 CHIP_DEF(PCI_CHIP_RV350_NS, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
180 CHIP_DEF(PCI_CHIP_RV350_NT, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
181 CHIP_DEF(PCI_CHIP_RV350_NV, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
182 /* 9600/FireGL T2 */
183 CHIP_DEF(PCI_CHIP_RV350_AP, RV350, CHIP_HAS_CRTC2),
184 CHIP_DEF(PCI_CHIP_RV350_AQ, RV350, CHIP_HAS_CRTC2),
185 CHIP_DEF(PCI_CHIP_RV360_AR, RV350, CHIP_HAS_CRTC2),
186 CHIP_DEF(PCI_CHIP_RV350_AS, RV350, CHIP_HAS_CRTC2),
187 CHIP_DEF(PCI_CHIP_RV350_AT, RV350, CHIP_HAS_CRTC2),
188 CHIP_DEF(PCI_CHIP_RV350_AV, RV350, CHIP_HAS_CRTC2),
189 /* 9800/Pro/FileGL X2 */
190 CHIP_DEF(PCI_CHIP_R350_AH, R350, CHIP_HAS_CRTC2),
191 CHIP_DEF(PCI_CHIP_R350_AI, R350, CHIP_HAS_CRTC2),
192 CHIP_DEF(PCI_CHIP_R350_AJ, R350, CHIP_HAS_CRTC2),
193 CHIP_DEF(PCI_CHIP_R350_AK, R350, CHIP_HAS_CRTC2),
194 CHIP_DEF(PCI_CHIP_R350_NH, R350, CHIP_HAS_CRTC2),
195 CHIP_DEF(PCI_CHIP_R350_NI, R350, CHIP_HAS_CRTC2),
196 CHIP_DEF(PCI_CHIP_R360_NJ, R350, CHIP_HAS_CRTC2),
197 CHIP_DEF(PCI_CHIP_R350_NK, R350, CHIP_HAS_CRTC2),
198 /* Newer stuff */
199 CHIP_DEF(PCI_CHIP_RV380_3E50, RV380, CHIP_HAS_CRTC2),
200 CHIP_DEF(PCI_CHIP_RV380_3E54, RV380, CHIP_HAS_CRTC2),
201 CHIP_DEF(PCI_CHIP_RV380_3150, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
202 CHIP_DEF(PCI_CHIP_RV380_3154, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
203 CHIP_DEF(PCI_CHIP_RV370_5B60, RV380, CHIP_HAS_CRTC2),
204 CHIP_DEF(PCI_CHIP_RV370_5B62, RV380, CHIP_HAS_CRTC2),
205 CHIP_DEF(PCI_CHIP_RV370_5B64, RV380, CHIP_HAS_CRTC2),
206 CHIP_DEF(PCI_CHIP_RV370_5B65, RV380, CHIP_HAS_CRTC2),
207 CHIP_DEF(PCI_CHIP_RV370_5460, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
208 CHIP_DEF(PCI_CHIP_RV370_5464, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
209 CHIP_DEF(PCI_CHIP_R420_JH, R420, CHIP_HAS_CRTC2),
210 CHIP_DEF(PCI_CHIP_R420_JI, R420, CHIP_HAS_CRTC2),
211 CHIP_DEF(PCI_CHIP_R420_JJ, R420, CHIP_HAS_CRTC2),
212 CHIP_DEF(PCI_CHIP_R420_JK, R420, CHIP_HAS_CRTC2),
213 CHIP_DEF(PCI_CHIP_R420_JL, R420, CHIP_HAS_CRTC2),
214 CHIP_DEF(PCI_CHIP_R420_JM, R420, CHIP_HAS_CRTC2),
215 CHIP_DEF(PCI_CHIP_R420_JN, R420, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
216 CHIP_DEF(PCI_CHIP_R420_JP, R420, CHIP_HAS_CRTC2),
217 CHIP_DEF(PCI_CHIP_R423_UH, R420, CHIP_HAS_CRTC2),
218 CHIP_DEF(PCI_CHIP_R423_UI, R420, CHIP_HAS_CRTC2),
219 CHIP_DEF(PCI_CHIP_R423_UJ, R420, CHIP_HAS_CRTC2),
220 CHIP_DEF(PCI_CHIP_R423_UK, R420, CHIP_HAS_CRTC2),
221 CHIP_DEF(PCI_CHIP_R423_UQ, R420, CHIP_HAS_CRTC2),
222 CHIP_DEF(PCI_CHIP_R423_UR, R420, CHIP_HAS_CRTC2),
223 CHIP_DEF(PCI_CHIP_R423_UT, R420, CHIP_HAS_CRTC2),
224 CHIP_DEF(PCI_CHIP_R423_5D57, R420, CHIP_HAS_CRTC2),
225 /* Original Radeon/7200 */
226 CHIP_DEF(PCI_CHIP_RADEON_QD, RADEON, 0),
227 CHIP_DEF(PCI_CHIP_RADEON_QE, RADEON, 0),
228 CHIP_DEF(PCI_CHIP_RADEON_QF, RADEON, 0),
229 CHIP_DEF(PCI_CHIP_RADEON_QG, RADEON, 0),
230 { 0, }
231 };
232 MODULE_DEVICE_TABLE(pci, radeonfb_pci_table);
233
234
235 typedef struct {
236 u16 reg;
237 u32 val;
238 } reg_val;
239
240
241 /* these common regs are cleared before mode setting so they do not
242 * interfere with anything
243 */
244 static reg_val common_regs[] = {
245 { OVR_CLR, 0 },
246 { OVR_WID_LEFT_RIGHT, 0 },
247 { OVR_WID_TOP_BOTTOM, 0 },
248 { OV0_SCALE_CNTL, 0 },
249 { SUBPIC_CNTL, 0 },
250 { VIPH_CONTROL, 0 },
251 { I2C_CNTL_1, 0 },
252 { GEN_INT_CNTL, 0 },
253 { CAP0_TRIG_CNTL, 0 },
254 { CAP1_TRIG_CNTL, 0 },
255 };
256
257 /*
258 * globals
259 */
260
261 static char *mode_option;
262 static char *monitor_layout;
263 static int noaccel = 0;
264 static int default_dynclk = -2;
265 static int nomodeset = 0;
266 static int ignore_edid = 0;
267 static int mirror = 0;
268 static int panel_yres = 0;
269 static int force_dfp = 0;
270 static int force_measure_pll = 0;
271 #ifdef CONFIG_MTRR
272 static int nomtrr = 0;
273 #endif
274 static int force_sleep;
275 static int ignore_devlist;
276 #ifdef CONFIG_PMAC_BACKLIGHT
277 static int backlight = 1;
278 #else
279 static int backlight = 0;
280 #endif
281
282 /*
283 * prototypes
284 */
285
286 static void radeon_unmap_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev)
287 {
288 if (!rinfo->bios_seg)
289 return;
290 pci_unmap_rom(dev, rinfo->bios_seg);
291 }
292
293 static int __devinit radeon_map_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev)
294 {
295 void __iomem *rom;
296 u16 dptr;
297 u8 rom_type;
298 size_t rom_size;
299
300 /* If this is a primary card, there is a shadow copy of the
301 * ROM somewhere in the first meg. We will just ignore the copy
302 * and use the ROM directly.
303 */
304
305 /* Fix from ATI for problem with Radeon hardware not leaving ROM enabled */
306 unsigned int temp;
307 temp = INREG(MPP_TB_CONFIG);
308 temp &= 0x00ffffffu;
309 temp |= 0x04 << 24;
310 OUTREG(MPP_TB_CONFIG, temp);
311 temp = INREG(MPP_TB_CONFIG);
312
313 rom = pci_map_rom(dev, &rom_size);
314 if (!rom) {
315 printk(KERN_ERR "radeonfb (%s): ROM failed to map\n",
316 pci_name(rinfo->pdev));
317 return -ENOMEM;
318 }
319
320 rinfo->bios_seg = rom;
321
322 /* Very simple test to make sure it appeared */
323 if (BIOS_IN16(0) != 0xaa55) {
324 printk(KERN_DEBUG "radeonfb (%s): Invalid ROM signature %x "
325 "should be 0xaa55\n",
326 pci_name(rinfo->pdev), BIOS_IN16(0));
327 goto failed;
328 }
329 /* Look for the PCI data to check the ROM type */
330 dptr = BIOS_IN16(0x18);
331
332 /* Check the PCI data signature. If it's wrong, we still assume a normal x86 ROM
333 * for now, until I've verified this works everywhere. The goal here is more
334 * to phase out Open Firmware images.
335 *
336 * Currently, we only look at the first PCI data, we could iteratre and deal with
337 * them all, and we should use fb_bios_start relative to start of image and not
338 * relative start of ROM, but so far, I never found a dual-image ATI card
339 *
340 * typedef struct {
341 * u32 signature; + 0x00
342 * u16 vendor; + 0x04
343 * u16 device; + 0x06
344 * u16 reserved_1; + 0x08
345 * u16 dlen; + 0x0a
346 * u8 drevision; + 0x0c
347 * u8 class_hi; + 0x0d
348 * u16 class_lo; + 0x0e
349 * u16 ilen; + 0x10
350 * u16 irevision; + 0x12
351 * u8 type; + 0x14
352 * u8 indicator; + 0x15
353 * u16 reserved_2; + 0x16
354 * } pci_data_t;
355 */
356 if (BIOS_IN32(dptr) != (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) {
357 printk(KERN_WARNING "radeonfb (%s): PCI DATA signature in ROM"
358 "incorrect: %08x\n", pci_name(rinfo->pdev), BIOS_IN32(dptr));
359 goto anyway;
360 }
361 rom_type = BIOS_IN8(dptr + 0x14);
362 switch(rom_type) {
363 case 0:
364 printk(KERN_INFO "radeonfb: Found Intel x86 BIOS ROM Image\n");
365 break;
366 case 1:
367 printk(KERN_INFO "radeonfb: Found Open Firmware ROM Image\n");
368 goto failed;
369 case 2:
370 printk(KERN_INFO "radeonfb: Found HP PA-RISC ROM Image\n");
371 goto failed;
372 default:
373 printk(KERN_INFO "radeonfb: Found unknown type %d ROM Image\n", rom_type);
374 goto failed;
375 }
376 anyway:
377 /* Locate the flat panel infos, do some sanity checking !!! */
378 rinfo->fp_bios_start = BIOS_IN16(0x48);
379 return 0;
380
381 failed:
382 rinfo->bios_seg = NULL;
383 radeon_unmap_ROM(rinfo, dev);
384 return -ENXIO;
385 }
386
387 #ifdef CONFIG_X86
388 static int __devinit radeon_find_mem_vbios(struct radeonfb_info *rinfo)
389 {
390 /* I simplified this code as we used to miss the signatures in
391 * a lot of case. It's now closer to XFree, we just don't check
392 * for signatures at all... Something better will have to be done
393 * if we end up having conflicts
394 */
395 u32 segstart;
396 void __iomem *rom_base = NULL;
397
398 for(segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) {
399 rom_base = ioremap(segstart, 0x10000);
400 if (rom_base == NULL)
401 return -ENOMEM;
402 if (readb(rom_base) == 0x55 && readb(rom_base + 1) == 0xaa)
403 break;
404 iounmap(rom_base);
405 rom_base = NULL;
406 }
407 if (rom_base == NULL)
408 return -ENXIO;
409
410 /* Locate the flat panel infos, do some sanity checking !!! */
411 rinfo->bios_seg = rom_base;
412 rinfo->fp_bios_start = BIOS_IN16(0x48);
413
414 return 0;
415 }
416 #endif
417
418 #if defined(CONFIG_PPC_OF) || defined(CONFIG_SPARC)
419 /*
420 * Read XTAL (ref clock), SCLK and MCLK from Open Firmware device
421 * tree. Hopefully, ATI OF driver is kind enough to fill these
422 */
423 static int __devinit radeon_read_xtal_OF (struct radeonfb_info *rinfo)
424 {
425 struct device_node *dp = rinfo->of_node;
426 const u32 *val;
427
428 if (dp == NULL)
429 return -ENODEV;
430 val = of_get_property(dp, "ATY,RefCLK", NULL);
431 if (!val || !*val) {
432 printk(KERN_WARNING "radeonfb: No ATY,RefCLK property !\n");
433 return -EINVAL;
434 }
435
436 rinfo->pll.ref_clk = (*val) / 10;
437
438 val = of_get_property(dp, "ATY,SCLK", NULL);
439 if (val && *val)
440 rinfo->pll.sclk = (*val) / 10;
441
442 val = of_get_property(dp, "ATY,MCLK", NULL);
443 if (val && *val)
444 rinfo->pll.mclk = (*val) / 10;
445
446 return 0;
447 }
448 #endif /* CONFIG_PPC_OF || CONFIG_SPARC */
449
450 /*
451 * Read PLL infos from chip registers
452 */
453 static int __devinit radeon_probe_pll_params(struct radeonfb_info *rinfo)
454 {
455 unsigned char ppll_div_sel;
456 unsigned Ns, Nm, M;
457 unsigned sclk, mclk, tmp, ref_div;
458 int hTotal, vTotal, num, denom, m, n;
459 unsigned long long hz, vclk;
460 long xtal;
461 struct timeval start_tv, stop_tv;
462 long total_secs, total_usecs;
463 int i;
464
465 /* Ugh, we cut interrupts, bad bad bad, but we want some precision
466 * here, so... --BenH
467 */
468
469 /* Flush PCI buffers ? */
470 tmp = INREG16(DEVICE_ID);
471
472 local_irq_disable();
473
474 for(i=0; i<1000000; i++)
475 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0)
476 break;
477
478 do_gettimeofday(&start_tv);
479
480 for(i=0; i<1000000; i++)
481 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) != 0)
482 break;
483
484 for(i=0; i<1000000; i++)
485 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0)
486 break;
487
488 do_gettimeofday(&stop_tv);
489
490 local_irq_enable();
491
492 total_secs = stop_tv.tv_sec - start_tv.tv_sec;
493 if (total_secs > 10)
494 return -1;
495 total_usecs = stop_tv.tv_usec - start_tv.tv_usec;
496 total_usecs += total_secs * 1000000;
497 if (total_usecs < 0)
498 total_usecs = -total_usecs;
499 hz = 1000000/total_usecs;
500
501 hTotal = ((INREG(CRTC_H_TOTAL_DISP) & 0x1ff) + 1) * 8;
502 vTotal = ((INREG(CRTC_V_TOTAL_DISP) & 0x3ff) + 1);
503 vclk = (long long)hTotal * (long long)vTotal * hz;
504
505 switch((INPLL(PPLL_REF_DIV) & 0x30000) >> 16) {
506 case 0:
507 default:
508 num = 1;
509 denom = 1;
510 break;
511 case 1:
512 n = ((INPLL(M_SPLL_REF_FB_DIV) >> 16) & 0xff);
513 m = (INPLL(M_SPLL_REF_FB_DIV) & 0xff);
514 num = 2*n;
515 denom = 2*m;
516 break;
517 case 2:
518 n = ((INPLL(M_SPLL_REF_FB_DIV) >> 8) & 0xff);
519 m = (INPLL(M_SPLL_REF_FB_DIV) & 0xff);
520 num = 2*n;
521 denom = 2*m;
522 break;
523 }
524
525 ppll_div_sel = INREG8(CLOCK_CNTL_INDEX + 1) & 0x3;
526 radeon_pll_errata_after_index(rinfo);
527
528 n = (INPLL(PPLL_DIV_0 + ppll_div_sel) & 0x7ff);
529 m = (INPLL(PPLL_REF_DIV) & 0x3ff);
530
531 num *= n;
532 denom *= m;
533
534 switch ((INPLL(PPLL_DIV_0 + ppll_div_sel) >> 16) & 0x7) {
535 case 1:
536 denom *= 2;
537 break;
538 case 2:
539 denom *= 4;
540 break;
541 case 3:
542 denom *= 8;
543 break;
544 case 4:
545 denom *= 3;
546 break;
547 case 6:
548 denom *= 6;
549 break;
550 case 7:
551 denom *= 12;
552 break;
553 }
554
555 vclk *= denom;
556 do_div(vclk, 1000 * num);
557 xtal = vclk;
558
559 if ((xtal > 26900) && (xtal < 27100))
560 xtal = 2700;
561 else if ((xtal > 14200) && (xtal < 14400))
562 xtal = 1432;
563 else if ((xtal > 29400) && (xtal < 29600))
564 xtal = 2950;
565 else {
566 printk(KERN_WARNING "xtal calculation failed: %ld\n", xtal);
567 return -1;
568 }
569
570 tmp = INPLL(M_SPLL_REF_FB_DIV);
571 ref_div = INPLL(PPLL_REF_DIV) & 0x3ff;
572
573 Ns = (tmp & 0xff0000) >> 16;
574 Nm = (tmp & 0xff00) >> 8;
575 M = (tmp & 0xff);
576 sclk = round_div((2 * Ns * xtal), (2 * M));
577 mclk = round_div((2 * Nm * xtal), (2 * M));
578
579 /* we're done, hopefully these are sane values */
580 rinfo->pll.ref_clk = xtal;
581 rinfo->pll.ref_div = ref_div;
582 rinfo->pll.sclk = sclk;
583 rinfo->pll.mclk = mclk;
584
585 return 0;
586 }
587
588 /*
589 * Retrieve PLL infos by different means (BIOS, Open Firmware, register probing...)
590 */
591 static void __devinit radeon_get_pllinfo(struct radeonfb_info *rinfo)
592 {
593 /*
594 * In the case nothing works, these are defaults; they are mostly
595 * incomplete, however. It does provide ppll_max and _min values
596 * even for most other methods, however.
597 */
598 switch (rinfo->chipset) {
599 case PCI_DEVICE_ID_ATI_RADEON_QW:
600 case PCI_DEVICE_ID_ATI_RADEON_QX:
601 rinfo->pll.ppll_max = 35000;
602 rinfo->pll.ppll_min = 12000;
603 rinfo->pll.mclk = 23000;
604 rinfo->pll.sclk = 23000;
605 rinfo->pll.ref_clk = 2700;
606 break;
607 case PCI_DEVICE_ID_ATI_RADEON_QL:
608 case PCI_DEVICE_ID_ATI_RADEON_QN:
609 case PCI_DEVICE_ID_ATI_RADEON_QO:
610 case PCI_DEVICE_ID_ATI_RADEON_Ql:
611 case PCI_DEVICE_ID_ATI_RADEON_BB:
612 rinfo->pll.ppll_max = 35000;
613 rinfo->pll.ppll_min = 12000;
614 rinfo->pll.mclk = 27500;
615 rinfo->pll.sclk = 27500;
616 rinfo->pll.ref_clk = 2700;
617 break;
618 case PCI_DEVICE_ID_ATI_RADEON_Id:
619 case PCI_DEVICE_ID_ATI_RADEON_Ie:
620 case PCI_DEVICE_ID_ATI_RADEON_If:
621 case PCI_DEVICE_ID_ATI_RADEON_Ig:
622 rinfo->pll.ppll_max = 35000;
623 rinfo->pll.ppll_min = 12000;
624 rinfo->pll.mclk = 25000;
625 rinfo->pll.sclk = 25000;
626 rinfo->pll.ref_clk = 2700;
627 break;
628 case PCI_DEVICE_ID_ATI_RADEON_ND:
629 case PCI_DEVICE_ID_ATI_RADEON_NE:
630 case PCI_DEVICE_ID_ATI_RADEON_NF:
631 case PCI_DEVICE_ID_ATI_RADEON_NG:
632 rinfo->pll.ppll_max = 40000;
633 rinfo->pll.ppll_min = 20000;
634 rinfo->pll.mclk = 27000;
635 rinfo->pll.sclk = 27000;
636 rinfo->pll.ref_clk = 2700;
637 break;
638 case PCI_DEVICE_ID_ATI_RADEON_QD:
639 case PCI_DEVICE_ID_ATI_RADEON_QE:
640 case PCI_DEVICE_ID_ATI_RADEON_QF:
641 case PCI_DEVICE_ID_ATI_RADEON_QG:
642 default:
643 rinfo->pll.ppll_max = 35000;
644 rinfo->pll.ppll_min = 12000;
645 rinfo->pll.mclk = 16600;
646 rinfo->pll.sclk = 16600;
647 rinfo->pll.ref_clk = 2700;
648 break;
649 }
650 rinfo->pll.ref_div = INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK;
651
652
653 #if defined(CONFIG_PPC_OF) || defined(CONFIG_SPARC)
654 /*
655 * Retrieve PLL infos from Open Firmware first
656 */
657 if (!force_measure_pll && radeon_read_xtal_OF(rinfo) == 0) {
658 printk(KERN_INFO "radeonfb: Retrieved PLL infos from Open Firmware\n");
659 goto found;
660 }
661 #endif /* CONFIG_PPC_OF || CONFIG_SPARC */
662
663 /*
664 * Check out if we have an X86 which gave us some PLL informations
665 * and if yes, retrieve them
666 */
667 if (!force_measure_pll && rinfo->bios_seg) {
668 u16 pll_info_block = BIOS_IN16(rinfo->fp_bios_start + 0x30);
669
670 rinfo->pll.sclk = BIOS_IN16(pll_info_block + 0x08);
671 rinfo->pll.mclk = BIOS_IN16(pll_info_block + 0x0a);
672 rinfo->pll.ref_clk = BIOS_IN16(pll_info_block + 0x0e);
673 rinfo->pll.ref_div = BIOS_IN16(pll_info_block + 0x10);
674 rinfo->pll.ppll_min = BIOS_IN32(pll_info_block + 0x12);
675 rinfo->pll.ppll_max = BIOS_IN32(pll_info_block + 0x16);
676
677 printk(KERN_INFO "radeonfb: Retrieved PLL infos from BIOS\n");
678 goto found;
679 }
680
681 /*
682 * We didn't get PLL parameters from either OF or BIOS, we try to
683 * probe them
684 */
685 if (radeon_probe_pll_params(rinfo) == 0) {
686 printk(KERN_INFO "radeonfb: Retrieved PLL infos from registers\n");
687 goto found;
688 }
689
690 /*
691 * Fall back to already-set defaults...
692 */
693 printk(KERN_INFO "radeonfb: Used default PLL infos\n");
694
695 found:
696 /*
697 * Some methods fail to retrieve SCLK and MCLK values, we apply default
698 * settings in this case (200Mhz). If that really happne often, we could
699 * fetch from registers instead...
700 */
701 if (rinfo->pll.mclk == 0)
702 rinfo->pll.mclk = 20000;
703 if (rinfo->pll.sclk == 0)
704 rinfo->pll.sclk = 20000;
705
706 printk("radeonfb: Reference=%d.%02d MHz (RefDiv=%d) Memory=%d.%02d Mhz, System=%d.%02d MHz\n",
707 rinfo->pll.ref_clk / 100, rinfo->pll.ref_clk % 100,
708 rinfo->pll.ref_div,
709 rinfo->pll.mclk / 100, rinfo->pll.mclk % 100,
710 rinfo->pll.sclk / 100, rinfo->pll.sclk % 100);
711 printk("radeonfb: PLL min %d max %d\n", rinfo->pll.ppll_min, rinfo->pll.ppll_max);
712 }
713
714 static int radeonfb_check_var (struct fb_var_screeninfo *var, struct fb_info *info)
715 {
716 struct radeonfb_info *rinfo = info->par;
717 struct fb_var_screeninfo v;
718 int nom, den;
719 unsigned int pitch;
720
721 if (radeon_match_mode(rinfo, &v, var))
722 return -EINVAL;
723
724 switch (v.bits_per_pixel) {
725 case 0 ... 8:
726 v.bits_per_pixel = 8;
727 break;
728 case 9 ... 16:
729 v.bits_per_pixel = 16;
730 break;
731 case 17 ... 24:
732 #if 0 /* Doesn't seem to work */
733 v.bits_per_pixel = 24;
734 break;
735 #endif
736 return -EINVAL;
737 case 25 ... 32:
738 v.bits_per_pixel = 32;
739 break;
740 default:
741 return -EINVAL;
742 }
743
744 switch (var_to_depth(&v)) {
745 case 8:
746 nom = den = 1;
747 v.red.offset = v.green.offset = v.blue.offset = 0;
748 v.red.length = v.green.length = v.blue.length = 8;
749 v.transp.offset = v.transp.length = 0;
750 break;
751 case 15:
752 nom = 2;
753 den = 1;
754 v.red.offset = 10;
755 v.green.offset = 5;
756 v.blue.offset = 0;
757 v.red.length = v.green.length = v.blue.length = 5;
758 v.transp.offset = v.transp.length = 0;
759 break;
760 case 16:
761 nom = 2;
762 den = 1;
763 v.red.offset = 11;
764 v.green.offset = 5;
765 v.blue.offset = 0;
766 v.red.length = 5;
767 v.green.length = 6;
768 v.blue.length = 5;
769 v.transp.offset = v.transp.length = 0;
770 break;
771 case 24:
772 nom = 4;
773 den = 1;
774 v.red.offset = 16;
775 v.green.offset = 8;
776 v.blue.offset = 0;
777 v.red.length = v.blue.length = v.green.length = 8;
778 v.transp.offset = v.transp.length = 0;
779 break;
780 case 32:
781 nom = 4;
782 den = 1;
783 v.red.offset = 16;
784 v.green.offset = 8;
785 v.blue.offset = 0;
786 v.red.length = v.blue.length = v.green.length = 8;
787 v.transp.offset = 24;
788 v.transp.length = 8;
789 break;
790 default:
791 printk ("radeonfb: mode %dx%dx%d rejected, color depth invalid\n",
792 var->xres, var->yres, var->bits_per_pixel);
793 return -EINVAL;
794 }
795
796 if (v.yres_virtual < v.yres)
797 v.yres_virtual = v.yres;
798 if (v.xres_virtual < v.xres)
799 v.xres_virtual = v.xres;
800
801
802 /* XXX I'm adjusting xres_virtual to the pitch, that may help XFree
803 * with some panels, though I don't quite like this solution
804 */
805 if (rinfo->info->flags & FBINFO_HWACCEL_DISABLED) {
806 v.xres_virtual = v.xres_virtual & ~7ul;
807 } else {
808 pitch = ((v.xres_virtual * ((v.bits_per_pixel + 1) / 8) + 0x3f)
809 & ~(0x3f)) >> 6;
810 v.xres_virtual = (pitch << 6) / ((v.bits_per_pixel + 1) / 8);
811 }
812
813 if (((v.xres_virtual * v.yres_virtual * nom) / den) > rinfo->mapped_vram)
814 return -EINVAL;
815
816 if (v.xres_virtual < v.xres)
817 v.xres = v.xres_virtual;
818
819 if (v.xoffset < 0)
820 v.xoffset = 0;
821 if (v.yoffset < 0)
822 v.yoffset = 0;
823
824 if (v.xoffset > v.xres_virtual - v.xres)
825 v.xoffset = v.xres_virtual - v.xres - 1;
826
827 if (v.yoffset > v.yres_virtual - v.yres)
828 v.yoffset = v.yres_virtual - v.yres - 1;
829
830 v.red.msb_right = v.green.msb_right = v.blue.msb_right =
831 v.transp.offset = v.transp.length =
832 v.transp.msb_right = 0;
833
834 memcpy(var, &v, sizeof(v));
835
836 return 0;
837 }
838
839
840 static int radeonfb_pan_display (struct fb_var_screeninfo *var,
841 struct fb_info *info)
842 {
843 struct radeonfb_info *rinfo = info->par;
844
845 if ((var->xoffset + var->xres > var->xres_virtual)
846 || (var->yoffset + var->yres > var->yres_virtual))
847 return -EINVAL;
848
849 if (rinfo->asleep)
850 return 0;
851
852 radeon_fifo_wait(2);
853 OUTREG(CRTC_OFFSET, ((var->yoffset * var->xres_virtual + var->xoffset)
854 * var->bits_per_pixel / 8) & ~7);
855 return 0;
856 }
857
858
859 static int radeonfb_ioctl (struct fb_info *info, unsigned int cmd,
860 unsigned long arg)
861 {
862 struct radeonfb_info *rinfo = info->par;
863 unsigned int tmp;
864 u32 value = 0;
865 int rc;
866
867 switch (cmd) {
868 /*
869 * TODO: set mirror accordingly for non-Mobility chipsets with 2 CRTC's
870 * and do something better using 2nd CRTC instead of just hackish
871 * routing to second output
872 */
873 case FBIO_RADEON_SET_MIRROR:
874 if (!rinfo->is_mobility)
875 return -EINVAL;
876
877 rc = get_user(value, (__u32 __user *)arg);
878
879 if (rc)
880 return rc;
881
882 radeon_fifo_wait(2);
883 if (value & 0x01) {
884 tmp = INREG(LVDS_GEN_CNTL);
885
886 tmp |= (LVDS_ON | LVDS_BLON);
887 } else {
888 tmp = INREG(LVDS_GEN_CNTL);
889
890 tmp &= ~(LVDS_ON | LVDS_BLON);
891 }
892
893 OUTREG(LVDS_GEN_CNTL, tmp);
894
895 if (value & 0x02) {
896 tmp = INREG(CRTC_EXT_CNTL);
897 tmp |= CRTC_CRT_ON;
898
899 mirror = 1;
900 } else {
901 tmp = INREG(CRTC_EXT_CNTL);
902 tmp &= ~CRTC_CRT_ON;
903
904 mirror = 0;
905 }
906
907 OUTREG(CRTC_EXT_CNTL, tmp);
908
909 return 0;
910 case FBIO_RADEON_GET_MIRROR:
911 if (!rinfo->is_mobility)
912 return -EINVAL;
913
914 tmp = INREG(LVDS_GEN_CNTL);
915 if ((LVDS_ON | LVDS_BLON) & tmp)
916 value |= 0x01;
917
918 tmp = INREG(CRTC_EXT_CNTL);
919 if (CRTC_CRT_ON & tmp)
920 value |= 0x02;
921
922 return put_user(value, (__u32 __user *)arg);
923 default:
924 return -EINVAL;
925 }
926
927 return -EINVAL;
928 }
929
930
931 int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch)
932 {
933 u32 val;
934 u32 tmp_pix_clks;
935 int unblank = 0;
936
937 if (rinfo->lock_blank)
938 return 0;
939
940 radeon_engine_idle();
941
942 val = INREG(CRTC_EXT_CNTL);
943 val &= ~(CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS |
944 CRTC_VSYNC_DIS);
945 switch (blank) {
946 case FB_BLANK_VSYNC_SUSPEND:
947 val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS);
948 break;
949 case FB_BLANK_HSYNC_SUSPEND:
950 val |= (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS);
951 break;
952 case FB_BLANK_POWERDOWN:
953 val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS |
954 CRTC_HSYNC_DIS);
955 break;
956 case FB_BLANK_NORMAL:
957 val |= CRTC_DISPLAY_DIS;
958 break;
959 case FB_BLANK_UNBLANK:
960 default:
961 unblank = 1;
962 }
963 OUTREG(CRTC_EXT_CNTL, val);
964
965
966 switch (rinfo->mon1_type) {
967 case MT_DFP:
968 if (unblank)
969 OUTREGP(FP_GEN_CNTL, (FP_FPON | FP_TMDS_EN),
970 ~(FP_FPON | FP_TMDS_EN));
971 else {
972 if (mode_switch || blank == FB_BLANK_NORMAL)
973 break;
974 OUTREGP(FP_GEN_CNTL, 0, ~(FP_FPON | FP_TMDS_EN));
975 }
976 break;
977 case MT_LCD:
978 del_timer_sync(&rinfo->lvds_timer);
979 val = INREG(LVDS_GEN_CNTL);
980 if (unblank) {
981 u32 target_val = (val & ~LVDS_DISPLAY_DIS) | LVDS_BLON | LVDS_ON
982 | LVDS_EN | (rinfo->init_state.lvds_gen_cntl
983 & (LVDS_DIGON | LVDS_BL_MOD_EN));
984 if ((val ^ target_val) == LVDS_DISPLAY_DIS)
985 OUTREG(LVDS_GEN_CNTL, target_val);
986 else if ((val ^ target_val) != 0) {
987 OUTREG(LVDS_GEN_CNTL, target_val
988 & ~(LVDS_ON | LVDS_BL_MOD_EN));
989 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
990 rinfo->init_state.lvds_gen_cntl |=
991 target_val & LVDS_STATE_MASK;
992 if (mode_switch) {
993 radeon_msleep(rinfo->panel_info.pwr_delay);
994 OUTREG(LVDS_GEN_CNTL, target_val);
995 }
996 else {
997 rinfo->pending_lvds_gen_cntl = target_val;
998 mod_timer(&rinfo->lvds_timer,
999 jiffies +
1000 msecs_to_jiffies(rinfo->panel_info.pwr_delay));
1001 }
1002 }
1003 } else {
1004 val |= LVDS_DISPLAY_DIS;
1005 OUTREG(LVDS_GEN_CNTL, val);
1006
1007 /* We don't do a full switch-off on a simple mode switch */
1008 if (mode_switch || blank == FB_BLANK_NORMAL)
1009 break;
1010
1011 /* Asic bug, when turning off LVDS_ON, we have to make sure
1012 * RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off
1013 */
1014 tmp_pix_clks = INPLL(PIXCLKS_CNTL);
1015 if (rinfo->is_mobility || rinfo->is_IGP)
1016 OUTPLLP(PIXCLKS_CNTL, 0, ~PIXCLK_LVDS_ALWAYS_ONb);
1017 val &= ~(LVDS_BL_MOD_EN);
1018 OUTREG(LVDS_GEN_CNTL, val);
1019 udelay(100);
1020 val &= ~(LVDS_ON | LVDS_EN);
1021 OUTREG(LVDS_GEN_CNTL, val);
1022 val &= ~LVDS_DIGON;
1023 rinfo->pending_lvds_gen_cntl = val;
1024 mod_timer(&rinfo->lvds_timer,
1025 jiffies +
1026 msecs_to_jiffies(rinfo->panel_info.pwr_delay));
1027 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
1028 rinfo->init_state.lvds_gen_cntl |= val & LVDS_STATE_MASK;
1029 if (rinfo->is_mobility || rinfo->is_IGP)
1030 OUTPLL(PIXCLKS_CNTL, tmp_pix_clks);
1031 }
1032 break;
1033 case MT_CRT:
1034 // todo: powerdown DAC
1035 default:
1036 break;
1037 }
1038
1039 return 0;
1040 }
1041
1042 static int radeonfb_blank (int blank, struct fb_info *info)
1043 {
1044 struct radeonfb_info *rinfo = info->par;
1045
1046 if (rinfo->asleep)
1047 return 0;
1048
1049 return radeon_screen_blank(rinfo, blank, 0);
1050 }
1051
1052 static int radeon_setcolreg (unsigned regno, unsigned red, unsigned green,
1053 unsigned blue, unsigned transp,
1054 struct radeonfb_info *rinfo)
1055 {
1056 u32 pindex;
1057 unsigned int i;
1058
1059
1060 if (regno > 255)
1061 return -EINVAL;
1062
1063 red >>= 8;
1064 green >>= 8;
1065 blue >>= 8;
1066 rinfo->palette[regno].red = red;
1067 rinfo->palette[regno].green = green;
1068 rinfo->palette[regno].blue = blue;
1069
1070 /* default */
1071 pindex = regno;
1072
1073 if (!rinfo->asleep) {
1074 radeon_fifo_wait(9);
1075
1076 if (rinfo->bpp == 16) {
1077 pindex = regno * 8;
1078
1079 if (rinfo->depth == 16 && regno > 63)
1080 return -EINVAL;
1081 if (rinfo->depth == 15 && regno > 31)
1082 return -EINVAL;
1083
1084 /* For 565, the green component is mixed one order
1085 * below
1086 */
1087 if (rinfo->depth == 16) {
1088 OUTREG(PALETTE_INDEX, pindex>>1);
1089 OUTREG(PALETTE_DATA,
1090 (rinfo->palette[regno>>1].red << 16) |
1091 (green << 8) |
1092 (rinfo->palette[regno>>1].blue));
1093 green = rinfo->palette[regno<<1].green;
1094 }
1095 }
1096
1097 if (rinfo->depth != 16 || regno < 32) {
1098 OUTREG(PALETTE_INDEX, pindex);
1099 OUTREG(PALETTE_DATA, (red << 16) |
1100 (green << 8) | blue);
1101 }
1102 }
1103 if (regno < 16) {
1104 u32 *pal = rinfo->info->pseudo_palette;
1105 switch (rinfo->depth) {
1106 case 15:
1107 pal[regno] = (regno << 10) | (regno << 5) | regno;
1108 break;
1109 case 16:
1110 pal[regno] = (regno << 11) | (regno << 5) | regno;
1111 break;
1112 case 24:
1113 pal[regno] = (regno << 16) | (regno << 8) | regno;
1114 break;
1115 case 32:
1116 i = (regno << 8) | regno;
1117 pal[regno] = (i << 16) | i;
1118 break;
1119 }
1120 }
1121 return 0;
1122 }
1123
1124 static int radeonfb_setcolreg (unsigned regno, unsigned red, unsigned green,
1125 unsigned blue, unsigned transp,
1126 struct fb_info *info)
1127 {
1128 struct radeonfb_info *rinfo = info->par;
1129 u32 dac_cntl2, vclk_cntl = 0;
1130 int rc;
1131
1132 if (!rinfo->asleep) {
1133 if (rinfo->is_mobility) {
1134 vclk_cntl = INPLL(VCLK_ECP_CNTL);
1135 OUTPLL(VCLK_ECP_CNTL,
1136 vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb);
1137 }
1138
1139 /* Make sure we are on first palette */
1140 if (rinfo->has_CRTC2) {
1141 dac_cntl2 = INREG(DAC_CNTL2);
1142 dac_cntl2 &= ~DAC2_PALETTE_ACCESS_CNTL;
1143 OUTREG(DAC_CNTL2, dac_cntl2);
1144 }
1145 }
1146
1147 rc = radeon_setcolreg (regno, red, green, blue, transp, rinfo);
1148
1149 if (!rinfo->asleep && rinfo->is_mobility)
1150 OUTPLL(VCLK_ECP_CNTL, vclk_cntl);
1151
1152 return rc;
1153 }
1154
1155 static int radeonfb_setcmap(struct fb_cmap *cmap, struct fb_info *info)
1156 {
1157 struct radeonfb_info *rinfo = info->par;
1158 u16 *red, *green, *blue, *transp;
1159 u32 dac_cntl2, vclk_cntl = 0;
1160 int i, start, rc = 0;
1161
1162 if (!rinfo->asleep) {
1163 if (rinfo->is_mobility) {
1164 vclk_cntl = INPLL(VCLK_ECP_CNTL);
1165 OUTPLL(VCLK_ECP_CNTL,
1166 vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb);
1167 }
1168
1169 /* Make sure we are on first palette */
1170 if (rinfo->has_CRTC2) {
1171 dac_cntl2 = INREG(DAC_CNTL2);
1172 dac_cntl2 &= ~DAC2_PALETTE_ACCESS_CNTL;
1173 OUTREG(DAC_CNTL2, dac_cntl2);
1174 }
1175 }
1176
1177 red = cmap->red;
1178 green = cmap->green;
1179 blue = cmap->blue;
1180 transp = cmap->transp;
1181 start = cmap->start;
1182
1183 for (i = 0; i < cmap->len; i++) {
1184 u_int hred, hgreen, hblue, htransp = 0xffff;
1185
1186 hred = *red++;
1187 hgreen = *green++;
1188 hblue = *blue++;
1189 if (transp)
1190 htransp = *transp++;
1191 rc = radeon_setcolreg (start++, hred, hgreen, hblue, htransp,
1192 rinfo);
1193 if (rc)
1194 break;
1195 }
1196
1197 if (!rinfo->asleep && rinfo->is_mobility)
1198 OUTPLL(VCLK_ECP_CNTL, vclk_cntl);
1199
1200 return rc;
1201 }
1202
1203 static void radeon_save_state (struct radeonfb_info *rinfo,
1204 struct radeon_regs *save)
1205 {
1206 /* CRTC regs */
1207 save->crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
1208 save->crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
1209 save->crtc_more_cntl = INREG(CRTC_MORE_CNTL);
1210 save->dac_cntl = INREG(DAC_CNTL);
1211 save->crtc_h_total_disp = INREG(CRTC_H_TOTAL_DISP);
1212 save->crtc_h_sync_strt_wid = INREG(CRTC_H_SYNC_STRT_WID);
1213 save->crtc_v_total_disp = INREG(CRTC_V_TOTAL_DISP);
1214 save->crtc_v_sync_strt_wid = INREG(CRTC_V_SYNC_STRT_WID);
1215 save->crtc_pitch = INREG(CRTC_PITCH);
1216 save->surface_cntl = INREG(SURFACE_CNTL);
1217
1218 /* FP regs */
1219 save->fp_crtc_h_total_disp = INREG(FP_CRTC_H_TOTAL_DISP);
1220 save->fp_crtc_v_total_disp = INREG(FP_CRTC_V_TOTAL_DISP);
1221 save->fp_gen_cntl = INREG(FP_GEN_CNTL);
1222 save->fp_h_sync_strt_wid = INREG(FP_H_SYNC_STRT_WID);
1223 save->fp_horz_stretch = INREG(FP_HORZ_STRETCH);
1224 save->fp_v_sync_strt_wid = INREG(FP_V_SYNC_STRT_WID);
1225 save->fp_vert_stretch = INREG(FP_VERT_STRETCH);
1226 save->lvds_gen_cntl = INREG(LVDS_GEN_CNTL);
1227 save->lvds_pll_cntl = INREG(LVDS_PLL_CNTL);
1228 save->tmds_crc = INREG(TMDS_CRC);
1229 save->tmds_transmitter_cntl = INREG(TMDS_TRANSMITTER_CNTL);
1230 save->vclk_ecp_cntl = INPLL(VCLK_ECP_CNTL);
1231
1232 /* PLL regs */
1233 save->clk_cntl_index = INREG(CLOCK_CNTL_INDEX) & ~0x3f;
1234 radeon_pll_errata_after_index(rinfo);
1235 save->ppll_div_3 = INPLL(PPLL_DIV_3);
1236 save->ppll_ref_div = INPLL(PPLL_REF_DIV);
1237 }
1238
1239
1240 static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *mode)
1241 {
1242 int i;
1243
1244 radeon_fifo_wait(20);
1245
1246 /* Workaround from XFree */
1247 if (rinfo->is_mobility) {
1248 /* A temporal workaround for the occational blanking on certain laptop
1249 * panels. This appears to related to the PLL divider registers
1250 * (fail to lock?). It occurs even when all dividers are the same
1251 * with their old settings. In this case we really don't need to
1252 * fiddle with PLL registers. By doing this we can avoid the blanking
1253 * problem with some panels.
1254 */
1255 if ((mode->ppll_ref_div == (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK)) &&
1256 (mode->ppll_div_3 == (INPLL(PPLL_DIV_3) &
1257 (PPLL_POST3_DIV_MASK | PPLL_FB3_DIV_MASK)))) {
1258 /* We still have to force a switch to selected PPLL div thanks to
1259 * an XFree86 driver bug which will switch it away in some cases
1260 * even when using UseFDev */
1261 OUTREGP(CLOCK_CNTL_INDEX,
1262 mode->clk_cntl_index & PPLL_DIV_SEL_MASK,
1263 ~PPLL_DIV_SEL_MASK);
1264 radeon_pll_errata_after_index(rinfo);
1265 radeon_pll_errata_after_data(rinfo);
1266 return;
1267 }
1268 }
1269
1270 /* Swich VCKL clock input to CPUCLK so it stays fed while PPLL updates*/
1271 OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_CPUCLK, ~VCLK_SRC_SEL_MASK);
1272
1273 /* Reset PPLL & enable atomic update */
1274 OUTPLLP(PPLL_CNTL,
1275 PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN,
1276 ~(PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));
1277
1278 /* Switch to selected PPLL divider */
1279 OUTREGP(CLOCK_CNTL_INDEX,
1280 mode->clk_cntl_index & PPLL_DIV_SEL_MASK,
1281 ~PPLL_DIV_SEL_MASK);
1282 radeon_pll_errata_after_index(rinfo);
1283 radeon_pll_errata_after_data(rinfo);
1284
1285 /* Set PPLL ref. div */
1286 if (rinfo->family == CHIP_FAMILY_R300 ||
1287 rinfo->family == CHIP_FAMILY_RS300 ||
1288 rinfo->family == CHIP_FAMILY_R350 ||
1289 rinfo->family == CHIP_FAMILY_RV350 ||
1290 rinfo->family == CHIP_FAMILY_RV380 ) {
1291 if (mode->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
1292 /* When restoring console mode, use saved PPLL_REF_DIV
1293 * setting.
1294 */
1295 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, 0);
1296 } else {
1297 /* R300 uses ref_div_acc field as real ref divider */
1298 OUTPLLP(PPLL_REF_DIV,
1299 (mode->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
1300 ~R300_PPLL_REF_DIV_ACC_MASK);
1301 }
1302 } else
1303 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK);
1304
1305 /* Set PPLL divider 3 & post divider*/
1306 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK);
1307 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK);
1308
1309 /* Write update */
1310 while (INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R)
1311 ;
1312 OUTPLLP(PPLL_REF_DIV, PPLL_ATOMIC_UPDATE_W, ~PPLL_ATOMIC_UPDATE_W);
1313
1314 /* Wait read update complete */
1315 /* FIXME: Certain revisions of R300 can't recover here. Not sure of
1316 the cause yet, but this workaround will mask the problem for now.
1317 Other chips usually will pass at the very first test, so the
1318 workaround shouldn't have any effect on them. */
1319 for (i = 0; (i < 10000 && INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R); i++)
1320 ;
1321
1322 OUTPLL(HTOTAL_CNTL, 0);
1323
1324 /* Clear reset & atomic update */
1325 OUTPLLP(PPLL_CNTL, 0,
1326 ~(PPLL_RESET | PPLL_SLEEP | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));
1327
1328 /* We may want some locking ... oh well */
1329 radeon_msleep(5);
1330
1331 /* Switch back VCLK source to PPLL */
1332 OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_PPLLCLK, ~VCLK_SRC_SEL_MASK);
1333 }
1334
1335 /*
1336 * Timer function for delayed LVDS panel power up/down
1337 */
1338 static void radeon_lvds_timer_func(unsigned long data)
1339 {
1340 struct radeonfb_info *rinfo = (struct radeonfb_info *)data;
1341
1342 radeon_engine_idle();
1343
1344 OUTREG(LVDS_GEN_CNTL, rinfo->pending_lvds_gen_cntl);
1345 }
1346
1347 /*
1348 * Apply a video mode. This will apply the whole register set, including
1349 * the PLL registers, to the card
1350 */
1351 void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode,
1352 int regs_only)
1353 {
1354 int i;
1355 int primary_mon = PRIMARY_MONITOR(rinfo);
1356
1357 if (nomodeset)
1358 return;
1359
1360 if (!regs_only)
1361 radeon_screen_blank(rinfo, FB_BLANK_NORMAL, 0);
1362
1363 radeon_fifo_wait(31);
1364 for (i=0; i<10; i++)
1365 OUTREG(common_regs[i].reg, common_regs[i].val);
1366
1367 /* Apply surface registers */
1368 for (i=0; i<8; i++) {
1369 OUTREG(SURFACE0_LOWER_BOUND + 0x10*i, mode->surf_lower_bound[i]);
1370 OUTREG(SURFACE0_UPPER_BOUND + 0x10*i, mode->surf_upper_bound[i]);
1371 OUTREG(SURFACE0_INFO + 0x10*i, mode->surf_info[i]);
1372 }
1373
1374 OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl);
1375 OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl,
1376 ~(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS));
1377 OUTREG(CRTC_MORE_CNTL, mode->crtc_more_cntl);
1378 OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING);
1379 OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp);
1380 OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid);
1381 OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp);
1382 OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid);
1383 OUTREG(CRTC_OFFSET, 0);
1384 OUTREG(CRTC_OFFSET_CNTL, 0);
1385 OUTREG(CRTC_PITCH, mode->crtc_pitch);
1386 OUTREG(SURFACE_CNTL, mode->surface_cntl);
1387
1388 radeon_write_pll_regs(rinfo, mode);
1389
1390 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1391 radeon_fifo_wait(10);
1392 OUTREG(FP_CRTC_H_TOTAL_DISP, mode->fp_crtc_h_total_disp);
1393 OUTREG(FP_CRTC_V_TOTAL_DISP, mode->fp_crtc_v_total_disp);
1394 OUTREG(FP_H_SYNC_STRT_WID, mode->fp_h_sync_strt_wid);
1395 OUTREG(FP_V_SYNC_STRT_WID, mode->fp_v_sync_strt_wid);
1396 OUTREG(FP_HORZ_STRETCH, mode->fp_horz_stretch);
1397 OUTREG(FP_VERT_STRETCH, mode->fp_vert_stretch);
1398 OUTREG(FP_GEN_CNTL, mode->fp_gen_cntl);
1399 OUTREG(TMDS_CRC, mode->tmds_crc);
1400 OUTREG(TMDS_TRANSMITTER_CNTL, mode->tmds_transmitter_cntl);
1401 }
1402
1403 if (!regs_only)
1404 radeon_screen_blank(rinfo, FB_BLANK_UNBLANK, 0);
1405
1406 radeon_fifo_wait(2);
1407 OUTPLL(VCLK_ECP_CNTL, mode->vclk_ecp_cntl);
1408
1409 return;
1410 }
1411
1412 /*
1413 * Calculate the PLL values for a given mode
1414 */
1415 static void radeon_calc_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *regs,
1416 unsigned long freq)
1417 {
1418 const struct {
1419 int divider;
1420 int bitvalue;
1421 } *post_div,
1422 post_divs[] = {
1423 { 1, 0 },
1424 { 2, 1 },
1425 { 4, 2 },
1426 { 8, 3 },
1427 { 3, 4 },
1428 { 16, 5 },
1429 { 6, 6 },
1430 { 12, 7 },
1431 { 0, 0 },
1432 };
1433 int fb_div, pll_output_freq = 0;
1434 int uses_dvo = 0;
1435
1436 /* Check if the DVO port is enabled and sourced from the primary CRTC. I'm
1437 * not sure which model starts having FP2_GEN_CNTL, I assume anything more
1438 * recent than an r(v)100...
1439 */
1440 #if 1
1441 /* XXX I had reports of flicker happening with the cinema display
1442 * on TMDS1 that seem to be fixed if I also forbit odd dividers in
1443 * this case. This could just be a bandwidth calculation issue, I
1444 * haven't implemented the bandwidth code yet, but in the meantime,
1445 * forcing uses_dvo to 1 fixes it and shouln't have bad side effects,
1446 * I haven't seen a case were were absolutely needed an odd PLL
1447 * divider. I'll find a better fix once I have more infos on the
1448 * real cause of the problem.
1449 */
1450 while (rinfo->has_CRTC2) {
1451 u32 fp2_gen_cntl = INREG(FP2_GEN_CNTL);
1452 u32 disp_output_cntl;
1453 int source;
1454
1455 /* FP2 path not enabled */
1456 if ((fp2_gen_cntl & FP2_ON) == 0)
1457 break;
1458 /* Not all chip revs have the same format for this register,
1459 * extract the source selection
1460 */
1461 if (rinfo->family == CHIP_FAMILY_R200 ||
1462 rinfo->family == CHIP_FAMILY_R300 ||
1463 rinfo->family == CHIP_FAMILY_R350 ||
1464 rinfo->family == CHIP_FAMILY_RV350) {
1465 source = (fp2_gen_cntl >> 10) & 0x3;
1466 /* sourced from transform unit, check for transform unit
1467 * own source
1468 */
1469 if (source == 3) {
1470 disp_output_cntl = INREG(DISP_OUTPUT_CNTL);
1471 source = (disp_output_cntl >> 12) & 0x3;
1472 }
1473 } else
1474 source = (fp2_gen_cntl >> 13) & 0x1;
1475 /* sourced from CRTC2 -> exit */
1476 if (source == 1)
1477 break;
1478
1479 /* so we end up on CRTC1, let's set uses_dvo to 1 now */
1480 uses_dvo = 1;
1481 break;
1482 }
1483 #else
1484 uses_dvo = 1;
1485 #endif
1486 if (freq > rinfo->pll.ppll_max)
1487 freq = rinfo->pll.ppll_max;
1488 if (freq*12 < rinfo->pll.ppll_min)
1489 freq = rinfo->pll.ppll_min / 12;
1490 RTRACE("freq = %lu, PLL min = %u, PLL max = %u\n",
1491 freq, rinfo->pll.ppll_min, rinfo->pll.ppll_max);
1492
1493 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
1494 pll_output_freq = post_div->divider * freq;
1495 /* If we output to the DVO port (external TMDS), we don't allow an
1496 * odd PLL divider as those aren't supported on this path
1497 */
1498 if (uses_dvo && (post_div->divider & 1))
1499 continue;
1500 if (pll_output_freq >= rinfo->pll.ppll_min &&
1501 pll_output_freq <= rinfo->pll.ppll_max)
1502 break;
1503 }
1504
1505 /* If we fall through the bottom, try the "default value"
1506 given by the terminal post_div->bitvalue */
1507 if ( !post_div->divider ) {
1508 post_div = &post_divs[post_div->bitvalue];
1509 pll_output_freq = post_div->divider * freq;
1510 }
1511 RTRACE("ref_div = %d, ref_clk = %d, output_freq = %d\n",
1512 rinfo->pll.ref_div, rinfo->pll.ref_clk,
1513 pll_output_freq);
1514
1515 /* If we fall through the bottom, try the "default value"
1516 given by the terminal post_div->bitvalue */
1517 if ( !post_div->divider ) {
1518 post_div = &post_divs[post_div->bitvalue];
1519 pll_output_freq = post_div->divider * freq;
1520 }
1521 RTRACE("ref_div = %d, ref_clk = %d, output_freq = %d\n",
1522 rinfo->pll.ref_div, rinfo->pll.ref_clk,
1523 pll_output_freq);
1524
1525 fb_div = round_div(rinfo->pll.ref_div*pll_output_freq,
1526 rinfo->pll.ref_clk);
1527 regs->ppll_ref_div = rinfo->pll.ref_div;
1528 regs->ppll_div_3 = fb_div | (post_div->bitvalue << 16);
1529
1530 RTRACE("post div = 0x%x\n", post_div->bitvalue);
1531 RTRACE("fb_div = 0x%x\n", fb_div);
1532 RTRACE("ppll_div_3 = 0x%x\n", regs->ppll_div_3);
1533 }
1534
1535 static int radeonfb_set_par(struct fb_info *info)
1536 {
1537 struct radeonfb_info *rinfo = info->par;
1538 struct fb_var_screeninfo *mode = &info->var;
1539 struct radeon_regs *newmode;
1540 int hTotal, vTotal, hSyncStart, hSyncEnd,
1541 hSyncPol, vSyncStart, vSyncEnd, vSyncPol, cSync;
1542 u8 hsync_adj_tab[] = {0, 0x12, 9, 9, 6, 5};
1543 u8 hsync_fudge_fp[] = {2, 2, 0, 0, 5, 5};
1544 u32 sync, h_sync_pol, v_sync_pol, dotClock, pixClock;
1545 int i, freq;
1546 int format = 0;
1547 int nopllcalc = 0;
1548 int hsync_start, hsync_fudge, bytpp, hsync_wid, vsync_wid;
1549 int primary_mon = PRIMARY_MONITOR(rinfo);
1550 int depth = var_to_depth(mode);
1551 int use_rmx = 0;
1552
1553 newmode = kmalloc(sizeof(struct radeon_regs), GFP_KERNEL);
1554 if (!newmode)
1555 return -ENOMEM;
1556
1557 /* We always want engine to be idle on a mode switch, even
1558 * if we won't actually change the mode
1559 */
1560 radeon_engine_idle();
1561
1562 hSyncStart = mode->xres + mode->right_margin;
1563 hSyncEnd = hSyncStart + mode->hsync_len;
1564 hTotal = hSyncEnd + mode->left_margin;
1565
1566 vSyncStart = mode->yres + mode->lower_margin;
1567 vSyncEnd = vSyncStart + mode->vsync_len;
1568 vTotal = vSyncEnd + mode->upper_margin;
1569 pixClock = mode->pixclock;
1570
1571 sync = mode->sync;
1572 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1573 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1574
1575 if (primary_mon == MT_DFP || primary_mon == MT_LCD) {
1576 if (rinfo->panel_info.xres < mode->xres)
1577 mode->xres = rinfo->panel_info.xres;
1578 if (rinfo->panel_info.yres < mode->yres)
1579 mode->yres = rinfo->panel_info.yres;
1580
1581 hTotal = mode->xres + rinfo->panel_info.hblank;
1582 hSyncStart = mode->xres + rinfo->panel_info.hOver_plus;
1583 hSyncEnd = hSyncStart + rinfo->panel_info.hSync_width;
1584
1585 vTotal = mode->yres + rinfo->panel_info.vblank;
1586 vSyncStart = mode->yres + rinfo->panel_info.vOver_plus;
1587 vSyncEnd = vSyncStart + rinfo->panel_info.vSync_width;
1588
1589 h_sync_pol = !rinfo->panel_info.hAct_high;
1590 v_sync_pol = !rinfo->panel_info.vAct_high;
1591
1592 pixClock = 100000000 / rinfo->panel_info.clock;
1593
1594 if (rinfo->panel_info.use_bios_dividers) {
1595 nopllcalc = 1;
1596 newmode->ppll_div_3 = rinfo->panel_info.fbk_divider |
1597 (rinfo->panel_info.post_divider << 16);
1598 newmode->ppll_ref_div = rinfo->panel_info.ref_divider;
1599 }
1600 }
1601 dotClock = 1000000000 / pixClock;
1602 freq = dotClock / 10; /* x100 */
1603
1604 RTRACE("hStart = %d, hEnd = %d, hTotal = %d\n",
1605 hSyncStart, hSyncEnd, hTotal);
1606 RTRACE("vStart = %d, vEnd = %d, vTotal = %d\n",
1607 vSyncStart, vSyncEnd, vTotal);
1608
1609 hsync_wid = (hSyncEnd - hSyncStart) / 8;
1610 vsync_wid = vSyncEnd - vSyncStart;
1611 if (hsync_wid == 0)
1612 hsync_wid = 1;
1613 else if (hsync_wid > 0x3f) /* max */
1614 hsync_wid = 0x3f;
1615
1616 if (vsync_wid == 0)
1617 vsync_wid = 1;
1618 else if (vsync_wid > 0x1f) /* max */
1619 vsync_wid = 0x1f;
1620
1621 hSyncPol = mode->sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1622 vSyncPol = mode->sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1623
1624 cSync = mode->sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0;
1625
1626 format = radeon_get_dstbpp(depth);
1627 bytpp = mode->bits_per_pixel >> 3;
1628
1629 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD))
1630 hsync_fudge = hsync_fudge_fp[format-1];
1631 else
1632 hsync_fudge = hsync_adj_tab[format-1];
1633
1634 hsync_start = hSyncStart - 8 + hsync_fudge;
1635
1636 newmode->crtc_gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN |
1637 (format << 8);
1638
1639 /* Clear auto-center etc... */
1640 newmode->crtc_more_cntl = rinfo->init_state.crtc_more_cntl;
1641 newmode->crtc_more_cntl &= 0xfffffff0;
1642
1643 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1644 newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN;
1645 if (mirror)
1646 newmode->crtc_ext_cntl |= CRTC_CRT_ON;
1647
1648 newmode->crtc_gen_cntl &= ~(CRTC_DBL_SCAN_EN |
1649 CRTC_INTERLACE_EN);
1650 } else {
1651 newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN |
1652 CRTC_CRT_ON;
1653 }
1654
1655 newmode->dac_cntl = /* INREG(DAC_CNTL) | */ DAC_MASK_ALL | DAC_VGA_ADR_EN |
1656 DAC_8BIT_EN;
1657
1658 newmode->crtc_h_total_disp = ((((hTotal / 8) - 1) & 0x3ff) |
1659 (((mode->xres / 8) - 1) << 16));
1660
1661 newmode->crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) |
1662 (hsync_wid << 16) | (h_sync_pol << 23));
1663
1664 newmode->crtc_v_total_disp = ((vTotal - 1) & 0xffff) |
1665 ((mode->yres - 1) << 16);
1666
1667 newmode->crtc_v_sync_strt_wid = (((vSyncStart - 1) & 0xfff) |
1668 (vsync_wid << 16) | (v_sync_pol << 23));
1669
1670 if (!(info->flags & FBINFO_HWACCEL_DISABLED)) {
1671 /* We first calculate the engine pitch */
1672 rinfo->pitch = ((mode->xres_virtual * ((mode->bits_per_pixel + 1) / 8) + 0x3f)
1673 & ~(0x3f)) >> 6;
1674
1675 /* Then, re-multiply it to get the CRTC pitch */
1676 newmode->crtc_pitch = (rinfo->pitch << 3) / ((mode->bits_per_pixel + 1) / 8);
1677 } else
1678 newmode->crtc_pitch = (mode->xres_virtual >> 3);
1679
1680 newmode->crtc_pitch |= (newmode->crtc_pitch << 16);
1681
1682 /*
1683 * It looks like recent chips have a problem with SURFACE_CNTL,
1684 * setting SURF_TRANSLATION_DIS completely disables the
1685 * swapper as well, so we leave it unset now.
1686 */
1687 newmode->surface_cntl = 0;
1688
1689 #if defined(__BIG_ENDIAN)
1690
1691 /* Setup swapping on both apertures, though we currently
1692 * only use aperture 0, enabling swapper on aperture 1
1693 * won't harm
1694 */
1695 switch (mode->bits_per_pixel) {
1696 case 16:
1697 newmode->surface_cntl |= NONSURF_AP0_SWP_16BPP;
1698 newmode->surface_cntl |= NONSURF_AP1_SWP_16BPP;
1699 break;
1700 case 24:
1701 case 32:
1702 newmode->surface_cntl |= NONSURF_AP0_SWP_32BPP;
1703 newmode->surface_cntl |= NONSURF_AP1_SWP_32BPP;
1704 break;
1705 }
1706 #endif
1707
1708 /* Clear surface registers */
1709 for (i=0; i<8; i++) {
1710 newmode->surf_lower_bound[i] = 0;
1711 newmode->surf_upper_bound[i] = 0x1f;
1712 newmode->surf_info[i] = 0;
1713 }
1714
1715 RTRACE("h_total_disp = 0x%x\t hsync_strt_wid = 0x%x\n",
1716 newmode->crtc_h_total_disp, newmode->crtc_h_sync_strt_wid);
1717 RTRACE("v_total_disp = 0x%x\t vsync_strt_wid = 0x%x\n",
1718 newmode->crtc_v_total_disp, newmode->crtc_v_sync_strt_wid);
1719
1720 rinfo->bpp = mode->bits_per_pixel;
1721 rinfo->depth = depth;
1722
1723 RTRACE("pixclock = %lu\n", (unsigned long)pixClock);
1724 RTRACE("freq = %lu\n", (unsigned long)freq);
1725
1726 /* We use PPLL_DIV_3 */
1727 newmode->clk_cntl_index = 0x300;
1728
1729 /* Calculate PPLL value if necessary */
1730 if (!nopllcalc)
1731 radeon_calc_pll_regs(rinfo, newmode, freq);
1732
1733 newmode->vclk_ecp_cntl = rinfo->init_state.vclk_ecp_cntl;
1734
1735 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1736 unsigned int hRatio, vRatio;
1737
1738 if (mode->xres > rinfo->panel_info.xres)
1739 mode->xres = rinfo->panel_info.xres;
1740 if (mode->yres > rinfo->panel_info.yres)
1741 mode->yres = rinfo->panel_info.yres;
1742
1743 newmode->fp_horz_stretch = (((rinfo->panel_info.xres / 8) - 1)
1744 << HORZ_PANEL_SHIFT);
1745 newmode->fp_vert_stretch = ((rinfo->panel_info.yres - 1)
1746 << VERT_PANEL_SHIFT);
1747
1748 if (mode->xres != rinfo->panel_info.xres) {
1749 hRatio = round_div(mode->xres * HORZ_STRETCH_RATIO_MAX,
1750 rinfo->panel_info.xres);
1751 newmode->fp_horz_stretch = (((((unsigned long)hRatio) & HORZ_STRETCH_RATIO_MASK)) |
1752 (newmode->fp_horz_stretch &
1753 (HORZ_PANEL_SIZE | HORZ_FP_LOOP_STRETCH |
1754 HORZ_AUTO_RATIO_INC)));
1755 newmode->fp_horz_stretch |= (HORZ_STRETCH_BLEND |
1756 HORZ_STRETCH_ENABLE);
1757 use_rmx = 1;
1758 }
1759 newmode->fp_horz_stretch &= ~HORZ_AUTO_RATIO;
1760
1761 if (mode->yres != rinfo->panel_info.yres) {
1762 vRatio = round_div(mode->yres * VERT_STRETCH_RATIO_MAX,
1763 rinfo->panel_info.yres);
1764 newmode->fp_vert_stretch = (((((unsigned long)vRatio) & VERT_STRETCH_RATIO_MASK)) |
1765 (newmode->fp_vert_stretch &
1766 (VERT_PANEL_SIZE | VERT_STRETCH_RESERVED)));
1767 newmode->fp_vert_stretch |= (VERT_STRETCH_BLEND |
1768 VERT_STRETCH_ENABLE);
1769 use_rmx = 1;
1770 }
1771 newmode->fp_vert_stretch &= ~VERT_AUTO_RATIO_EN;
1772
1773 newmode->fp_gen_cntl = (rinfo->init_state.fp_gen_cntl & (u32)
1774 ~(FP_SEL_CRTC2 |
1775 FP_RMX_HVSYNC_CONTROL_EN |
1776 FP_DFP_SYNC_SEL |
1777 FP_CRT_SYNC_SEL |
1778 FP_CRTC_LOCK_8DOT |
1779 FP_USE_SHADOW_EN |
1780 FP_CRTC_USE_SHADOW_VEND |
1781 FP_CRT_SYNC_ALT));
1782
1783 newmode->fp_gen_cntl |= (FP_CRTC_DONT_SHADOW_VPAR |
1784 FP_CRTC_DONT_SHADOW_HEND |
1785 FP_PANEL_FORMAT);
1786
1787 if (IS_R300_VARIANT(rinfo) ||
1788 (rinfo->family == CHIP_FAMILY_R200)) {
1789 newmode->fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
1790 if (use_rmx)
1791 newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX;
1792 else
1793 newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;
1794 } else
1795 newmode->fp_gen_cntl |= FP_SEL_CRTC1;
1796
1797 newmode->lvds_gen_cntl = rinfo->init_state.lvds_gen_cntl;
1798 newmode->lvds_pll_cntl = rinfo->init_state.lvds_pll_cntl;
1799 newmode->tmds_crc = rinfo->init_state.tmds_crc;
1800 newmode->tmds_transmitter_cntl = rinfo->init_state.tmds_transmitter_cntl;
1801
1802 if (primary_mon == MT_LCD) {
1803 newmode->lvds_gen_cntl |= (LVDS_ON | LVDS_BLON);
1804 newmode->fp_gen_cntl &= ~(FP_FPON | FP_TMDS_EN);
1805 } else {
1806 /* DFP */
1807 newmode->fp_gen_cntl |= (FP_FPON | FP_TMDS_EN);
1808 newmode->tmds_transmitter_cntl &= ~(TMDS_PLLRST);
1809 /* TMDS_PLL_EN bit is reversed on RV (and mobility) chips */
1810 if (IS_R300_VARIANT(rinfo) ||
1811 (rinfo->family == CHIP_FAMILY_R200) || !rinfo->has_CRTC2)
1812 newmode->tmds_transmitter_cntl &= ~TMDS_PLL_EN;
1813 else
1814 newmode->tmds_transmitter_cntl |= TMDS_PLL_EN;
1815 newmode->crtc_ext_cntl &= ~CRTC_CRT_ON;
1816 }
1817
1818 newmode->fp_crtc_h_total_disp = (((rinfo->panel_info.hblank / 8) & 0x3ff) |
1819 (((mode->xres / 8) - 1) << 16));
1820 newmode->fp_crtc_v_total_disp = (rinfo->panel_info.vblank & 0xffff) |
1821 ((mode->yres - 1) << 16);
1822 newmode->fp_h_sync_strt_wid = ((rinfo->panel_info.hOver_plus & 0x1fff) |
1823 (hsync_wid << 16) | (h_sync_pol << 23));
1824 newmode->fp_v_sync_strt_wid = ((rinfo->panel_info.vOver_plus & 0xfff) |
1825 (vsync_wid << 16) | (v_sync_pol << 23));
1826 }
1827
1828 /* do it! */
1829 if (!rinfo->asleep) {
1830 memcpy(&rinfo->state, newmode, sizeof(*newmode));
1831 radeon_write_mode (rinfo, newmode, 0);
1832 /* (re)initialize the engine */
1833 if (!(info->flags & FBINFO_HWACCEL_DISABLED))
1834 radeonfb_engine_init (rinfo);
1835 }
1836 /* Update fix */
1837 if (!(info->flags & FBINFO_HWACCEL_DISABLED))
1838 info->fix.line_length = rinfo->pitch*64;
1839 else
1840 info->fix.line_length = mode->xres_virtual
1841 * ((mode->bits_per_pixel + 1) / 8);
1842 info->fix.visual = rinfo->depth == 8 ? FB_VISUAL_PSEUDOCOLOR
1843 : FB_VISUAL_DIRECTCOLOR;
1844
1845 #ifdef CONFIG_BOOTX_TEXT
1846 /* Update debug text engine */
1847 btext_update_display(rinfo->fb_base_phys, mode->xres, mode->yres,
1848 rinfo->depth, info->fix.line_length);
1849 #endif
1850
1851 kfree(newmode);
1852 return 0;
1853 }
1854
1855
1856 static struct fb_ops radeonfb_ops = {
1857 .owner = THIS_MODULE,
1858 .fb_check_var = radeonfb_check_var,
1859 .fb_set_par = radeonfb_set_par,
1860 .fb_setcolreg = radeonfb_setcolreg,
1861 .fb_setcmap = radeonfb_setcmap,
1862 .fb_pan_display = radeonfb_pan_display,
1863 .fb_blank = radeonfb_blank,
1864 .fb_ioctl = radeonfb_ioctl,
1865 .fb_sync = radeonfb_sync,
1866 .fb_fillrect = radeonfb_fillrect,
1867 .fb_copyarea = radeonfb_copyarea,
1868 .fb_imageblit = radeonfb_imageblit,
1869 };
1870
1871
1872 static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo)
1873 {
1874 struct fb_info *info = rinfo->info;
1875
1876 info->par = rinfo;
1877 info->pseudo_palette = rinfo->pseudo_palette;
1878 info->flags = FBINFO_DEFAULT
1879 | FBINFO_HWACCEL_COPYAREA
1880 | FBINFO_HWACCEL_FILLRECT
1881 | FBINFO_HWACCEL_XPAN
1882 | FBINFO_HWACCEL_YPAN;
1883 info->fbops = &radeonfb_ops;
1884 info->screen_base = rinfo->fb_base;
1885 info->screen_size = rinfo->mapped_vram;
1886 /* Fill fix common fields */
1887 strlcpy(info->fix.id, rinfo->name, sizeof(info->fix.id));
1888 info->fix.smem_start = rinfo->fb_base_phys;
1889 info->fix.smem_len = rinfo->video_ram;
1890 info->fix.type = FB_TYPE_PACKED_PIXELS;
1891 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
1892 info->fix.xpanstep = 8;
1893 info->fix.ypanstep = 1;
1894 info->fix.ywrapstep = 0;
1895 info->fix.type_aux = 0;
1896 info->fix.mmio_start = rinfo->mmio_base_phys;
1897 info->fix.mmio_len = RADEON_REGSIZE;
1898 info->fix.accel = FB_ACCEL_ATI_RADEON;
1899
1900 fb_alloc_cmap(&info->cmap, 256, 0);
1901
1902 if (noaccel)
1903 info->flags |= FBINFO_HWACCEL_DISABLED;
1904
1905 return 0;
1906 }
1907
1908 /*
1909 * This reconfigure the card's internal memory map. In theory, we'd like
1910 * to setup the card's memory at the same address as it's PCI bus address,
1911 * and the AGP aperture right after that so that system RAM on 32 bits
1912 * machines at least, is directly accessible. However, doing so would
1913 * conflict with the current XFree drivers...
1914 * Ultimately, I hope XFree, GATOS and ATI binary drivers will all agree
1915 * on the proper way to set this up and duplicate this here. In the meantime,
1916 * I put the card's memory at 0 in card space and AGP at some random high
1917 * local (0xe0000000 for now) that will be changed by XFree/DRI anyway
1918 */
1919 #ifdef CONFIG_PPC_OF
1920 #undef SET_MC_FB_FROM_APERTURE
1921 static void fixup_memory_mappings(struct radeonfb_info *rinfo)
1922 {
1923 u32 save_crtc_gen_cntl, save_crtc2_gen_cntl = 0;
1924 u32 save_crtc_ext_cntl;
1925 u32 aper_base, aper_size;
1926 u32 agp_base;
1927
1928 /* First, we disable display to avoid interfering */
1929 if (rinfo->has_CRTC2) {
1930 save_crtc2_gen_cntl = INREG(CRTC2_GEN_CNTL);
1931 OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl | CRTC2_DISP_REQ_EN_B);
1932 }
1933 save_crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
1934 save_crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
1935
1936 OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl | CRTC_DISPLAY_DIS);
1937 OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl | CRTC_DISP_REQ_EN_B);
1938 mdelay(100);
1939
1940 aper_base = INREG(CONFIG_APER_0_BASE);
1941 aper_size = INREG(CONFIG_APER_SIZE);
1942
1943 #ifdef SET_MC_FB_FROM_APERTURE
1944 /* Set framebuffer to be at the same address as set in PCI BAR */
1945 OUTREG(MC_FB_LOCATION,
1946 ((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16));
1947 rinfo->fb_local_base = aper_base;
1948 #else
1949 OUTREG(MC_FB_LOCATION, 0x7fff0000);
1950 rinfo->fb_local_base = 0;
1951 #endif
1952 agp_base = aper_base + aper_size;
1953 if (agp_base & 0xf0000000)
1954 agp_base = (aper_base | 0x0fffffff) + 1;
1955
1956 /* Set AGP to be just after the framebuffer on a 256Mb boundary. This
1957 * assumes the FB isn't mapped to 0xf0000000 or above, but this is
1958 * always the case on PPCs afaik.
1959 */
1960 #ifdef SET_MC_FB_FROM_APERTURE
1961 OUTREG(MC_AGP_LOCATION, 0xffff0000 | (agp_base >> 16));
1962 #else
1963 OUTREG(MC_AGP_LOCATION, 0xffffe000);
1964 #endif
1965
1966 /* Fixup the display base addresses & engine offsets while we
1967 * are at it as well
1968 */
1969 #ifdef SET_MC_FB_FROM_APERTURE
1970 OUTREG(DISPLAY_BASE_ADDR, aper_base);
1971 if (rinfo->has_CRTC2)
1972 OUTREG(CRTC2_DISPLAY_BASE_ADDR, aper_base);
1973 OUTREG(OV0_BASE_ADDR, aper_base);
1974 #else
1975 OUTREG(DISPLAY_BASE_ADDR, 0);
1976 if (rinfo->has_CRTC2)
1977 OUTREG(CRTC2_DISPLAY_BASE_ADDR, 0);
1978 OUTREG(OV0_BASE_ADDR, 0);
1979 #endif
1980 mdelay(100);
1981
1982 /* Restore display settings */
1983 OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl);
1984 OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl);
1985 if (rinfo->has_CRTC2)
1986 OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl);
1987
1988 RTRACE("aper_base: %08x MC_FB_LOC to: %08x, MC_AGP_LOC to: %08x\n",
1989 aper_base,
1990 ((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16),
1991 0xffff0000 | (agp_base >> 16));
1992 }
1993 #endif /* CONFIG_PPC_OF */
1994
1995
1996 static void radeon_identify_vram(struct radeonfb_info *rinfo)
1997 {
1998 u32 tmp;
1999
2000 /* framebuffer size */
2001 if ((rinfo->family == CHIP_FAMILY_RS100) ||
2002 (rinfo->family == CHIP_FAMILY_RS200) ||
2003 (rinfo->family == CHIP_FAMILY_RS300) ||
2004 (rinfo->family == CHIP_FAMILY_RC410) ||
2005 (rinfo->family == CHIP_FAMILY_RS480) ) {
2006 u32 tom = INREG(NB_TOM);
2007 tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024);
2008
2009 radeon_fifo_wait(6);
2010 OUTREG(MC_FB_LOCATION, tom);
2011 OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
2012 OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
2013 OUTREG(OV0_BASE_ADDR, (tom & 0xffff) << 16);
2014
2015 /* This is supposed to fix the crtc2 noise problem. */
2016 OUTREG(GRPH2_BUFFER_CNTL, INREG(GRPH2_BUFFER_CNTL) & ~0x7f0000);
2017
2018 if ((rinfo->family == CHIP_FAMILY_RS100) ||
2019 (rinfo->family == CHIP_FAMILY_RS200)) {
2020 /* This is to workaround the asic bug for RMX, some versions
2021 of BIOS dosen't have this register initialized correctly.
2022 */
2023 OUTREGP(CRTC_MORE_CNTL, CRTC_H_CUTOFF_ACTIVE_EN,
2024 ~CRTC_H_CUTOFF_ACTIVE_EN);
2025 }
2026 } else {
2027 tmp = INREG(CONFIG_MEMSIZE);
2028 }
2029
2030 /* mem size is bits [28:0], mask off the rest */
2031 rinfo->video_ram = tmp & CONFIG_MEMSIZE_MASK;
2032
2033 /*
2034 * Hack to get around some busted production M6's
2035 * reporting no ram
2036 */
2037 if (rinfo->video_ram == 0) {
2038 switch (rinfo->pdev->device) {
2039 case PCI_CHIP_RADEON_LY:
2040 case PCI_CHIP_RADEON_LZ:
2041 rinfo->video_ram = 8192 * 1024;
2042 break;
2043 default:
2044 break;
2045 }
2046 }
2047
2048
2049 /*
2050 * Now try to identify VRAM type
2051 */
2052 if (rinfo->is_IGP || (rinfo->family >= CHIP_FAMILY_R300) ||
2053 (INREG(MEM_SDRAM_MODE_REG) & (1<<30)))
2054 rinfo->vram_ddr = 1;
2055 else
2056 rinfo->vram_ddr = 0;
2057
2058 tmp = INREG(MEM_CNTL);
2059 if (IS_R300_VARIANT(rinfo)) {
2060 tmp &= R300_MEM_NUM_CHANNELS_MASK;
2061 switch (tmp) {
2062 case 0: rinfo->vram_width = 64; break;
2063 case 1: rinfo->vram_width = 128; break;
2064 case 2: rinfo->vram_width = 256; break;
2065 default: rinfo->vram_width = 128; break;
2066 }
2067 } else if ((rinfo->family == CHIP_FAMILY_RV100) ||
2068 (rinfo->family == CHIP_FAMILY_RS100) ||
2069 (rinfo->family == CHIP_FAMILY_RS200)){
2070 if (tmp & RV100_MEM_HALF_MODE)
2071 rinfo->vram_width = 32;
2072 else
2073 rinfo->vram_width = 64;
2074 } else {
2075 if (tmp & MEM_NUM_CHANNELS_MASK)
2076 rinfo->vram_width = 128;
2077 else
2078 rinfo->vram_width = 64;
2079 }
2080
2081 /* This may not be correct, as some cards can have half of channel disabled
2082 * ToDo: identify these cases
2083 */
2084
2085 RTRACE("radeonfb (%s): Found %ldk of %s %d bits wide videoram\n",
2086 pci_name(rinfo->pdev),
2087 rinfo->video_ram / 1024,
2088 rinfo->vram_ddr ? "DDR" : "SDRAM",
2089 rinfo->vram_width);
2090 }
2091
2092 /*
2093 * Sysfs
2094 */
2095
2096 static ssize_t radeon_show_one_edid(char *buf, loff_t off, size_t count, const u8 *edid)
2097 {
2098 if (off > EDID_LENGTH)
2099 return 0;
2100
2101 if (off + count > EDID_LENGTH)
2102 count = EDID_LENGTH - off;
2103
2104 memcpy(buf, edid + off, count);
2105
2106 return count;
2107 }
2108
2109
2110 static ssize_t radeon_show_edid1(struct kobject *kobj,
2111 struct bin_attribute *bin_attr,
2112 char *buf, loff_t off, size_t count)
2113 {
2114 struct device *dev = container_of(kobj, struct device, kobj);
2115 struct pci_dev *pdev = to_pci_dev(dev);
2116 struct fb_info *info = pci_get_drvdata(pdev);
2117 struct radeonfb_info *rinfo = info->par;
2118
2119 return radeon_show_one_edid(buf, off, count, rinfo->mon1_EDID);
2120 }
2121
2122
2123 static ssize_t radeon_show_edid2(struct kobject *kobj,
2124 struct bin_attribute *bin_attr,
2125 char *buf, loff_t off, size_t count)
2126 {
2127 struct device *dev = container_of(kobj, struct device, kobj);
2128 struct pci_dev *pdev = to_pci_dev(dev);
2129 struct fb_info *info = pci_get_drvdata(pdev);
2130 struct radeonfb_info *rinfo = info->par;
2131
2132 return radeon_show_one_edid(buf, off, count, rinfo->mon2_EDID);
2133 }
2134
2135 static struct bin_attribute edid1_attr = {
2136 .attr = {
2137 .name = "edid1",
2138 .mode = 0444,
2139 },
2140 .size = EDID_LENGTH,
2141 .read = radeon_show_edid1,
2142 };
2143
2144 static struct bin_attribute edid2_attr = {
2145 .attr = {
2146 .name = "edid2",
2147 .mode = 0444,
2148 },
2149 .size = EDID_LENGTH,
2150 .read = radeon_show_edid2,
2151 };
2152
2153
2154 static int __devinit radeonfb_pci_register (struct pci_dev *pdev,
2155 const struct pci_device_id *ent)
2156 {
2157 struct fb_info *info;
2158 struct radeonfb_info *rinfo;
2159 int ret;
2160
2161 RTRACE("radeonfb_pci_register BEGIN\n");
2162
2163 /* Enable device in PCI config */
2164 ret = pci_enable_device(pdev);
2165 if (ret < 0) {
2166 printk(KERN_ERR "radeonfb (%s): Cannot enable PCI device\n",
2167 pci_name(pdev));
2168 goto err_out;
2169 }
2170
2171 info = framebuffer_alloc(sizeof(struct radeonfb_info), &pdev->dev);
2172 if (!info) {
2173 printk (KERN_ERR "radeonfb (%s): could not allocate memory\n",
2174 pci_name(pdev));
2175 ret = -ENOMEM;
2176 goto err_disable;
2177 }
2178 rinfo = info->par;
2179 rinfo->info = info;
2180 rinfo->pdev = pdev;
2181
2182 spin_lock_init(&rinfo->reg_lock);
2183 init_timer(&rinfo->lvds_timer);
2184 rinfo->lvds_timer.function = radeon_lvds_timer_func;
2185 rinfo->lvds_timer.data = (unsigned long)rinfo;
2186
2187 strcpy(rinfo->name, "ATI Radeon XX ");
2188 rinfo->name[11] = ent->device >> 8;
2189 rinfo->name[12] = ent->device & 0xFF;
2190 rinfo->family = ent->driver_data & CHIP_FAMILY_MASK;
2191 rinfo->chipset = pdev->device;
2192 rinfo->has_CRTC2 = (ent->driver_data & CHIP_HAS_CRTC2) != 0;
2193 rinfo->is_mobility = (ent->driver_data & CHIP_IS_MOBILITY) != 0;
2194 rinfo->is_IGP = (ent->driver_data & CHIP_IS_IGP) != 0;
2195
2196 /* Set base addrs */
2197 rinfo->fb_base_phys = pci_resource_start (pdev, 0);
2198 rinfo->mmio_base_phys = pci_resource_start (pdev, 2);
2199
2200 /* request the mem regions */
2201 ret = pci_request_region(pdev, 0, "radeonfb framebuffer");
2202 if (ret < 0) {
2203 printk( KERN_ERR "radeonfb (%s): cannot request region 0.\n",
2204 pci_name(rinfo->pdev));
2205 goto err_release_fb;
2206 }
2207
2208 ret = pci_request_region(pdev, 2, "radeonfb mmio");
2209 if (ret < 0) {
2210 printk( KERN_ERR "radeonfb (%s): cannot request region 2.\n",
2211 pci_name(rinfo->pdev));
2212 goto err_release_pci0;
2213 }
2214
2215 /* map the regions */
2216 rinfo->mmio_base = ioremap(rinfo->mmio_base_phys, RADEON_REGSIZE);
2217 if (!rinfo->mmio_base) {
2218 printk(KERN_ERR "radeonfb (%s): cannot map MMIO\n",
2219 pci_name(rinfo->pdev));
2220 ret = -EIO;
2221 goto err_release_pci2;
2222 }
2223
2224 rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16;
2225
2226 /*
2227 * Check for errata
2228 */
2229 rinfo->errata = 0;
2230 if (rinfo->family == CHIP_FAMILY_R300 &&
2231 (INREG(CONFIG_CNTL) & CFG_ATI_REV_ID_MASK)
2232 == CFG_ATI_REV_A11)
2233 rinfo->errata |= CHIP_ERRATA_R300_CG;
2234
2235 if (rinfo->family == CHIP_FAMILY_RV200 ||
2236 rinfo->family == CHIP_FAMILY_RS200)
2237 rinfo->errata |= CHIP_ERRATA_PLL_DUMMYREADS;
2238
2239 if (rinfo->family == CHIP_FAMILY_RV100 ||
2240 rinfo->family == CHIP_FAMILY_RS100 ||
2241 rinfo->family == CHIP_FAMILY_RS200)
2242 rinfo->errata |= CHIP_ERRATA_PLL_DELAY;
2243
2244 #if defined(CONFIG_PPC_OF) || defined(CONFIG_SPARC)
2245 /* On PPC, we obtain the OF device-node pointer to the firmware
2246 * data for this chip
2247 */
2248 rinfo->of_node = pci_device_to_OF_node(pdev);
2249 if (rinfo->of_node == NULL)
2250 printk(KERN_WARNING "radeonfb (%s): Cannot match card to OF node !\n",
2251 pci_name(rinfo->pdev));
2252
2253 #endif /* CONFIG_PPC_OF || CONFIG_SPARC */
2254 #ifdef CONFIG_PPC_OF
2255 /* On PPC, the firmware sets up a memory mapping that tends
2256 * to cause lockups when enabling the engine. We reconfigure
2257 * the card internal memory mappings properly
2258 */
2259 fixup_memory_mappings(rinfo);
2260 #endif /* CONFIG_PPC_OF */
2261
2262 /* Get VRAM size and type */
2263 radeon_identify_vram(rinfo);
2264
2265 rinfo->mapped_vram = min_t(unsigned long, MAX_MAPPED_VRAM, rinfo->video_ram);
2266
2267 do {
2268 rinfo->fb_base = ioremap (rinfo->fb_base_phys,
2269 rinfo->mapped_vram);
2270 } while ( rinfo->fb_base == 0 &&
2271 ((rinfo->mapped_vram /=2) >= MIN_MAPPED_VRAM) );
2272
2273 if (rinfo->fb_base == NULL) {
2274 printk (KERN_ERR "radeonfb (%s): cannot map FB\n",
2275 pci_name(rinfo->pdev));
2276 ret = -EIO;
2277 goto err_unmap_rom;
2278 }
2279
2280 RTRACE("radeonfb (%s): mapped %ldk videoram\n", pci_name(rinfo->pdev),
2281 rinfo->mapped_vram/1024);
2282
2283 /*
2284 * Map the BIOS ROM if any and retrieve PLL parameters from
2285 * the BIOS. We skip that on mobility chips as the real panel
2286 * values we need aren't in the ROM but in the BIOS image in
2287 * memory. This is definitely not the best meacnism though,
2288 * we really need the arch code to tell us which is the "primary"
2289 * video adapter to use the memory image (or better, the arch
2290 * should provide us a copy of the BIOS image to shield us from
2291 * archs who would store that elsewhere and/or could initialize
2292 * more than one adapter during boot).
2293 */
2294 if (!rinfo->is_mobility)
2295 radeon_map_ROM(rinfo, pdev);
2296
2297 /*
2298 * On x86, the primary display on laptop may have it's BIOS
2299 * ROM elsewhere, try to locate it at the legacy memory hole.
2300 * We probably need to make sure this is the primary display,
2301 * but that is difficult without some arch support.
2302 */
2303 #ifdef CONFIG_X86
2304 if (rinfo->bios_seg == NULL)
2305 radeon_find_mem_vbios(rinfo);
2306 #endif
2307
2308 /* If both above failed, try the BIOS ROM again for mobility
2309 * chips
2310 */
2311 if (rinfo->bios_seg == NULL && rinfo->is_mobility)
2312 radeon_map_ROM(rinfo, pdev);
2313
2314 /* Get informations about the board's PLL */
2315 radeon_get_pllinfo(rinfo);
2316
2317 #ifdef CONFIG_FB_RADEON_I2C
2318 /* Register I2C bus */
2319 radeon_create_i2c_busses(rinfo);
2320 #endif
2321
2322 /* set all the vital stuff */
2323 radeon_set_fbinfo (rinfo);
2324
2325 /* Probe screen types */
2326 radeon_probe_screens(rinfo, monitor_layout, ignore_edid);
2327
2328 /* Build mode list, check out panel native model */
2329 radeon_check_modes(rinfo, mode_option);
2330
2331 /* Register some sysfs stuff (should be done better) */
2332 if (rinfo->mon1_EDID)
2333 sysfs_create_bin_file(&rinfo->pdev->dev.kobj, &edid1_attr);
2334 if (rinfo->mon2_EDID)
2335 sysfs_create_bin_file(&rinfo->pdev->dev.kobj, &edid2_attr);
2336
2337 /* save current mode regs before we switch into the new one
2338 * so we can restore this upon __exit
2339 */
2340 radeon_save_state (rinfo, &rinfo->init_state);
2341 memcpy(&rinfo->state, &rinfo->init_state, sizeof(struct radeon_regs));
2342
2343 /* Setup Power Management capabilities */
2344 if (default_dynclk < -1) {
2345 /* -2 is special: means ON on mobility chips and do not
2346 * change on others
2347 */
2348 radeonfb_pm_init(rinfo, rinfo->is_mobility ? 1 : -1, ignore_devlist, force_sleep);
2349 } else
2350 radeonfb_pm_init(rinfo, default_dynclk, ignore_devlist, force_sleep);
2351
2352 pci_set_drvdata(pdev, info);
2353
2354 /* Register with fbdev layer */
2355 ret = register_framebuffer(info);
2356 if (ret < 0) {
2357 printk (KERN_ERR "radeonfb (%s): could not register framebuffer\n",
2358 pci_name(rinfo->pdev));
2359 goto err_unmap_fb;
2360 }
2361
2362 #ifdef CONFIG_MTRR
2363 rinfo->mtrr_hdl = nomtrr ? -1 : mtrr_add(rinfo->fb_base_phys,
2364 rinfo->video_ram,
2365 MTRR_TYPE_WRCOMB, 1);
2366 #endif
2367
2368 if (backlight)
2369 radeonfb_bl_init(rinfo);
2370
2371 printk ("radeonfb (%s): %s\n", pci_name(rinfo->pdev), rinfo->name);
2372
2373 if (rinfo->bios_seg)
2374 radeon_unmap_ROM(rinfo, pdev);
2375 RTRACE("radeonfb_pci_register END\n");
2376
2377 return 0;
2378 err_unmap_fb:
2379 iounmap(rinfo->fb_base);
2380 err_unmap_rom:
2381 kfree(rinfo->mon1_EDID);
2382 kfree(rinfo->mon2_EDID);
2383 if (rinfo->mon1_modedb)
2384 fb_destroy_modedb(rinfo->mon1_modedb);
2385 fb_dealloc_cmap(&info->cmap);
2386 #ifdef CONFIG_FB_RADEON_I2C
2387 radeon_delete_i2c_busses(rinfo);
2388 #endif
2389 if (rinfo->bios_seg)
2390 radeon_unmap_ROM(rinfo, pdev);
2391 iounmap(rinfo->mmio_base);
2392 err_release_pci2:
2393 pci_release_region(pdev, 2);
2394 err_release_pci0:
2395 pci_release_region(pdev, 0);
2396 err_release_fb:
2397 framebuffer_release(info);
2398 err_disable:
2399 err_out:
2400 return ret;
2401 }
2402
2403
2404
2405 static void __devexit radeonfb_pci_unregister (struct pci_dev *pdev)
2406 {
2407 struct fb_info *info = pci_get_drvdata(pdev);
2408 struct radeonfb_info *rinfo = info->par;
2409
2410 if (!rinfo)
2411 return;
2412
2413 radeonfb_pm_exit(rinfo);
2414
2415 if (rinfo->mon1_EDID)
2416 sysfs_remove_bin_file(&rinfo->pdev->dev.kobj, &edid1_attr);
2417 if (rinfo->mon2_EDID)
2418 sysfs_remove_bin_file(&rinfo->pdev->dev.kobj, &edid2_attr);
2419
2420 #if 0
2421 /* restore original state
2422 *
2423 * Doesn't quite work yet, I suspect if we come from a legacy
2424 * VGA mode (or worse, text mode), we need to do some VGA black
2425 * magic here that I know nothing about. --BenH
2426 */
2427 radeon_write_mode (rinfo, &rinfo->init_state, 1);
2428 #endif
2429
2430 del_timer_sync(&rinfo->lvds_timer);
2431
2432 #ifdef CONFIG_MTRR
2433 if (rinfo->mtrr_hdl >= 0)
2434 mtrr_del(rinfo->mtrr_hdl, 0, 0);
2435 #endif
2436
2437 unregister_framebuffer(info);
2438
2439 radeonfb_bl_exit(rinfo);
2440
2441 iounmap(rinfo->mmio_base);
2442 iounmap(rinfo->fb_base);
2443
2444 pci_release_region(pdev, 2);
2445 pci_release_region(pdev, 0);
2446
2447 kfree(rinfo->mon1_EDID);
2448 kfree(rinfo->mon2_EDID);
2449 if (rinfo->mon1_modedb)
2450 fb_destroy_modedb(rinfo->mon1_modedb);
2451 #ifdef CONFIG_FB_RADEON_I2C
2452 radeon_delete_i2c_busses(rinfo);
2453 #endif
2454 fb_dealloc_cmap(&info->cmap);
2455 framebuffer_release(info);
2456 }
2457
2458
2459 static struct pci_driver radeonfb_driver = {
2460 .name = "radeonfb",
2461 .id_table = radeonfb_pci_table,
2462 .probe = radeonfb_pci_register,
2463 .remove = __devexit_p(radeonfb_pci_unregister),
2464 #ifdef CONFIG_PM
2465 .suspend = radeonfb_pci_suspend,
2466 .resume = radeonfb_pci_resume,
2467 #endif /* CONFIG_PM */
2468 };
2469
2470 #ifndef MODULE
2471 static int __init radeonfb_setup (char *options)
2472 {
2473 char *this_opt;
2474
2475 if (!options || !*options)
2476 return 0;
2477
2478 while ((this_opt = strsep (&options, ",")) != NULL) {
2479 if (!*this_opt)
2480 continue;
2481
2482 if (!strncmp(this_opt, "noaccel", 7)) {
2483 noaccel = 1;
2484 } else if (!strncmp(this_opt, "mirror", 6)) {
2485 mirror = 1;
2486 } else if (!strncmp(this_opt, "force_dfp", 9)) {
2487 force_dfp = 1;
2488 } else if (!strncmp(this_opt, "panel_yres:", 11)) {
2489 panel_yres = simple_strtoul((this_opt+11), NULL, 0);
2490 } else if (!strncmp(this_opt, "backlight:", 10)) {
2491 backlight = simple_strtoul(this_opt+10, NULL, 0);
2492 #ifdef CONFIG_MTRR
2493 } else if (!strncmp(this_opt, "nomtrr", 6)) {
2494 nomtrr = 1;
2495 #endif
2496 } else if (!strncmp(this_opt, "nomodeset", 9)) {
2497 nomodeset = 1;
2498 } else if (!strncmp(this_opt, "force_measure_pll", 17)) {
2499 force_measure_pll = 1;
2500 } else if (!strncmp(this_opt, "ignore_edid", 11)) {
2501 ignore_edid = 1;
2502 #if defined(CONFIG_PM) && defined(CONFIG_X86)
2503 } else if (!strncmp(this_opt, "force_sleep", 11)) {
2504 force_sleep = 1;
2505 } else if (!strncmp(this_opt, "ignore_devlist", 14)) {
2506 ignore_devlist = 1;
2507 #endif
2508 } else
2509 mode_option = this_opt;
2510 }
2511 return 0;
2512 }
2513 #endif /* MODULE */
2514
2515 static int __init radeonfb_init (void)
2516 {
2517 #ifndef MODULE
2518 char *option = NULL;
2519
2520 if (fb_get_options("radeonfb", &option))
2521 return -ENODEV;
2522 radeonfb_setup(option);
2523 #endif
2524 return pci_register_driver (&radeonfb_driver);
2525 }
2526
2527
2528 static void __exit radeonfb_exit (void)
2529 {
2530 pci_unregister_driver (&radeonfb_driver);
2531 }
2532
2533 module_init(radeonfb_init);
2534 module_exit(radeonfb_exit);
2535
2536 MODULE_AUTHOR("Ani Joshi");
2537 MODULE_DESCRIPTION("framebuffer driver for ATI Radeon chipset");
2538 MODULE_LICENSE("GPL");
2539 module_param(noaccel, bool, 0);
2540 module_param(default_dynclk, int, 0);
2541 MODULE_PARM_DESC(default_dynclk, "int: -2=enable on mobility only,-1=do not change,0=off,1=on");
2542 MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
2543 module_param(nomodeset, bool, 0);
2544 MODULE_PARM_DESC(nomodeset, "bool: disable actual setting of video mode");
2545 module_param(mirror, bool, 0);
2546 MODULE_PARM_DESC(mirror, "bool: mirror the display to both monitors");
2547 module_param(force_dfp, bool, 0);
2548 MODULE_PARM_DESC(force_dfp, "bool: force display to dfp");
2549 module_param(ignore_edid, bool, 0);
2550 MODULE_PARM_DESC(ignore_edid, "bool: Ignore EDID data when doing DDC probe");
2551 module_param(monitor_layout, charp, 0);
2552 MODULE_PARM_DESC(monitor_layout, "Specify monitor mapping (like XFree86)");
2553 module_param(force_measure_pll, bool, 0);
2554 MODULE_PARM_DESC(force_measure_pll, "Force measurement of PLL (debug)");
2555 #ifdef CONFIG_MTRR
2556 module_param(nomtrr, bool, 0);
2557 MODULE_PARM_DESC(nomtrr, "bool: disable use of MTRR registers");
2558 #endif
2559 module_param(panel_yres, int, 0);
2560 MODULE_PARM_DESC(panel_yres, "int: set panel yres");
2561 module_param(mode_option, charp, 0);
2562 MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
2563 #if defined(CONFIG_PM) && defined(CONFIG_X86)
2564 module_param(force_sleep, bool, 0);
2565 MODULE_PARM_DESC(force_sleep, "bool: force D2 sleep mode on all hardware");
2566 module_param(ignore_devlist, bool, 0);
2567 MODULE_PARM_DESC(ignore_devlist, "bool: ignore workarounds for bugs in specific laptops");
2568 #endif
Verdex Pro support