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cxgb3 - Add dual licensing
[linux-2.6/verdex.git] / drivers / net / mace.c
blob9ec24f0d5d6834e280fbe245d116d77c01277f02
1 /*
2 * Network device driver for the MACE ethernet controller on
3 * Apple Powermacs. Assumes it's under a DBDMA controller.
4 *
5 * Copyright (C) 1996 Paul Mackerras.
6 */
7
8 #include <linux/module.h>
9 #include <linux/kernel.h>
10 #include <linux/netdevice.h>
11 #include <linux/etherdevice.h>
12 #include <linux/delay.h>
13 #include <linux/string.h>
14 #include <linux/timer.h>
15 #include <linux/init.h>
16 #include <linux/crc32.h>
17 #include <linux/spinlock.h>
18 #include <linux/bitrev.h>
19 #include <asm/prom.h>
20 #include <asm/dbdma.h>
21 #include <asm/io.h>
22 #include <asm/pgtable.h>
23 #include <asm/macio.h>
24
25 #include "mace.h"
26
27 static int port_aaui = -1;
28
29 #define N_RX_RING 8
30 #define N_TX_RING 6
31 #define MAX_TX_ACTIVE 1
32 #define NCMDS_TX 1 /* dma commands per element in tx ring */
33 #define RX_BUFLEN (ETH_FRAME_LEN + 8)
34 #define TX_TIMEOUT HZ /* 1 second */
35
36 /* Chip rev needs workaround on HW & multicast addr change */
37 #define BROKEN_ADDRCHG_REV 0x0941
38
39 /* Bits in transmit DMA status */
40 #define TX_DMA_ERR 0x80
41
42 struct mace_data {
43 volatile struct mace __iomem *mace;
44 volatile struct dbdma_regs __iomem *tx_dma;
45 int tx_dma_intr;
46 volatile struct dbdma_regs __iomem *rx_dma;
47 int rx_dma_intr;
48 volatile struct dbdma_cmd *tx_cmds; /* xmit dma command list */
49 volatile struct dbdma_cmd *rx_cmds; /* recv dma command list */
50 struct sk_buff *rx_bufs[N_RX_RING];
51 int rx_fill;
52 int rx_empty;
53 struct sk_buff *tx_bufs[N_TX_RING];
54 int tx_fill;
55 int tx_empty;
56 unsigned char maccc;
57 unsigned char tx_fullup;
58 unsigned char tx_active;
59 unsigned char tx_bad_runt;
60 struct net_device_stats stats;
61 struct timer_list tx_timeout;
62 int timeout_active;
63 int port_aaui;
64 int chipid;
65 struct macio_dev *mdev;
66 spinlock_t lock;
67 };
68
69 /*
70 * Number of bytes of private data per MACE: allow enough for
71 * the rx and tx dma commands plus a branch dma command each,
72 * and another 16 bytes to allow us to align the dma command
73 * buffers on a 16 byte boundary.
74 */
75 #define PRIV_BYTES (sizeof(struct mace_data) \
76 + (N_RX_RING + NCMDS_TX * N_TX_RING + 3) * sizeof(struct dbdma_cmd))
77
78 static int mace_open(struct net_device *dev);
79 static int mace_close(struct net_device *dev);
80 static int mace_xmit_start(struct sk_buff *skb, struct net_device *dev);
81 static struct net_device_stats *mace_stats(struct net_device *dev);
82 static void mace_set_multicast(struct net_device *dev);
83 static void mace_reset(struct net_device *dev);
84 static int mace_set_address(struct net_device *dev, void *addr);
85 static irqreturn_t mace_interrupt(int irq, void *dev_id);
86 static irqreturn_t mace_txdma_intr(int irq, void *dev_id);
87 static irqreturn_t mace_rxdma_intr(int irq, void *dev_id);
88 static void mace_set_timeout(struct net_device *dev);
89 static void mace_tx_timeout(unsigned long data);
90 static inline void dbdma_reset(volatile struct dbdma_regs __iomem *dma);
91 static inline void mace_clean_rings(struct mace_data *mp);
92 static void __mace_set_address(struct net_device *dev, void *addr);
93
94 /*
95 * If we can't get a skbuff when we need it, we use this area for DMA.
96 */
97 static unsigned char *dummy_buf;
98
99 static int __devinit mace_probe(struct macio_dev *mdev, const struct of_device_id *match)
100 {
101 struct device_node *mace = macio_get_of_node(mdev);
102 struct net_device *dev;
103 struct mace_data *mp;
104 const unsigned char *addr;
105 int j, rev, rc = -EBUSY;
106
107 if (macio_resource_count(mdev) != 3 || macio_irq_count(mdev) != 3) {
108 printk(KERN_ERR "can't use MACE %s: need 3 addrs and 3 irqs\n",
109 mace->full_name);
110 return -ENODEV;
111 }
112
113 addr = get_property(mace, "mac-address", NULL);
114 if (addr == NULL) {
115 addr = get_property(mace, "local-mac-address", NULL);
116 if (addr == NULL) {
117 printk(KERN_ERR "Can't get mac-address for MACE %s\n",
118 mace->full_name);
119 return -ENODEV;
120 }
121 }
122
123 /*
124 * lazy allocate the driver-wide dummy buffer. (Note that we
125 * never have more than one MACE in the system anyway)
126 */
127 if (dummy_buf == NULL) {
128 dummy_buf = kmalloc(RX_BUFLEN+2, GFP_KERNEL);
129 if (dummy_buf == NULL) {
130 printk(KERN_ERR "MACE: couldn't allocate dummy buffer\n");
131 return -ENOMEM;
132 }
133 }
134
135 if (macio_request_resources(mdev, "mace")) {
136 printk(KERN_ERR "MACE: can't request IO resources !\n");
137 return -EBUSY;
138 }
139
140 dev = alloc_etherdev(PRIV_BYTES);
141 if (!dev) {
142 printk(KERN_ERR "MACE: can't allocate ethernet device !\n");
143 rc = -ENOMEM;
144 goto err_release;
145 }
146 SET_MODULE_OWNER(dev);
147 SET_NETDEV_DEV(dev, &mdev->ofdev.dev);
148
149 mp = dev->priv;
150 mp->mdev = mdev;
151 macio_set_drvdata(mdev, dev);
152
153 dev->base_addr = macio_resource_start(mdev, 0);
154 mp->mace = ioremap(dev->base_addr, 0x1000);
155 if (mp->mace == NULL) {
156 printk(KERN_ERR "MACE: can't map IO resources !\n");
157 rc = -ENOMEM;
158 goto err_free;
159 }
160 dev->irq = macio_irq(mdev, 0);
161
162 rev = addr[0] == 0 && addr[1] == 0xA0;
163 for (j = 0; j < 6; ++j) {
164 dev->dev_addr[j] = rev ? bitrev8(addr[j]): addr[j];
165 }
166 mp->chipid = (in_8(&mp->mace->chipid_hi) << 8) |
167 in_8(&mp->mace->chipid_lo);
168
169
170 mp = (struct mace_data *) dev->priv;
171 mp->maccc = ENXMT | ENRCV;
172
173 mp->tx_dma = ioremap(macio_resource_start(mdev, 1), 0x1000);
174 if (mp->tx_dma == NULL) {
175 printk(KERN_ERR "MACE: can't map TX DMA resources !\n");
176 rc = -ENOMEM;
177 goto err_unmap_io;
178 }
179 mp->tx_dma_intr = macio_irq(mdev, 1);
180
181 mp->rx_dma = ioremap(macio_resource_start(mdev, 2), 0x1000);
182 if (mp->rx_dma == NULL) {
183 printk(KERN_ERR "MACE: can't map RX DMA resources !\n");
184 rc = -ENOMEM;
185 goto err_unmap_tx_dma;
186 }
187 mp->rx_dma_intr = macio_irq(mdev, 2);
188
189 mp->tx_cmds = (volatile struct dbdma_cmd *) DBDMA_ALIGN(mp + 1);
190 mp->rx_cmds = mp->tx_cmds + NCMDS_TX * N_TX_RING + 1;
191
192 memset(&mp->stats, 0, sizeof(mp->stats));
193 memset((char *) mp->tx_cmds, 0,
194 (NCMDS_TX*N_TX_RING + N_RX_RING + 2) * sizeof(struct dbdma_cmd));
195 init_timer(&mp->tx_timeout);
196 spin_lock_init(&mp->lock);
197 mp->timeout_active = 0;
198
199 if (port_aaui >= 0)
200 mp->port_aaui = port_aaui;
201 else {
202 /* Apple Network Server uses the AAUI port */
203 if (machine_is_compatible("AAPL,ShinerESB"))
204 mp->port_aaui = 1;
205 else {
206 #ifdef CONFIG_MACE_AAUI_PORT
207 mp->port_aaui = 1;
208 #else
209 mp->port_aaui = 0;
210 #endif
211 }
212 }
213
214 dev->open = mace_open;
215 dev->stop = mace_close;
216 dev->hard_start_xmit = mace_xmit_start;
217 dev->get_stats = mace_stats;
218 dev->set_multicast_list = mace_set_multicast;
219 dev->set_mac_address = mace_set_address;
220
221 /*
222 * Most of what is below could be moved to mace_open()
223 */
224 mace_reset(dev);
225
226 rc = request_irq(dev->irq, mace_interrupt, 0, "MACE", dev);
227 if (rc) {
228 printk(KERN_ERR "MACE: can't get irq %d\n", dev->irq);
229 goto err_unmap_rx_dma;
230 }
231 rc = request_irq(mp->tx_dma_intr, mace_txdma_intr, 0, "MACE-txdma", dev);
232 if (rc) {
233 printk(KERN_ERR "MACE: can't get irq %d\n", mp->tx_dma_intr);
234 goto err_free_irq;
235 }
236 rc = request_irq(mp->rx_dma_intr, mace_rxdma_intr, 0, "MACE-rxdma", dev);
237 if (rc) {
238 printk(KERN_ERR "MACE: can't get irq %d\n", mp->rx_dma_intr);
239 goto err_free_tx_irq;
240 }
241
242 rc = register_netdev(dev);
243 if (rc) {
244 printk(KERN_ERR "MACE: Cannot register net device, aborting.\n");
245 goto err_free_rx_irq;
246 }
247
248 printk(KERN_INFO "%s: MACE at", dev->name);
249 for (j = 0; j < 6; ++j) {
250 printk("%c%.2x", (j? ':': ' '), dev->dev_addr[j]);
251 }
252 printk(", chip revision %d.%d\n", mp->chipid >> 8, mp->chipid & 0xff);
253
254 return 0;
255
256 err_free_rx_irq:
257 free_irq(macio_irq(mdev, 2), dev);
258 err_free_tx_irq:
259 free_irq(macio_irq(mdev, 1), dev);
260 err_free_irq:
261 free_irq(macio_irq(mdev, 0), dev);
262 err_unmap_rx_dma:
263 iounmap(mp->rx_dma);
264 err_unmap_tx_dma:
265 iounmap(mp->tx_dma);
266 err_unmap_io:
267 iounmap(mp->mace);
268 err_free:
269 free_netdev(dev);
270 err_release:
271 macio_release_resources(mdev);
272
273 return rc;
274 }
275
276 static int __devexit mace_remove(struct macio_dev *mdev)
277 {
278 struct net_device *dev = macio_get_drvdata(mdev);
279 struct mace_data *mp;
280
281 BUG_ON(dev == NULL);
282
283 macio_set_drvdata(mdev, NULL);
284
285 mp = dev->priv;
286
287 unregister_netdev(dev);
288
289 free_irq(dev->irq, dev);
290 free_irq(mp->tx_dma_intr, dev);
291 free_irq(mp->rx_dma_intr, dev);
292
293 iounmap(mp->rx_dma);
294 iounmap(mp->tx_dma);
295 iounmap(mp->mace);
296
297 free_netdev(dev);
298
299 macio_release_resources(mdev);
300
301 return 0;
302 }
303
304 static void dbdma_reset(volatile struct dbdma_regs __iomem *dma)
305 {
306 int i;
307
308 out_le32(&dma->control, (WAKE|FLUSH|PAUSE|RUN) << 16);
309
310 /*
311 * Yes this looks peculiar, but apparently it needs to be this
312 * way on some machines.
313 */
314 for (i = 200; i > 0; --i)
315 if (ld_le32(&dma->control) & RUN)
316 udelay(1);
317 }
318
319 static void mace_reset(struct net_device *dev)
320 {
321 struct mace_data *mp = (struct mace_data *) dev->priv;
322 volatile struct mace __iomem *mb = mp->mace;
323 int i;
324
325 /* soft-reset the chip */
326 i = 200;
327 while (--i) {
328 out_8(&mb->biucc, SWRST);
329 if (in_8(&mb->biucc) & SWRST) {
330 udelay(10);
331 continue;
332 }
333 break;
334 }
335 if (!i) {
336 printk(KERN_ERR "mace: cannot reset chip!\n");
337 return;
338 }
339
340 out_8(&mb->imr, 0xff); /* disable all intrs for now */
341 i = in_8(&mb->ir);
342 out_8(&mb->maccc, 0); /* turn off tx, rx */
343
344 out_8(&mb->biucc, XMTSP_64);
345 out_8(&mb->utr, RTRD);
346 out_8(&mb->fifocc, RCVFW_32 | XMTFW_16 | XMTFWU | RCVFWU | XMTBRST);
347 out_8(&mb->xmtfc, AUTO_PAD_XMIT); /* auto-pad short frames */
348 out_8(&mb->rcvfc, 0);
349
350 /* load up the hardware address */
351 __mace_set_address(dev, dev->dev_addr);
352
353 /* clear the multicast filter */
354 if (mp->chipid == BROKEN_ADDRCHG_REV)
355 out_8(&mb->iac, LOGADDR);
356 else {
357 out_8(&mb->iac, ADDRCHG | LOGADDR);
358 while ((in_8(&mb->iac) & ADDRCHG) != 0)
359 ;
360 }
361 for (i = 0; i < 8; ++i)
362 out_8(&mb->ladrf, 0);
363
364 /* done changing address */
365 if (mp->chipid != BROKEN_ADDRCHG_REV)
366 out_8(&mb->iac, 0);
367
368 if (mp->port_aaui)
369 out_8(&mb->plscc, PORTSEL_AUI + ENPLSIO);
370 else
371 out_8(&mb->plscc, PORTSEL_GPSI + ENPLSIO);
372 }
373
374 static void __mace_set_address(struct net_device *dev, void *addr)
375 {
376 struct mace_data *mp = (struct mace_data *) dev->priv;
377 volatile struct mace __iomem *mb = mp->mace;
378 unsigned char *p = addr;
379 int i;
380
381 /* load up the hardware address */
382 if (mp->chipid == BROKEN_ADDRCHG_REV)
383 out_8(&mb->iac, PHYADDR);
384 else {
385 out_8(&mb->iac, ADDRCHG | PHYADDR);
386 while ((in_8(&mb->iac) & ADDRCHG) != 0)
387 ;
388 }
389 for (i = 0; i < 6; ++i)
390 out_8(&mb->padr, dev->dev_addr[i] = p[i]);
391 if (mp->chipid != BROKEN_ADDRCHG_REV)
392 out_8(&mb->iac, 0);
393 }
394
395 static int mace_set_address(struct net_device *dev, void *addr)
396 {
397 struct mace_data *mp = (struct mace_data *) dev->priv;
398 volatile struct mace __iomem *mb = mp->mace;
399 unsigned long flags;
400
401 spin_lock_irqsave(&mp->lock, flags);
402
403 __mace_set_address(dev, addr);
404
405 /* note: setting ADDRCHG clears ENRCV */
406 out_8(&mb->maccc, mp->maccc);
407
408 spin_unlock_irqrestore(&mp->lock, flags);
409 return 0;
410 }
411
412 static inline void mace_clean_rings(struct mace_data *mp)
413 {
414 int i;
415
416 /* free some skb's */
417 for (i = 0; i < N_RX_RING; ++i) {
418 if (mp->rx_bufs[i] != 0) {
419 dev_kfree_skb(mp->rx_bufs[i]);
420 mp->rx_bufs[i] = NULL;
421 }
422 }
423 for (i = mp->tx_empty; i != mp->tx_fill; ) {
424 dev_kfree_skb(mp->tx_bufs[i]);
425 if (++i >= N_TX_RING)
426 i = 0;
427 }
428 }
429
430 static int mace_open(struct net_device *dev)
431 {
432 struct mace_data *mp = (struct mace_data *) dev->priv;
433 volatile struct mace __iomem *mb = mp->mace;
434 volatile struct dbdma_regs __iomem *rd = mp->rx_dma;
435 volatile struct dbdma_regs __iomem *td = mp->tx_dma;
436 volatile struct dbdma_cmd *cp;
437 int i;
438 struct sk_buff *skb;
439 unsigned char *data;
440
441 /* reset the chip */
442 mace_reset(dev);
443
444 /* initialize list of sk_buffs for receiving and set up recv dma */
445 mace_clean_rings(mp);
446 memset((char *)mp->rx_cmds, 0, N_RX_RING * sizeof(struct dbdma_cmd));
447 cp = mp->rx_cmds;
448 for (i = 0; i < N_RX_RING - 1; ++i) {
449 skb = dev_alloc_skb(RX_BUFLEN + 2);
450 if (skb == 0) {
451 data = dummy_buf;
452 } else {
453 skb_reserve(skb, 2); /* so IP header lands on 4-byte bdry */
454 data = skb->data;
455 }
456 mp->rx_bufs[i] = skb;
457 st_le16(&cp->req_count, RX_BUFLEN);
458 st_le16(&cp->command, INPUT_LAST + INTR_ALWAYS);
459 st_le32(&cp->phy_addr, virt_to_bus(data));
460 cp->xfer_status = 0;
461 ++cp;
462 }
463 mp->rx_bufs[i] = NULL;
464 st_le16(&cp->command, DBDMA_STOP);
465 mp->rx_fill = i;
466 mp->rx_empty = 0;
467
468 /* Put a branch back to the beginning of the receive command list */
469 ++cp;
470 st_le16(&cp->command, DBDMA_NOP + BR_ALWAYS);
471 st_le32(&cp->cmd_dep, virt_to_bus(mp->rx_cmds));
472
473 /* start rx dma */
474 out_le32(&rd->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* clear run bit */
475 out_le32(&rd->cmdptr, virt_to_bus(mp->rx_cmds));
476 out_le32(&rd->control, (RUN << 16) | RUN);
477
478 /* put a branch at the end of the tx command list */
479 cp = mp->tx_cmds + NCMDS_TX * N_TX_RING;
480 st_le16(&cp->command, DBDMA_NOP + BR_ALWAYS);
481 st_le32(&cp->cmd_dep, virt_to_bus(mp->tx_cmds));
482
483 /* reset tx dma */
484 out_le32(&td->control, (RUN|PAUSE|FLUSH|WAKE) << 16);
485 out_le32(&td->cmdptr, virt_to_bus(mp->tx_cmds));
486 mp->tx_fill = 0;
487 mp->tx_empty = 0;
488 mp->tx_fullup = 0;
489 mp->tx_active = 0;
490 mp->tx_bad_runt = 0;
491
492 /* turn it on! */
493 out_8(&mb->maccc, mp->maccc);
494 /* enable all interrupts except receive interrupts */
495 out_8(&mb->imr, RCVINT);
496
497 return 0;
498 }
499
500 static int mace_close(struct net_device *dev)
501 {
502 struct mace_data *mp = (struct mace_data *) dev->priv;
503 volatile struct mace __iomem *mb = mp->mace;
504 volatile struct dbdma_regs __iomem *rd = mp->rx_dma;
505 volatile struct dbdma_regs __iomem *td = mp->tx_dma;
506
507 /* disable rx and tx */
508 out_8(&mb->maccc, 0);
509 out_8(&mb->imr, 0xff); /* disable all intrs */
510
511 /* disable rx and tx dma */
512 st_le32(&rd->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* clear run bit */
513 st_le32(&td->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* clear run bit */
514
515 mace_clean_rings(mp);
516
517 return 0;
518 }
519
520 static inline void mace_set_timeout(struct net_device *dev)
521 {
522 struct mace_data *mp = (struct mace_data *) dev->priv;
523
524 if (mp->timeout_active)
525 del_timer(&mp->tx_timeout);
526 mp->tx_timeout.expires = jiffies + TX_TIMEOUT;
527 mp->tx_timeout.function = mace_tx_timeout;
528 mp->tx_timeout.data = (unsigned long) dev;
529 add_timer(&mp->tx_timeout);
530 mp->timeout_active = 1;
531 }
532
533 static int mace_xmit_start(struct sk_buff *skb, struct net_device *dev)
534 {
535 struct mace_data *mp = (struct mace_data *) dev->priv;
536 volatile struct dbdma_regs __iomem *td = mp->tx_dma;
537 volatile struct dbdma_cmd *cp, *np;
538 unsigned long flags;
539 int fill, next, len;
540
541 /* see if there's a free slot in the tx ring */
542 spin_lock_irqsave(&mp->lock, flags);
543 fill = mp->tx_fill;
544 next = fill + 1;
545 if (next >= N_TX_RING)
546 next = 0;
547 if (next == mp->tx_empty) {
548 netif_stop_queue(dev);
549 mp->tx_fullup = 1;
550 spin_unlock_irqrestore(&mp->lock, flags);
551 return 1; /* can't take it at the moment */
552 }
553 spin_unlock_irqrestore(&mp->lock, flags);
554
555 /* partially fill in the dma command block */
556 len = skb->len;
557 if (len > ETH_FRAME_LEN) {
558 printk(KERN_DEBUG "mace: xmit frame too long (%d)\n", len);
559 len = ETH_FRAME_LEN;
560 }
561 mp->tx_bufs[fill] = skb;
562 cp = mp->tx_cmds + NCMDS_TX * fill;
563 st_le16(&cp->req_count, len);
564 st_le32(&cp->phy_addr, virt_to_bus(skb->data));
565
566 np = mp->tx_cmds + NCMDS_TX * next;
567 out_le16(&np->command, DBDMA_STOP);
568
569 /* poke the tx dma channel */
570 spin_lock_irqsave(&mp->lock, flags);
571 mp->tx_fill = next;
572 if (!mp->tx_bad_runt && mp->tx_active < MAX_TX_ACTIVE) {
573 out_le16(&cp->xfer_status, 0);
574 out_le16(&cp->command, OUTPUT_LAST);
575 out_le32(&td->control, ((RUN|WAKE) << 16) + (RUN|WAKE));
576 ++mp->tx_active;
577 mace_set_timeout(dev);
578 }
579 if (++next >= N_TX_RING)
580 next = 0;
581 if (next == mp->tx_empty)
582 netif_stop_queue(dev);
583 spin_unlock_irqrestore(&mp->lock, flags);
584
585 return 0;
586 }
587
588 static struct net_device_stats *mace_stats(struct net_device *dev)
589 {
590 struct mace_data *p = (struct mace_data *) dev->priv;
591
592 return &p->stats;
593 }
594
595 static void mace_set_multicast(struct net_device *dev)
596 {
597 struct mace_data *mp = (struct mace_data *) dev->priv;
598 volatile struct mace __iomem *mb = mp->mace;
599 int i, j;
600 u32 crc;
601 unsigned long flags;
602
603 spin_lock_irqsave(&mp->lock, flags);
604 mp->maccc &= ~PROM;
605 if (dev->flags & IFF_PROMISC) {
606 mp->maccc |= PROM;
607 } else {
608 unsigned char multicast_filter[8];
609 struct dev_mc_list *dmi = dev->mc_list;
610
611 if (dev->flags & IFF_ALLMULTI) {
612 for (i = 0; i < 8; i++)
613 multicast_filter[i] = 0xff;
614 } else {
615 for (i = 0; i < 8; i++)
616 multicast_filter[i] = 0;
617 for (i = 0; i < dev->mc_count; i++) {
618 crc = ether_crc_le(6, dmi->dmi_addr);
619 j = crc >> 26; /* bit number in multicast_filter */
620 multicast_filter[j >> 3] |= 1 << (j & 7);
621 dmi = dmi->next;
622 }
623 }
624 #if 0
625 printk("Multicast filter :");
626 for (i = 0; i < 8; i++)
627 printk("%02x ", multicast_filter[i]);
628 printk("\n");
629 #endif
630
631 if (mp->chipid == BROKEN_ADDRCHG_REV)
632 out_8(&mb->iac, LOGADDR);
633 else {
634 out_8(&mb->iac, ADDRCHG | LOGADDR);
635 while ((in_8(&mb->iac) & ADDRCHG) != 0)
636 ;
637 }
638 for (i = 0; i < 8; ++i)
639 out_8(&mb->ladrf, multicast_filter[i]);
640 if (mp->chipid != BROKEN_ADDRCHG_REV)
641 out_8(&mb->iac, 0);
642 }
643 /* reset maccc */
644 out_8(&mb->maccc, mp->maccc);
645 spin_unlock_irqrestore(&mp->lock, flags);
646 }
647
648 static void mace_handle_misc_intrs(struct mace_data *mp, int intr)
649 {
650 volatile struct mace __iomem *mb = mp->mace;
651 static int mace_babbles, mace_jabbers;
652
653 if (intr & MPCO)
654 mp->stats.rx_missed_errors += 256;
655 mp->stats.rx_missed_errors += in_8(&mb->mpc); /* reading clears it */
656 if (intr & RNTPCO)
657 mp->stats.rx_length_errors += 256;
658 mp->stats.rx_length_errors += in_8(&mb->rntpc); /* reading clears it */
659 if (intr & CERR)
660 ++mp->stats.tx_heartbeat_errors;
661 if (intr & BABBLE)
662 if (mace_babbles++ < 4)
663 printk(KERN_DEBUG "mace: babbling transmitter\n");
664 if (intr & JABBER)
665 if (mace_jabbers++ < 4)
666 printk(KERN_DEBUG "mace: jabbering transceiver\n");
667 }
668
669 static irqreturn_t mace_interrupt(int irq, void *dev_id)
670 {
671 struct net_device *dev = (struct net_device *) dev_id;
672 struct mace_data *mp = (struct mace_data *) dev->priv;
673 volatile struct mace __iomem *mb = mp->mace;
674 volatile struct dbdma_regs __iomem *td = mp->tx_dma;
675 volatile struct dbdma_cmd *cp;
676 int intr, fs, i, stat, x;
677 int xcount, dstat;
678 unsigned long flags;
679 /* static int mace_last_fs, mace_last_xcount; */
680
681 spin_lock_irqsave(&mp->lock, flags);
682 intr = in_8(&mb->ir); /* read interrupt register */
683 in_8(&mb->xmtrc); /* get retries */
684 mace_handle_misc_intrs(mp, intr);
685
686 i = mp->tx_empty;
687 while (in_8(&mb->pr) & XMTSV) {
688 del_timer(&mp->tx_timeout);
689 mp->timeout_active = 0;
690 /*
691 * Clear any interrupt indication associated with this status
692 * word. This appears to unlatch any error indication from
693 * the DMA controller.
694 */
695 intr = in_8(&mb->ir);
696 if (intr != 0)
697 mace_handle_misc_intrs(mp, intr);
698 if (mp->tx_bad_runt) {
699 fs = in_8(&mb->xmtfs);
700 mp->tx_bad_runt = 0;
701 out_8(&mb->xmtfc, AUTO_PAD_XMIT);
702 continue;
703 }
704 dstat = ld_le32(&td->status);
705 /* stop DMA controller */
706 out_le32(&td->control, RUN << 16);
707 /*
708 * xcount is the number of complete frames which have been
709 * written to the fifo but for which status has not been read.
710 */
711 xcount = (in_8(&mb->fifofc) >> XMTFC_SH) & XMTFC_MASK;
712 if (xcount == 0 || (dstat & DEAD)) {
713 /*
714 * If a packet was aborted before the DMA controller has
715 * finished transferring it, it seems that there are 2 bytes
716 * which are stuck in some buffer somewhere. These will get
717 * transmitted as soon as we read the frame status (which
718 * reenables the transmit data transfer request). Turning
719 * off the DMA controller and/or resetting the MACE doesn't
720 * help. So we disable auto-padding and FCS transmission
721 * so the two bytes will only be a runt packet which should
722 * be ignored by other stations.
723 */
724 out_8(&mb->xmtfc, DXMTFCS);
725 }
726 fs = in_8(&mb->xmtfs);
727 if ((fs & XMTSV) == 0) {
728 printk(KERN_ERR "mace: xmtfs not valid! (fs=%x xc=%d ds=%x)\n",
729 fs, xcount, dstat);
730 mace_reset(dev);
731 /*
732 * XXX mace likes to hang the machine after a xmtfs error.
733 * This is hard to reproduce, reseting *may* help
734 */
735 }
736 cp = mp->tx_cmds + NCMDS_TX * i;
737 stat = ld_le16(&cp->xfer_status);
738 if ((fs & (UFLO|LCOL|LCAR|RTRY)) || (dstat & DEAD) || xcount == 0) {
739 /*
740 * Check whether there were in fact 2 bytes written to
741 * the transmit FIFO.
742 */
743 udelay(1);
744 x = (in_8(&mb->fifofc) >> XMTFC_SH) & XMTFC_MASK;
745 if (x != 0) {
746 /* there were two bytes with an end-of-packet indication */
747 mp->tx_bad_runt = 1;
748 mace_set_timeout(dev);
749 } else {
750 /*
751 * Either there weren't the two bytes buffered up, or they
752 * didn't have an end-of-packet indication.
753 * We flush the transmit FIFO just in case (by setting the
754 * XMTFWU bit with the transmitter disabled).
755 */
756 out_8(&mb->maccc, in_8(&mb->maccc) & ~ENXMT);
757 out_8(&mb->fifocc, in_8(&mb->fifocc) | XMTFWU);
758 udelay(1);
759 out_8(&mb->maccc, in_8(&mb->maccc) | ENXMT);
760 out_8(&mb->xmtfc, AUTO_PAD_XMIT);
761 }
762 }
763 /* dma should have finished */
764 if (i == mp->tx_fill) {
765 printk(KERN_DEBUG "mace: tx ring ran out? (fs=%x xc=%d ds=%x)\n",
766 fs, xcount, dstat);
767 continue;
768 }
769 /* Update stats */
770 if (fs & (UFLO|LCOL|LCAR|RTRY)) {
771 ++mp->stats.tx_errors;
772 if (fs & LCAR)
773 ++mp->stats.tx_carrier_errors;
774 if (fs & (UFLO|LCOL|RTRY))
775 ++mp->stats.tx_aborted_errors;
776 } else {
777 mp->stats.tx_bytes += mp->tx_bufs[i]->len;
778 ++mp->stats.tx_packets;
779 }
780 dev_kfree_skb_irq(mp->tx_bufs[i]);
781 --mp->tx_active;
782 if (++i >= N_TX_RING)
783 i = 0;
784 #if 0
785 mace_last_fs = fs;
786 mace_last_xcount = xcount;
787 #endif
788 }
789
790 if (i != mp->tx_empty) {
791 mp->tx_fullup = 0;
792 netif_wake_queue(dev);
793 }
794 mp->tx_empty = i;
795 i += mp->tx_active;
796 if (i >= N_TX_RING)
797 i -= N_TX_RING;
798 if (!mp->tx_bad_runt && i != mp->tx_fill && mp->tx_active < MAX_TX_ACTIVE) {
799 do {
800 /* set up the next one */
801 cp = mp->tx_cmds + NCMDS_TX * i;
802 out_le16(&cp->xfer_status, 0);
803 out_le16(&cp->command, OUTPUT_LAST);
804 ++mp->tx_active;
805 if (++i >= N_TX_RING)
806 i = 0;
807 } while (i != mp->tx_fill && mp->tx_active < MAX_TX_ACTIVE);
808 out_le32(&td->control, ((RUN|WAKE) << 16) + (RUN|WAKE));
809 mace_set_timeout(dev);
810 }
811 spin_unlock_irqrestore(&mp->lock, flags);
812 return IRQ_HANDLED;
813 }
814
815 static void mace_tx_timeout(unsigned long data)
816 {
817 struct net_device *dev = (struct net_device *) data;
818 struct mace_data *mp = (struct mace_data *) dev->priv;
819 volatile struct mace __iomem *mb = mp->mace;
820 volatile struct dbdma_regs __iomem *td = mp->tx_dma;
821 volatile struct dbdma_regs __iomem *rd = mp->rx_dma;
822 volatile struct dbdma_cmd *cp;
823 unsigned long flags;
824 int i;
825
826 spin_lock_irqsave(&mp->lock, flags);
827 mp->timeout_active = 0;
828 if (mp->tx_active == 0 && !mp->tx_bad_runt)
829 goto out;
830
831 /* update various counters */
832 mace_handle_misc_intrs(mp, in_8(&mb->ir));
833
834 cp = mp->tx_cmds + NCMDS_TX * mp->tx_empty;
835
836 /* turn off both tx and rx and reset the chip */
837 out_8(&mb->maccc, 0);
838 printk(KERN_ERR "mace: transmit timeout - resetting\n");
839 dbdma_reset(td);
840 mace_reset(dev);
841
842 /* restart rx dma */
843 cp = bus_to_virt(ld_le32(&rd->cmdptr));
844 dbdma_reset(rd);
845 out_le16(&cp->xfer_status, 0);
846 out_le32(&rd->cmdptr, virt_to_bus(cp));
847 out_le32(&rd->control, (RUN << 16) | RUN);
848
849 /* fix up the transmit side */
850 i = mp->tx_empty;
851 mp->tx_active = 0;
852 ++mp->stats.tx_errors;
853 if (mp->tx_bad_runt) {
854 mp->tx_bad_runt = 0;
855 } else if (i != mp->tx_fill) {
856 dev_kfree_skb(mp->tx_bufs[i]);
857 if (++i >= N_TX_RING)
858 i = 0;
859 mp->tx_empty = i;
860 }
861 mp->tx_fullup = 0;
862 netif_wake_queue(dev);
863 if (i != mp->tx_fill) {
864 cp = mp->tx_cmds + NCMDS_TX * i;
865 out_le16(&cp->xfer_status, 0);
866 out_le16(&cp->command, OUTPUT_LAST);
867 out_le32(&td->cmdptr, virt_to_bus(cp));
868 out_le32(&td->control, (RUN << 16) | RUN);
869 ++mp->tx_active;
870 mace_set_timeout(dev);
871 }
872
873 /* turn it back on */
874 out_8(&mb->imr, RCVINT);
875 out_8(&mb->maccc, mp->maccc);
876
877 out:
878 spin_unlock_irqrestore(&mp->lock, flags);
879 }
880
881 static irqreturn_t mace_txdma_intr(int irq, void *dev_id)
882 {
883 return IRQ_HANDLED;
884 }
885
886 static irqreturn_t mace_rxdma_intr(int irq, void *dev_id)
887 {
888 struct net_device *dev = (struct net_device *) dev_id;
889 struct mace_data *mp = (struct mace_data *) dev->priv;
890 volatile struct dbdma_regs __iomem *rd = mp->rx_dma;
891 volatile struct dbdma_cmd *cp, *np;
892 int i, nb, stat, next;
893 struct sk_buff *skb;
894 unsigned frame_status;
895 static int mace_lost_status;
896 unsigned char *data;
897 unsigned long flags;
898
899 spin_lock_irqsave(&mp->lock, flags);
900 for (i = mp->rx_empty; i != mp->rx_fill; ) {
901 cp = mp->rx_cmds + i;
902 stat = ld_le16(&cp->xfer_status);
903 if ((stat & ACTIVE) == 0) {
904 next = i + 1;
905 if (next >= N_RX_RING)
906 next = 0;
907 np = mp->rx_cmds + next;
908 if (next != mp->rx_fill
909 && (ld_le16(&np->xfer_status) & ACTIVE) != 0) {
910 printk(KERN_DEBUG "mace: lost a status word\n");
911 ++mace_lost_status;
912 } else
913 break;
914 }
915 nb = ld_le16(&cp->req_count) - ld_le16(&cp->res_count);
916 out_le16(&cp->command, DBDMA_STOP);
917 /* got a packet, have a look at it */
918 skb = mp->rx_bufs[i];
919 if (skb == 0) {
920 ++mp->stats.rx_dropped;
921 } else if (nb > 8) {
922 data = skb->data;
923 frame_status = (data[nb-3] << 8) + data[nb-4];
924 if (frame_status & (RS_OFLO|RS_CLSN|RS_FRAMERR|RS_FCSERR)) {
925 ++mp->stats.rx_errors;
926 if (frame_status & RS_OFLO)
927 ++mp->stats.rx_over_errors;
928 if (frame_status & RS_FRAMERR)
929 ++mp->stats.rx_frame_errors;
930 if (frame_status & RS_FCSERR)
931 ++mp->stats.rx_crc_errors;
932 } else {
933 /* Mace feature AUTO_STRIP_RCV is on by default, dropping the
934 * FCS on frames with 802.3 headers. This means that Ethernet
935 * frames have 8 extra octets at the end, while 802.3 frames
936 * have only 4. We need to correctly account for this. */
937 if (*(unsigned short *)(data+12) < 1536) /* 802.3 header */
938 nb -= 4;
939 else /* Ethernet header; mace includes FCS */
940 nb -= 8;
941 skb_put(skb, nb);
942 skb->dev = dev;
943 skb->protocol = eth_type_trans(skb, dev);
944 mp->stats.rx_bytes += skb->len;
945 netif_rx(skb);
946 dev->last_rx = jiffies;
947 mp->rx_bufs[i] = NULL;
948 ++mp->stats.rx_packets;
949 }
950 } else {
951 ++mp->stats.rx_errors;
952 ++mp->stats.rx_length_errors;
953 }
954
955 /* advance to next */
956 if (++i >= N_RX_RING)
957 i = 0;
958 }
959 mp->rx_empty = i;
960
961 i = mp->rx_fill;
962 for (;;) {
963 next = i + 1;
964 if (next >= N_RX_RING)
965 next = 0;
966 if (next == mp->rx_empty)
967 break;
968 cp = mp->rx_cmds + i;
969 skb = mp->rx_bufs[i];
970 if (skb == 0) {
971 skb = dev_alloc_skb(RX_BUFLEN + 2);
972 if (skb != 0) {
973 skb_reserve(skb, 2);
974 mp->rx_bufs[i] = skb;
975 }
976 }
977 st_le16(&cp->req_count, RX_BUFLEN);
978 data = skb? skb->data: dummy_buf;
979 st_le32(&cp->phy_addr, virt_to_bus(data));
980 out_le16(&cp->xfer_status, 0);
981 out_le16(&cp->command, INPUT_LAST + INTR_ALWAYS);
982 #if 0
983 if ((ld_le32(&rd->status) & ACTIVE) != 0) {
984 out_le32(&rd->control, (PAUSE << 16) | PAUSE);
985 while ((in_le32(&rd->status) & ACTIVE) != 0)
986 ;
987 }
988 #endif
989 i = next;
990 }
991 if (i != mp->rx_fill) {
992 out_le32(&rd->control, ((RUN|WAKE) << 16) | (RUN|WAKE));
993 mp->rx_fill = i;
994 }
995 spin_unlock_irqrestore(&mp->lock, flags);
996 return IRQ_HANDLED;
997 }
998
999 static struct of_device_id mace_match[] =
1000 {
1001 {
1002 .name = "mace",
1003 },
1004 {},
1005 };
1006 MODULE_DEVICE_TABLE (of, mace_match);
1007
1008 static struct macio_driver mace_driver =
1009 {
1010 .name = "mace",
1011 .match_table = mace_match,
1012 .probe = mace_probe,
1013 .remove = mace_remove,
1014 };
1015
1016
1017 static int __init mace_init(void)
1018 {
1019 return macio_register_driver(&mace_driver);
1020 }
1021
1022 static void __exit mace_cleanup(void)
1023 {
1024 macio_unregister_driver(&mace_driver);
1025
1026 kfree(dummy_buf);
1027 dummy_buf = NULL;
1028 }
1029
1030 MODULE_AUTHOR("Paul Mackerras");
1031 MODULE_DESCRIPTION("PowerMac MACE driver.");
1032 module_param(port_aaui, int, 0);
1033 MODULE_PARM_DESC(port_aaui, "MACE uses AAUI port (0-1)");
1034 MODULE_LICENSE("GPL");
1035
1036 module_init(mace_init);
1037 module_exit(mace_cleanup);
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