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MIPS: Alchemy: remove get/set_au1x00_lcd_clock().
[linux-2.6/verdex.git] / arch / mips / include / asm / mach-au1x00 / au1000.h
blobd07632e3230b4d263d68e550dae23be4e82057e0
1 /*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * Include file for Alchemy Semiconductor's Au1k CPU.
5 *
6 * Copyright 2000-2001, 2006-2008 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc. <source@mvista.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 *
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 */
29
30 /*
31 * some definitions add by takuzo@sm.sony.co.jp and sato@sm.sony.co.jp
32 */
33
34 #ifndef _AU1000_H_
35 #define _AU1000_H_
36
37
38 #ifndef _LANGUAGE_ASSEMBLY
39
40 #include <linux/delay.h>
41 #include <linux/types.h>
42
43 #include <linux/io.h>
44 #include <linux/irq.h>
45
46 /* cpu pipeline flush */
47 void static inline au_sync(void)
48 {
49 __asm__ volatile ("sync");
50 }
51
52 void static inline au_sync_udelay(int us)
53 {
54 __asm__ volatile ("sync");
55 udelay(us);
56 }
57
58 void static inline au_sync_delay(int ms)
59 {
60 __asm__ volatile ("sync");
61 mdelay(ms);
62 }
63
64 void static inline au_writeb(u8 val, unsigned long reg)
65 {
66 *(volatile u8 *)reg = val;
67 }
68
69 void static inline au_writew(u16 val, unsigned long reg)
70 {
71 *(volatile u16 *)reg = val;
72 }
73
74 void static inline au_writel(u32 val, unsigned long reg)
75 {
76 *(volatile u32 *)reg = val;
77 }
78
79 static inline u8 au_readb(unsigned long reg)
80 {
81 return *(volatile u8 *)reg;
82 }
83
84 static inline u16 au_readw(unsigned long reg)
85 {
86 return *(volatile u16 *)reg;
87 }
88
89 static inline u32 au_readl(unsigned long reg)
90 {
91 return *(volatile u32 *)reg;
92 }
93
94
95 /* arch/mips/au1000/common/clocks.c */
96 extern void set_au1x00_speed(unsigned int new_freq);
97 extern unsigned int get_au1x00_speed(void);
98 extern void set_au1x00_uart_baud_base(unsigned long new_baud_base);
99 extern unsigned long get_au1x00_uart_baud_base(void);
100
101 /*
102 * Every board describes its IRQ mapping with this table.
103 */
104 struct au1xxx_irqmap {
105 int im_irq;
106 int im_type;
107 int im_request;
108 };
109
110 /* core calls this function to let boards initialize other IRQ sources */
111 void board_init_irq(void);
112
113 /* boards call this to register additional (GPIO) interrupts */
114 void au1xxx_setup_irqmap(struct au1xxx_irqmap *map, int count);
115
116 #endif /* !defined (_LANGUAGE_ASSEMBLY) */
117
118 /*
119 * SDRAM register offsets
120 */
121 #if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || \
122 defined(CONFIG_SOC_AU1100)
123 #define MEM_SDMODE0 0x0000
124 #define MEM_SDMODE1 0x0004
125 #define MEM_SDMODE2 0x0008
126 #define MEM_SDADDR0 0x000C
127 #define MEM_SDADDR1 0x0010
128 #define MEM_SDADDR2 0x0014
129 #define MEM_SDREFCFG 0x0018
130 #define MEM_SDPRECMD 0x001C
131 #define MEM_SDAUTOREF 0x0020
132 #define MEM_SDWRMD0 0x0024
133 #define MEM_SDWRMD1 0x0028
134 #define MEM_SDWRMD2 0x002C
135 #define MEM_SDSLEEP 0x0030
136 #define MEM_SDSMCKE 0x0034
137
138 /*
139 * MEM_SDMODE register content definitions
140 */
141 #define MEM_SDMODE_F (1 << 22)
142 #define MEM_SDMODE_SR (1 << 21)
143 #define MEM_SDMODE_BS (1 << 20)
144 #define MEM_SDMODE_RS (3 << 18)
145 #define MEM_SDMODE_CS (7 << 15)
146 #define MEM_SDMODE_TRAS (15 << 11)
147 #define MEM_SDMODE_TMRD (3 << 9)
148 #define MEM_SDMODE_TWR (3 << 7)
149 #define MEM_SDMODE_TRP (3 << 5)
150 #define MEM_SDMODE_TRCD (3 << 3)
151 #define MEM_SDMODE_TCL (7 << 0)
152
153 #define MEM_SDMODE_BS_2Bank (0 << 20)
154 #define MEM_SDMODE_BS_4Bank (1 << 20)
155 #define MEM_SDMODE_RS_11Row (0 << 18)
156 #define MEM_SDMODE_RS_12Row (1 << 18)
157 #define MEM_SDMODE_RS_13Row (2 << 18)
158 #define MEM_SDMODE_RS_N(N) ((N) << 18)
159 #define MEM_SDMODE_CS_7Col (0 << 15)
160 #define MEM_SDMODE_CS_8Col (1 << 15)
161 #define MEM_SDMODE_CS_9Col (2 << 15)
162 #define MEM_SDMODE_CS_10Col (3 << 15)
163 #define MEM_SDMODE_CS_11Col (4 << 15)
164 #define MEM_SDMODE_CS_N(N) ((N) << 15)
165 #define MEM_SDMODE_TRAS_N(N) ((N) << 11)
166 #define MEM_SDMODE_TMRD_N(N) ((N) << 9)
167 #define MEM_SDMODE_TWR_N(N) ((N) << 7)
168 #define MEM_SDMODE_TRP_N(N) ((N) << 5)
169 #define MEM_SDMODE_TRCD_N(N) ((N) << 3)
170 #define MEM_SDMODE_TCL_N(N) ((N) << 0)
171
172 /*
173 * MEM_SDADDR register contents definitions
174 */
175 #define MEM_SDADDR_E (1 << 20)
176 #define MEM_SDADDR_CSBA (0x03FF << 10)
177 #define MEM_SDADDR_CSMASK (0x03FF << 0)
178 #define MEM_SDADDR_CSBA_N(N) ((N) & (0x03FF << 22) >> 12)
179 #define MEM_SDADDR_CSMASK_N(N) ((N)&(0x03FF << 22) >> 22)
180
181 /*
182 * MEM_SDREFCFG register content definitions
183 */
184 #define MEM_SDREFCFG_TRC (15 << 28)
185 #define MEM_SDREFCFG_TRPM (3 << 26)
186 #define MEM_SDREFCFG_E (1 << 25)
187 #define MEM_SDREFCFG_RE (0x1ffffff << 0)
188 #define MEM_SDREFCFG_TRC_N(N) ((N) << MEM_SDREFCFG_TRC)
189 #define MEM_SDREFCFG_TRPM_N(N) ((N) << MEM_SDREFCFG_TRPM)
190 #define MEM_SDREFCFG_REF_N(N) (N)
191 #endif
192
193 /***********************************************************************/
194
195 /*
196 * Au1550 SDRAM Register Offsets
197 */
198
199 /***********************************************************************/
200
201 #if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
202 #define MEM_SDMODE0 0x0800
203 #define MEM_SDMODE1 0x0808
204 #define MEM_SDMODE2 0x0810
205 #define MEM_SDADDR0 0x0820
206 #define MEM_SDADDR1 0x0828
207 #define MEM_SDADDR2 0x0830
208 #define MEM_SDCONFIGA 0x0840
209 #define MEM_SDCONFIGB 0x0848
210 #define MEM_SDSTAT 0x0850
211 #define MEM_SDERRADDR 0x0858
212 #define MEM_SDSTRIDE0 0x0860
213 #define MEM_SDSTRIDE1 0x0868
214 #define MEM_SDSTRIDE2 0x0870
215 #define MEM_SDWRMD0 0x0880
216 #define MEM_SDWRMD1 0x0888
217 #define MEM_SDWRMD2 0x0890
218 #define MEM_SDPRECMD 0x08C0
219 #define MEM_SDAUTOREF 0x08C8
220 #define MEM_SDSREF 0x08D0
221 #define MEM_SDSLEEP MEM_SDSREF
222
223 #endif
224
225 /*
226 * Physical base addresses for integrated peripherals
227 */
228
229 #ifdef CONFIG_SOC_AU1000
230 #define MEM_PHYS_ADDR 0x14000000
231 #define STATIC_MEM_PHYS_ADDR 0x14001000
232 #define DMA0_PHYS_ADDR 0x14002000
233 #define DMA1_PHYS_ADDR 0x14002100
234 #define DMA2_PHYS_ADDR 0x14002200
235 #define DMA3_PHYS_ADDR 0x14002300
236 #define DMA4_PHYS_ADDR 0x14002400
237 #define DMA5_PHYS_ADDR 0x14002500
238 #define DMA6_PHYS_ADDR 0x14002600
239 #define DMA7_PHYS_ADDR 0x14002700
240 #define IC0_PHYS_ADDR 0x10400000
241 #define IC1_PHYS_ADDR 0x11800000
242 #define AC97_PHYS_ADDR 0x10000000
243 #define USBH_PHYS_ADDR 0x10100000
244 #define USBD_PHYS_ADDR 0x10200000
245 #define IRDA_PHYS_ADDR 0x10300000
246 #define MAC0_PHYS_ADDR 0x10500000
247 #define MAC1_PHYS_ADDR 0x10510000
248 #define MACEN_PHYS_ADDR 0x10520000
249 #define MACDMA0_PHYS_ADDR 0x14004000
250 #define MACDMA1_PHYS_ADDR 0x14004200
251 #define I2S_PHYS_ADDR 0x11000000
252 #define UART0_PHYS_ADDR 0x11100000
253 #define UART1_PHYS_ADDR 0x11200000
254 #define UART2_PHYS_ADDR 0x11300000
255 #define UART3_PHYS_ADDR 0x11400000
256 #define SSI0_PHYS_ADDR 0x11600000
257 #define SSI1_PHYS_ADDR 0x11680000
258 #define SYS_PHYS_ADDR 0x11900000
259 #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
260 #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
261 #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
262 #endif
263
264 /********************************************************************/
265
266 #ifdef CONFIG_SOC_AU1500
267 #define MEM_PHYS_ADDR 0x14000000
268 #define STATIC_MEM_PHYS_ADDR 0x14001000
269 #define DMA0_PHYS_ADDR 0x14002000
270 #define DMA1_PHYS_ADDR 0x14002100
271 #define DMA2_PHYS_ADDR 0x14002200
272 #define DMA3_PHYS_ADDR 0x14002300
273 #define DMA4_PHYS_ADDR 0x14002400
274 #define DMA5_PHYS_ADDR 0x14002500
275 #define DMA6_PHYS_ADDR 0x14002600
276 #define DMA7_PHYS_ADDR 0x14002700
277 #define IC0_PHYS_ADDR 0x10400000
278 #define IC1_PHYS_ADDR 0x11800000
279 #define AC97_PHYS_ADDR 0x10000000
280 #define USBH_PHYS_ADDR 0x10100000
281 #define USBD_PHYS_ADDR 0x10200000
282 #define PCI_PHYS_ADDR 0x14005000
283 #define MAC0_PHYS_ADDR 0x11500000
284 #define MAC1_PHYS_ADDR 0x11510000
285 #define MACEN_PHYS_ADDR 0x11520000
286 #define MACDMA0_PHYS_ADDR 0x14004000
287 #define MACDMA1_PHYS_ADDR 0x14004200
288 #define I2S_PHYS_ADDR 0x11000000
289 #define UART0_PHYS_ADDR 0x11100000
290 #define UART3_PHYS_ADDR 0x11400000
291 #define GPIO2_PHYS_ADDR 0x11700000
292 #define SYS_PHYS_ADDR 0x11900000
293 #define PCI_MEM_PHYS_ADDR 0x400000000ULL
294 #define PCI_IO_PHYS_ADDR 0x500000000ULL
295 #define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL
296 #define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL
297 #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
298 #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
299 #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
300 #endif
301
302 /********************************************************************/
303
304 #ifdef CONFIG_SOC_AU1100
305 #define MEM_PHYS_ADDR 0x14000000
306 #define STATIC_MEM_PHYS_ADDR 0x14001000
307 #define DMA0_PHYS_ADDR 0x14002000
308 #define DMA1_PHYS_ADDR 0x14002100
309 #define DMA2_PHYS_ADDR 0x14002200
310 #define DMA3_PHYS_ADDR 0x14002300
311 #define DMA4_PHYS_ADDR 0x14002400
312 #define DMA5_PHYS_ADDR 0x14002500
313 #define DMA6_PHYS_ADDR 0x14002600
314 #define DMA7_PHYS_ADDR 0x14002700
315 #define IC0_PHYS_ADDR 0x10400000
316 #define SD0_PHYS_ADDR 0x10600000
317 #define SD1_PHYS_ADDR 0x10680000
318 #define IC1_PHYS_ADDR 0x11800000
319 #define AC97_PHYS_ADDR 0x10000000
320 #define USBH_PHYS_ADDR 0x10100000
321 #define USBD_PHYS_ADDR 0x10200000
322 #define IRDA_PHYS_ADDR 0x10300000
323 #define MAC0_PHYS_ADDR 0x10500000
324 #define MACEN_PHYS_ADDR 0x10520000
325 #define MACDMA0_PHYS_ADDR 0x14004000
326 #define MACDMA1_PHYS_ADDR 0x14004200
327 #define I2S_PHYS_ADDR 0x11000000
328 #define UART0_PHYS_ADDR 0x11100000
329 #define UART1_PHYS_ADDR 0x11200000
330 #define UART3_PHYS_ADDR 0x11400000
331 #define SSI0_PHYS_ADDR 0x11600000
332 #define SSI1_PHYS_ADDR 0x11680000
333 #define GPIO2_PHYS_ADDR 0x11700000
334 #define SYS_PHYS_ADDR 0x11900000
335 #define LCD_PHYS_ADDR 0x15000000
336 #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
337 #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
338 #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
339 #endif
340
341 /***********************************************************************/
342
343 #ifdef CONFIG_SOC_AU1550
344 #define MEM_PHYS_ADDR 0x14000000
345 #define STATIC_MEM_PHYS_ADDR 0x14001000
346 #define IC0_PHYS_ADDR 0x10400000
347 #define IC1_PHYS_ADDR 0x11800000
348 #define USBH_PHYS_ADDR 0x14020000
349 #define USBD_PHYS_ADDR 0x10200000
350 #define PCI_PHYS_ADDR 0x14005000
351 #define MAC0_PHYS_ADDR 0x10500000
352 #define MAC1_PHYS_ADDR 0x10510000
353 #define MACEN_PHYS_ADDR 0x10520000
354 #define MACDMA0_PHYS_ADDR 0x14004000
355 #define MACDMA1_PHYS_ADDR 0x14004200
356 #define UART0_PHYS_ADDR 0x11100000
357 #define UART1_PHYS_ADDR 0x11200000
358 #define UART3_PHYS_ADDR 0x11400000
359 #define GPIO2_PHYS_ADDR 0x11700000
360 #define SYS_PHYS_ADDR 0x11900000
361 #define DDMA_PHYS_ADDR 0x14002000
362 #define PE_PHYS_ADDR 0x14008000
363 #define PSC0_PHYS_ADDR 0x11A00000
364 #define PSC1_PHYS_ADDR 0x11B00000
365 #define PSC2_PHYS_ADDR 0x10A00000
366 #define PSC3_PHYS_ADDR 0x10B00000
367 #define PCI_MEM_PHYS_ADDR 0x400000000ULL
368 #define PCI_IO_PHYS_ADDR 0x500000000ULL
369 #define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL
370 #define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL
371 #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
372 #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
373 #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
374 #endif
375
376 /***********************************************************************/
377
378 #ifdef CONFIG_SOC_AU1200
379 #define MEM_PHYS_ADDR 0x14000000
380 #define STATIC_MEM_PHYS_ADDR 0x14001000
381 #define AES_PHYS_ADDR 0x10300000
382 #define CIM_PHYS_ADDR 0x14004000
383 #define IC0_PHYS_ADDR 0x10400000
384 #define IC1_PHYS_ADDR 0x11800000
385 #define USBM_PHYS_ADDR 0x14020000
386 #define USBH_PHYS_ADDR 0x14020100
387 #define UART0_PHYS_ADDR 0x11100000
388 #define UART1_PHYS_ADDR 0x11200000
389 #define GPIO2_PHYS_ADDR 0x11700000
390 #define SYS_PHYS_ADDR 0x11900000
391 #define DDMA_PHYS_ADDR 0x14002000
392 #define PSC0_PHYS_ADDR 0x11A00000
393 #define PSC1_PHYS_ADDR 0x11B00000
394 #define SD0_PHYS_ADDR 0x10600000
395 #define SD1_PHYS_ADDR 0x10680000
396 #define LCD_PHYS_ADDR 0x15000000
397 #define SWCNT_PHYS_ADDR 0x1110010C
398 #define MAEFE_PHYS_ADDR 0x14012000
399 #define MAEBE_PHYS_ADDR 0x14010000
400 #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
401 #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
402 #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
403 #endif
404
405 /* Static Bus Controller */
406 #define MEM_STCFG0 0xB4001000
407 #define MEM_STTIME0 0xB4001004
408 #define MEM_STADDR0 0xB4001008
409
410 #define MEM_STCFG1 0xB4001010
411 #define MEM_STTIME1 0xB4001014
412 #define MEM_STADDR1 0xB4001018
413
414 #define MEM_STCFG2 0xB4001020
415 #define MEM_STTIME2 0xB4001024
416 #define MEM_STADDR2 0xB4001028
417
418 #define MEM_STCFG3 0xB4001030
419 #define MEM_STTIME3 0xB4001034
420 #define MEM_STADDR3 0xB4001038
421
422 #if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
423 #define MEM_STNDCTL 0xB4001100
424 #define MEM_STSTAT 0xB4001104
425
426 #define MEM_STNAND_CMD 0x0
427 #define MEM_STNAND_ADDR 0x4
428 #define MEM_STNAND_DATA 0x20
429 #endif
430
431 /* Interrupt Controller 0 */
432 #define IC0_CFG0RD 0xB0400040
433 #define IC0_CFG0SET 0xB0400040
434 #define IC0_CFG0CLR 0xB0400044
435
436 #define IC0_CFG1RD 0xB0400048
437 #define IC0_CFG1SET 0xB0400048
438 #define IC0_CFG1CLR 0xB040004C
439
440 #define IC0_CFG2RD 0xB0400050
441 #define IC0_CFG2SET 0xB0400050
442 #define IC0_CFG2CLR 0xB0400054
443
444 #define IC0_REQ0INT 0xB0400054
445 #define IC0_SRCRD 0xB0400058
446 #define IC0_SRCSET 0xB0400058
447 #define IC0_SRCCLR 0xB040005C
448 #define IC0_REQ1INT 0xB040005C
449
450 #define IC0_ASSIGNRD 0xB0400060
451 #define IC0_ASSIGNSET 0xB0400060
452 #define IC0_ASSIGNCLR 0xB0400064
453
454 #define IC0_WAKERD 0xB0400068
455 #define IC0_WAKESET 0xB0400068
456 #define IC0_WAKECLR 0xB040006C
457
458 #define IC0_MASKRD 0xB0400070
459 #define IC0_MASKSET 0xB0400070
460 #define IC0_MASKCLR 0xB0400074
461
462 #define IC0_RISINGRD 0xB0400078
463 #define IC0_RISINGCLR 0xB0400078
464 #define IC0_FALLINGRD 0xB040007C
465 #define IC0_FALLINGCLR 0xB040007C
466
467 #define IC0_TESTBIT 0xB0400080
468
469 /* Interrupt Controller 1 */
470 #define IC1_CFG0RD 0xB1800040
471 #define IC1_CFG0SET 0xB1800040
472 #define IC1_CFG0CLR 0xB1800044
473
474 #define IC1_CFG1RD 0xB1800048
475 #define IC1_CFG1SET 0xB1800048
476 #define IC1_CFG1CLR 0xB180004C
477
478 #define IC1_CFG2RD 0xB1800050
479 #define IC1_CFG2SET 0xB1800050
480 #define IC1_CFG2CLR 0xB1800054
481
482 #define IC1_REQ0INT 0xB1800054
483 #define IC1_SRCRD 0xB1800058
484 #define IC1_SRCSET 0xB1800058
485 #define IC1_SRCCLR 0xB180005C
486 #define IC1_REQ1INT 0xB180005C
487
488 #define IC1_ASSIGNRD 0xB1800060
489 #define IC1_ASSIGNSET 0xB1800060
490 #define IC1_ASSIGNCLR 0xB1800064
491
492 #define IC1_WAKERD 0xB1800068
493 #define IC1_WAKESET 0xB1800068
494 #define IC1_WAKECLR 0xB180006C
495
496 #define IC1_MASKRD 0xB1800070
497 #define IC1_MASKSET 0xB1800070
498 #define IC1_MASKCLR 0xB1800074
499
500 #define IC1_RISINGRD 0xB1800078
501 #define IC1_RISINGCLR 0xB1800078
502 #define IC1_FALLINGRD 0xB180007C
503 #define IC1_FALLINGCLR 0xB180007C
504
505 #define IC1_TESTBIT 0xB1800080
506
507 /* Interrupt Numbers */
508 /* Au1000 */
509 #ifdef CONFIG_SOC_AU1000
510 enum soc_au1000_ints {
511 AU1000_FIRST_INT = MIPS_CPU_IRQ_BASE + 8,
512 AU1000_UART0_INT = AU1000_FIRST_INT,
513 AU1000_UART1_INT, /* au1000 */
514 AU1000_UART2_INT, /* au1000 */
515 AU1000_UART3_INT,
516 AU1000_SSI0_INT, /* au1000 */
517 AU1000_SSI1_INT, /* au1000 */
518 AU1000_DMA_INT_BASE,
519
520 AU1000_TOY_INT = AU1000_FIRST_INT + 14,
521 AU1000_TOY_MATCH0_INT,
522 AU1000_TOY_MATCH1_INT,
523 AU1000_TOY_MATCH2_INT,
524 AU1000_RTC_INT,
525 AU1000_RTC_MATCH0_INT,
526 AU1000_RTC_MATCH1_INT,
527 AU1000_RTC_MATCH2_INT,
528 AU1000_IRDA_TX_INT, /* au1000 */
529 AU1000_IRDA_RX_INT, /* au1000 */
530 AU1000_USB_DEV_REQ_INT,
531 AU1000_USB_DEV_SUS_INT,
532 AU1000_USB_HOST_INT,
533 AU1000_ACSYNC_INT,
534 AU1000_MAC0_DMA_INT,
535 AU1000_MAC1_DMA_INT,
536 AU1000_I2S_UO_INT, /* au1000 */
537 AU1000_AC97C_INT,
538 AU1000_GPIO_0,
539 AU1000_GPIO_1,
540 AU1000_GPIO_2,
541 AU1000_GPIO_3,
542 AU1000_GPIO_4,
543 AU1000_GPIO_5,
544 AU1000_GPIO_6,
545 AU1000_GPIO_7,
546 AU1000_GPIO_8,
547 AU1000_GPIO_9,
548 AU1000_GPIO_10,
549 AU1000_GPIO_11,
550 AU1000_GPIO_12,
551 AU1000_GPIO_13,
552 AU1000_GPIO_14,
553 AU1000_GPIO_15,
554 AU1000_GPIO_16,
555 AU1000_GPIO_17,
556 AU1000_GPIO_18,
557 AU1000_GPIO_19,
558 AU1000_GPIO_20,
559 AU1000_GPIO_21,
560 AU1000_GPIO_22,
561 AU1000_GPIO_23,
562 AU1000_GPIO_24,
563 AU1000_GPIO_25,
564 AU1000_GPIO_26,
565 AU1000_GPIO_27,
566 AU1000_GPIO_28,
567 AU1000_GPIO_29,
568 AU1000_GPIO_30,
569 AU1000_GPIO_31,
570 };
571
572 #define UART0_ADDR 0xB1100000
573 #define UART1_ADDR 0xB1200000
574 #define UART2_ADDR 0xB1300000
575 #define UART3_ADDR 0xB1400000
576
577 #define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */
578 #define USB_HOST_CONFIG 0xB017FFFC
579
580 #define AU1000_ETH0_BASE 0xB0500000
581 #define AU1000_ETH1_BASE 0xB0510000
582 #define AU1000_MAC0_ENABLE 0xB0520000
583 #define AU1000_MAC1_ENABLE 0xB0520004
584 #define NUM_ETH_INTERFACES 2
585 #endif /* CONFIG_SOC_AU1000 */
586
587 /* Au1500 */
588 #ifdef CONFIG_SOC_AU1500
589 enum soc_au1500_ints {
590 AU1500_FIRST_INT = MIPS_CPU_IRQ_BASE + 8,
591 AU1500_UART0_INT = AU1500_FIRST_INT,
592 AU1000_PCI_INTA, /* au1500 */
593 AU1000_PCI_INTB, /* au1500 */
594 AU1500_UART3_INT,
595 AU1000_PCI_INTC, /* au1500 */
596 AU1000_PCI_INTD, /* au1500 */
597 AU1000_DMA_INT_BASE,
598
599 AU1000_TOY_INT = AU1500_FIRST_INT + 14,
600 AU1000_TOY_MATCH0_INT,
601 AU1000_TOY_MATCH1_INT,
602 AU1000_TOY_MATCH2_INT,
603 AU1000_RTC_INT,
604 AU1000_RTC_MATCH0_INT,
605 AU1000_RTC_MATCH1_INT,
606 AU1000_RTC_MATCH2_INT,
607 AU1500_PCI_ERR_INT,
608 AU1500_RESERVED_INT,
609 AU1000_USB_DEV_REQ_INT,
610 AU1000_USB_DEV_SUS_INT,
611 AU1000_USB_HOST_INT,
612 AU1000_ACSYNC_INT,
613 AU1500_MAC0_DMA_INT,
614 AU1500_MAC1_DMA_INT,
615 AU1000_AC97C_INT = AU1500_FIRST_INT + 31,
616 AU1000_GPIO_0,
617 AU1000_GPIO_1,
618 AU1000_GPIO_2,
619 AU1000_GPIO_3,
620 AU1000_GPIO_4,
621 AU1000_GPIO_5,
622 AU1000_GPIO_6,
623 AU1000_GPIO_7,
624 AU1000_GPIO_8,
625 AU1000_GPIO_9,
626 AU1000_GPIO_10,
627 AU1000_GPIO_11,
628 AU1000_GPIO_12,
629 AU1000_GPIO_13,
630 AU1000_GPIO_14,
631 AU1000_GPIO_15,
632 AU1500_GPIO_200,
633 AU1500_GPIO_201,
634 AU1500_GPIO_202,
635 AU1500_GPIO_203,
636 AU1500_GPIO_20,
637 AU1500_GPIO_204,
638 AU1500_GPIO_205,
639 AU1500_GPIO_23,
640 AU1500_GPIO_24,
641 AU1500_GPIO_25,
642 AU1500_GPIO_26,
643 AU1500_GPIO_27,
644 AU1500_GPIO_28,
645 AU1500_GPIO_206,
646 AU1500_GPIO_207,
647 AU1500_GPIO_208_215,
648 };
649
650 /* shortcuts */
651 #define INTA AU1000_PCI_INTA
652 #define INTB AU1000_PCI_INTB
653 #define INTC AU1000_PCI_INTC
654 #define INTD AU1000_PCI_INTD
655
656 #define UART0_ADDR 0xB1100000
657 #define UART3_ADDR 0xB1400000
658
659 #define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */
660 #define USB_HOST_CONFIG 0xB017fffc
661
662 #define AU1500_ETH0_BASE 0xB1500000
663 #define AU1500_ETH1_BASE 0xB1510000
664 #define AU1500_MAC0_ENABLE 0xB1520000
665 #define AU1500_MAC1_ENABLE 0xB1520004
666 #define NUM_ETH_INTERFACES 2
667 #endif /* CONFIG_SOC_AU1500 */
668
669 /* Au1100 */
670 #ifdef CONFIG_SOC_AU1100
671 enum soc_au1100_ints {
672 AU1100_FIRST_INT = MIPS_CPU_IRQ_BASE + 8,
673 AU1100_UART0_INT,
674 AU1100_UART1_INT,
675 AU1100_SD_INT,
676 AU1100_UART3_INT,
677 AU1000_SSI0_INT,
678 AU1000_SSI1_INT,
679 AU1000_DMA_INT_BASE,
680
681 AU1000_TOY_INT = AU1100_FIRST_INT + 14,
682 AU1000_TOY_MATCH0_INT,
683 AU1000_TOY_MATCH1_INT,
684 AU1000_TOY_MATCH2_INT,
685 AU1000_RTC_INT,
686 AU1000_RTC_MATCH0_INT,
687 AU1000_RTC_MATCH1_INT,
688 AU1000_RTC_MATCH2_INT,
689 AU1000_IRDA_TX_INT,
690 AU1000_IRDA_RX_INT,
691 AU1000_USB_DEV_REQ_INT,
692 AU1000_USB_DEV_SUS_INT,
693 AU1000_USB_HOST_INT,
694 AU1000_ACSYNC_INT,
695 AU1100_MAC0_DMA_INT,
696 AU1100_GPIO_208_215,
697 AU1100_LCD_INT,
698 AU1000_AC97C_INT,
699 AU1000_GPIO_0,
700 AU1000_GPIO_1,
701 AU1000_GPIO_2,
702 AU1000_GPIO_3,
703 AU1000_GPIO_4,
704 AU1000_GPIO_5,
705 AU1000_GPIO_6,
706 AU1000_GPIO_7,
707 AU1000_GPIO_8,
708 AU1000_GPIO_9,
709 AU1000_GPIO_10,
710 AU1000_GPIO_11,
711 AU1000_GPIO_12,
712 AU1000_GPIO_13,
713 AU1000_GPIO_14,
714 AU1000_GPIO_15,
715 AU1000_GPIO_16,
716 AU1000_GPIO_17,
717 AU1000_GPIO_18,
718 AU1000_GPIO_19,
719 AU1000_GPIO_20,
720 AU1000_GPIO_21,
721 AU1000_GPIO_22,
722 AU1000_GPIO_23,
723 AU1000_GPIO_24,
724 AU1000_GPIO_25,
725 AU1000_GPIO_26,
726 AU1000_GPIO_27,
727 AU1000_GPIO_28,
728 AU1000_GPIO_29,
729 AU1000_GPIO_30,
730 AU1000_GPIO_31,
731 };
732
733 #define UART0_ADDR 0xB1100000
734 #define UART1_ADDR 0xB1200000
735 #define UART3_ADDR 0xB1400000
736
737 #define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */
738 #define USB_HOST_CONFIG 0xB017FFFC
739
740 #define AU1100_ETH0_BASE 0xB0500000
741 #define AU1100_MAC0_ENABLE 0xB0520000
742 #define NUM_ETH_INTERFACES 1
743 #endif /* CONFIG_SOC_AU1100 */
744
745 #ifdef CONFIG_SOC_AU1550
746 enum soc_au1550_ints {
747 AU1550_FIRST_INT = MIPS_CPU_IRQ_BASE + 8,
748 AU1550_UART0_INT = AU1550_FIRST_INT,
749 AU1550_PCI_INTA,
750 AU1550_PCI_INTB,
751 AU1550_DDMA_INT,
752 AU1550_CRYPTO_INT,
753 AU1550_PCI_INTC,
754 AU1550_PCI_INTD,
755 AU1550_PCI_RST_INT,
756 AU1550_UART1_INT,
757 AU1550_UART3_INT,
758 AU1550_PSC0_INT,
759 AU1550_PSC1_INT,
760 AU1550_PSC2_INT,
761 AU1550_PSC3_INT,
762 AU1000_TOY_INT,
763 AU1000_TOY_MATCH0_INT,
764 AU1000_TOY_MATCH1_INT,
765 AU1000_TOY_MATCH2_INT,
766 AU1000_RTC_INT,
767 AU1000_RTC_MATCH0_INT,
768 AU1000_RTC_MATCH1_INT,
769 AU1000_RTC_MATCH2_INT,
770
771 AU1550_NAND_INT = AU1550_FIRST_INT + 23,
772 AU1550_USB_DEV_REQ_INT,
773 AU1000_USB_DEV_REQ_INT = AU1550_USB_DEV_REQ_INT,
774 AU1550_USB_DEV_SUS_INT,
775 AU1000_USB_DEV_SUS_INT = AU1550_USB_DEV_SUS_INT,
776 AU1550_USB_HOST_INT,
777 AU1000_USB_HOST_INT = AU1550_USB_HOST_INT,
778 AU1550_MAC0_DMA_INT,
779 AU1550_MAC1_DMA_INT,
780 AU1000_GPIO_0 = AU1550_FIRST_INT + 32,
781 AU1000_GPIO_1,
782 AU1000_GPIO_2,
783 AU1000_GPIO_3,
784 AU1000_GPIO_4,
785 AU1000_GPIO_5,
786 AU1000_GPIO_6,
787 AU1000_GPIO_7,
788 AU1000_GPIO_8,
789 AU1000_GPIO_9,
790 AU1000_GPIO_10,
791 AU1000_GPIO_11,
792 AU1000_GPIO_12,
793 AU1000_GPIO_13,
794 AU1000_GPIO_14,
795 AU1000_GPIO_15,
796 AU1550_GPIO_200,
797 AU1500_GPIO_201_205, /* Logical or of GPIO201:205 */
798 AU1500_GPIO_16,
799 AU1500_GPIO_17,
800 AU1500_GPIO_20,
801 AU1500_GPIO_21,
802 AU1500_GPIO_22,
803 AU1500_GPIO_23,
804 AU1500_GPIO_24,
805 AU1500_GPIO_25,
806 AU1500_GPIO_26,
807 AU1500_GPIO_27,
808 AU1500_GPIO_28,
809 AU1500_GPIO_206,
810 AU1500_GPIO_207,
811 AU1500_GPIO_208_218, /* Logical or of GPIO208:218 */
812 };
813
814 /* shortcuts */
815 #define INTA AU1550_PCI_INTA
816 #define INTB AU1550_PCI_INTB
817 #define INTC AU1550_PCI_INTC
818 #define INTD AU1550_PCI_INTD
819
820 #define UART0_ADDR 0xB1100000
821 #define UART1_ADDR 0xB1200000
822 #define UART3_ADDR 0xB1400000
823
824 #define USB_OHCI_BASE 0x14020000 /* phys addr for ioremap */
825 #define USB_OHCI_LEN 0x00060000
826 #define USB_HOST_CONFIG 0xB4027ffc
827
828 #define AU1550_ETH0_BASE 0xB0500000
829 #define AU1550_ETH1_BASE 0xB0510000
830 #define AU1550_MAC0_ENABLE 0xB0520000
831 #define AU1550_MAC1_ENABLE 0xB0520004
832 #define NUM_ETH_INTERFACES 2
833 #endif /* CONFIG_SOC_AU1550 */
834
835 #ifdef CONFIG_SOC_AU1200
836 enum soc_au1200_ints {
837 AU1200_FIRST_INT = MIPS_CPU_IRQ_BASE + 8,
838 AU1200_UART0_INT = AU1200_FIRST_INT,
839 AU1200_SWT_INT,
840 AU1200_SD_INT,
841 AU1200_DDMA_INT,
842 AU1200_MAE_BE_INT,
843 AU1200_GPIO_200,
844 AU1200_GPIO_201,
845 AU1200_GPIO_202,
846 AU1200_UART1_INT,
847 AU1200_MAE_FE_INT,
848 AU1200_PSC0_INT,
849 AU1200_PSC1_INT,
850 AU1200_AES_INT,
851 AU1200_CAMERA_INT,
852 AU1000_TOY_INT,
853 AU1000_TOY_MATCH0_INT,
854 AU1000_TOY_MATCH1_INT,
855 AU1000_TOY_MATCH2_INT,
856 AU1000_RTC_INT,
857 AU1000_RTC_MATCH0_INT,
858 AU1000_RTC_MATCH1_INT,
859 AU1000_RTC_MATCH2_INT,
860
861 AU1200_NAND_INT = AU1200_FIRST_INT + 23,
862 AU1200_GPIO_204,
863 AU1200_GPIO_205,
864 AU1200_GPIO_206,
865 AU1200_GPIO_207,
866 AU1200_GPIO_208_215, /* Logical OR of 208:215 */
867 AU1200_USB_INT,
868 AU1000_USB_HOST_INT = AU1200_USB_INT,
869 AU1200_LCD_INT,
870 AU1200_MAE_BOTH_INT,
871 AU1000_GPIO_0,
872 AU1000_GPIO_1,
873 AU1000_GPIO_2,
874 AU1000_GPIO_3,
875 AU1000_GPIO_4,
876 AU1000_GPIO_5,
877 AU1000_GPIO_6,
878 AU1000_GPIO_7,
879 AU1000_GPIO_8,
880 AU1000_GPIO_9,
881 AU1000_GPIO_10,
882 AU1000_GPIO_11,
883 AU1000_GPIO_12,
884 AU1000_GPIO_13,
885 AU1000_GPIO_14,
886 AU1000_GPIO_15,
887 AU1000_GPIO_16,
888 AU1000_GPIO_17,
889 AU1000_GPIO_18,
890 AU1000_GPIO_19,
891 AU1000_GPIO_20,
892 AU1000_GPIO_21,
893 AU1000_GPIO_22,
894 AU1000_GPIO_23,
895 AU1000_GPIO_24,
896 AU1000_GPIO_25,
897 AU1000_GPIO_26,
898 AU1000_GPIO_27,
899 AU1000_GPIO_28,
900 AU1000_GPIO_29,
901 AU1000_GPIO_30,
902 AU1000_GPIO_31,
903 };
904
905 #define UART0_ADDR 0xB1100000
906 #define UART1_ADDR 0xB1200000
907
908 #define USB_UOC_BASE 0x14020020
909 #define USB_UOC_LEN 0x20
910 #define USB_OHCI_BASE 0x14020100
911 #define USB_OHCI_LEN 0x100
912 #define USB_EHCI_BASE 0x14020200
913 #define USB_EHCI_LEN 0x100
914 #define USB_UDC_BASE 0x14022000
915 #define USB_UDC_LEN 0x2000
916 #define USB_MSR_BASE 0xB4020000
917 #define USB_MSR_MCFG 4
918 #define USBMSRMCFG_OMEMEN 0
919 #define USBMSRMCFG_OBMEN 1
920 #define USBMSRMCFG_EMEMEN 2
921 #define USBMSRMCFG_EBMEN 3
922 #define USBMSRMCFG_DMEMEN 4
923 #define USBMSRMCFG_DBMEN 5
924 #define USBMSRMCFG_GMEMEN 6
925 #define USBMSRMCFG_OHCCLKEN 16
926 #define USBMSRMCFG_EHCCLKEN 17
927 #define USBMSRMCFG_UDCCLKEN 18
928 #define USBMSRMCFG_PHYPLLEN 19
929 #define USBMSRMCFG_RDCOMB 30
930 #define USBMSRMCFG_PFEN 31
931
932 #endif /* CONFIG_SOC_AU1200 */
933
934 #define AU1000_INTC0_INT_BASE (MIPS_CPU_IRQ_BASE + 8)
935 #define AU1000_INTC0_INT_LAST (AU1000_INTC0_INT_BASE + 31)
936 #define AU1000_INTC1_INT_BASE (AU1000_INTC0_INT_BASE + 32)
937 #define AU1000_INTC1_INT_LAST (AU1000_INTC1_INT_BASE + 31)
938
939 #define AU1000_MAX_INTR AU1000_INTC1_INT_LAST
940 #define INTX 0xFF /* not valid */
941
942 /* Programmable Counters 0 and 1 */
943 #define SYS_BASE 0xB1900000
944 #define SYS_COUNTER_CNTRL (SYS_BASE + 0x14)
945 # define SYS_CNTRL_E1S (1 << 23)
946 # define SYS_CNTRL_T1S (1 << 20)
947 # define SYS_CNTRL_M21 (1 << 19)
948 # define SYS_CNTRL_M11 (1 << 18)
949 # define SYS_CNTRL_M01 (1 << 17)
950 # define SYS_CNTRL_C1S (1 << 16)
951 # define SYS_CNTRL_BP (1 << 14)
952 # define SYS_CNTRL_EN1 (1 << 13)
953 # define SYS_CNTRL_BT1 (1 << 12)
954 # define SYS_CNTRL_EN0 (1 << 11)
955 # define SYS_CNTRL_BT0 (1 << 10)
956 # define SYS_CNTRL_E0 (1 << 8)
957 # define SYS_CNTRL_E0S (1 << 7)
958 # define SYS_CNTRL_32S (1 << 5)
959 # define SYS_CNTRL_T0S (1 << 4)
960 # define SYS_CNTRL_M20 (1 << 3)
961 # define SYS_CNTRL_M10 (1 << 2)
962 # define SYS_CNTRL_M00 (1 << 1)
963 # define SYS_CNTRL_C0S (1 << 0)
964
965 /* Programmable Counter 0 Registers */
966 #define SYS_TOYTRIM (SYS_BASE + 0)
967 #define SYS_TOYWRITE (SYS_BASE + 4)
968 #define SYS_TOYMATCH0 (SYS_BASE + 8)
969 #define SYS_TOYMATCH1 (SYS_BASE + 0xC)
970 #define SYS_TOYMATCH2 (SYS_BASE + 0x10)
971 #define SYS_TOYREAD (SYS_BASE + 0x40)
972
973 /* Programmable Counter 1 Registers */
974 #define SYS_RTCTRIM (SYS_BASE + 0x44)
975 #define SYS_RTCWRITE (SYS_BASE + 0x48)
976 #define SYS_RTCMATCH0 (SYS_BASE + 0x4C)
977 #define SYS_RTCMATCH1 (SYS_BASE + 0x50)
978 #define SYS_RTCMATCH2 (SYS_BASE + 0x54)
979 #define SYS_RTCREAD (SYS_BASE + 0x58)
980
981 /* I2S Controller */
982 #define I2S_DATA 0xB1000000
983 # define I2S_DATA_MASK 0xffffff
984 #define I2S_CONFIG 0xB1000004
985 # define I2S_CONFIG_XU (1 << 25)
986 # define I2S_CONFIG_XO (1 << 24)
987 # define I2S_CONFIG_RU (1 << 23)
988 # define I2S_CONFIG_RO (1 << 22)
989 # define I2S_CONFIG_TR (1 << 21)
990 # define I2S_CONFIG_TE (1 << 20)
991 # define I2S_CONFIG_TF (1 << 19)
992 # define I2S_CONFIG_RR (1 << 18)
993 # define I2S_CONFIG_RE (1 << 17)
994 # define I2S_CONFIG_RF (1 << 16)
995 # define I2S_CONFIG_PD (1 << 11)
996 # define I2S_CONFIG_LB (1 << 10)
997 # define I2S_CONFIG_IC (1 << 9)
998 # define I2S_CONFIG_FM_BIT 7
999 # define I2S_CONFIG_FM_MASK (0x3 << I2S_CONFIG_FM_BIT)
1000 # define I2S_CONFIG_FM_I2S (0x0 << I2S_CONFIG_FM_BIT)
1001 # define I2S_CONFIG_FM_LJ (0x1 << I2S_CONFIG_FM_BIT)
1002 # define I2S_CONFIG_FM_RJ (0x2 << I2S_CONFIG_FM_BIT)
1003 # define I2S_CONFIG_TN (1 << 6)
1004 # define I2S_CONFIG_RN (1 << 5)
1005 # define I2S_CONFIG_SZ_BIT 0
1006 # define I2S_CONFIG_SZ_MASK (0x1F << I2S_CONFIG_SZ_BIT)
1007
1008 #define I2S_CONTROL 0xB1000008
1009 # define I2S_CONTROL_D (1 << 1)
1010 # define I2S_CONTROL_CE (1 << 0)
1011
1012 /* USB Host Controller */
1013 #ifndef USB_OHCI_LEN
1014 #define USB_OHCI_LEN 0x00100000
1015 #endif
1016
1017 #ifndef CONFIG_SOC_AU1200
1018
1019 /* USB Device Controller */
1020 #define USBD_EP0RD 0xB0200000
1021 #define USBD_EP0WR 0xB0200004
1022 #define USBD_EP2WR 0xB0200008
1023 #define USBD_EP3WR 0xB020000C
1024 #define USBD_EP4RD 0xB0200010
1025 #define USBD_EP5RD 0xB0200014
1026 #define USBD_INTEN 0xB0200018
1027 #define USBD_INTSTAT 0xB020001C
1028 # define USBDEV_INT_SOF (1 << 12)
1029 # define USBDEV_INT_HF_BIT 6
1030 # define USBDEV_INT_HF_MASK (0x3f << USBDEV_INT_HF_BIT)
1031 # define USBDEV_INT_CMPLT_BIT 0
1032 # define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT)
1033 #define USBD_CONFIG 0xB0200020
1034 #define USBD_EP0CS 0xB0200024
1035 #define USBD_EP2CS 0xB0200028
1036 #define USBD_EP3CS 0xB020002C
1037 #define USBD_EP4CS 0xB0200030
1038 #define USBD_EP5CS 0xB0200034
1039 # define USBDEV_CS_SU (1 << 14)
1040 # define USBDEV_CS_NAK (1 << 13)
1041 # define USBDEV_CS_ACK (1 << 12)
1042 # define USBDEV_CS_BUSY (1 << 11)
1043 # define USBDEV_CS_TSIZE_BIT 1
1044 # define USBDEV_CS_TSIZE_MASK (0x3ff << USBDEV_CS_TSIZE_BIT)
1045 # define USBDEV_CS_STALL (1 << 0)
1046 #define USBD_EP0RDSTAT 0xB0200040
1047 #define USBD_EP0WRSTAT 0xB0200044
1048 #define USBD_EP2WRSTAT 0xB0200048
1049 #define USBD_EP3WRSTAT 0xB020004C
1050 #define USBD_EP4RDSTAT 0xB0200050
1051 #define USBD_EP5RDSTAT 0xB0200054
1052 # define USBDEV_FSTAT_FLUSH (1 << 6)
1053 # define USBDEV_FSTAT_UF (1 << 5)
1054 # define USBDEV_FSTAT_OF (1 << 4)
1055 # define USBDEV_FSTAT_FCNT_BIT 0
1056 # define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT)
1057 #define USBD_ENABLE 0xB0200058
1058 # define USBDEV_ENABLE (1 << 1)
1059 # define USBDEV_CE (1 << 0)
1060
1061 #endif /* !CONFIG_SOC_AU1200 */
1062
1063 /* Ethernet Controllers */
1064
1065 /* 4 byte offsets from AU1000_ETH_BASE */
1066 #define MAC_CONTROL 0x0
1067 # define MAC_RX_ENABLE (1 << 2)
1068 # define MAC_TX_ENABLE (1 << 3)
1069 # define MAC_DEF_CHECK (1 << 5)
1070 # define MAC_SET_BL(X) (((X) & 0x3) << 6)
1071 # define MAC_AUTO_PAD (1 << 8)
1072 # define MAC_DISABLE_RETRY (1 << 10)
1073 # define MAC_DISABLE_BCAST (1 << 11)
1074 # define MAC_LATE_COL (1 << 12)
1075 # define MAC_HASH_MODE (1 << 13)
1076 # define MAC_HASH_ONLY (1 << 15)
1077 # define MAC_PASS_ALL (1 << 16)
1078 # define MAC_INVERSE_FILTER (1 << 17)
1079 # define MAC_PROMISCUOUS (1 << 18)
1080 # define MAC_PASS_ALL_MULTI (1 << 19)
1081 # define MAC_FULL_DUPLEX (1 << 20)
1082 # define MAC_NORMAL_MODE 0
1083 # define MAC_INT_LOOPBACK (1 << 21)
1084 # define MAC_EXT_LOOPBACK (1 << 22)
1085 # define MAC_DISABLE_RX_OWN (1 << 23)
1086 # define MAC_BIG_ENDIAN (1 << 30)
1087 # define MAC_RX_ALL (1 << 31)
1088 #define MAC_ADDRESS_HIGH 0x4
1089 #define MAC_ADDRESS_LOW 0x8
1090 #define MAC_MCAST_HIGH 0xC
1091 #define MAC_MCAST_LOW 0x10
1092 #define MAC_MII_CNTRL 0x14
1093 # define MAC_MII_BUSY (1 << 0)
1094 # define MAC_MII_READ 0
1095 # define MAC_MII_WRITE (1 << 1)
1096 # define MAC_SET_MII_SELECT_REG(X) (((X) & 0x1f) << 6)
1097 # define MAC_SET_MII_SELECT_PHY(X) (((X) & 0x1f) << 11)
1098 #define MAC_MII_DATA 0x18
1099 #define MAC_FLOW_CNTRL 0x1C
1100 # define MAC_FLOW_CNTRL_BUSY (1 << 0)
1101 # define MAC_FLOW_CNTRL_ENABLE (1 << 1)
1102 # define MAC_PASS_CONTROL (1 << 2)
1103 # define MAC_SET_PAUSE(X) (((X) & 0xffff) << 16)
1104 #define MAC_VLAN1_TAG 0x20
1105 #define MAC_VLAN2_TAG 0x24
1106
1107 /* Ethernet Controller Enable */
1108
1109 # define MAC_EN_CLOCK_ENABLE (1 << 0)
1110 # define MAC_EN_RESET0 (1 << 1)
1111 # define MAC_EN_TOSS (0 << 2)
1112 # define MAC_EN_CACHEABLE (1 << 3)
1113 # define MAC_EN_RESET1 (1 << 4)
1114 # define MAC_EN_RESET2 (1 << 5)
1115 # define MAC_DMA_RESET (1 << 6)
1116
1117 /* Ethernet Controller DMA Channels */
1118
1119 #define MAC0_TX_DMA_ADDR 0xB4004000
1120 #define MAC1_TX_DMA_ADDR 0xB4004200
1121 /* offsets from MAC_TX_RING_ADDR address */
1122 #define MAC_TX_BUFF0_STATUS 0x0
1123 # define TX_FRAME_ABORTED (1 << 0)
1124 # define TX_JAB_TIMEOUT (1 << 1)
1125 # define TX_NO_CARRIER (1 << 2)
1126 # define TX_LOSS_CARRIER (1 << 3)
1127 # define TX_EXC_DEF (1 << 4)
1128 # define TX_LATE_COLL_ABORT (1 << 5)
1129 # define TX_EXC_COLL (1 << 6)
1130 # define TX_UNDERRUN (1 << 7)
1131 # define TX_DEFERRED (1 << 8)
1132 # define TX_LATE_COLL (1 << 9)
1133 # define TX_COLL_CNT_MASK (0xF << 10)
1134 # define TX_PKT_RETRY (1 << 31)
1135 #define MAC_TX_BUFF0_ADDR 0x4
1136 # define TX_DMA_ENABLE (1 << 0)
1137 # define TX_T_DONE (1 << 1)
1138 # define TX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3)
1139 #define MAC_TX_BUFF0_LEN 0x8
1140 #define MAC_TX_BUFF1_STATUS 0x10
1141 #define MAC_TX_BUFF1_ADDR 0x14
1142 #define MAC_TX_BUFF1_LEN 0x18
1143 #define MAC_TX_BUFF2_STATUS 0x20
1144 #define MAC_TX_BUFF2_ADDR 0x24
1145 #define MAC_TX_BUFF2_LEN 0x28
1146 #define MAC_TX_BUFF3_STATUS 0x30
1147 #define MAC_TX_BUFF3_ADDR 0x34
1148 #define MAC_TX_BUFF3_LEN 0x38
1149
1150 #define MAC0_RX_DMA_ADDR 0xB4004100
1151 #define MAC1_RX_DMA_ADDR 0xB4004300
1152 /* offsets from MAC_RX_RING_ADDR */
1153 #define MAC_RX_BUFF0_STATUS 0x0
1154 # define RX_FRAME_LEN_MASK 0x3fff
1155 # define RX_WDOG_TIMER (1 << 14)
1156 # define RX_RUNT (1 << 15)
1157 # define RX_OVERLEN (1 << 16)
1158 # define RX_COLL (1 << 17)
1159 # define RX_ETHER (1 << 18)
1160 # define RX_MII_ERROR (1 << 19)
1161 # define RX_DRIBBLING (1 << 20)
1162 # define RX_CRC_ERROR (1 << 21)
1163 # define RX_VLAN1 (1 << 22)
1164 # define RX_VLAN2 (1 << 23)
1165 # define RX_LEN_ERROR (1 << 24)
1166 # define RX_CNTRL_FRAME (1 << 25)
1167 # define RX_U_CNTRL_FRAME (1 << 26)
1168 # define RX_MCAST_FRAME (1 << 27)
1169 # define RX_BCAST_FRAME (1 << 28)
1170 # define RX_FILTER_FAIL (1 << 29)
1171 # define RX_PACKET_FILTER (1 << 30)
1172 # define RX_MISSED_FRAME (1 << 31)
1173
1174 # define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \
1175 RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \
1176 RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME)
1177 #define MAC_RX_BUFF0_ADDR 0x4
1178 # define RX_DMA_ENABLE (1 << 0)
1179 # define RX_T_DONE (1 << 1)
1180 # define RX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3)
1181 # define RX_SET_BUFF_ADDR(X) ((X) & 0xffffffc0)
1182 #define MAC_RX_BUFF1_STATUS 0x10
1183 #define MAC_RX_BUFF1_ADDR 0x14
1184 #define MAC_RX_BUFF2_STATUS 0x20
1185 #define MAC_RX_BUFF2_ADDR 0x24
1186 #define MAC_RX_BUFF3_STATUS 0x30
1187 #define MAC_RX_BUFF3_ADDR 0x34
1188
1189 /* UARTS 0-3 */
1190 #define UART_BASE UART0_ADDR
1191 #ifdef CONFIG_SOC_AU1200
1192 #define UART_DEBUG_BASE UART1_ADDR
1193 #else
1194 #define UART_DEBUG_BASE UART3_ADDR
1195 #endif
1196
1197 #define UART_RX 0 /* Receive buffer */
1198 #define UART_TX 4 /* Transmit buffer */
1199 #define UART_IER 8 /* Interrupt Enable Register */
1200 #define UART_IIR 0xC /* Interrupt ID Register */
1201 #define UART_FCR 0x10 /* FIFO Control Register */
1202 #define UART_LCR 0x14 /* Line Control Register */
1203 #define UART_MCR 0x18 /* Modem Control Register */
1204 #define UART_LSR 0x1C /* Line Status Register */
1205 #define UART_MSR 0x20 /* Modem Status Register */
1206 #define UART_CLK 0x28 /* Baud Rate Clock Divider */
1207 #define UART_MOD_CNTRL 0x100 /* Module Control */
1208
1209 #define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */
1210 #define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
1211 #define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
1212 #define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */
1213 #define UART_FCR_TRIGGER_MASK 0xF0 /* Mask for the FIFO trigger range */
1214 #define UART_FCR_R_TRIGGER_1 0x00 /* Mask for receive trigger set at 1 */
1215 #define UART_FCR_R_TRIGGER_4 0x40 /* Mask for receive trigger set at 4 */
1216 #define UART_FCR_R_TRIGGER_8 0x80 /* Mask for receive trigger set at 8 */
1217 #define UART_FCR_R_TRIGGER_14 0xA0 /* Mask for receive trigger set at 14 */
1218 #define UART_FCR_T_TRIGGER_0 0x00 /* Mask for transmit trigger set at 0 */
1219 #define UART_FCR_T_TRIGGER_4 0x10 /* Mask for transmit trigger set at 4 */
1220 #define UART_FCR_T_TRIGGER_8 0x20 /* Mask for transmit trigger set at 8 */
1221 #define UART_FCR_T_TRIGGER_12 0x30 /* Mask for transmit trigger set at 12 */
1222
1223 /*
1224 * These are the definitions for the Line Control Register
1225 */
1226 #define UART_LCR_SBC 0x40 /* Set break control */
1227 #define UART_LCR_SPAR 0x20 /* Stick parity (?) */
1228 #define UART_LCR_EPAR 0x10 /* Even parity select */
1229 #define UART_LCR_PARITY 0x08 /* Parity Enable */
1230 #define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */
1231 #define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */
1232 #define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */
1233 #define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */
1234 #define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
1235
1236 /*
1237 * These are the definitions for the Line Status Register
1238 */
1239 #define UART_LSR_TEMT 0x40 /* Transmitter empty */
1240 #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
1241 #define UART_LSR_BI 0x10 /* Break interrupt indicator */
1242 #define UART_LSR_FE 0x08 /* Frame error indicator */
1243 #define UART_LSR_PE 0x04 /* Parity error indicator */
1244 #define UART_LSR_OE 0x02 /* Overrun error indicator */
1245 #define UART_LSR_DR 0x01 /* Receiver data ready */
1246
1247 /*
1248 * These are the definitions for the Interrupt Identification Register
1249 */
1250 #define UART_IIR_NO_INT 0x01 /* No interrupts pending */
1251 #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
1252 #define UART_IIR_MSI 0x00 /* Modem status interrupt */
1253 #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
1254 #define UART_IIR_RDI 0x04 /* Receiver data interrupt */
1255 #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
1256
1257 /*
1258 * These are the definitions for the Interrupt Enable Register
1259 */
1260 #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
1261 #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
1262 #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
1263 #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
1264
1265 /*
1266 * These are the definitions for the Modem Control Register
1267 */
1268 #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
1269 #define UART_MCR_OUT2 0x08 /* Out2 complement */
1270 #define UART_MCR_OUT1 0x04 /* Out1 complement */
1271 #define UART_MCR_RTS 0x02 /* RTS complement */
1272 #define UART_MCR_DTR 0x01 /* DTR complement */
1273
1274 /*
1275 * These are the definitions for the Modem Status Register
1276 */
1277 #define UART_MSR_DCD 0x80 /* Data Carrier Detect */
1278 #define UART_MSR_RI 0x40 /* Ring Indicator */
1279 #define UART_MSR_DSR 0x20 /* Data Set Ready */
1280 #define UART_MSR_CTS 0x10 /* Clear to Send */
1281 #define UART_MSR_DDCD 0x08 /* Delta DCD */
1282 #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
1283 #define UART_MSR_DDSR 0x02 /* Delta DSR */
1284 #define UART_MSR_DCTS 0x01 /* Delta CTS */
1285 #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
1286
1287 /* SSIO */
1288 #define SSI0_STATUS 0xB1600000
1289 # define SSI_STATUS_BF (1 << 4)
1290 # define SSI_STATUS_OF (1 << 3)
1291 # define SSI_STATUS_UF (1 << 2)
1292 # define SSI_STATUS_D (1 << 1)
1293 # define SSI_STATUS_B (1 << 0)
1294 #define SSI0_INT 0xB1600004
1295 # define SSI_INT_OI (1 << 3)
1296 # define SSI_INT_UI (1 << 2)
1297 # define SSI_INT_DI (1 << 1)
1298 #define SSI0_INT_ENABLE 0xB1600008
1299 # define SSI_INTE_OIE (1 << 3)
1300 # define SSI_INTE_UIE (1 << 2)
1301 # define SSI_INTE_DIE (1 << 1)
1302 #define SSI0_CONFIG 0xB1600020
1303 # define SSI_CONFIG_AO (1 << 24)
1304 # define SSI_CONFIG_DO (1 << 23)
1305 # define SSI_CONFIG_ALEN_BIT 20
1306 # define SSI_CONFIG_ALEN_MASK (0x7 << 20)
1307 # define SSI_CONFIG_DLEN_BIT 16
1308 # define SSI_CONFIG_DLEN_MASK (0x7 << 16)
1309 # define SSI_CONFIG_DD (1 << 11)
1310 # define SSI_CONFIG_AD (1 << 10)
1311 # define SSI_CONFIG_BM_BIT 8
1312 # define SSI_CONFIG_BM_MASK (0x3 << 8)
1313 # define SSI_CONFIG_CE (1 << 7)
1314 # define SSI_CONFIG_DP (1 << 6)
1315 # define SSI_CONFIG_DL (1 << 5)
1316 # define SSI_CONFIG_EP (1 << 4)
1317 #define SSI0_ADATA 0xB1600024
1318 # define SSI_AD_D (1 << 24)
1319 # define SSI_AD_ADDR_BIT 16
1320 # define SSI_AD_ADDR_MASK (0xff << 16)
1321 # define SSI_AD_DATA_BIT 0
1322 # define SSI_AD_DATA_MASK (0xfff << 0)
1323 #define SSI0_CLKDIV 0xB1600028
1324 #define SSI0_CONTROL 0xB1600100
1325 # define SSI_CONTROL_CD (1 << 1)
1326 # define SSI_CONTROL_E (1 << 0)
1327
1328 /* SSI1 */
1329 #define SSI1_STATUS 0xB1680000
1330 #define SSI1_INT 0xB1680004
1331 #define SSI1_INT_ENABLE 0xB1680008
1332 #define SSI1_CONFIG 0xB1680020
1333 #define SSI1_ADATA 0xB1680024
1334 #define SSI1_CLKDIV 0xB1680028
1335 #define SSI1_ENABLE 0xB1680100
1336
1337 /*
1338 * Register content definitions
1339 */
1340 #define SSI_STATUS_BF (1 << 4)
1341 #define SSI_STATUS_OF (1 << 3)
1342 #define SSI_STATUS_UF (1 << 2)
1343 #define SSI_STATUS_D (1 << 1)
1344 #define SSI_STATUS_B (1 << 0)
1345
1346 /* SSI_INT */
1347 #define SSI_INT_OI (1 << 3)
1348 #define SSI_INT_UI (1 << 2)
1349 #define SSI_INT_DI (1 << 1)
1350
1351 /* SSI_INTEN */
1352 #define SSI_INTEN_OIE (1 << 3)
1353 #define SSI_INTEN_UIE (1 << 2)
1354 #define SSI_INTEN_DIE (1 << 1)
1355
1356 #define SSI_CONFIG_AO (1 << 24)
1357 #define SSI_CONFIG_DO (1 << 23)
1358 #define SSI_CONFIG_ALEN (7 << 20)
1359 #define SSI_CONFIG_DLEN (15 << 16)
1360 #define SSI_CONFIG_DD (1 << 11)
1361 #define SSI_CONFIG_AD (1 << 10)
1362 #define SSI_CONFIG_BM (3 << 8)
1363 #define SSI_CONFIG_CE (1 << 7)
1364 #define SSI_CONFIG_DP (1 << 6)
1365 #define SSI_CONFIG_DL (1 << 5)
1366 #define SSI_CONFIG_EP (1 << 4)
1367 #define SSI_CONFIG_ALEN_N(N) ((N-1) << 20)
1368 #define SSI_CONFIG_DLEN_N(N) ((N-1) << 16)
1369 #define SSI_CONFIG_BM_HI (0 << 8)
1370 #define SSI_CONFIG_BM_LO (1 << 8)
1371 #define SSI_CONFIG_BM_CY (2 << 8)
1372
1373 #define SSI_ADATA_D (1 << 24)
1374 #define SSI_ADATA_ADDR (0xFF << 16)
1375 #define SSI_ADATA_DATA 0x0FFF
1376 #define SSI_ADATA_ADDR_N(N) (N << 16)
1377
1378 #define SSI_ENABLE_CD (1 << 1)
1379 #define SSI_ENABLE_E (1 << 0)
1380
1381 /* IrDA Controller */
1382 #define IRDA_BASE 0xB0300000
1383 #define IR_RING_PTR_STATUS (IRDA_BASE + 0x00)
1384 #define IR_RING_BASE_ADDR_H (IRDA_BASE + 0x04)
1385 #define IR_RING_BASE_ADDR_L (IRDA_BASE + 0x08)
1386 #define IR_RING_SIZE (IRDA_BASE + 0x0C)
1387 #define IR_RING_PROMPT (IRDA_BASE + 0x10)
1388 #define IR_RING_ADDR_CMPR (IRDA_BASE + 0x14)
1389 #define IR_INT_CLEAR (IRDA_BASE + 0x18)
1390 #define IR_CONFIG_1 (IRDA_BASE + 0x20)
1391 # define IR_RX_INVERT_LED (1 << 0)
1392 # define IR_TX_INVERT_LED (1 << 1)
1393 # define IR_ST (1 << 2)
1394 # define IR_SF (1 << 3)
1395 # define IR_SIR (1 << 4)
1396 # define IR_MIR (1 << 5)
1397 # define IR_FIR (1 << 6)
1398 # define IR_16CRC (1 << 7)
1399 # define IR_TD (1 << 8)
1400 # define IR_RX_ALL (1 << 9)
1401 # define IR_DMA_ENABLE (1 << 10)
1402 # define IR_RX_ENABLE (1 << 11)
1403 # define IR_TX_ENABLE (1 << 12)
1404 # define IR_LOOPBACK (1 << 14)
1405 # define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \
1406 IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC)
1407 #define IR_SIR_FLAGS (IRDA_BASE + 0x24)
1408 #define IR_ENABLE (IRDA_BASE + 0x28)
1409 # define IR_RX_STATUS (1 << 9)
1410 # define IR_TX_STATUS (1 << 10)
1411 #define IR_READ_PHY_CONFIG (IRDA_BASE + 0x2C)
1412 #define IR_WRITE_PHY_CONFIG (IRDA_BASE + 0x30)
1413 #define IR_MAX_PKT_LEN (IRDA_BASE + 0x34)
1414 #define IR_RX_BYTE_CNT (IRDA_BASE + 0x38)
1415 #define IR_CONFIG_2 (IRDA_BASE + 0x3C)
1416 # define IR_MODE_INV (1 << 0)
1417 # define IR_ONE_PIN (1 << 1)
1418 #define IR_INTERFACE_CONFIG (IRDA_BASE + 0x40)
1419
1420 /* GPIO */
1421 #define SYS_PINFUNC 0xB190002C
1422 # define SYS_PF_USB (1 << 15) /* 2nd USB device/host */
1423 # define SYS_PF_U3 (1 << 14) /* GPIO23/U3TXD */
1424 # define SYS_PF_U2 (1 << 13) /* GPIO22/U2TXD */
1425 # define SYS_PF_U1 (1 << 12) /* GPIO21/U1TXD */
1426 # define SYS_PF_SRC (1 << 11) /* GPIO6/SROMCKE */
1427 # define SYS_PF_CK5 (1 << 10) /* GPIO3/CLK5 */
1428 # define SYS_PF_CK4 (1 << 9) /* GPIO2/CLK4 */
1429 # define SYS_PF_IRF (1 << 8) /* GPIO15/IRFIRSEL */
1430 # define SYS_PF_UR3 (1 << 7) /* GPIO[14:9]/UART3 */
1431 # define SYS_PF_I2D (1 << 6) /* GPIO8/I2SDI */
1432 # define SYS_PF_I2S (1 << 5) /* I2S/GPIO[29:31] */
1433 # define SYS_PF_NI2 (1 << 4) /* NI2/GPIO[24:28] */
1434 # define SYS_PF_U0 (1 << 3) /* U0TXD/GPIO20 */
1435 # define SYS_PF_RD (1 << 2) /* IRTXD/GPIO19 */
1436 # define SYS_PF_A97 (1 << 1) /* AC97/SSL1 */
1437 # define SYS_PF_S0 (1 << 0) /* SSI_0/GPIO[16:18] */
1438
1439 /* Au1100 only */
1440 # define SYS_PF_PC (1 << 18) /* PCMCIA/GPIO[207:204] */
1441 # define SYS_PF_LCD (1 << 17) /* extern lcd/GPIO[203:200] */
1442 # define SYS_PF_CS (1 << 16) /* EXTCLK0/32KHz to gpio2 */
1443 # define SYS_PF_EX0 (1 << 9) /* GPIO2/clock */
1444
1445 /* Au1550 only. Redefines lots of pins */
1446 # define SYS_PF_PSC2_MASK (7 << 17)
1447 # define SYS_PF_PSC2_AC97 0
1448 # define SYS_PF_PSC2_SPI 0
1449 # define SYS_PF_PSC2_I2S (1 << 17)
1450 # define SYS_PF_PSC2_SMBUS (3 << 17)
1451 # define SYS_PF_PSC2_GPIO (7 << 17)
1452 # define SYS_PF_PSC3_MASK (7 << 20)
1453 # define SYS_PF_PSC3_AC97 0
1454 # define SYS_PF_PSC3_SPI 0
1455 # define SYS_PF_PSC3_I2S (1 << 20)
1456 # define SYS_PF_PSC3_SMBUS (3 << 20)
1457 # define SYS_PF_PSC3_GPIO (7 << 20)
1458 # define SYS_PF_PSC1_S1 (1 << 1)
1459 # define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2))
1460
1461 /* Au1200 only */
1462 #ifdef CONFIG_SOC_AU1200
1463 #define SYS_PINFUNC_DMA (1 << 31)
1464 #define SYS_PINFUNC_S0A (1 << 30)
1465 #define SYS_PINFUNC_S1A (1 << 29)
1466 #define SYS_PINFUNC_LP0 (1 << 28)
1467 #define SYS_PINFUNC_LP1 (1 << 27)
1468 #define SYS_PINFUNC_LD16 (1 << 26)
1469 #define SYS_PINFUNC_LD8 (1 << 25)
1470 #define SYS_PINFUNC_LD1 (1 << 24)
1471 #define SYS_PINFUNC_LD0 (1 << 23)
1472 #define SYS_PINFUNC_P1A (3 << 21)
1473 #define SYS_PINFUNC_P1B (1 << 20)
1474 #define SYS_PINFUNC_FS3 (1 << 19)
1475 #define SYS_PINFUNC_P0A (3 << 17)
1476 #define SYS_PINFUNC_CS (1 << 16)
1477 #define SYS_PINFUNC_CIM (1 << 15)
1478 #define SYS_PINFUNC_P1C (1 << 14)
1479 #define SYS_PINFUNC_U1T (1 << 12)
1480 #define SYS_PINFUNC_U1R (1 << 11)
1481 #define SYS_PINFUNC_EX1 (1 << 10)
1482 #define SYS_PINFUNC_EX0 (1 << 9)
1483 #define SYS_PINFUNC_U0R (1 << 8)
1484 #define SYS_PINFUNC_MC (1 << 7)
1485 #define SYS_PINFUNC_S0B (1 << 6)
1486 #define SYS_PINFUNC_S0C (1 << 5)
1487 #define SYS_PINFUNC_P0B (1 << 4)
1488 #define SYS_PINFUNC_U0T (1 << 3)
1489 #define SYS_PINFUNC_S1B (1 << 2)
1490 #endif
1491
1492 #define SYS_TRIOUTRD 0xB1900100
1493 #define SYS_TRIOUTCLR 0xB1900100
1494 #define SYS_OUTPUTRD 0xB1900108
1495 #define SYS_OUTPUTSET 0xB1900108
1496 #define SYS_OUTPUTCLR 0xB190010C
1497 #define SYS_PINSTATERD 0xB1900110
1498 #define SYS_PININPUTEN 0xB1900110
1499
1500 /* GPIO2, Au1500, Au1550 only */
1501 #define GPIO2_BASE 0xB1700000
1502 #define GPIO2_DIR (GPIO2_BASE + 0)
1503 #define GPIO2_OUTPUT (GPIO2_BASE + 8)
1504 #define GPIO2_PINSTATE (GPIO2_BASE + 0xC)
1505 #define GPIO2_INTENABLE (GPIO2_BASE + 0x10)
1506 #define GPIO2_ENABLE (GPIO2_BASE + 0x14)
1507
1508 /* Power Management */
1509 #define SYS_SCRATCH0 0xB1900018
1510 #define SYS_SCRATCH1 0xB190001C
1511 #define SYS_WAKEMSK 0xB1900034
1512 #define SYS_ENDIAN 0xB1900038
1513 #define SYS_POWERCTRL 0xB190003C
1514 #define SYS_WAKESRC 0xB190005C
1515 #define SYS_SLPPWR 0xB1900078
1516 #define SYS_SLEEP 0xB190007C
1517
1518 /* Clock Controller */
1519 #define SYS_FREQCTRL0 0xB1900020
1520 # define SYS_FC_FRDIV2_BIT 22
1521 # define SYS_FC_FRDIV2_MASK (0xff << SYS_FC_FRDIV2_BIT)
1522 # define SYS_FC_FE2 (1 << 21)
1523 # define SYS_FC_FS2 (1 << 20)
1524 # define SYS_FC_FRDIV1_BIT 12
1525 # define SYS_FC_FRDIV1_MASK (0xff << SYS_FC_FRDIV1_BIT)
1526 # define SYS_FC_FE1 (1 << 11)
1527 # define SYS_FC_FS1 (1 << 10)
1528 # define SYS_FC_FRDIV0_BIT 2
1529 # define SYS_FC_FRDIV0_MASK (0xff << SYS_FC_FRDIV0_BIT)
1530 # define SYS_FC_FE0 (1 << 1)
1531 # define SYS_FC_FS0 (1 << 0)
1532 #define SYS_FREQCTRL1 0xB1900024
1533 # define SYS_FC_FRDIV5_BIT 22
1534 # define SYS_FC_FRDIV5_MASK (0xff << SYS_FC_FRDIV5_BIT)
1535 # define SYS_FC_FE5 (1 << 21)
1536 # define SYS_FC_FS5 (1 << 20)
1537 # define SYS_FC_FRDIV4_BIT 12
1538 # define SYS_FC_FRDIV4_MASK (0xff << SYS_FC_FRDIV4_BIT)
1539 # define SYS_FC_FE4 (1 << 11)
1540 # define SYS_FC_FS4 (1 << 10)
1541 # define SYS_FC_FRDIV3_BIT 2
1542 # define SYS_FC_FRDIV3_MASK (0xff << SYS_FC_FRDIV3_BIT)
1543 # define SYS_FC_FE3 (1 << 1)
1544 # define SYS_FC_FS3 (1 << 0)
1545 #define SYS_CLKSRC 0xB1900028
1546 # define SYS_CS_ME1_BIT 27
1547 # define SYS_CS_ME1_MASK (0x7 << SYS_CS_ME1_BIT)
1548 # define SYS_CS_DE1 (1 << 26)
1549 # define SYS_CS_CE1 (1 << 25)
1550 # define SYS_CS_ME0_BIT 22
1551 # define SYS_CS_ME0_MASK (0x7 << SYS_CS_ME0_BIT)
1552 # define SYS_CS_DE0 (1 << 21)
1553 # define SYS_CS_CE0 (1 << 20)
1554 # define SYS_CS_MI2_BIT 17
1555 # define SYS_CS_MI2_MASK (0x7 << SYS_CS_MI2_BIT)
1556 # define SYS_CS_DI2 (1 << 16)
1557 # define SYS_CS_CI2 (1 << 15)
1558 #ifdef CONFIG_SOC_AU1100
1559 # define SYS_CS_ML_BIT 7
1560 # define SYS_CS_ML_MASK (0x7 << SYS_CS_ML_BIT)
1561 # define SYS_CS_DL (1 << 6)
1562 # define SYS_CS_CL (1 << 5)
1563 #else
1564 # define SYS_CS_MUH_BIT 12
1565 # define SYS_CS_MUH_MASK (0x7 << SYS_CS_MUH_BIT)
1566 # define SYS_CS_DUH (1 << 11)
1567 # define SYS_CS_CUH (1 << 10)
1568 # define SYS_CS_MUD_BIT 7
1569 # define SYS_CS_MUD_MASK (0x7 << SYS_CS_MUD_BIT)
1570 # define SYS_CS_DUD (1 << 6)
1571 # define SYS_CS_CUD (1 << 5)
1572 #endif
1573 # define SYS_CS_MIR_BIT 2
1574 # define SYS_CS_MIR_MASK (0x7 << SYS_CS_MIR_BIT)
1575 # define SYS_CS_DIR (1 << 1)
1576 # define SYS_CS_CIR (1 << 0)
1577
1578 # define SYS_CS_MUX_AUX 0x1
1579 # define SYS_CS_MUX_FQ0 0x2
1580 # define SYS_CS_MUX_FQ1 0x3
1581 # define SYS_CS_MUX_FQ2 0x4
1582 # define SYS_CS_MUX_FQ3 0x5
1583 # define SYS_CS_MUX_FQ4 0x6
1584 # define SYS_CS_MUX_FQ5 0x7
1585 #define SYS_CPUPLL 0xB1900060
1586 #define SYS_AUXPLL 0xB1900064
1587
1588 /* AC97 Controller */
1589 #define AC97C_CONFIG 0xB0000000
1590 # define AC97C_RECV_SLOTS_BIT 13
1591 # define AC97C_RECV_SLOTS_MASK (0x3ff << AC97C_RECV_SLOTS_BIT)
1592 # define AC97C_XMIT_SLOTS_BIT 3
1593 # define AC97C_XMIT_SLOTS_MASK (0x3ff << AC97C_XMIT_SLOTS_BIT)
1594 # define AC97C_SG (1 << 2)
1595 # define AC97C_SYNC (1 << 1)
1596 # define AC97C_RESET (1 << 0)
1597 #define AC97C_STATUS 0xB0000004
1598 # define AC97C_XU (1 << 11)
1599 # define AC97C_XO (1 << 10)
1600 # define AC97C_RU (1 << 9)
1601 # define AC97C_RO (1 << 8)
1602 # define AC97C_READY (1 << 7)
1603 # define AC97C_CP (1 << 6)
1604 # define AC97C_TR (1 << 5)
1605 # define AC97C_TE (1 << 4)
1606 # define AC97C_TF (1 << 3)
1607 # define AC97C_RR (1 << 2)
1608 # define AC97C_RE (1 << 1)
1609 # define AC97C_RF (1 << 0)
1610 #define AC97C_DATA 0xB0000008
1611 #define AC97C_CMD 0xB000000C
1612 # define AC97C_WD_BIT 16
1613 # define AC97C_READ (1 << 7)
1614 # define AC97C_INDEX_MASK 0x7f
1615 #define AC97C_CNTRL 0xB0000010
1616 # define AC97C_RS (1 << 1)
1617 # define AC97C_CE (1 << 0)
1618
1619 /* Secure Digital (SD) Controller */
1620 #define SD0_XMIT_FIFO 0xB0600000
1621 #define SD0_RECV_FIFO 0xB0600004
1622 #define SD1_XMIT_FIFO 0xB0680000
1623 #define SD1_RECV_FIFO 0xB0680004
1624
1625 #if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
1626 /* Au1500 PCI Controller */
1627 #define Au1500_CFG_BASE 0xB4005000 /* virtual, KSEG1 addr */
1628 #define Au1500_PCI_CMEM (Au1500_CFG_BASE + 0)
1629 #define Au1500_PCI_CFG (Au1500_CFG_BASE + 4)
1630 # define PCI_ERROR ((1 << 22) | (1 << 23) | (1 << 24) | \
1631 (1 << 25) | (1 << 26) | (1 << 27))
1632 #define Au1500_PCI_B2BMASK_CCH (Au1500_CFG_BASE + 8)
1633 #define Au1500_PCI_B2B0_VID (Au1500_CFG_BASE + 0xC)
1634 #define Au1500_PCI_B2B1_ID (Au1500_CFG_BASE + 0x10)
1635 #define Au1500_PCI_MWMASK_DEV (Au1500_CFG_BASE + 0x14)
1636 #define Au1500_PCI_MWBASE_REV_CCL (Au1500_CFG_BASE + 0x18)
1637 #define Au1500_PCI_ERR_ADDR (Au1500_CFG_BASE + 0x1C)
1638 #define Au1500_PCI_SPEC_INTACK (Au1500_CFG_BASE + 0x20)
1639 #define Au1500_PCI_ID (Au1500_CFG_BASE + 0x100)
1640 #define Au1500_PCI_STATCMD (Au1500_CFG_BASE + 0x104)
1641 #define Au1500_PCI_CLASSREV (Au1500_CFG_BASE + 0x108)
1642 #define Au1500_PCI_HDRTYPE (Au1500_CFG_BASE + 0x10C)
1643 #define Au1500_PCI_MBAR (Au1500_CFG_BASE + 0x110)
1644
1645 #define Au1500_PCI_HDR 0xB4005100 /* virtual, KSEG1 addr */
1646
1647 /*
1648 * All of our structures, like PCI resource, have 32-bit members.
1649 * Drivers are expected to do an ioremap on the PCI MEM resource, but it's
1650 * hard to store 0x4 0000 0000 in a 32-bit type. We require a small patch
1651 * to __ioremap to check for addresses between (u32)Au1500_PCI_MEM_START and
1652 * (u32)Au1500_PCI_MEM_END and change those to the full 36-bit PCI MEM
1653 * addresses. For PCI I/O, it's simpler because we get to do the ioremap
1654 * ourselves and then adjust the device's resources.
1655 */
1656 #define Au1500_EXT_CFG 0x600000000ULL
1657 #define Au1500_EXT_CFG_TYPE1 0x680000000ULL
1658 #define Au1500_PCI_IO_START 0x500000000ULL
1659 #define Au1500_PCI_IO_END 0x5000FFFFFULL
1660 #define Au1500_PCI_MEM_START 0x440000000ULL
1661 #define Au1500_PCI_MEM_END 0x44FFFFFFFULL
1662
1663 #define PCI_IO_START 0x00001000
1664 #define PCI_IO_END 0x000FFFFF
1665 #define PCI_MEM_START 0x40000000
1666 #define PCI_MEM_END 0x4FFFFFFF
1667
1668 #define PCI_FIRST_DEVFN (0 << 3)
1669 #define PCI_LAST_DEVFN (19 << 3)
1670
1671 #define IOPORT_RESOURCE_START 0x00001000 /* skip legacy probing */
1672 #define IOPORT_RESOURCE_END 0xffffffff
1673 #define IOMEM_RESOURCE_START 0x10000000
1674 #define IOMEM_RESOURCE_END 0xffffffff
1675
1676 #else /* Au1000 and Au1100 and Au1200 */
1677
1678 /* Don't allow any legacy ports probing */
1679 #define IOPORT_RESOURCE_START 0x10000000
1680 #define IOPORT_RESOURCE_END 0xffffffff
1681 #define IOMEM_RESOURCE_START 0x10000000
1682 #define IOMEM_RESOURCE_END 0xffffffff
1683
1684 #define PCI_IO_START 0
1685 #define PCI_IO_END 0
1686 #define PCI_MEM_START 0
1687 #define PCI_MEM_END 0
1688 #define PCI_FIRST_DEVFN 0
1689 #define PCI_LAST_DEVFN 0
1690
1691 #endif
1692
1693 #ifndef _LANGUAGE_ASSEMBLY
1694 typedef volatile struct {
1695 /* 0x0000 */ u32 toytrim;
1696 /* 0x0004 */ u32 toywrite;
1697 /* 0x0008 */ u32 toymatch0;
1698 /* 0x000C */ u32 toymatch1;
1699 /* 0x0010 */ u32 toymatch2;
1700 /* 0x0014 */ u32 cntrctrl;
1701 /* 0x0018 */ u32 scratch0;
1702 /* 0x001C */ u32 scratch1;
1703 /* 0x0020 */ u32 freqctrl0;
1704 /* 0x0024 */ u32 freqctrl1;
1705 /* 0x0028 */ u32 clksrc;
1706 /* 0x002C */ u32 pinfunc;
1707 /* 0x0030 */ u32 reserved0;
1708 /* 0x0034 */ u32 wakemsk;
1709 /* 0x0038 */ u32 endian;
1710 /* 0x003C */ u32 powerctrl;
1711 /* 0x0040 */ u32 toyread;
1712 /* 0x0044 */ u32 rtctrim;
1713 /* 0x0048 */ u32 rtcwrite;
1714 /* 0x004C */ u32 rtcmatch0;
1715 /* 0x0050 */ u32 rtcmatch1;
1716 /* 0x0054 */ u32 rtcmatch2;
1717 /* 0x0058 */ u32 rtcread;
1718 /* 0x005C */ u32 wakesrc;
1719 /* 0x0060 */ u32 cpupll;
1720 /* 0x0064 */ u32 auxpll;
1721 /* 0x0068 */ u32 reserved1;
1722 /* 0x006C */ u32 reserved2;
1723 /* 0x0070 */ u32 reserved3;
1724 /* 0x0074 */ u32 reserved4;
1725 /* 0x0078 */ u32 slppwr;
1726 /* 0x007C */ u32 sleep;
1727 /* 0x0080 */ u32 reserved5[32];
1728 /* 0x0100 */ u32 trioutrd;
1729 #define trioutclr trioutrd
1730 /* 0x0104 */ u32 reserved6;
1731 /* 0x0108 */ u32 outputrd;
1732 #define outputset outputrd
1733 /* 0x010C */ u32 outputclr;
1734 /* 0x0110 */ u32 pinstaterd;
1735 #define pininputen pinstaterd
1736 } AU1X00_SYS;
1737
1738 static AU1X00_SYS * const sys = (AU1X00_SYS *)SYS_BASE;
1739
1740 #endif
1741
1742 /*
1743 * Processor information based on PRID.
1744 * Copied from PowerPC.
1745 */
1746 #ifndef _LANGUAGE_ASSEMBLY
1747 struct cpu_spec {
1748 /* CPU is matched via (PRID & prid_mask) == prid_value */
1749 unsigned int prid_mask;
1750 unsigned int prid_value;
1751
1752 char *cpu_name;
1753 unsigned char cpu_od; /* Set Config[OD] */
1754 unsigned char cpu_bclk; /* Enable BCLK switching */
1755 unsigned char cpu_pll_wo; /* sys_cpupll reg. write-only */
1756 };
1757
1758 extern struct cpu_spec cpu_specs[];
1759 extern struct cpu_spec *cur_cpu_spec[];
1760 #endif
1761
1762 #endif
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