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sfc: Add support for sub-10G speeds
[linux-2.6/verdex.git] / drivers / net / sfc / falcon.c
blobf09eded40fba0ad0006a34c6f8640eff8f5ec18c
1 /****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2008 Solarflare Communications Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11 #include <linux/bitops.h>
12 #include <linux/delay.h>
13 #include <linux/pci.h>
14 #include <linux/module.h>
15 #include <linux/seq_file.h>
16 #include <linux/i2c.h>
17 #include <linux/i2c-algo-bit.h>
18 #include <linux/mii.h>
19 #include "net_driver.h"
20 #include "bitfield.h"
21 #include "efx.h"
22 #include "mac.h"
23 #include "spi.h"
24 #include "falcon.h"
25 #include "falcon_hwdefs.h"
26 #include "falcon_io.h"
27 #include "mdio_10g.h"
28 #include "phy.h"
29 #include "boards.h"
30 #include "workarounds.h"
31
32 /* Falcon hardware control.
33 * Falcon is the internal codename for the SFC4000 controller that is
34 * present in SFE400X evaluation boards
35 */
36
37 /**
38 * struct falcon_nic_data - Falcon NIC state
39 * @next_buffer_table: First available buffer table id
40 * @pci_dev2: The secondary PCI device if present
41 * @i2c_data: Operations and state for I2C bit-bashing algorithm
42 */
43 struct falcon_nic_data {
44 unsigned next_buffer_table;
45 struct pci_dev *pci_dev2;
46 struct i2c_algo_bit_data i2c_data;
47 };
48
49 /**************************************************************************
50 *
51 * Configurable values
52 *
53 **************************************************************************
54 */
55
56 static int disable_dma_stats;
57
58 /* This is set to 16 for a good reason. In summary, if larger than
59 * 16, the descriptor cache holds more than a default socket
60 * buffer's worth of packets (for UDP we can only have at most one
61 * socket buffer's worth outstanding). This combined with the fact
62 * that we only get 1 TX event per descriptor cache means the NIC
63 * goes idle.
64 */
65 #define TX_DC_ENTRIES 16
66 #define TX_DC_ENTRIES_ORDER 0
67 #define TX_DC_BASE 0x130000
68
69 #define RX_DC_ENTRIES 64
70 #define RX_DC_ENTRIES_ORDER 2
71 #define RX_DC_BASE 0x100000
72
73 static const unsigned int
74 /* "Large" EEPROM device: Atmel AT25640 or similar
75 * 8 KB, 16-bit address, 32 B write block */
76 large_eeprom_type = ((13 << SPI_DEV_TYPE_SIZE_LBN)
77 | (2 << SPI_DEV_TYPE_ADDR_LEN_LBN)
78 | (5 << SPI_DEV_TYPE_BLOCK_SIZE_LBN)),
79 /* Default flash device: Atmel AT25F1024
80 * 128 KB, 24-bit address, 32 KB erase block, 256 B write block */
81 default_flash_type = ((17 << SPI_DEV_TYPE_SIZE_LBN)
82 | (3 << SPI_DEV_TYPE_ADDR_LEN_LBN)
83 | (0x52 << SPI_DEV_TYPE_ERASE_CMD_LBN)
84 | (15 << SPI_DEV_TYPE_ERASE_SIZE_LBN)
85 | (8 << SPI_DEV_TYPE_BLOCK_SIZE_LBN));
86
87 /* RX FIFO XOFF watermark
88 *
89 * When the amount of the RX FIFO increases used increases past this
90 * watermark send XOFF. Only used if RX flow control is enabled (ethtool -A)
91 * This also has an effect on RX/TX arbitration
92 */
93 static int rx_xoff_thresh_bytes = -1;
94 module_param(rx_xoff_thresh_bytes, int, 0644);
95 MODULE_PARM_DESC(rx_xoff_thresh_bytes, "RX fifo XOFF threshold");
96
97 /* RX FIFO XON watermark
98 *
99 * When the amount of the RX FIFO used decreases below this
100 * watermark send XON. Only used if TX flow control is enabled (ethtool -A)
101 * This also has an effect on RX/TX arbitration
102 */
103 static int rx_xon_thresh_bytes = -1;
104 module_param(rx_xon_thresh_bytes, int, 0644);
105 MODULE_PARM_DESC(rx_xon_thresh_bytes, "RX fifo XON threshold");
106
107 /* TX descriptor ring size - min 512 max 4k */
108 #define FALCON_TXD_RING_ORDER TX_DESCQ_SIZE_1K
109 #define FALCON_TXD_RING_SIZE 1024
110 #define FALCON_TXD_RING_MASK (FALCON_TXD_RING_SIZE - 1)
111
112 /* RX descriptor ring size - min 512 max 4k */
113 #define FALCON_RXD_RING_ORDER RX_DESCQ_SIZE_1K
114 #define FALCON_RXD_RING_SIZE 1024
115 #define FALCON_RXD_RING_MASK (FALCON_RXD_RING_SIZE - 1)
116
117 /* Event queue size - max 32k */
118 #define FALCON_EVQ_ORDER EVQ_SIZE_4K
119 #define FALCON_EVQ_SIZE 4096
120 #define FALCON_EVQ_MASK (FALCON_EVQ_SIZE - 1)
121
122 /* Max number of internal errors. After this resets will not be performed */
123 #define FALCON_MAX_INT_ERRORS 4
124
125 /* We poll for events every FLUSH_INTERVAL ms, and check FLUSH_POLL_COUNT times
126 */
127 #define FALCON_FLUSH_INTERVAL 10
128 #define FALCON_FLUSH_POLL_COUNT 100
129
130 /**************************************************************************
131 *
132 * Falcon constants
133 *
134 **************************************************************************
135 */
136
137 /* DMA address mask */
138 #define FALCON_DMA_MASK DMA_BIT_MASK(46)
139
140 /* TX DMA length mask (13-bit) */
141 #define FALCON_TX_DMA_MASK (4096 - 1)
142
143 /* Size and alignment of special buffers (4KB) */
144 #define FALCON_BUF_SIZE 4096
145
146 /* Dummy SRAM size code */
147 #define SRM_NB_BSZ_ONCHIP_ONLY (-1)
148
149 /* Be nice if these (or equiv.) were in linux/pci_regs.h, but they're not. */
150 #define PCI_EXP_DEVCAP_PWR_VAL_LBN 18
151 #define PCI_EXP_DEVCAP_PWR_SCL_LBN 26
152 #define PCI_EXP_DEVCTL_PAYLOAD_LBN 5
153 #define PCI_EXP_LNKSTA_LNK_WID 0x3f0
154 #define PCI_EXP_LNKSTA_LNK_WID_LBN 4
155
156 #define FALCON_IS_DUAL_FUNC(efx) \
157 (falcon_rev(efx) < FALCON_REV_B0)
158
159 /**************************************************************************
160 *
161 * Falcon hardware access
162 *
163 **************************************************************************/
164
165 /* Read the current event from the event queue */
166 static inline efx_qword_t *falcon_event(struct efx_channel *channel,
167 unsigned int index)
168 {
169 return (((efx_qword_t *) (channel->eventq.addr)) + index);
170 }
171
172 /* See if an event is present
173 *
174 * We check both the high and low dword of the event for all ones. We
175 * wrote all ones when we cleared the event, and no valid event can
176 * have all ones in either its high or low dwords. This approach is
177 * robust against reordering.
178 *
179 * Note that using a single 64-bit comparison is incorrect; even
180 * though the CPU read will be atomic, the DMA write may not be.
181 */
182 static inline int falcon_event_present(efx_qword_t *event)
183 {
184 return (!(EFX_DWORD_IS_ALL_ONES(event->dword[0]) |
185 EFX_DWORD_IS_ALL_ONES(event->dword[1])));
186 }
187
188 /**************************************************************************
189 *
190 * I2C bus - this is a bit-bashing interface using GPIO pins
191 * Note that it uses the output enables to tristate the outputs
192 * SDA is the data pin and SCL is the clock
193 *
194 **************************************************************************
195 */
196 static void falcon_setsda(void *data, int state)
197 {
198 struct efx_nic *efx = (struct efx_nic *)data;
199 efx_oword_t reg;
200
201 falcon_read(efx, &reg, GPIO_CTL_REG_KER);
202 EFX_SET_OWORD_FIELD(reg, GPIO3_OEN, !state);
203 falcon_write(efx, &reg, GPIO_CTL_REG_KER);
204 }
205
206 static void falcon_setscl(void *data, int state)
207 {
208 struct efx_nic *efx = (struct efx_nic *)data;
209 efx_oword_t reg;
210
211 falcon_read(efx, &reg, GPIO_CTL_REG_KER);
212 EFX_SET_OWORD_FIELD(reg, GPIO0_OEN, !state);
213 falcon_write(efx, &reg, GPIO_CTL_REG_KER);
214 }
215
216 static int falcon_getsda(void *data)
217 {
218 struct efx_nic *efx = (struct efx_nic *)data;
219 efx_oword_t reg;
220
221 falcon_read(efx, &reg, GPIO_CTL_REG_KER);
222 return EFX_OWORD_FIELD(reg, GPIO3_IN);
223 }
224
225 static int falcon_getscl(void *data)
226 {
227 struct efx_nic *efx = (struct efx_nic *)data;
228 efx_oword_t reg;
229
230 falcon_read(efx, &reg, GPIO_CTL_REG_KER);
231 return EFX_OWORD_FIELD(reg, GPIO0_IN);
232 }
233
234 static struct i2c_algo_bit_data falcon_i2c_bit_operations = {
235 .setsda = falcon_setsda,
236 .setscl = falcon_setscl,
237 .getsda = falcon_getsda,
238 .getscl = falcon_getscl,
239 .udelay = 5,
240 /* Wait up to 50 ms for slave to let us pull SCL high */
241 .timeout = DIV_ROUND_UP(HZ, 20),
242 };
243
244 /**************************************************************************
245 *
246 * Falcon special buffer handling
247 * Special buffers are used for event queues and the TX and RX
248 * descriptor rings.
249 *
250 *************************************************************************/
251
252 /*
253 * Initialise a Falcon special buffer
254 *
255 * This will define a buffer (previously allocated via
256 * falcon_alloc_special_buffer()) in Falcon's buffer table, allowing
257 * it to be used for event queues, descriptor rings etc.
258 */
259 static void
260 falcon_init_special_buffer(struct efx_nic *efx,
261 struct efx_special_buffer *buffer)
262 {
263 efx_qword_t buf_desc;
264 int index;
265 dma_addr_t dma_addr;
266 int i;
267
268 EFX_BUG_ON_PARANOID(!buffer->addr);
269
270 /* Write buffer descriptors to NIC */
271 for (i = 0; i < buffer->entries; i++) {
272 index = buffer->index + i;
273 dma_addr = buffer->dma_addr + (i * 4096);
274 EFX_LOG(efx, "mapping special buffer %d at %llx\n",
275 index, (unsigned long long)dma_addr);
276 EFX_POPULATE_QWORD_4(buf_desc,
277 IP_DAT_BUF_SIZE, IP_DAT_BUF_SIZE_4K,
278 BUF_ADR_REGION, 0,
279 BUF_ADR_FBUF, (dma_addr >> 12),
280 BUF_OWNER_ID_FBUF, 0);
281 falcon_write_sram(efx, &buf_desc, index);
282 }
283 }
284
285 /* Unmaps a buffer from Falcon and clears the buffer table entries */
286 static void
287 falcon_fini_special_buffer(struct efx_nic *efx,
288 struct efx_special_buffer *buffer)
289 {
290 efx_oword_t buf_tbl_upd;
291 unsigned int start = buffer->index;
292 unsigned int end = (buffer->index + buffer->entries - 1);
293
294 if (!buffer->entries)
295 return;
296
297 EFX_LOG(efx, "unmapping special buffers %d-%d\n",
298 buffer->index, buffer->index + buffer->entries - 1);
299
300 EFX_POPULATE_OWORD_4(buf_tbl_upd,
301 BUF_UPD_CMD, 0,
302 BUF_CLR_CMD, 1,
303 BUF_CLR_END_ID, end,
304 BUF_CLR_START_ID, start);
305 falcon_write(efx, &buf_tbl_upd, BUF_TBL_UPD_REG_KER);
306 }
307
308 /*
309 * Allocate a new Falcon special buffer
310 *
311 * This allocates memory for a new buffer, clears it and allocates a
312 * new buffer ID range. It does not write into Falcon's buffer table.
313 *
314 * This call will allocate 4KB buffers, since Falcon can't use 8KB
315 * buffers for event queues and descriptor rings.
316 */
317 static int falcon_alloc_special_buffer(struct efx_nic *efx,
318 struct efx_special_buffer *buffer,
319 unsigned int len)
320 {
321 struct falcon_nic_data *nic_data = efx->nic_data;
322
323 len = ALIGN(len, FALCON_BUF_SIZE);
324
325 buffer->addr = pci_alloc_consistent(efx->pci_dev, len,
326 &buffer->dma_addr);
327 if (!buffer->addr)
328 return -ENOMEM;
329 buffer->len = len;
330 buffer->entries = len / FALCON_BUF_SIZE;
331 BUG_ON(buffer->dma_addr & (FALCON_BUF_SIZE - 1));
332
333 /* All zeros is a potentially valid event so memset to 0xff */
334 memset(buffer->addr, 0xff, len);
335
336 /* Select new buffer ID */
337 buffer->index = nic_data->next_buffer_table;
338 nic_data->next_buffer_table += buffer->entries;
339
340 EFX_LOG(efx, "allocating special buffers %d-%d at %llx+%x "
341 "(virt %p phys %lx)\n", buffer->index,
342 buffer->index + buffer->entries - 1,
343 (unsigned long long)buffer->dma_addr, len,
344 buffer->addr, virt_to_phys(buffer->addr));
345
346 return 0;
347 }
348
349 static void falcon_free_special_buffer(struct efx_nic *efx,
350 struct efx_special_buffer *buffer)
351 {
352 if (!buffer->addr)
353 return;
354
355 EFX_LOG(efx, "deallocating special buffers %d-%d at %llx+%x "
356 "(virt %p phys %lx)\n", buffer->index,
357 buffer->index + buffer->entries - 1,
358 (unsigned long long)buffer->dma_addr, buffer->len,
359 buffer->addr, virt_to_phys(buffer->addr));
360
361 pci_free_consistent(efx->pci_dev, buffer->len, buffer->addr,
362 buffer->dma_addr);
363 buffer->addr = NULL;
364 buffer->entries = 0;
365 }
366
367 /**************************************************************************
368 *
369 * Falcon generic buffer handling
370 * These buffers are used for interrupt status and MAC stats
371 *
372 **************************************************************************/
373
374 static int falcon_alloc_buffer(struct efx_nic *efx,
375 struct efx_buffer *buffer, unsigned int len)
376 {
377 buffer->addr = pci_alloc_consistent(efx->pci_dev, len,
378 &buffer->dma_addr);
379 if (!buffer->addr)
380 return -ENOMEM;
381 buffer->len = len;
382 memset(buffer->addr, 0, len);
383 return 0;
384 }
385
386 static void falcon_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer)
387 {
388 if (buffer->addr) {
389 pci_free_consistent(efx->pci_dev, buffer->len,
390 buffer->addr, buffer->dma_addr);
391 buffer->addr = NULL;
392 }
393 }
394
395 /**************************************************************************
396 *
397 * Falcon TX path
398 *
399 **************************************************************************/
400
401 /* Returns a pointer to the specified transmit descriptor in the TX
402 * descriptor queue belonging to the specified channel.
403 */
404 static inline efx_qword_t *falcon_tx_desc(struct efx_tx_queue *tx_queue,
405 unsigned int index)
406 {
407 return (((efx_qword_t *) (tx_queue->txd.addr)) + index);
408 }
409
410 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
411 static inline void falcon_notify_tx_desc(struct efx_tx_queue *tx_queue)
412 {
413 unsigned write_ptr;
414 efx_dword_t reg;
415
416 write_ptr = tx_queue->write_count & FALCON_TXD_RING_MASK;
417 EFX_POPULATE_DWORD_1(reg, TX_DESC_WPTR_DWORD, write_ptr);
418 falcon_writel_page(tx_queue->efx, &reg,
419 TX_DESC_UPD_REG_KER_DWORD, tx_queue->queue);
420 }
421
422
423 /* For each entry inserted into the software descriptor ring, create a
424 * descriptor in the hardware TX descriptor ring (in host memory), and
425 * write a doorbell.
426 */
427 void falcon_push_buffers(struct efx_tx_queue *tx_queue)
428 {
429
430 struct efx_tx_buffer *buffer;
431 efx_qword_t *txd;
432 unsigned write_ptr;
433
434 BUG_ON(tx_queue->write_count == tx_queue->insert_count);
435
436 do {
437 write_ptr = tx_queue->write_count & FALCON_TXD_RING_MASK;
438 buffer = &tx_queue->buffer[write_ptr];
439 txd = falcon_tx_desc(tx_queue, write_ptr);
440 ++tx_queue->write_count;
441
442 /* Create TX descriptor ring entry */
443 EFX_POPULATE_QWORD_5(*txd,
444 TX_KER_PORT, 0,
445 TX_KER_CONT, buffer->continuation,
446 TX_KER_BYTE_CNT, buffer->len,
447 TX_KER_BUF_REGION, 0,
448 TX_KER_BUF_ADR, buffer->dma_addr);
449 } while (tx_queue->write_count != tx_queue->insert_count);
450
451 wmb(); /* Ensure descriptors are written before they are fetched */
452 falcon_notify_tx_desc(tx_queue);
453 }
454
455 /* Allocate hardware resources for a TX queue */
456 int falcon_probe_tx(struct efx_tx_queue *tx_queue)
457 {
458 struct efx_nic *efx = tx_queue->efx;
459 return falcon_alloc_special_buffer(efx, &tx_queue->txd,
460 FALCON_TXD_RING_SIZE *
461 sizeof(efx_qword_t));
462 }
463
464 void falcon_init_tx(struct efx_tx_queue *tx_queue)
465 {
466 efx_oword_t tx_desc_ptr;
467 struct efx_nic *efx = tx_queue->efx;
468
469 tx_queue->flushed = false;
470
471 /* Pin TX descriptor ring */
472 falcon_init_special_buffer(efx, &tx_queue->txd);
473
474 /* Push TX descriptor ring to card */
475 EFX_POPULATE_OWORD_10(tx_desc_ptr,
476 TX_DESCQ_EN, 1,
477 TX_ISCSI_DDIG_EN, 0,
478 TX_ISCSI_HDIG_EN, 0,
479 TX_DESCQ_BUF_BASE_ID, tx_queue->txd.index,
480 TX_DESCQ_EVQ_ID, tx_queue->channel->channel,
481 TX_DESCQ_OWNER_ID, 0,
482 TX_DESCQ_LABEL, tx_queue->queue,
483 TX_DESCQ_SIZE, FALCON_TXD_RING_ORDER,
484 TX_DESCQ_TYPE, 0,
485 TX_NON_IP_DROP_DIS_B0, 1);
486
487 if (falcon_rev(efx) >= FALCON_REV_B0) {
488 int csum = tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM;
489 EFX_SET_OWORD_FIELD(tx_desc_ptr, TX_IP_CHKSM_DIS_B0, !csum);
490 EFX_SET_OWORD_FIELD(tx_desc_ptr, TX_TCP_CHKSM_DIS_B0, !csum);
491 }
492
493 falcon_write_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
494 tx_queue->queue);
495
496 if (falcon_rev(efx) < FALCON_REV_B0) {
497 efx_oword_t reg;
498
499 /* Only 128 bits in this register */
500 BUILD_BUG_ON(EFX_TX_QUEUE_COUNT >= 128);
501
502 falcon_read(efx, &reg, TX_CHKSM_CFG_REG_KER_A1);
503 if (tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM)
504 clear_bit_le(tx_queue->queue, (void *)&reg);
505 else
506 set_bit_le(tx_queue->queue, (void *)&reg);
507 falcon_write(efx, &reg, TX_CHKSM_CFG_REG_KER_A1);
508 }
509 }
510
511 static void falcon_flush_tx_queue(struct efx_tx_queue *tx_queue)
512 {
513 struct efx_nic *efx = tx_queue->efx;
514 efx_oword_t tx_flush_descq;
515
516 /* Post a flush command */
517 EFX_POPULATE_OWORD_2(tx_flush_descq,
518 TX_FLUSH_DESCQ_CMD, 1,
519 TX_FLUSH_DESCQ, tx_queue->queue);
520 falcon_write(efx, &tx_flush_descq, TX_FLUSH_DESCQ_REG_KER);
521 }
522
523 void falcon_fini_tx(struct efx_tx_queue *tx_queue)
524 {
525 struct efx_nic *efx = tx_queue->efx;
526 efx_oword_t tx_desc_ptr;
527
528 /* The queue should have been flushed */
529 WARN_ON(!tx_queue->flushed);
530
531 /* Remove TX descriptor ring from card */
532 EFX_ZERO_OWORD(tx_desc_ptr);
533 falcon_write_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
534 tx_queue->queue);
535
536 /* Unpin TX descriptor ring */
537 falcon_fini_special_buffer(efx, &tx_queue->txd);
538 }
539
540 /* Free buffers backing TX queue */
541 void falcon_remove_tx(struct efx_tx_queue *tx_queue)
542 {
543 falcon_free_special_buffer(tx_queue->efx, &tx_queue->txd);
544 }
545
546 /**************************************************************************
547 *
548 * Falcon RX path
549 *
550 **************************************************************************/
551
552 /* Returns a pointer to the specified descriptor in the RX descriptor queue */
553 static inline efx_qword_t *falcon_rx_desc(struct efx_rx_queue *rx_queue,
554 unsigned int index)
555 {
556 return (((efx_qword_t *) (rx_queue->rxd.addr)) + index);
557 }
558
559 /* This creates an entry in the RX descriptor queue */
560 static inline void falcon_build_rx_desc(struct efx_rx_queue *rx_queue,
561 unsigned index)
562 {
563 struct efx_rx_buffer *rx_buf;
564 efx_qword_t *rxd;
565
566 rxd = falcon_rx_desc(rx_queue, index);
567 rx_buf = efx_rx_buffer(rx_queue, index);
568 EFX_POPULATE_QWORD_3(*rxd,
569 RX_KER_BUF_SIZE,
570 rx_buf->len -
571 rx_queue->efx->type->rx_buffer_padding,
572 RX_KER_BUF_REGION, 0,
573 RX_KER_BUF_ADR, rx_buf->dma_addr);
574 }
575
576 /* This writes to the RX_DESC_WPTR register for the specified receive
577 * descriptor ring.
578 */
579 void falcon_notify_rx_desc(struct efx_rx_queue *rx_queue)
580 {
581 efx_dword_t reg;
582 unsigned write_ptr;
583
584 while (rx_queue->notified_count != rx_queue->added_count) {
585 falcon_build_rx_desc(rx_queue,
586 rx_queue->notified_count &
587 FALCON_RXD_RING_MASK);
588 ++rx_queue->notified_count;
589 }
590
591 wmb();
592 write_ptr = rx_queue->added_count & FALCON_RXD_RING_MASK;
593 EFX_POPULATE_DWORD_1(reg, RX_DESC_WPTR_DWORD, write_ptr);
594 falcon_writel_page(rx_queue->efx, &reg,
595 RX_DESC_UPD_REG_KER_DWORD, rx_queue->queue);
596 }
597
598 int falcon_probe_rx(struct efx_rx_queue *rx_queue)
599 {
600 struct efx_nic *efx = rx_queue->efx;
601 return falcon_alloc_special_buffer(efx, &rx_queue->rxd,
602 FALCON_RXD_RING_SIZE *
603 sizeof(efx_qword_t));
604 }
605
606 void falcon_init_rx(struct efx_rx_queue *rx_queue)
607 {
608 efx_oword_t rx_desc_ptr;
609 struct efx_nic *efx = rx_queue->efx;
610 bool is_b0 = falcon_rev(efx) >= FALCON_REV_B0;
611 bool iscsi_digest_en = is_b0;
612
613 EFX_LOG(efx, "RX queue %d ring in special buffers %d-%d\n",
614 rx_queue->queue, rx_queue->rxd.index,
615 rx_queue->rxd.index + rx_queue->rxd.entries - 1);
616
617 rx_queue->flushed = false;
618
619 /* Pin RX descriptor ring */
620 falcon_init_special_buffer(efx, &rx_queue->rxd);
621
622 /* Push RX descriptor ring to card */
623 EFX_POPULATE_OWORD_10(rx_desc_ptr,
624 RX_ISCSI_DDIG_EN, iscsi_digest_en,
625 RX_ISCSI_HDIG_EN, iscsi_digest_en,
626 RX_DESCQ_BUF_BASE_ID, rx_queue->rxd.index,
627 RX_DESCQ_EVQ_ID, rx_queue->channel->channel,
628 RX_DESCQ_OWNER_ID, 0,
629 RX_DESCQ_LABEL, rx_queue->queue,
630 RX_DESCQ_SIZE, FALCON_RXD_RING_ORDER,
631 RX_DESCQ_TYPE, 0 /* kernel queue */ ,
632 /* For >=B0 this is scatter so disable */
633 RX_DESCQ_JUMBO, !is_b0,
634 RX_DESCQ_EN, 1);
635 falcon_write_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
636 rx_queue->queue);
637 }
638
639 static void falcon_flush_rx_queue(struct efx_rx_queue *rx_queue)
640 {
641 struct efx_nic *efx = rx_queue->efx;
642 efx_oword_t rx_flush_descq;
643
644 /* Post a flush command */
645 EFX_POPULATE_OWORD_2(rx_flush_descq,
646 RX_FLUSH_DESCQ_CMD, 1,
647 RX_FLUSH_DESCQ, rx_queue->queue);
648 falcon_write(efx, &rx_flush_descq, RX_FLUSH_DESCQ_REG_KER);
649 }
650
651 void falcon_fini_rx(struct efx_rx_queue *rx_queue)
652 {
653 efx_oword_t rx_desc_ptr;
654 struct efx_nic *efx = rx_queue->efx;
655
656 /* The queue should already have been flushed */
657 WARN_ON(!rx_queue->flushed);
658
659 /* Remove RX descriptor ring from card */
660 EFX_ZERO_OWORD(rx_desc_ptr);
661 falcon_write_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
662 rx_queue->queue);
663
664 /* Unpin RX descriptor ring */
665 falcon_fini_special_buffer(efx, &rx_queue->rxd);
666 }
667
668 /* Free buffers backing RX queue */
669 void falcon_remove_rx(struct efx_rx_queue *rx_queue)
670 {
671 falcon_free_special_buffer(rx_queue->efx, &rx_queue->rxd);
672 }
673
674 /**************************************************************************
675 *
676 * Falcon event queue processing
677 * Event queues are processed by per-channel tasklets.
678 *
679 **************************************************************************/
680
681 /* Update a channel's event queue's read pointer (RPTR) register
682 *
683 * This writes the EVQ_RPTR_REG register for the specified channel's
684 * event queue.
685 *
686 * Note that EVQ_RPTR_REG contains the index of the "last read" event,
687 * whereas channel->eventq_read_ptr contains the index of the "next to
688 * read" event.
689 */
690 void falcon_eventq_read_ack(struct efx_channel *channel)
691 {
692 efx_dword_t reg;
693 struct efx_nic *efx = channel->efx;
694
695 EFX_POPULATE_DWORD_1(reg, EVQ_RPTR_DWORD, channel->eventq_read_ptr);
696 falcon_writel_table(efx, &reg, efx->type->evq_rptr_tbl_base,
697 channel->channel);
698 }
699
700 /* Use HW to insert a SW defined event */
701 void falcon_generate_event(struct efx_channel *channel, efx_qword_t *event)
702 {
703 efx_oword_t drv_ev_reg;
704
705 EFX_POPULATE_OWORD_2(drv_ev_reg,
706 DRV_EV_QID, channel->channel,
707 DRV_EV_DATA,
708 EFX_QWORD_FIELD64(*event, WHOLE_EVENT));
709 falcon_write(channel->efx, &drv_ev_reg, DRV_EV_REG_KER);
710 }
711
712 /* Handle a transmit completion event
713 *
714 * Falcon batches TX completion events; the message we receive is of
715 * the form "complete all TX events up to this index".
716 */
717 static void falcon_handle_tx_event(struct efx_channel *channel,
718 efx_qword_t *event)
719 {
720 unsigned int tx_ev_desc_ptr;
721 unsigned int tx_ev_q_label;
722 struct efx_tx_queue *tx_queue;
723 struct efx_nic *efx = channel->efx;
724
725 if (likely(EFX_QWORD_FIELD(*event, TX_EV_COMP))) {
726 /* Transmit completion */
727 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, TX_EV_DESC_PTR);
728 tx_ev_q_label = EFX_QWORD_FIELD(*event, TX_EV_Q_LABEL);
729 tx_queue = &efx->tx_queue[tx_ev_q_label];
730 efx_xmit_done(tx_queue, tx_ev_desc_ptr);
731 } else if (EFX_QWORD_FIELD(*event, TX_EV_WQ_FF_FULL)) {
732 /* Rewrite the FIFO write pointer */
733 tx_ev_q_label = EFX_QWORD_FIELD(*event, TX_EV_Q_LABEL);
734 tx_queue = &efx->tx_queue[tx_ev_q_label];
735
736 if (efx_dev_registered(efx))
737 netif_tx_lock(efx->net_dev);
738 falcon_notify_tx_desc(tx_queue);
739 if (efx_dev_registered(efx))
740 netif_tx_unlock(efx->net_dev);
741 } else if (EFX_QWORD_FIELD(*event, TX_EV_PKT_ERR) &&
742 EFX_WORKAROUND_10727(efx)) {
743 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
744 } else {
745 EFX_ERR(efx, "channel %d unexpected TX event "
746 EFX_QWORD_FMT"\n", channel->channel,
747 EFX_QWORD_VAL(*event));
748 }
749 }
750
751 /* Detect errors included in the rx_evt_pkt_ok bit. */
752 static void falcon_handle_rx_not_ok(struct efx_rx_queue *rx_queue,
753 const efx_qword_t *event,
754 bool *rx_ev_pkt_ok,
755 bool *discard)
756 {
757 struct efx_nic *efx = rx_queue->efx;
758 bool rx_ev_buf_owner_id_err, rx_ev_ip_hdr_chksum_err;
759 bool rx_ev_tcp_udp_chksum_err, rx_ev_eth_crc_err;
760 bool rx_ev_frm_trunc, rx_ev_drib_nib, rx_ev_tobe_disc;
761 bool rx_ev_other_err, rx_ev_pause_frm;
762 bool rx_ev_ip_frag_err, rx_ev_hdr_type, rx_ev_mcast_pkt;
763 unsigned rx_ev_pkt_type;
764
765 rx_ev_hdr_type = EFX_QWORD_FIELD(*event, RX_EV_HDR_TYPE);
766 rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, RX_EV_MCAST_PKT);
767 rx_ev_tobe_disc = EFX_QWORD_FIELD(*event, RX_EV_TOBE_DISC);
768 rx_ev_pkt_type = EFX_QWORD_FIELD(*event, RX_EV_PKT_TYPE);
769 rx_ev_buf_owner_id_err = EFX_QWORD_FIELD(*event,
770 RX_EV_BUF_OWNER_ID_ERR);
771 rx_ev_ip_frag_err = EFX_QWORD_FIELD(*event, RX_EV_IF_FRAG_ERR);
772 rx_ev_ip_hdr_chksum_err = EFX_QWORD_FIELD(*event,
773 RX_EV_IP_HDR_CHKSUM_ERR);
774 rx_ev_tcp_udp_chksum_err = EFX_QWORD_FIELD(*event,
775 RX_EV_TCP_UDP_CHKSUM_ERR);
776 rx_ev_eth_crc_err = EFX_QWORD_FIELD(*event, RX_EV_ETH_CRC_ERR);
777 rx_ev_frm_trunc = EFX_QWORD_FIELD(*event, RX_EV_FRM_TRUNC);
778 rx_ev_drib_nib = ((falcon_rev(efx) >= FALCON_REV_B0) ?
779 0 : EFX_QWORD_FIELD(*event, RX_EV_DRIB_NIB));
780 rx_ev_pause_frm = EFX_QWORD_FIELD(*event, RX_EV_PAUSE_FRM_ERR);
781
782 /* Every error apart from tobe_disc and pause_frm */
783 rx_ev_other_err = (rx_ev_drib_nib | rx_ev_tcp_udp_chksum_err |
784 rx_ev_buf_owner_id_err | rx_ev_eth_crc_err |
785 rx_ev_frm_trunc | rx_ev_ip_hdr_chksum_err);
786
787 /* Count errors that are not in MAC stats. Ignore expected
788 * checksum errors during self-test. */
789 if (rx_ev_frm_trunc)
790 ++rx_queue->channel->n_rx_frm_trunc;
791 else if (rx_ev_tobe_disc)
792 ++rx_queue->channel->n_rx_tobe_disc;
793 else if (!efx->loopback_selftest) {
794 if (rx_ev_ip_hdr_chksum_err)
795 ++rx_queue->channel->n_rx_ip_hdr_chksum_err;
796 else if (rx_ev_tcp_udp_chksum_err)
797 ++rx_queue->channel->n_rx_tcp_udp_chksum_err;
798 }
799 if (rx_ev_ip_frag_err)
800 ++rx_queue->channel->n_rx_ip_frag_err;
801
802 /* The frame must be discarded if any of these are true. */
803 *discard = (rx_ev_eth_crc_err | rx_ev_frm_trunc | rx_ev_drib_nib |
804 rx_ev_tobe_disc | rx_ev_pause_frm);
805
806 /* TOBE_DISC is expected on unicast mismatches; don't print out an
807 * error message. FRM_TRUNC indicates RXDP dropped the packet due
808 * to a FIFO overflow.
809 */
810 #ifdef EFX_ENABLE_DEBUG
811 if (rx_ev_other_err) {
812 EFX_INFO_RL(efx, " RX queue %d unexpected RX event "
813 EFX_QWORD_FMT "%s%s%s%s%s%s%s%s\n",
814 rx_queue->queue, EFX_QWORD_VAL(*event),
815 rx_ev_buf_owner_id_err ? " [OWNER_ID_ERR]" : "",
816 rx_ev_ip_hdr_chksum_err ?
817 " [IP_HDR_CHKSUM_ERR]" : "",
818 rx_ev_tcp_udp_chksum_err ?
819 " [TCP_UDP_CHKSUM_ERR]" : "",
820 rx_ev_eth_crc_err ? " [ETH_CRC_ERR]" : "",
821 rx_ev_frm_trunc ? " [FRM_TRUNC]" : "",
822 rx_ev_drib_nib ? " [DRIB_NIB]" : "",
823 rx_ev_tobe_disc ? " [TOBE_DISC]" : "",
824 rx_ev_pause_frm ? " [PAUSE]" : "");
825 }
826 #endif
827
828 if (unlikely(rx_ev_eth_crc_err && EFX_WORKAROUND_10750(efx) &&
829 efx->phy_type == PHY_TYPE_10XPRESS))
830 tenxpress_crc_err(efx);
831 }
832
833 /* Handle receive events that are not in-order. */
834 static void falcon_handle_rx_bad_index(struct efx_rx_queue *rx_queue,
835 unsigned index)
836 {
837 struct efx_nic *efx = rx_queue->efx;
838 unsigned expected, dropped;
839
840 expected = rx_queue->removed_count & FALCON_RXD_RING_MASK;
841 dropped = ((index + FALCON_RXD_RING_SIZE - expected) &
842 FALCON_RXD_RING_MASK);
843 EFX_INFO(efx, "dropped %d events (index=%d expected=%d)\n",
844 dropped, index, expected);
845
846 efx_schedule_reset(efx, EFX_WORKAROUND_5676(efx) ?
847 RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
848 }
849
850 /* Handle a packet received event
851 *
852 * Falcon silicon gives a "discard" flag if it's a unicast packet with the
853 * wrong destination address
854 * Also "is multicast" and "matches multicast filter" flags can be used to
855 * discard non-matching multicast packets.
856 */
857 static void falcon_handle_rx_event(struct efx_channel *channel,
858 const efx_qword_t *event)
859 {
860 unsigned int rx_ev_desc_ptr, rx_ev_byte_cnt;
861 unsigned int rx_ev_hdr_type, rx_ev_mcast_pkt;
862 unsigned expected_ptr;
863 bool rx_ev_pkt_ok, discard = false, checksummed;
864 struct efx_rx_queue *rx_queue;
865 struct efx_nic *efx = channel->efx;
866
867 /* Basic packet information */
868 rx_ev_byte_cnt = EFX_QWORD_FIELD(*event, RX_EV_BYTE_CNT);
869 rx_ev_pkt_ok = EFX_QWORD_FIELD(*event, RX_EV_PKT_OK);
870 rx_ev_hdr_type = EFX_QWORD_FIELD(*event, RX_EV_HDR_TYPE);
871 WARN_ON(EFX_QWORD_FIELD(*event, RX_EV_JUMBO_CONT));
872 WARN_ON(EFX_QWORD_FIELD(*event, RX_EV_SOP) != 1);
873 WARN_ON(EFX_QWORD_FIELD(*event, RX_EV_Q_LABEL) != channel->channel);
874
875 rx_queue = &efx->rx_queue[channel->channel];
876
877 rx_ev_desc_ptr = EFX_QWORD_FIELD(*event, RX_EV_DESC_PTR);
878 expected_ptr = rx_queue->removed_count & FALCON_RXD_RING_MASK;
879 if (unlikely(rx_ev_desc_ptr != expected_ptr))
880 falcon_handle_rx_bad_index(rx_queue, rx_ev_desc_ptr);
881
882 if (likely(rx_ev_pkt_ok)) {
883 /* If packet is marked as OK and packet type is TCP/IPv4 or
884 * UDP/IPv4, then we can rely on the hardware checksum.
885 */
886 checksummed = RX_EV_HDR_TYPE_HAS_CHECKSUMS(rx_ev_hdr_type);
887 } else {
888 falcon_handle_rx_not_ok(rx_queue, event, &rx_ev_pkt_ok,
889 &discard);
890 checksummed = false;
891 }
892
893 /* Detect multicast packets that didn't match the filter */
894 rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, RX_EV_MCAST_PKT);
895 if (rx_ev_mcast_pkt) {
896 unsigned int rx_ev_mcast_hash_match =
897 EFX_QWORD_FIELD(*event, RX_EV_MCAST_HASH_MATCH);
898
899 if (unlikely(!rx_ev_mcast_hash_match))
900 discard = true;
901 }
902
903 /* Handle received packet */
904 efx_rx_packet(rx_queue, rx_ev_desc_ptr, rx_ev_byte_cnt,
905 checksummed, discard);
906 }
907
908 /* Global events are basically PHY events */
909 static void falcon_handle_global_event(struct efx_channel *channel,
910 efx_qword_t *event)
911 {
912 struct efx_nic *efx = channel->efx;
913 bool is_phy_event = false, handled = false;
914
915 /* Check for interrupt on either port. Some boards have a
916 * single PHY wired to the interrupt line for port 1. */
917 if (EFX_QWORD_FIELD(*event, G_PHY0_INTR) ||
918 EFX_QWORD_FIELD(*event, G_PHY1_INTR) ||
919 EFX_QWORD_FIELD(*event, XG_PHY_INTR))
920 is_phy_event = true;
921
922 if ((falcon_rev(efx) >= FALCON_REV_B0) &&
923 EFX_QWORD_FIELD(*event, XG_MNT_INTR_B0))
924 is_phy_event = true;
925
926 if (is_phy_event) {
927 efx->phy_op->clear_interrupt(efx);
928 queue_work(efx->workqueue, &efx->reconfigure_work);
929 handled = true;
930 }
931
932 if (EFX_QWORD_FIELD_VER(efx, *event, RX_RECOVERY)) {
933 EFX_ERR(efx, "channel %d seen global RX_RESET "
934 "event. Resetting.\n", channel->channel);
935
936 atomic_inc(&efx->rx_reset);
937 efx_schedule_reset(efx, EFX_WORKAROUND_6555(efx) ?
938 RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
939 handled = true;
940 }
941
942 if (!handled)
943 EFX_ERR(efx, "channel %d unknown global event "
944 EFX_QWORD_FMT "\n", channel->channel,
945 EFX_QWORD_VAL(*event));
946 }
947
948 static void falcon_handle_driver_event(struct efx_channel *channel,
949 efx_qword_t *event)
950 {
951 struct efx_nic *efx = channel->efx;
952 unsigned int ev_sub_code;
953 unsigned int ev_sub_data;
954
955 ev_sub_code = EFX_QWORD_FIELD(*event, DRIVER_EV_SUB_CODE);
956 ev_sub_data = EFX_QWORD_FIELD(*event, DRIVER_EV_SUB_DATA);
957
958 switch (ev_sub_code) {
959 case TX_DESCQ_FLS_DONE_EV_DECODE:
960 EFX_TRACE(efx, "channel %d TXQ %d flushed\n",
961 channel->channel, ev_sub_data);
962 break;
963 case RX_DESCQ_FLS_DONE_EV_DECODE:
964 EFX_TRACE(efx, "channel %d RXQ %d flushed\n",
965 channel->channel, ev_sub_data);
966 break;
967 case EVQ_INIT_DONE_EV_DECODE:
968 EFX_LOG(efx, "channel %d EVQ %d initialised\n",
969 channel->channel, ev_sub_data);
970 break;
971 case SRM_UPD_DONE_EV_DECODE:
972 EFX_TRACE(efx, "channel %d SRAM update done\n",
973 channel->channel);
974 break;
975 case WAKE_UP_EV_DECODE:
976 EFX_TRACE(efx, "channel %d RXQ %d wakeup event\n",
977 channel->channel, ev_sub_data);
978 break;
979 case TIMER_EV_DECODE:
980 EFX_TRACE(efx, "channel %d RX queue %d timer expired\n",
981 channel->channel, ev_sub_data);
982 break;
983 case RX_RECOVERY_EV_DECODE:
984 EFX_ERR(efx, "channel %d seen DRIVER RX_RESET event. "
985 "Resetting.\n", channel->channel);
986 atomic_inc(&efx->rx_reset);
987 efx_schedule_reset(efx,
988 EFX_WORKAROUND_6555(efx) ?
989 RESET_TYPE_RX_RECOVERY :
990 RESET_TYPE_DISABLE);
991 break;
992 case RX_DSC_ERROR_EV_DECODE:
993 EFX_ERR(efx, "RX DMA Q %d reports descriptor fetch error."
994 " RX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
995 efx_schedule_reset(efx, RESET_TYPE_RX_DESC_FETCH);
996 break;
997 case TX_DSC_ERROR_EV_DECODE:
998 EFX_ERR(efx, "TX DMA Q %d reports descriptor fetch error."
999 " TX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
1000 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
1001 break;
1002 default:
1003 EFX_TRACE(efx, "channel %d unknown driver event code %d "
1004 "data %04x\n", channel->channel, ev_sub_code,
1005 ev_sub_data);
1006 break;
1007 }
1008 }
1009
1010 int falcon_process_eventq(struct efx_channel *channel, int rx_quota)
1011 {
1012 unsigned int read_ptr;
1013 efx_qword_t event, *p_event;
1014 int ev_code;
1015 int rx_packets = 0;
1016
1017 read_ptr = channel->eventq_read_ptr;
1018
1019 do {
1020 p_event = falcon_event(channel, read_ptr);
1021 event = *p_event;
1022
1023 if (!falcon_event_present(&event))
1024 /* End of events */
1025 break;
1026
1027 EFX_TRACE(channel->efx, "channel %d event is "EFX_QWORD_FMT"\n",
1028 channel->channel, EFX_QWORD_VAL(event));
1029
1030 /* Clear this event by marking it all ones */
1031 EFX_SET_QWORD(*p_event);
1032
1033 ev_code = EFX_QWORD_FIELD(event, EV_CODE);
1034
1035 switch (ev_code) {
1036 case RX_IP_EV_DECODE:
1037 falcon_handle_rx_event(channel, &event);
1038 ++rx_packets;
1039 break;
1040 case TX_IP_EV_DECODE:
1041 falcon_handle_tx_event(channel, &event);
1042 break;
1043 case DRV_GEN_EV_DECODE:
1044 channel->eventq_magic
1045 = EFX_QWORD_FIELD(event, EVQ_MAGIC);
1046 EFX_LOG(channel->efx, "channel %d received generated "
1047 "event "EFX_QWORD_FMT"\n", channel->channel,
1048 EFX_QWORD_VAL(event));
1049 break;
1050 case GLOBAL_EV_DECODE:
1051 falcon_handle_global_event(channel, &event);
1052 break;
1053 case DRIVER_EV_DECODE:
1054 falcon_handle_driver_event(channel, &event);
1055 break;
1056 default:
1057 EFX_ERR(channel->efx, "channel %d unknown event type %d"
1058 " (data " EFX_QWORD_FMT ")\n", channel->channel,
1059 ev_code, EFX_QWORD_VAL(event));
1060 }
1061
1062 /* Increment read pointer */
1063 read_ptr = (read_ptr + 1) & FALCON_EVQ_MASK;
1064
1065 } while (rx_packets < rx_quota);
1066
1067 channel->eventq_read_ptr = read_ptr;
1068 return rx_packets;
1069 }
1070
1071 void falcon_set_int_moderation(struct efx_channel *channel)
1072 {
1073 efx_dword_t timer_cmd;
1074 struct efx_nic *efx = channel->efx;
1075
1076 /* Set timer register */
1077 if (channel->irq_moderation) {
1078 /* Round to resolution supported by hardware. The value we
1079 * program is based at 0. So actual interrupt moderation
1080 * achieved is ((x + 1) * res).
1081 */
1082 unsigned int res = 5;
1083 channel->irq_moderation -= (channel->irq_moderation % res);
1084 if (channel->irq_moderation < res)
1085 channel->irq_moderation = res;
1086 EFX_POPULATE_DWORD_2(timer_cmd,
1087 TIMER_MODE, TIMER_MODE_INT_HLDOFF,
1088 TIMER_VAL,
1089 (channel->irq_moderation / res) - 1);
1090 } else {
1091 EFX_POPULATE_DWORD_2(timer_cmd,
1092 TIMER_MODE, TIMER_MODE_DIS,
1093 TIMER_VAL, 0);
1094 }
1095 falcon_writel_page_locked(efx, &timer_cmd, TIMER_CMD_REG_KER,
1096 channel->channel);
1097
1098 }
1099
1100 /* Allocate buffer table entries for event queue */
1101 int falcon_probe_eventq(struct efx_channel *channel)
1102 {
1103 struct efx_nic *efx = channel->efx;
1104 unsigned int evq_size;
1105
1106 evq_size = FALCON_EVQ_SIZE * sizeof(efx_qword_t);
1107 return falcon_alloc_special_buffer(efx, &channel->eventq, evq_size);
1108 }
1109
1110 void falcon_init_eventq(struct efx_channel *channel)
1111 {
1112 efx_oword_t evq_ptr;
1113 struct efx_nic *efx = channel->efx;
1114
1115 EFX_LOG(efx, "channel %d event queue in special buffers %d-%d\n",
1116 channel->channel, channel->eventq.index,
1117 channel->eventq.index + channel->eventq.entries - 1);
1118
1119 /* Pin event queue buffer */
1120 falcon_init_special_buffer(efx, &channel->eventq);
1121
1122 /* Fill event queue with all ones (i.e. empty events) */
1123 memset(channel->eventq.addr, 0xff, channel->eventq.len);
1124
1125 /* Push event queue to card */
1126 EFX_POPULATE_OWORD_3(evq_ptr,
1127 EVQ_EN, 1,
1128 EVQ_SIZE, FALCON_EVQ_ORDER,
1129 EVQ_BUF_BASE_ID, channel->eventq.index);
1130 falcon_write_table(efx, &evq_ptr, efx->type->evq_ptr_tbl_base,
1131 channel->channel);
1132
1133 falcon_set_int_moderation(channel);
1134 }
1135
1136 void falcon_fini_eventq(struct efx_channel *channel)
1137 {
1138 efx_oword_t eventq_ptr;
1139 struct efx_nic *efx = channel->efx;
1140
1141 /* Remove event queue from card */
1142 EFX_ZERO_OWORD(eventq_ptr);
1143 falcon_write_table(efx, &eventq_ptr, efx->type->evq_ptr_tbl_base,
1144 channel->channel);
1145
1146 /* Unpin event queue */
1147 falcon_fini_special_buffer(efx, &channel->eventq);
1148 }
1149
1150 /* Free buffers backing event queue */
1151 void falcon_remove_eventq(struct efx_channel *channel)
1152 {
1153 falcon_free_special_buffer(channel->efx, &channel->eventq);
1154 }
1155
1156
1157 /* Generates a test event on the event queue. A subsequent call to
1158 * process_eventq() should pick up the event and place the value of
1159 * "magic" into channel->eventq_magic;
1160 */
1161 void falcon_generate_test_event(struct efx_channel *channel, unsigned int magic)
1162 {
1163 efx_qword_t test_event;
1164
1165 EFX_POPULATE_QWORD_2(test_event,
1166 EV_CODE, DRV_GEN_EV_DECODE,
1167 EVQ_MAGIC, magic);
1168 falcon_generate_event(channel, &test_event);
1169 }
1170
1171 void falcon_sim_phy_event(struct efx_nic *efx)
1172 {
1173 efx_qword_t phy_event;
1174
1175 EFX_POPULATE_QWORD_1(phy_event, EV_CODE, GLOBAL_EV_DECODE);
1176 if (EFX_IS10G(efx))
1177 EFX_SET_OWORD_FIELD(phy_event, XG_PHY_INTR, 1);
1178 else
1179 EFX_SET_OWORD_FIELD(phy_event, G_PHY0_INTR, 1);
1180
1181 falcon_generate_event(&efx->channel[0], &phy_event);
1182 }
1183
1184 /**************************************************************************
1185 *
1186 * Flush handling
1187 *
1188 **************************************************************************/
1189
1190
1191 static void falcon_poll_flush_events(struct efx_nic *efx)
1192 {
1193 struct efx_channel *channel = &efx->channel[0];
1194 struct efx_tx_queue *tx_queue;
1195 struct efx_rx_queue *rx_queue;
1196 unsigned int read_ptr, i;
1197
1198 read_ptr = channel->eventq_read_ptr;
1199 for (i = 0; i < FALCON_EVQ_SIZE; ++i) {
1200 efx_qword_t *event = falcon_event(channel, read_ptr);
1201 int ev_code, ev_sub_code, ev_queue;
1202 bool ev_failed;
1203 if (!falcon_event_present(event))
1204 break;
1205
1206 ev_code = EFX_QWORD_FIELD(*event, EV_CODE);
1207 if (ev_code != DRIVER_EV_DECODE)
1208 continue;
1209
1210 ev_sub_code = EFX_QWORD_FIELD(*event, DRIVER_EV_SUB_CODE);
1211 switch (ev_sub_code) {
1212 case TX_DESCQ_FLS_DONE_EV_DECODE:
1213 ev_queue = EFX_QWORD_FIELD(*event,
1214 DRIVER_EV_TX_DESCQ_ID);
1215 if (ev_queue < EFX_TX_QUEUE_COUNT) {
1216 tx_queue = efx->tx_queue + ev_queue;
1217 tx_queue->flushed = true;
1218 }
1219 break;
1220 case RX_DESCQ_FLS_DONE_EV_DECODE:
1221 ev_queue = EFX_QWORD_FIELD(*event,
1222 DRIVER_EV_RX_DESCQ_ID);
1223 ev_failed = EFX_QWORD_FIELD(*event,
1224 DRIVER_EV_RX_FLUSH_FAIL);
1225 if (ev_queue < efx->n_rx_queues) {
1226 rx_queue = efx->rx_queue + ev_queue;
1227
1228 /* retry the rx flush */
1229 if (ev_failed)
1230 falcon_flush_rx_queue(rx_queue);
1231 else
1232 rx_queue->flushed = true;
1233 }
1234 break;
1235 }
1236
1237 read_ptr = (read_ptr + 1) & FALCON_EVQ_MASK;
1238 }
1239 }
1240
1241 /* Handle tx and rx flushes at the same time, since they run in
1242 * parallel in the hardware and there's no reason for us to
1243 * serialise them */
1244 int falcon_flush_queues(struct efx_nic *efx)
1245 {
1246 struct efx_rx_queue *rx_queue;
1247 struct efx_tx_queue *tx_queue;
1248 int i;
1249 bool outstanding;
1250
1251 /* Issue flush requests */
1252 efx_for_each_tx_queue(tx_queue, efx) {
1253 tx_queue->flushed = false;
1254 falcon_flush_tx_queue(tx_queue);
1255 }
1256 efx_for_each_rx_queue(rx_queue, efx) {
1257 rx_queue->flushed = false;
1258 falcon_flush_rx_queue(rx_queue);
1259 }
1260
1261 /* Poll the evq looking for flush completions. Since we're not pushing
1262 * any more rx or tx descriptors at this point, we're in no danger of
1263 * overflowing the evq whilst we wait */
1264 for (i = 0; i < FALCON_FLUSH_POLL_COUNT; ++i) {
1265 msleep(FALCON_FLUSH_INTERVAL);
1266 falcon_poll_flush_events(efx);
1267
1268 /* Check if every queue has been succesfully flushed */
1269 outstanding = false;
1270 efx_for_each_tx_queue(tx_queue, efx)
1271 outstanding |= !tx_queue->flushed;
1272 efx_for_each_rx_queue(rx_queue, efx)
1273 outstanding |= !rx_queue->flushed;
1274 if (!outstanding)
1275 return 0;
1276 }
1277
1278 /* Mark the queues as all flushed. We're going to return failure
1279 * leading to a reset, or fake up success anyway. "flushed" now
1280 * indicates that we tried to flush. */
1281 efx_for_each_tx_queue(tx_queue, efx) {
1282 if (!tx_queue->flushed)
1283 EFX_ERR(efx, "tx queue %d flush command timed out\n",
1284 tx_queue->queue);
1285 tx_queue->flushed = true;
1286 }
1287 efx_for_each_rx_queue(rx_queue, efx) {
1288 if (!rx_queue->flushed)
1289 EFX_ERR(efx, "rx queue %d flush command timed out\n",
1290 rx_queue->queue);
1291 rx_queue->flushed = true;
1292 }
1293
1294 if (EFX_WORKAROUND_7803(efx))
1295 return 0;
1296
1297 return -ETIMEDOUT;
1298 }
1299
1300 /**************************************************************************
1301 *
1302 * Falcon hardware interrupts
1303 * The hardware interrupt handler does very little work; all the event
1304 * queue processing is carried out by per-channel tasklets.
1305 *
1306 **************************************************************************/
1307
1308 /* Enable/disable/generate Falcon interrupts */
1309 static inline void falcon_interrupts(struct efx_nic *efx, int enabled,
1310 int force)
1311 {
1312 efx_oword_t int_en_reg_ker;
1313
1314 EFX_POPULATE_OWORD_2(int_en_reg_ker,
1315 KER_INT_KER, force,
1316 DRV_INT_EN_KER, enabled);
1317 falcon_write(efx, &int_en_reg_ker, INT_EN_REG_KER);
1318 }
1319
1320 void falcon_enable_interrupts(struct efx_nic *efx)
1321 {
1322 efx_oword_t int_adr_reg_ker;
1323 struct efx_channel *channel;
1324
1325 EFX_ZERO_OWORD(*((efx_oword_t *) efx->irq_status.addr));
1326 wmb(); /* Ensure interrupt vector is clear before interrupts enabled */
1327
1328 /* Program address */
1329 EFX_POPULATE_OWORD_2(int_adr_reg_ker,
1330 NORM_INT_VEC_DIS_KER, EFX_INT_MODE_USE_MSI(efx),
1331 INT_ADR_KER, efx->irq_status.dma_addr);
1332 falcon_write(efx, &int_adr_reg_ker, INT_ADR_REG_KER);
1333
1334 /* Enable interrupts */
1335 falcon_interrupts(efx, 1, 0);
1336
1337 /* Force processing of all the channels to get the EVQ RPTRs up to
1338 date */
1339 efx_for_each_channel(channel, efx)
1340 efx_schedule_channel(channel);
1341 }
1342
1343 void falcon_disable_interrupts(struct efx_nic *efx)
1344 {
1345 /* Disable interrupts */
1346 falcon_interrupts(efx, 0, 0);
1347 }
1348
1349 /* Generate a Falcon test interrupt
1350 * Interrupt must already have been enabled, otherwise nasty things
1351 * may happen.
1352 */
1353 void falcon_generate_interrupt(struct efx_nic *efx)
1354 {
1355 falcon_interrupts(efx, 1, 1);
1356 }
1357
1358 /* Acknowledge a legacy interrupt from Falcon
1359 *
1360 * This acknowledges a legacy (not MSI) interrupt via INT_ACK_KER_REG.
1361 *
1362 * Due to SFC bug 3706 (silicon revision <=A1) reads can be duplicated in the
1363 * BIU. Interrupt acknowledge is read sensitive so must write instead
1364 * (then read to ensure the BIU collector is flushed)
1365 *
1366 * NB most hardware supports MSI interrupts
1367 */
1368 static inline void falcon_irq_ack_a1(struct efx_nic *efx)
1369 {
1370 efx_dword_t reg;
1371
1372 EFX_POPULATE_DWORD_1(reg, INT_ACK_DUMMY_DATA, 0xb7eb7e);
1373 falcon_writel(efx, &reg, INT_ACK_REG_KER_A1);
1374 falcon_readl(efx, &reg, WORK_AROUND_BROKEN_PCI_READS_REG_KER_A1);
1375 }
1376
1377 /* Process a fatal interrupt
1378 * Disable bus mastering ASAP and schedule a reset
1379 */
1380 static irqreturn_t falcon_fatal_interrupt(struct efx_nic *efx)
1381 {
1382 struct falcon_nic_data *nic_data = efx->nic_data;
1383 efx_oword_t *int_ker = efx->irq_status.addr;
1384 efx_oword_t fatal_intr;
1385 int error, mem_perr;
1386 static int n_int_errors;
1387
1388 falcon_read(efx, &fatal_intr, FATAL_INTR_REG_KER);
1389 error = EFX_OWORD_FIELD(fatal_intr, INT_KER_ERROR);
1390
1391 EFX_ERR(efx, "SYSTEM ERROR " EFX_OWORD_FMT " status "
1392 EFX_OWORD_FMT ": %s\n", EFX_OWORD_VAL(*int_ker),
1393 EFX_OWORD_VAL(fatal_intr),
1394 error ? "disabling bus mastering" : "no recognised error");
1395 if (error == 0)
1396 goto out;
1397
1398 /* If this is a memory parity error dump which blocks are offending */
1399 mem_perr = EFX_OWORD_FIELD(fatal_intr, MEM_PERR_INT_KER);
1400 if (mem_perr) {
1401 efx_oword_t reg;
1402 falcon_read(efx, &reg, MEM_STAT_REG_KER);
1403 EFX_ERR(efx, "SYSTEM ERROR: memory parity error "
1404 EFX_OWORD_FMT "\n", EFX_OWORD_VAL(reg));
1405 }
1406
1407 /* Disable both devices */
1408 pci_disable_device(efx->pci_dev);
1409 if (FALCON_IS_DUAL_FUNC(efx))
1410 pci_disable_device(nic_data->pci_dev2);
1411 falcon_disable_interrupts(efx);
1412
1413 if (++n_int_errors < FALCON_MAX_INT_ERRORS) {
1414 EFX_ERR(efx, "SYSTEM ERROR - reset scheduled\n");
1415 efx_schedule_reset(efx, RESET_TYPE_INT_ERROR);
1416 } else {
1417 EFX_ERR(efx, "SYSTEM ERROR - max number of errors seen."
1418 "NIC will be disabled\n");
1419 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1420 }
1421 out:
1422 return IRQ_HANDLED;
1423 }
1424
1425 /* Handle a legacy interrupt from Falcon
1426 * Acknowledges the interrupt and schedule event queue processing.
1427 */
1428 static irqreturn_t falcon_legacy_interrupt_b0(int irq, void *dev_id)
1429 {
1430 struct efx_nic *efx = dev_id;
1431 efx_oword_t *int_ker = efx->irq_status.addr;
1432 struct efx_channel *channel;
1433 efx_dword_t reg;
1434 u32 queues;
1435 int syserr;
1436
1437 /* Read the ISR which also ACKs the interrupts */
1438 falcon_readl(efx, &reg, INT_ISR0_B0);
1439 queues = EFX_EXTRACT_DWORD(reg, 0, 31);
1440
1441 /* Check to see if we have a serious error condition */
1442 syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT);
1443 if (unlikely(syserr))
1444 return falcon_fatal_interrupt(efx);
1445
1446 if (queues == 0)
1447 return IRQ_NONE;
1448
1449 efx->last_irq_cpu = raw_smp_processor_id();
1450 EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
1451 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
1452
1453 /* Schedule processing of any interrupting queues */
1454 channel = &efx->channel[0];
1455 while (queues) {
1456 if (queues & 0x01)
1457 efx_schedule_channel(channel);
1458 channel++;
1459 queues >>= 1;
1460 }
1461
1462 return IRQ_HANDLED;
1463 }
1464
1465
1466 static irqreturn_t falcon_legacy_interrupt_a1(int irq, void *dev_id)
1467 {
1468 struct efx_nic *efx = dev_id;
1469 efx_oword_t *int_ker = efx->irq_status.addr;
1470 struct efx_channel *channel;
1471 int syserr;
1472 int queues;
1473
1474 /* Check to see if this is our interrupt. If it isn't, we
1475 * exit without having touched the hardware.
1476 */
1477 if (unlikely(EFX_OWORD_IS_ZERO(*int_ker))) {
1478 EFX_TRACE(efx, "IRQ %d on CPU %d not for me\n", irq,
1479 raw_smp_processor_id());
1480 return IRQ_NONE;
1481 }
1482 efx->last_irq_cpu = raw_smp_processor_id();
1483 EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1484 irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1485
1486 /* Check to see if we have a serious error condition */
1487 syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT);
1488 if (unlikely(syserr))
1489 return falcon_fatal_interrupt(efx);
1490
1491 /* Determine interrupting queues, clear interrupt status
1492 * register and acknowledge the device interrupt.
1493 */
1494 BUILD_BUG_ON(INT_EVQS_WIDTH > EFX_MAX_CHANNELS);
1495 queues = EFX_OWORD_FIELD(*int_ker, INT_EVQS);
1496 EFX_ZERO_OWORD(*int_ker);
1497 wmb(); /* Ensure the vector is cleared before interrupt ack */
1498 falcon_irq_ack_a1(efx);
1499
1500 /* Schedule processing of any interrupting queues */
1501 channel = &efx->channel[0];
1502 while (queues) {
1503 if (queues & 0x01)
1504 efx_schedule_channel(channel);
1505 channel++;
1506 queues >>= 1;
1507 }
1508
1509 return IRQ_HANDLED;
1510 }
1511
1512 /* Handle an MSI interrupt from Falcon
1513 *
1514 * Handle an MSI hardware interrupt. This routine schedules event
1515 * queue processing. No interrupt acknowledgement cycle is necessary.
1516 * Also, we never need to check that the interrupt is for us, since
1517 * MSI interrupts cannot be shared.
1518 */
1519 static irqreturn_t falcon_msi_interrupt(int irq, void *dev_id)
1520 {
1521 struct efx_channel *channel = dev_id;
1522 struct efx_nic *efx = channel->efx;
1523 efx_oword_t *int_ker = efx->irq_status.addr;
1524 int syserr;
1525
1526 efx->last_irq_cpu = raw_smp_processor_id();
1527 EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1528 irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1529
1530 /* Check to see if we have a serious error condition */
1531 syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT);
1532 if (unlikely(syserr))
1533 return falcon_fatal_interrupt(efx);
1534
1535 /* Schedule processing of the channel */
1536 efx_schedule_channel(channel);
1537
1538 return IRQ_HANDLED;
1539 }
1540
1541
1542 /* Setup RSS indirection table.
1543 * This maps from the hash value of the packet to RXQ
1544 */
1545 static void falcon_setup_rss_indir_table(struct efx_nic *efx)
1546 {
1547 int i = 0;
1548 unsigned long offset;
1549 efx_dword_t dword;
1550
1551 if (falcon_rev(efx) < FALCON_REV_B0)
1552 return;
1553
1554 for (offset = RX_RSS_INDIR_TBL_B0;
1555 offset < RX_RSS_INDIR_TBL_B0 + 0x800;
1556 offset += 0x10) {
1557 EFX_POPULATE_DWORD_1(dword, RX_RSS_INDIR_ENT_B0,
1558 i % efx->n_rx_queues);
1559 falcon_writel(efx, &dword, offset);
1560 i++;
1561 }
1562 }
1563
1564 /* Hook interrupt handler(s)
1565 * Try MSI and then legacy interrupts.
1566 */
1567 int falcon_init_interrupt(struct efx_nic *efx)
1568 {
1569 struct efx_channel *channel;
1570 int rc;
1571
1572 if (!EFX_INT_MODE_USE_MSI(efx)) {
1573 irq_handler_t handler;
1574 if (falcon_rev(efx) >= FALCON_REV_B0)
1575 handler = falcon_legacy_interrupt_b0;
1576 else
1577 handler = falcon_legacy_interrupt_a1;
1578
1579 rc = request_irq(efx->legacy_irq, handler, IRQF_SHARED,
1580 efx->name, efx);
1581 if (rc) {
1582 EFX_ERR(efx, "failed to hook legacy IRQ %d\n",
1583 efx->pci_dev->irq);
1584 goto fail1;
1585 }
1586 return 0;
1587 }
1588
1589 /* Hook MSI or MSI-X interrupt */
1590 efx_for_each_channel(channel, efx) {
1591 rc = request_irq(channel->irq, falcon_msi_interrupt,
1592 IRQF_PROBE_SHARED, /* Not shared */
1593 channel->name, channel);
1594 if (rc) {
1595 EFX_ERR(efx, "failed to hook IRQ %d\n", channel->irq);
1596 goto fail2;
1597 }
1598 }
1599
1600 return 0;
1601
1602 fail2:
1603 efx_for_each_channel(channel, efx)
1604 free_irq(channel->irq, channel);
1605 fail1:
1606 return rc;
1607 }
1608
1609 void falcon_fini_interrupt(struct efx_nic *efx)
1610 {
1611 struct efx_channel *channel;
1612 efx_oword_t reg;
1613
1614 /* Disable MSI/MSI-X interrupts */
1615 efx_for_each_channel(channel, efx) {
1616 if (channel->irq)
1617 free_irq(channel->irq, channel);
1618 }
1619
1620 /* ACK legacy interrupt */
1621 if (falcon_rev(efx) >= FALCON_REV_B0)
1622 falcon_read(efx, &reg, INT_ISR0_B0);
1623 else
1624 falcon_irq_ack_a1(efx);
1625
1626 /* Disable legacy interrupt */
1627 if (efx->legacy_irq)
1628 free_irq(efx->legacy_irq, efx);
1629 }
1630
1631 /**************************************************************************
1632 *
1633 * EEPROM/flash
1634 *
1635 **************************************************************************
1636 */
1637
1638 #define FALCON_SPI_MAX_LEN sizeof(efx_oword_t)
1639
1640 static int falcon_spi_poll(struct efx_nic *efx)
1641 {
1642 efx_oword_t reg;
1643 falcon_read(efx, &reg, EE_SPI_HCMD_REG_KER);
1644 return EFX_OWORD_FIELD(reg, EE_SPI_HCMD_CMD_EN) ? -EBUSY : 0;
1645 }
1646
1647 /* Wait for SPI command completion */
1648 static int falcon_spi_wait(struct efx_nic *efx)
1649 {
1650 /* Most commands will finish quickly, so we start polling at
1651 * very short intervals. Sometimes the command may have to
1652 * wait for VPD or expansion ROM access outside of our
1653 * control, so we allow up to 100 ms. */
1654 unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 10);
1655 int i;
1656
1657 for (i = 0; i < 10; i++) {
1658 if (!falcon_spi_poll(efx))
1659 return 0;
1660 udelay(10);
1661 }
1662
1663 for (;;) {
1664 if (!falcon_spi_poll(efx))
1665 return 0;
1666 if (time_after_eq(jiffies, timeout)) {
1667 EFX_ERR(efx, "timed out waiting for SPI\n");
1668 return -ETIMEDOUT;
1669 }
1670 schedule_timeout_uninterruptible(1);
1671 }
1672 }
1673
1674 int falcon_spi_cmd(const struct efx_spi_device *spi,
1675 unsigned int command, int address,
1676 const void *in, void *out, size_t len)
1677 {
1678 struct efx_nic *efx = spi->efx;
1679 bool addressed = (address >= 0);
1680 bool reading = (out != NULL);
1681 efx_oword_t reg;
1682 int rc;
1683
1684 /* Input validation */
1685 if (len > FALCON_SPI_MAX_LEN)
1686 return -EINVAL;
1687 BUG_ON(!mutex_is_locked(&efx->spi_lock));
1688
1689 /* Check that previous command is not still running */
1690 rc = falcon_spi_poll(efx);
1691 if (rc)
1692 return rc;
1693
1694 /* Program address register, if we have an address */
1695 if (addressed) {
1696 EFX_POPULATE_OWORD_1(reg, EE_SPI_HADR_ADR, address);
1697 falcon_write(efx, &reg, EE_SPI_HADR_REG_KER);
1698 }
1699
1700 /* Program data register, if we have data */
1701 if (in != NULL) {
1702 memcpy(&reg, in, len);
1703 falcon_write(efx, &reg, EE_SPI_HDATA_REG_KER);
1704 }
1705
1706 /* Issue read/write command */
1707 EFX_POPULATE_OWORD_7(reg,
1708 EE_SPI_HCMD_CMD_EN, 1,
1709 EE_SPI_HCMD_SF_SEL, spi->device_id,
1710 EE_SPI_HCMD_DABCNT, len,
1711 EE_SPI_HCMD_READ, reading,
1712 EE_SPI_HCMD_DUBCNT, 0,
1713 EE_SPI_HCMD_ADBCNT,
1714 (addressed ? spi->addr_len : 0),
1715 EE_SPI_HCMD_ENC, command);
1716 falcon_write(efx, &reg, EE_SPI_HCMD_REG_KER);
1717
1718 /* Wait for read/write to complete */
1719 rc = falcon_spi_wait(efx);
1720 if (rc)
1721 return rc;
1722
1723 /* Read data */
1724 if (out != NULL) {
1725 falcon_read(efx, &reg, EE_SPI_HDATA_REG_KER);
1726 memcpy(out, &reg, len);
1727 }
1728
1729 return 0;
1730 }
1731
1732 static size_t
1733 falcon_spi_write_limit(const struct efx_spi_device *spi, size_t start)
1734 {
1735 return min(FALCON_SPI_MAX_LEN,
1736 (spi->block_size - (start & (spi->block_size - 1))));
1737 }
1738
1739 static inline u8
1740 efx_spi_munge_command(const struct efx_spi_device *spi,
1741 const u8 command, const unsigned int address)
1742 {
1743 return command | (((address >> 8) & spi->munge_address) << 3);
1744 }
1745
1746 /* Wait up to 10 ms for buffered write completion */
1747 int falcon_spi_wait_write(const struct efx_spi_device *spi)
1748 {
1749 struct efx_nic *efx = spi->efx;
1750 unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 100);
1751 u8 status;
1752 int rc;
1753
1754 for (;;) {
1755 rc = falcon_spi_cmd(spi, SPI_RDSR, -1, NULL,
1756 &status, sizeof(status));
1757 if (rc)
1758 return rc;
1759 if (!(status & SPI_STATUS_NRDY))
1760 return 0;
1761 if (time_after_eq(jiffies, timeout)) {
1762 EFX_ERR(efx, "SPI write timeout on device %d"
1763 " last status=0x%02x\n",
1764 spi->device_id, status);
1765 return -ETIMEDOUT;
1766 }
1767 schedule_timeout_uninterruptible(1);
1768 }
1769 }
1770
1771 int falcon_spi_read(const struct efx_spi_device *spi, loff_t start,
1772 size_t len, size_t *retlen, u8 *buffer)
1773 {
1774 size_t block_len, pos = 0;
1775 unsigned int command;
1776 int rc = 0;
1777
1778 while (pos < len) {
1779 block_len = min(len - pos, FALCON_SPI_MAX_LEN);
1780
1781 command = efx_spi_munge_command(spi, SPI_READ, start + pos);
1782 rc = falcon_spi_cmd(spi, command, start + pos, NULL,
1783 buffer + pos, block_len);
1784 if (rc)
1785 break;
1786 pos += block_len;
1787
1788 /* Avoid locking up the system */
1789 cond_resched();
1790 if (signal_pending(current)) {
1791 rc = -EINTR;
1792 break;
1793 }
1794 }
1795
1796 if (retlen)
1797 *retlen = pos;
1798 return rc;
1799 }
1800
1801 int falcon_spi_write(const struct efx_spi_device *spi, loff_t start,
1802 size_t len, size_t *retlen, const u8 *buffer)
1803 {
1804 u8 verify_buffer[FALCON_SPI_MAX_LEN];
1805 size_t block_len, pos = 0;
1806 unsigned int command;
1807 int rc = 0;
1808
1809 while (pos < len) {
1810 rc = falcon_spi_cmd(spi, SPI_WREN, -1, NULL, NULL, 0);
1811 if (rc)
1812 break;
1813
1814 block_len = min(len - pos,
1815 falcon_spi_write_limit(spi, start + pos));
1816 command = efx_spi_munge_command(spi, SPI_WRITE, start + pos);
1817 rc = falcon_spi_cmd(spi, command, start + pos,
1818 buffer + pos, NULL, block_len);
1819 if (rc)
1820 break;
1821
1822 rc = falcon_spi_wait_write(spi);
1823 if (rc)
1824 break;
1825
1826 command = efx_spi_munge_command(spi, SPI_READ, start + pos);
1827 rc = falcon_spi_cmd(spi, command, start + pos,
1828 NULL, verify_buffer, block_len);
1829 if (memcmp(verify_buffer, buffer + pos, block_len)) {
1830 rc = -EIO;
1831 break;
1832 }
1833
1834 pos += block_len;
1835
1836 /* Avoid locking up the system */
1837 cond_resched();
1838 if (signal_pending(current)) {
1839 rc = -EINTR;
1840 break;
1841 }
1842 }
1843
1844 if (retlen)
1845 *retlen = pos;
1846 return rc;
1847 }
1848
1849 /**************************************************************************
1850 *
1851 * MAC wrapper
1852 *
1853 **************************************************************************
1854 */
1855
1856 static int falcon_reset_macs(struct efx_nic *efx)
1857 {
1858 efx_oword_t reg;
1859 int count;
1860
1861 if (falcon_rev(efx) < FALCON_REV_B0) {
1862 /* It's not safe to use GLB_CTL_REG to reset the
1863 * macs, so instead use the internal MAC resets
1864 */
1865 if (!EFX_IS10G(efx)) {
1866 EFX_POPULATE_OWORD_1(reg, GM_SW_RST, 1);
1867 falcon_write(efx, &reg, GM_CFG1_REG);
1868 udelay(1000);
1869
1870 EFX_POPULATE_OWORD_1(reg, GM_SW_RST, 0);
1871 falcon_write(efx, &reg, GM_CFG1_REG);
1872 udelay(1000);
1873 return 0;
1874 } else {
1875 EFX_POPULATE_OWORD_1(reg, XM_CORE_RST, 1);
1876 falcon_write(efx, &reg, XM_GLB_CFG_REG);
1877
1878 for (count = 0; count < 10000; count++) {
1879 falcon_read(efx, &reg, XM_GLB_CFG_REG);
1880 if (EFX_OWORD_FIELD(reg, XM_CORE_RST) == 0)
1881 return 0;
1882 udelay(10);
1883 }
1884
1885 EFX_ERR(efx, "timed out waiting for XMAC core reset\n");
1886 return -ETIMEDOUT;
1887 }
1888 }
1889
1890 /* MAC stats will fail whilst the TX fifo is draining. Serialise
1891 * the drain sequence with the statistics fetch */
1892 spin_lock(&efx->stats_lock);
1893
1894 falcon_read(efx, &reg, MAC0_CTRL_REG_KER);
1895 EFX_SET_OWORD_FIELD(reg, TXFIFO_DRAIN_EN_B0, 1);
1896 falcon_write(efx, &reg, MAC0_CTRL_REG_KER);
1897
1898 falcon_read(efx, &reg, GLB_CTL_REG_KER);
1899 EFX_SET_OWORD_FIELD(reg, RST_XGTX, 1);
1900 EFX_SET_OWORD_FIELD(reg, RST_XGRX, 1);
1901 EFX_SET_OWORD_FIELD(reg, RST_EM, 1);
1902 falcon_write(efx, &reg, GLB_CTL_REG_KER);
1903
1904 count = 0;
1905 while (1) {
1906 falcon_read(efx, &reg, GLB_CTL_REG_KER);
1907 if (!EFX_OWORD_FIELD(reg, RST_XGTX) &&
1908 !EFX_OWORD_FIELD(reg, RST_XGRX) &&
1909 !EFX_OWORD_FIELD(reg, RST_EM)) {
1910 EFX_LOG(efx, "Completed MAC reset after %d loops\n",
1911 count);
1912 break;
1913 }
1914 if (count > 20) {
1915 EFX_ERR(efx, "MAC reset failed\n");
1916 break;
1917 }
1918 count++;
1919 udelay(10);
1920 }
1921
1922 spin_unlock(&efx->stats_lock);
1923
1924 /* If we've reset the EM block and the link is up, then
1925 * we'll have to kick the XAUI link so the PHY can recover */
1926 if (efx->link_up && EFX_IS10G(efx) && EFX_WORKAROUND_5147(efx))
1927 falcon_reset_xaui(efx);
1928
1929 return 0;
1930 }
1931
1932 void falcon_drain_tx_fifo(struct efx_nic *efx)
1933 {
1934 efx_oword_t reg;
1935
1936 if ((falcon_rev(efx) < FALCON_REV_B0) ||
1937 (efx->loopback_mode != LOOPBACK_NONE))
1938 return;
1939
1940 falcon_read(efx, &reg, MAC0_CTRL_REG_KER);
1941 /* There is no point in draining more than once */
1942 if (EFX_OWORD_FIELD(reg, TXFIFO_DRAIN_EN_B0))
1943 return;
1944
1945 falcon_reset_macs(efx);
1946 }
1947
1948 void falcon_deconfigure_mac_wrapper(struct efx_nic *efx)
1949 {
1950 efx_oword_t reg;
1951
1952 if (falcon_rev(efx) < FALCON_REV_B0)
1953 return;
1954
1955 /* Isolate the MAC -> RX */
1956 falcon_read(efx, &reg, RX_CFG_REG_KER);
1957 EFX_SET_OWORD_FIELD(reg, RX_INGR_EN_B0, 0);
1958 falcon_write(efx, &reg, RX_CFG_REG_KER);
1959
1960 if (!efx->link_up)
1961 falcon_drain_tx_fifo(efx);
1962 }
1963
1964 void falcon_reconfigure_mac_wrapper(struct efx_nic *efx)
1965 {
1966 efx_oword_t reg;
1967 int link_speed;
1968 bool tx_fc;
1969
1970 switch (efx->link_speed) {
1971 case 10000: link_speed = 3; break;
1972 case 1000: link_speed = 2; break;
1973 case 100: link_speed = 1; break;
1974 default: link_speed = 0; break;
1975 }
1976 /* MAC_LINK_STATUS controls MAC backpressure but doesn't work
1977 * as advertised. Disable to ensure packets are not
1978 * indefinitely held and TX queue can be flushed at any point
1979 * while the link is down. */
1980 EFX_POPULATE_OWORD_5(reg,
1981 MAC_XOFF_VAL, 0xffff /* max pause time */,
1982 MAC_BCAD_ACPT, 1,
1983 MAC_UC_PROM, efx->promiscuous,
1984 MAC_LINK_STATUS, 1, /* always set */
1985 MAC_SPEED, link_speed);
1986 /* On B0, MAC backpressure can be disabled and packets get
1987 * discarded. */
1988 if (falcon_rev(efx) >= FALCON_REV_B0) {
1989 EFX_SET_OWORD_FIELD(reg, TXFIFO_DRAIN_EN_B0,
1990 !efx->link_up);
1991 }
1992
1993 falcon_write(efx, &reg, MAC0_CTRL_REG_KER);
1994
1995 /* Restore the multicast hash registers. */
1996 falcon_set_multicast_hash(efx);
1997
1998 /* Transmission of pause frames when RX crosses the threshold is
1999 * covered by RX_XOFF_MAC_EN and XM_TX_CFG_REG:XM_FCNTL.
2000 * Action on receipt of pause frames is controller by XM_DIS_FCNTL */
2001 tx_fc = !!(efx->flow_control & EFX_FC_TX);
2002 falcon_read(efx, &reg, RX_CFG_REG_KER);
2003 EFX_SET_OWORD_FIELD_VER(efx, reg, RX_XOFF_MAC_EN, tx_fc);
2004
2005 /* Unisolate the MAC -> RX */
2006 if (falcon_rev(efx) >= FALCON_REV_B0)
2007 EFX_SET_OWORD_FIELD(reg, RX_INGR_EN_B0, 1);
2008 falcon_write(efx, &reg, RX_CFG_REG_KER);
2009 }
2010
2011 int falcon_dma_stats(struct efx_nic *efx, unsigned int done_offset)
2012 {
2013 efx_oword_t reg;
2014 u32 *dma_done;
2015 int i;
2016
2017 if (disable_dma_stats)
2018 return 0;
2019
2020 /* Statistics fetch will fail if the MAC is in TX drain */
2021 if (falcon_rev(efx) >= FALCON_REV_B0) {
2022 efx_oword_t temp;
2023 falcon_read(efx, &temp, MAC0_CTRL_REG_KER);
2024 if (EFX_OWORD_FIELD(temp, TXFIFO_DRAIN_EN_B0))
2025 return 0;
2026 }
2027
2028 dma_done = (efx->stats_buffer.addr + done_offset);
2029 *dma_done = FALCON_STATS_NOT_DONE;
2030 wmb(); /* ensure done flag is clear */
2031
2032 /* Initiate DMA transfer of stats */
2033 EFX_POPULATE_OWORD_2(reg,
2034 MAC_STAT_DMA_CMD, 1,
2035 MAC_STAT_DMA_ADR,
2036 efx->stats_buffer.dma_addr);
2037 falcon_write(efx, &reg, MAC0_STAT_DMA_REG_KER);
2038
2039 /* Wait for transfer to complete */
2040 for (i = 0; i < 400; i++) {
2041 if (*(volatile u32 *)dma_done == FALCON_STATS_DONE) {
2042 rmb(); /* Ensure the stats are valid. */
2043 return 0;
2044 }
2045 udelay(10);
2046 }
2047
2048 EFX_ERR(efx, "timed out waiting for statistics\n");
2049 return -ETIMEDOUT;
2050 }
2051
2052 /**************************************************************************
2053 *
2054 * PHY access via GMII
2055 *
2056 **************************************************************************
2057 */
2058
2059 /* Use the top bit of the MII PHY id to indicate the PHY type
2060 * (1G/10G), with the remaining bits as the actual PHY id.
2061 *
2062 * This allows us to avoid leaking information from the mii_if_info
2063 * structure into other data structures.
2064 */
2065 #define FALCON_PHY_ID_ID_WIDTH EFX_WIDTH(MD_PRT_DEV_ADR)
2066 #define FALCON_PHY_ID_ID_MASK ((1 << FALCON_PHY_ID_ID_WIDTH) - 1)
2067 #define FALCON_PHY_ID_WIDTH (FALCON_PHY_ID_ID_WIDTH + 1)
2068 #define FALCON_PHY_ID_MASK ((1 << FALCON_PHY_ID_WIDTH) - 1)
2069 #define FALCON_PHY_ID_10G (1 << (FALCON_PHY_ID_WIDTH - 1))
2070
2071
2072 /* Packing the clause 45 port and device fields into a single value */
2073 #define MD_PRT_ADR_COMP_LBN (MD_PRT_ADR_LBN - MD_DEV_ADR_LBN)
2074 #define MD_PRT_ADR_COMP_WIDTH MD_PRT_ADR_WIDTH
2075 #define MD_DEV_ADR_COMP_LBN 0
2076 #define MD_DEV_ADR_COMP_WIDTH MD_DEV_ADR_WIDTH
2077
2078
2079 /* Wait for GMII access to complete */
2080 static int falcon_gmii_wait(struct efx_nic *efx)
2081 {
2082 efx_dword_t md_stat;
2083 int count;
2084
2085 /* wait upto 50ms - taken max from datasheet */
2086 for (count = 0; count < 5000; count++) {
2087 falcon_readl(efx, &md_stat, MD_STAT_REG_KER);
2088 if (EFX_DWORD_FIELD(md_stat, MD_BSY) == 0) {
2089 if (EFX_DWORD_FIELD(md_stat, MD_LNFL) != 0 ||
2090 EFX_DWORD_FIELD(md_stat, MD_BSERR) != 0) {
2091 EFX_ERR(efx, "error from GMII access "
2092 EFX_DWORD_FMT"\n",
2093 EFX_DWORD_VAL(md_stat));
2094 return -EIO;
2095 }
2096 return 0;
2097 }
2098 udelay(10);
2099 }
2100 EFX_ERR(efx, "timed out waiting for GMII\n");
2101 return -ETIMEDOUT;
2102 }
2103
2104 /* Writes a GMII register of a PHY connected to Falcon using MDIO. */
2105 static void falcon_mdio_write(struct net_device *net_dev, int phy_id,
2106 int addr, int value)
2107 {
2108 struct efx_nic *efx = netdev_priv(net_dev);
2109 unsigned int phy_id2 = phy_id & FALCON_PHY_ID_ID_MASK;
2110 efx_oword_t reg;
2111
2112 /* The 'generic' prt/dev packing in mdio_10g.h is conveniently
2113 * chosen so that the only current user, Falcon, can take the
2114 * packed value and use them directly.
2115 * Fail to build if this assumption is broken.
2116 */
2117 BUILD_BUG_ON(FALCON_PHY_ID_10G != MDIO45_XPRT_ID_IS10G);
2118 BUILD_BUG_ON(FALCON_PHY_ID_ID_WIDTH != MDIO45_PRT_DEV_WIDTH);
2119 BUILD_BUG_ON(MD_PRT_ADR_COMP_LBN != MDIO45_PRT_ID_COMP_LBN);
2120 BUILD_BUG_ON(MD_DEV_ADR_COMP_LBN != MDIO45_DEV_ID_COMP_LBN);
2121
2122 if (phy_id2 == PHY_ADDR_INVALID)
2123 return;
2124
2125 /* See falcon_mdio_read for an explanation. */
2126 if (!(phy_id & FALCON_PHY_ID_10G)) {
2127 int mmd = ffs(efx->phy_op->mmds) - 1;
2128 EFX_TRACE(efx, "Fixing erroneous clause22 write\n");
2129 phy_id2 = mdio_clause45_pack(phy_id2, mmd)
2130 & FALCON_PHY_ID_ID_MASK;
2131 }
2132
2133 EFX_REGDUMP(efx, "writing GMII %d register %02x with %04x\n", phy_id,
2134 addr, value);
2135
2136 spin_lock_bh(&efx->phy_lock);
2137
2138 /* Check MII not currently being accessed */
2139 if (falcon_gmii_wait(efx) != 0)
2140 goto out;
2141
2142 /* Write the address/ID register */
2143 EFX_POPULATE_OWORD_1(reg, MD_PHY_ADR, addr);
2144 falcon_write(efx, &reg, MD_PHY_ADR_REG_KER);
2145
2146 EFX_POPULATE_OWORD_1(reg, MD_PRT_DEV_ADR, phy_id2);
2147 falcon_write(efx, &reg, MD_ID_REG_KER);
2148
2149 /* Write data */
2150 EFX_POPULATE_OWORD_1(reg, MD_TXD, value);
2151 falcon_write(efx, &reg, MD_TXD_REG_KER);
2152
2153 EFX_POPULATE_OWORD_2(reg,
2154 MD_WRC, 1,
2155 MD_GC, 0);
2156 falcon_write(efx, &reg, MD_CS_REG_KER);
2157
2158 /* Wait for data to be written */
2159 if (falcon_gmii_wait(efx) != 0) {
2160 /* Abort the write operation */
2161 EFX_POPULATE_OWORD_2(reg,
2162 MD_WRC, 0,
2163 MD_GC, 1);
2164 falcon_write(efx, &reg, MD_CS_REG_KER);
2165 udelay(10);
2166 }
2167
2168 out:
2169 spin_unlock_bh(&efx->phy_lock);
2170 }
2171
2172 /* Reads a GMII register from a PHY connected to Falcon. If no value
2173 * could be read, -1 will be returned. */
2174 static int falcon_mdio_read(struct net_device *net_dev, int phy_id, int addr)
2175 {
2176 struct efx_nic *efx = netdev_priv(net_dev);
2177 unsigned int phy_addr = phy_id & FALCON_PHY_ID_ID_MASK;
2178 efx_oword_t reg;
2179 int value = -1;
2180
2181 if (phy_addr == PHY_ADDR_INVALID)
2182 return -1;
2183
2184 /* Our PHY code knows whether it needs to talk clause 22(1G) or 45(10G)
2185 * but the generic Linux code does not make any distinction or have
2186 * any state for this.
2187 * We spot the case where someone tried to talk 22 to a 45 PHY and
2188 * redirect the request to the lowest numbered MMD as a clause45
2189 * request. This is enough to allow simple queries like id and link
2190 * state to succeed. TODO: We may need to do more in future.
2191 */
2192 if (!(phy_id & FALCON_PHY_ID_10G)) {
2193 int mmd = ffs(efx->phy_op->mmds) - 1;
2194 EFX_TRACE(efx, "Fixing erroneous clause22 read\n");
2195 phy_addr = mdio_clause45_pack(phy_addr, mmd)
2196 & FALCON_PHY_ID_ID_MASK;
2197 }
2198
2199 spin_lock_bh(&efx->phy_lock);
2200
2201 /* Check MII not currently being accessed */
2202 if (falcon_gmii_wait(efx) != 0)
2203 goto out;
2204
2205 EFX_POPULATE_OWORD_1(reg, MD_PHY_ADR, addr);
2206 falcon_write(efx, &reg, MD_PHY_ADR_REG_KER);
2207
2208 EFX_POPULATE_OWORD_1(reg, MD_PRT_DEV_ADR, phy_addr);
2209 falcon_write(efx, &reg, MD_ID_REG_KER);
2210
2211 /* Request data to be read */
2212 EFX_POPULATE_OWORD_2(reg, MD_RDC, 1, MD_GC, 0);
2213 falcon_write(efx, &reg, MD_CS_REG_KER);
2214
2215 /* Wait for data to become available */
2216 value = falcon_gmii_wait(efx);
2217 if (value == 0) {
2218 falcon_read(efx, &reg, MD_RXD_REG_KER);
2219 value = EFX_OWORD_FIELD(reg, MD_RXD);
2220 EFX_REGDUMP(efx, "read from GMII %d register %02x, got %04x\n",
2221 phy_id, addr, value);
2222 } else {
2223 /* Abort the read operation */
2224 EFX_POPULATE_OWORD_2(reg,
2225 MD_RIC, 0,
2226 MD_GC, 1);
2227 falcon_write(efx, &reg, MD_CS_REG_KER);
2228
2229 EFX_LOG(efx, "read from GMII 0x%x register %02x, got "
2230 "error %d\n", phy_id, addr, value);
2231 }
2232
2233 out:
2234 spin_unlock_bh(&efx->phy_lock);
2235
2236 return value;
2237 }
2238
2239 static void falcon_init_mdio(struct mii_if_info *gmii)
2240 {
2241 gmii->mdio_read = falcon_mdio_read;
2242 gmii->mdio_write = falcon_mdio_write;
2243 gmii->phy_id_mask = FALCON_PHY_ID_MASK;
2244 gmii->reg_num_mask = ((1 << EFX_WIDTH(MD_PHY_ADR)) - 1);
2245 }
2246
2247 static int falcon_probe_phy(struct efx_nic *efx)
2248 {
2249 switch (efx->phy_type) {
2250 case PHY_TYPE_10XPRESS:
2251 efx->phy_op = &falcon_tenxpress_phy_ops;
2252 break;
2253 case PHY_TYPE_XFP:
2254 efx->phy_op = &falcon_xfp_phy_ops;
2255 break;
2256 default:
2257 EFX_ERR(efx, "Unknown PHY type %d\n",
2258 efx->phy_type);
2259 return -1;
2260 }
2261
2262 if (efx->phy_op->macs & EFX_XMAC)
2263 efx->loopback_modes |= ((1 << LOOPBACK_XGMII) |
2264 (1 << LOOPBACK_XGXS) |
2265 (1 << LOOPBACK_XAUI));
2266 if (efx->phy_op->macs & EFX_GMAC)
2267 efx->loopback_modes |= (1 << LOOPBACK_GMAC);
2268 efx->loopback_modes |= efx->phy_op->loopbacks;
2269
2270 return 0;
2271 }
2272
2273 int falcon_switch_mac(struct efx_nic *efx)
2274 {
2275 struct efx_mac_operations *old_mac_op = efx->mac_op;
2276 efx_oword_t nic_stat;
2277 unsigned strap_val;
2278
2279 /* Internal loopbacks override the phy speed setting */
2280 if (efx->loopback_mode == LOOPBACK_GMAC) {
2281 efx->link_speed = 1000;
2282 efx->link_fd = true;
2283 } else if (LOOPBACK_INTERNAL(efx)) {
2284 efx->link_speed = 10000;
2285 efx->link_fd = true;
2286 }
2287
2288 efx->mac_op = (EFX_IS10G(efx) ?
2289 &falcon_xmac_operations : &falcon_gmac_operations);
2290 if (old_mac_op == efx->mac_op)
2291 return 0;
2292
2293 WARN_ON(!mutex_is_locked(&efx->mac_lock));
2294
2295 /* Not all macs support a mac-level link state */
2296 efx->mac_up = true;
2297
2298 falcon_read(efx, &nic_stat, NIC_STAT_REG);
2299 strap_val = EFX_IS10G(efx) ? 5 : 3;
2300 if (falcon_rev(efx) >= FALCON_REV_B0) {
2301 EFX_SET_OWORD_FIELD(nic_stat, EE_STRAP_EN, 1);
2302 EFX_SET_OWORD_FIELD(nic_stat, EE_STRAP_OVR, strap_val);
2303 falcon_write(efx, &nic_stat, NIC_STAT_REG);
2304 } else {
2305 /* Falcon A1 does not support 1G/10G speed switching
2306 * and must not be used with a PHY that does. */
2307 BUG_ON(EFX_OWORD_FIELD(nic_stat, STRAP_PINS) != strap_val);
2308 }
2309
2310
2311 EFX_LOG(efx, "selected %cMAC\n", EFX_IS10G(efx) ? 'X' : 'G');
2312 return falcon_reset_macs(efx);
2313 }
2314
2315 /* This call is responsible for hooking in the MAC and PHY operations */
2316 int falcon_probe_port(struct efx_nic *efx)
2317 {
2318 int rc;
2319
2320 /* Hook in PHY operations table */
2321 rc = falcon_probe_phy(efx);
2322 if (rc)
2323 return rc;
2324
2325 /* Set up GMII structure for PHY */
2326 efx->mii.supports_gmii = true;
2327 falcon_init_mdio(&efx->mii);
2328
2329 /* Hardware flow ctrl. FalconA RX FIFO too small for pause generation */
2330 if (falcon_rev(efx) >= FALCON_REV_B0)
2331 efx->flow_control = EFX_FC_RX | EFX_FC_TX;
2332 else
2333 efx->flow_control = EFX_FC_RX;
2334
2335 /* Allocate buffer for stats */
2336 rc = falcon_alloc_buffer(efx, &efx->stats_buffer,
2337 FALCON_MAC_STATS_SIZE);
2338 if (rc)
2339 return rc;
2340 EFX_LOG(efx, "stats buffer at %llx (virt %p phys %lx)\n",
2341 (unsigned long long)efx->stats_buffer.dma_addr,
2342 efx->stats_buffer.addr,
2343 virt_to_phys(efx->stats_buffer.addr));
2344
2345 return 0;
2346 }
2347
2348 void falcon_remove_port(struct efx_nic *efx)
2349 {
2350 falcon_free_buffer(efx, &efx->stats_buffer);
2351 }
2352
2353 /**************************************************************************
2354 *
2355 * Multicast filtering
2356 *
2357 **************************************************************************
2358 */
2359
2360 void falcon_set_multicast_hash(struct efx_nic *efx)
2361 {
2362 union efx_multicast_hash *mc_hash = &efx->multicast_hash;
2363
2364 /* Broadcast packets go through the multicast hash filter.
2365 * ether_crc_le() of the broadcast address is 0xbe2612ff
2366 * so we always add bit 0xff to the mask.
2367 */
2368 set_bit_le(0xff, mc_hash->byte);
2369
2370 falcon_write(efx, &mc_hash->oword[0], MAC_MCAST_HASH_REG0_KER);
2371 falcon_write(efx, &mc_hash->oword[1], MAC_MCAST_HASH_REG1_KER);
2372 }
2373
2374
2375 /**************************************************************************
2376 *
2377 * Falcon test code
2378 *
2379 **************************************************************************/
2380
2381 int falcon_read_nvram(struct efx_nic *efx, struct falcon_nvconfig *nvconfig_out)
2382 {
2383 struct falcon_nvconfig *nvconfig;
2384 struct efx_spi_device *spi;
2385 void *region;
2386 int rc, magic_num, struct_ver;
2387 __le16 *word, *limit;
2388 u32 csum;
2389
2390 spi = efx->spi_flash ? efx->spi_flash : efx->spi_eeprom;
2391 if (!spi)
2392 return -EINVAL;
2393
2394 region = kmalloc(FALCON_NVCONFIG_END, GFP_KERNEL);
2395 if (!region)
2396 return -ENOMEM;
2397 nvconfig = region + NVCONFIG_OFFSET;
2398
2399 mutex_lock(&efx->spi_lock);
2400 rc = falcon_spi_read(spi, 0, FALCON_NVCONFIG_END, NULL, region);
2401 mutex_unlock(&efx->spi_lock);
2402 if (rc) {
2403 EFX_ERR(efx, "Failed to read %s\n",
2404 efx->spi_flash ? "flash" : "EEPROM");
2405 rc = -EIO;
2406 goto out;
2407 }
2408
2409 magic_num = le16_to_cpu(nvconfig->board_magic_num);
2410 struct_ver = le16_to_cpu(nvconfig->board_struct_ver);
2411
2412 rc = -EINVAL;
2413 if (magic_num != NVCONFIG_BOARD_MAGIC_NUM) {
2414 EFX_ERR(efx, "NVRAM bad magic 0x%x\n", magic_num);
2415 goto out;
2416 }
2417 if (struct_ver < 2) {
2418 EFX_ERR(efx, "NVRAM has ancient version 0x%x\n", struct_ver);
2419 goto out;
2420 } else if (struct_ver < 4) {
2421 word = &nvconfig->board_magic_num;
2422 limit = (__le16 *) (nvconfig + 1);
2423 } else {
2424 word = region;
2425 limit = region + FALCON_NVCONFIG_END;
2426 }
2427 for (csum = 0; word < limit; ++word)
2428 csum += le16_to_cpu(*word);
2429
2430 if (~csum & 0xffff) {
2431 EFX_ERR(efx, "NVRAM has incorrect checksum\n");
2432 goto out;
2433 }
2434
2435 rc = 0;
2436 if (nvconfig_out)
2437 memcpy(nvconfig_out, nvconfig, sizeof(*nvconfig));
2438
2439 out:
2440 kfree(region);
2441 return rc;
2442 }
2443
2444 /* Registers tested in the falcon register test */
2445 static struct {
2446 unsigned address;
2447 efx_oword_t mask;
2448 } efx_test_registers[] = {
2449 { ADR_REGION_REG_KER,
2450 EFX_OWORD32(0x0001FFFF, 0x0001FFFF, 0x0001FFFF, 0x0001FFFF) },
2451 { RX_CFG_REG_KER,
2452 EFX_OWORD32(0xFFFFFFFE, 0x00017FFF, 0x00000000, 0x00000000) },
2453 { TX_CFG_REG_KER,
2454 EFX_OWORD32(0x7FFF0037, 0x00000000, 0x00000000, 0x00000000) },
2455 { TX_CFG2_REG_KER,
2456 EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
2457 { MAC0_CTRL_REG_KER,
2458 EFX_OWORD32(0xFFFF0000, 0x00000000, 0x00000000, 0x00000000) },
2459 { SRM_TX_DC_CFG_REG_KER,
2460 EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
2461 { RX_DC_CFG_REG_KER,
2462 EFX_OWORD32(0x0000000F, 0x00000000, 0x00000000, 0x00000000) },
2463 { RX_DC_PF_WM_REG_KER,
2464 EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
2465 { DP_CTRL_REG,
2466 EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
2467 { GM_CFG2_REG,
2468 EFX_OWORD32(0x00007337, 0x00000000, 0x00000000, 0x00000000) },
2469 { GMF_CFG0_REG,
2470 EFX_OWORD32(0x00001F1F, 0x00000000, 0x00000000, 0x00000000) },
2471 { XM_GLB_CFG_REG,
2472 EFX_OWORD32(0x00000C68, 0x00000000, 0x00000000, 0x00000000) },
2473 { XM_TX_CFG_REG,
2474 EFX_OWORD32(0x00080164, 0x00000000, 0x00000000, 0x00000000) },
2475 { XM_RX_CFG_REG,
2476 EFX_OWORD32(0x07100A0C, 0x00000000, 0x00000000, 0x00000000) },
2477 { XM_RX_PARAM_REG,
2478 EFX_OWORD32(0x00001FF8, 0x00000000, 0x00000000, 0x00000000) },
2479 { XM_FC_REG,
2480 EFX_OWORD32(0xFFFF0001, 0x00000000, 0x00000000, 0x00000000) },
2481 { XM_ADR_LO_REG,
2482 EFX_OWORD32(0xFFFFFFFF, 0x00000000, 0x00000000, 0x00000000) },
2483 { XX_SD_CTL_REG,
2484 EFX_OWORD32(0x0003FF0F, 0x00000000, 0x00000000, 0x00000000) },
2485 };
2486
2487 static bool efx_masked_compare_oword(const efx_oword_t *a, const efx_oword_t *b,
2488 const efx_oword_t *mask)
2489 {
2490 return ((a->u64[0] ^ b->u64[0]) & mask->u64[0]) ||
2491 ((a->u64[1] ^ b->u64[1]) & mask->u64[1]);
2492 }
2493
2494 int falcon_test_registers(struct efx_nic *efx)
2495 {
2496 unsigned address = 0, i, j;
2497 efx_oword_t mask, imask, original, reg, buf;
2498
2499 /* Falcon should be in loopback to isolate the XMAC from the PHY */
2500 WARN_ON(!LOOPBACK_INTERNAL(efx));
2501
2502 for (i = 0; i < ARRAY_SIZE(efx_test_registers); ++i) {
2503 address = efx_test_registers[i].address;
2504 mask = imask = efx_test_registers[i].mask;
2505 EFX_INVERT_OWORD(imask);
2506
2507 falcon_read(efx, &original, address);
2508
2509 /* bit sweep on and off */
2510 for (j = 0; j < 128; j++) {
2511 if (!EFX_EXTRACT_OWORD32(mask, j, j))
2512 continue;
2513
2514 /* Test this testable bit can be set in isolation */
2515 EFX_AND_OWORD(reg, original, mask);
2516 EFX_SET_OWORD32(reg, j, j, 1);
2517
2518 falcon_write(efx, &reg, address);
2519 falcon_read(efx, &buf, address);
2520
2521 if (efx_masked_compare_oword(&reg, &buf, &mask))
2522 goto fail;
2523
2524 /* Test this testable bit can be cleared in isolation */
2525 EFX_OR_OWORD(reg, original, mask);
2526 EFX_SET_OWORD32(reg, j, j, 0);
2527
2528 falcon_write(efx, &reg, address);
2529 falcon_read(efx, &buf, address);
2530
2531 if (efx_masked_compare_oword(&reg, &buf, &mask))
2532 goto fail;
2533 }
2534
2535 falcon_write(efx, &original, address);
2536 }
2537
2538 return 0;
2539
2540 fail:
2541 EFX_ERR(efx, "wrote "EFX_OWORD_FMT" read "EFX_OWORD_FMT
2542 " at address 0x%x mask "EFX_OWORD_FMT"\n", EFX_OWORD_VAL(reg),
2543 EFX_OWORD_VAL(buf), address, EFX_OWORD_VAL(mask));
2544 return -EIO;
2545 }
2546
2547 /**************************************************************************
2548 *
2549 * Device reset
2550 *
2551 **************************************************************************
2552 */
2553
2554 /* Resets NIC to known state. This routine must be called in process
2555 * context and is allowed to sleep. */
2556 int falcon_reset_hw(struct efx_nic *efx, enum reset_type method)
2557 {
2558 struct falcon_nic_data *nic_data = efx->nic_data;
2559 efx_oword_t glb_ctl_reg_ker;
2560 int rc;
2561
2562 EFX_LOG(efx, "performing hardware reset (%d)\n", method);
2563
2564 /* Initiate device reset */
2565 if (method == RESET_TYPE_WORLD) {
2566 rc = pci_save_state(efx->pci_dev);
2567 if (rc) {
2568 EFX_ERR(efx, "failed to backup PCI state of primary "
2569 "function prior to hardware reset\n");
2570 goto fail1;
2571 }
2572 if (FALCON_IS_DUAL_FUNC(efx)) {
2573 rc = pci_save_state(nic_data->pci_dev2);
2574 if (rc) {
2575 EFX_ERR(efx, "failed to backup PCI state of "
2576 "secondary function prior to "
2577 "hardware reset\n");
2578 goto fail2;
2579 }
2580 }
2581
2582 EFX_POPULATE_OWORD_2(glb_ctl_reg_ker,
2583 EXT_PHY_RST_DUR, 0x7,
2584 SWRST, 1);
2585 } else {
2586 int reset_phy = (method == RESET_TYPE_INVISIBLE ?
2587 EXCLUDE_FROM_RESET : 0);
2588
2589 EFX_POPULATE_OWORD_7(glb_ctl_reg_ker,
2590 EXT_PHY_RST_CTL, reset_phy,
2591 PCIE_CORE_RST_CTL, EXCLUDE_FROM_RESET,
2592 PCIE_NSTCK_RST_CTL, EXCLUDE_FROM_RESET,
2593 PCIE_SD_RST_CTL, EXCLUDE_FROM_RESET,
2594 EE_RST_CTL, EXCLUDE_FROM_RESET,
2595 EXT_PHY_RST_DUR, 0x7 /* 10ms */,
2596 SWRST, 1);
2597 }
2598 falcon_write(efx, &glb_ctl_reg_ker, GLB_CTL_REG_KER);
2599
2600 EFX_LOG(efx, "waiting for hardware reset\n");
2601 schedule_timeout_uninterruptible(HZ / 20);
2602
2603 /* Restore PCI configuration if needed */
2604 if (method == RESET_TYPE_WORLD) {
2605 if (FALCON_IS_DUAL_FUNC(efx)) {
2606 rc = pci_restore_state(nic_data->pci_dev2);
2607 if (rc) {
2608 EFX_ERR(efx, "failed to restore PCI config for "
2609 "the secondary function\n");
2610 goto fail3;
2611 }
2612 }
2613 rc = pci_restore_state(efx->pci_dev);
2614 if (rc) {
2615 EFX_ERR(efx, "failed to restore PCI config for the "
2616 "primary function\n");
2617 goto fail4;
2618 }
2619 EFX_LOG(efx, "successfully restored PCI config\n");
2620 }
2621
2622 /* Assert that reset complete */
2623 falcon_read(efx, &glb_ctl_reg_ker, GLB_CTL_REG_KER);
2624 if (EFX_OWORD_FIELD(glb_ctl_reg_ker, SWRST) != 0) {
2625 rc = -ETIMEDOUT;
2626 EFX_ERR(efx, "timed out waiting for hardware reset\n");
2627 goto fail5;
2628 }
2629 EFX_LOG(efx, "hardware reset complete\n");
2630
2631 return 0;
2632
2633 /* pci_save_state() and pci_restore_state() MUST be called in pairs */
2634 fail2:
2635 fail3:
2636 pci_restore_state(efx->pci_dev);
2637 fail1:
2638 fail4:
2639 fail5:
2640 return rc;
2641 }
2642
2643 /* Zeroes out the SRAM contents. This routine must be called in
2644 * process context and is allowed to sleep.
2645 */
2646 static int falcon_reset_sram(struct efx_nic *efx)
2647 {
2648 efx_oword_t srm_cfg_reg_ker, gpio_cfg_reg_ker;
2649 int count;
2650
2651 /* Set the SRAM wake/sleep GPIO appropriately. */
2652 falcon_read(efx, &gpio_cfg_reg_ker, GPIO_CTL_REG_KER);
2653 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, GPIO1_OEN, 1);
2654 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, GPIO1_OUT, 1);
2655 falcon_write(efx, &gpio_cfg_reg_ker, GPIO_CTL_REG_KER);
2656
2657 /* Initiate SRAM reset */
2658 EFX_POPULATE_OWORD_2(srm_cfg_reg_ker,
2659 SRAM_OOB_BT_INIT_EN, 1,
2660 SRM_NUM_BANKS_AND_BANK_SIZE, 0);
2661 falcon_write(efx, &srm_cfg_reg_ker, SRM_CFG_REG_KER);
2662
2663 /* Wait for SRAM reset to complete */
2664 count = 0;
2665 do {
2666 EFX_LOG(efx, "waiting for SRAM reset (attempt %d)...\n", count);
2667
2668 /* SRAM reset is slow; expect around 16ms */
2669 schedule_timeout_uninterruptible(HZ / 50);
2670
2671 /* Check for reset complete */
2672 falcon_read(efx, &srm_cfg_reg_ker, SRM_CFG_REG_KER);
2673 if (!EFX_OWORD_FIELD(srm_cfg_reg_ker, SRAM_OOB_BT_INIT_EN)) {
2674 EFX_LOG(efx, "SRAM reset complete\n");
2675
2676 return 0;
2677 }
2678 } while (++count < 20); /* wait upto 0.4 sec */
2679
2680 EFX_ERR(efx, "timed out waiting for SRAM reset\n");
2681 return -ETIMEDOUT;
2682 }
2683
2684 static int falcon_spi_device_init(struct efx_nic *efx,
2685 struct efx_spi_device **spi_device_ret,
2686 unsigned int device_id, u32 device_type)
2687 {
2688 struct efx_spi_device *spi_device;
2689
2690 if (device_type != 0) {
2691 spi_device = kmalloc(sizeof(*spi_device), GFP_KERNEL);
2692 if (!spi_device)
2693 return -ENOMEM;
2694 spi_device->device_id = device_id;
2695 spi_device->size =
2696 1 << SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_SIZE);
2697 spi_device->addr_len =
2698 SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ADDR_LEN);
2699 spi_device->munge_address = (spi_device->size == 1 << 9 &&
2700 spi_device->addr_len == 1);
2701 spi_device->erase_command =
2702 SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ERASE_CMD);
2703 spi_device->erase_size =
2704 1 << SPI_DEV_TYPE_FIELD(device_type,
2705 SPI_DEV_TYPE_ERASE_SIZE);
2706 spi_device->block_size =
2707 1 << SPI_DEV_TYPE_FIELD(device_type,
2708 SPI_DEV_TYPE_BLOCK_SIZE);
2709
2710 spi_device->efx = efx;
2711 } else {
2712 spi_device = NULL;
2713 }
2714
2715 kfree(*spi_device_ret);
2716 *spi_device_ret = spi_device;
2717 return 0;
2718 }
2719
2720
2721 static void falcon_remove_spi_devices(struct efx_nic *efx)
2722 {
2723 kfree(efx->spi_eeprom);
2724 efx->spi_eeprom = NULL;
2725 kfree(efx->spi_flash);
2726 efx->spi_flash = NULL;
2727 }
2728
2729 /* Extract non-volatile configuration */
2730 static int falcon_probe_nvconfig(struct efx_nic *efx)
2731 {
2732 struct falcon_nvconfig *nvconfig;
2733 int board_rev;
2734 int rc;
2735
2736 nvconfig = kmalloc(sizeof(*nvconfig), GFP_KERNEL);
2737 if (!nvconfig)
2738 return -ENOMEM;
2739
2740 rc = falcon_read_nvram(efx, nvconfig);
2741 if (rc == -EINVAL) {
2742 EFX_ERR(efx, "NVRAM is invalid therefore using defaults\n");
2743 efx->phy_type = PHY_TYPE_NONE;
2744 efx->mii.phy_id = PHY_ADDR_INVALID;
2745 board_rev = 0;
2746 rc = 0;
2747 } else if (rc) {
2748 goto fail1;
2749 } else {
2750 struct falcon_nvconfig_board_v2 *v2 = &nvconfig->board_v2;
2751 struct falcon_nvconfig_board_v3 *v3 = &nvconfig->board_v3;
2752
2753 efx->phy_type = v2->port0_phy_type;
2754 efx->mii.phy_id = v2->port0_phy_addr;
2755 board_rev = le16_to_cpu(v2->board_revision);
2756
2757 if (le16_to_cpu(nvconfig->board_struct_ver) >= 3) {
2758 __le32 fl = v3->spi_device_type[EE_SPI_FLASH];
2759 __le32 ee = v3->spi_device_type[EE_SPI_EEPROM];
2760 rc = falcon_spi_device_init(efx, &efx->spi_flash,
2761 EE_SPI_FLASH,
2762 le32_to_cpu(fl));
2763 if (rc)
2764 goto fail2;
2765 rc = falcon_spi_device_init(efx, &efx->spi_eeprom,
2766 EE_SPI_EEPROM,
2767 le32_to_cpu(ee));
2768 if (rc)
2769 goto fail2;
2770 }
2771 }
2772
2773 /* Read the MAC addresses */
2774 memcpy(efx->mac_address, nvconfig->mac_address[0], ETH_ALEN);
2775
2776 EFX_LOG(efx, "PHY is %d phy_id %d\n", efx->phy_type, efx->mii.phy_id);
2777
2778 efx_set_board_info(efx, board_rev);
2779
2780 kfree(nvconfig);
2781 return 0;
2782
2783 fail2:
2784 falcon_remove_spi_devices(efx);
2785 fail1:
2786 kfree(nvconfig);
2787 return rc;
2788 }
2789
2790 /* Probe the NIC variant (revision, ASIC vs FPGA, function count, port
2791 * count, port speed). Set workaround and feature flags accordingly.
2792 */
2793 static int falcon_probe_nic_variant(struct efx_nic *efx)
2794 {
2795 efx_oword_t altera_build;
2796 efx_oword_t nic_stat;
2797
2798 falcon_read(efx, &altera_build, ALTERA_BUILD_REG_KER);
2799 if (EFX_OWORD_FIELD(altera_build, VER_ALL)) {
2800 EFX_ERR(efx, "Falcon FPGA not supported\n");
2801 return -ENODEV;
2802 }
2803
2804 falcon_read(efx, &nic_stat, NIC_STAT_REG);
2805
2806 switch (falcon_rev(efx)) {
2807 case FALCON_REV_A0:
2808 case 0xff:
2809 EFX_ERR(efx, "Falcon rev A0 not supported\n");
2810 return -ENODEV;
2811
2812 case FALCON_REV_A1:
2813 if (EFX_OWORD_FIELD(nic_stat, STRAP_PCIE) == 0) {
2814 EFX_ERR(efx, "Falcon rev A1 PCI-X not supported\n");
2815 return -ENODEV;
2816 }
2817 break;
2818
2819 case FALCON_REV_B0:
2820 break;
2821
2822 default:
2823 EFX_ERR(efx, "Unknown Falcon rev %d\n", falcon_rev(efx));
2824 return -ENODEV;
2825 }
2826
2827 /* Initial assumed speed */
2828 efx->link_speed = EFX_OWORD_FIELD(nic_stat, STRAP_10G) ? 10000 : 1000;
2829
2830 return 0;
2831 }
2832
2833 /* Probe all SPI devices on the NIC */
2834 static void falcon_probe_spi_devices(struct efx_nic *efx)
2835 {
2836 efx_oword_t nic_stat, gpio_ctl, ee_vpd_cfg;
2837 int boot_dev;
2838
2839 falcon_read(efx, &gpio_ctl, GPIO_CTL_REG_KER);
2840 falcon_read(efx, &nic_stat, NIC_STAT_REG);
2841 falcon_read(efx, &ee_vpd_cfg, EE_VPD_CFG_REG_KER);
2842
2843 if (EFX_OWORD_FIELD(gpio_ctl, BOOTED_USING_NVDEVICE)) {
2844 boot_dev = (EFX_OWORD_FIELD(nic_stat, SF_PRST) ?
2845 EE_SPI_FLASH : EE_SPI_EEPROM);
2846 EFX_LOG(efx, "Booted from %s\n",
2847 boot_dev == EE_SPI_FLASH ? "flash" : "EEPROM");
2848 } else {
2849 /* Disable VPD and set clock dividers to safe
2850 * values for initial programming. */
2851 boot_dev = -1;
2852 EFX_LOG(efx, "Booted from internal ASIC settings;"
2853 " setting SPI config\n");
2854 EFX_POPULATE_OWORD_3(ee_vpd_cfg, EE_VPD_EN, 0,
2855 /* 125 MHz / 7 ~= 20 MHz */
2856 EE_SF_CLOCK_DIV, 7,
2857 /* 125 MHz / 63 ~= 2 MHz */
2858 EE_EE_CLOCK_DIV, 63);
2859 falcon_write(efx, &ee_vpd_cfg, EE_VPD_CFG_REG_KER);
2860 }
2861
2862 if (boot_dev == EE_SPI_FLASH)
2863 falcon_spi_device_init(efx, &efx->spi_flash, EE_SPI_FLASH,
2864 default_flash_type);
2865 if (boot_dev == EE_SPI_EEPROM)
2866 falcon_spi_device_init(efx, &efx->spi_eeprom, EE_SPI_EEPROM,
2867 large_eeprom_type);
2868 }
2869
2870 int falcon_probe_nic(struct efx_nic *efx)
2871 {
2872 struct falcon_nic_data *nic_data;
2873 int rc;
2874
2875 /* Allocate storage for hardware specific data */
2876 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
2877 if (!nic_data)
2878 return -ENOMEM;
2879 efx->nic_data = nic_data;
2880
2881 /* Determine number of ports etc. */
2882 rc = falcon_probe_nic_variant(efx);
2883 if (rc)
2884 goto fail1;
2885
2886 /* Probe secondary function if expected */
2887 if (FALCON_IS_DUAL_FUNC(efx)) {
2888 struct pci_dev *dev = pci_dev_get(efx->pci_dev);
2889
2890 while ((dev = pci_get_device(EFX_VENDID_SFC, FALCON_A_S_DEVID,
2891 dev))) {
2892 if (dev->bus == efx->pci_dev->bus &&
2893 dev->devfn == efx->pci_dev->devfn + 1) {
2894 nic_data->pci_dev2 = dev;
2895 break;
2896 }
2897 }
2898 if (!nic_data->pci_dev2) {
2899 EFX_ERR(efx, "failed to find secondary function\n");
2900 rc = -ENODEV;
2901 goto fail2;
2902 }
2903 }
2904
2905 /* Now we can reset the NIC */
2906 rc = falcon_reset_hw(efx, RESET_TYPE_ALL);
2907 if (rc) {
2908 EFX_ERR(efx, "failed to reset NIC\n");
2909 goto fail3;
2910 }
2911
2912 /* Allocate memory for INT_KER */
2913 rc = falcon_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t));
2914 if (rc)
2915 goto fail4;
2916 BUG_ON(efx->irq_status.dma_addr & 0x0f);
2917
2918 EFX_LOG(efx, "INT_KER at %llx (virt %p phys %lx)\n",
2919 (unsigned long long)efx->irq_status.dma_addr,
2920 efx->irq_status.addr, virt_to_phys(efx->irq_status.addr));
2921
2922 falcon_probe_spi_devices(efx);
2923
2924 /* Read in the non-volatile configuration */
2925 rc = falcon_probe_nvconfig(efx);
2926 if (rc)
2927 goto fail5;
2928
2929 /* Initialise I2C adapter */
2930 efx->i2c_adap.owner = THIS_MODULE;
2931 nic_data->i2c_data = falcon_i2c_bit_operations;
2932 nic_data->i2c_data.data = efx;
2933 efx->i2c_adap.algo_data = &nic_data->i2c_data;
2934 efx->i2c_adap.dev.parent = &efx->pci_dev->dev;
2935 strlcpy(efx->i2c_adap.name, "SFC4000 GPIO", sizeof(efx->i2c_adap.name));
2936 rc = i2c_bit_add_bus(&efx->i2c_adap);
2937 if (rc)
2938 goto fail5;
2939
2940 return 0;
2941
2942 fail5:
2943 falcon_remove_spi_devices(efx);
2944 falcon_free_buffer(efx, &efx->irq_status);
2945 fail4:
2946 fail3:
2947 if (nic_data->pci_dev2) {
2948 pci_dev_put(nic_data->pci_dev2);
2949 nic_data->pci_dev2 = NULL;
2950 }
2951 fail2:
2952 fail1:
2953 kfree(efx->nic_data);
2954 return rc;
2955 }
2956
2957 /* This call performs hardware-specific global initialisation, such as
2958 * defining the descriptor cache sizes and number of RSS channels.
2959 * It does not set up any buffers, descriptor rings or event queues.
2960 */
2961 int falcon_init_nic(struct efx_nic *efx)
2962 {
2963 efx_oword_t temp;
2964 unsigned thresh;
2965 int rc;
2966
2967 /* Use on-chip SRAM */
2968 falcon_read(efx, &temp, NIC_STAT_REG);
2969 EFX_SET_OWORD_FIELD(temp, ONCHIP_SRAM, 1);
2970 falcon_write(efx, &temp, NIC_STAT_REG);
2971
2972 /* Set buffer table mode */
2973 EFX_POPULATE_OWORD_1(temp, BUF_TBL_MODE, BUF_TBL_MODE_FULL);
2974 falcon_write(efx, &temp, BUF_TBL_CFG_REG_KER);
2975
2976 rc = falcon_reset_sram(efx);
2977 if (rc)
2978 return rc;
2979
2980 /* Set positions of descriptor caches in SRAM. */
2981 EFX_POPULATE_OWORD_1(temp, SRM_TX_DC_BASE_ADR, TX_DC_BASE / 8);
2982 falcon_write(efx, &temp, SRM_TX_DC_CFG_REG_KER);
2983 EFX_POPULATE_OWORD_1(temp, SRM_RX_DC_BASE_ADR, RX_DC_BASE / 8);
2984 falcon_write(efx, &temp, SRM_RX_DC_CFG_REG_KER);
2985
2986 /* Set TX descriptor cache size. */
2987 BUILD_BUG_ON(TX_DC_ENTRIES != (16 << TX_DC_ENTRIES_ORDER));
2988 EFX_POPULATE_OWORD_1(temp, TX_DC_SIZE, TX_DC_ENTRIES_ORDER);
2989 falcon_write(efx, &temp, TX_DC_CFG_REG_KER);
2990
2991 /* Set RX descriptor cache size. Set low watermark to size-8, as
2992 * this allows most efficient prefetching.
2993 */
2994 BUILD_BUG_ON(RX_DC_ENTRIES != (16 << RX_DC_ENTRIES_ORDER));
2995 EFX_POPULATE_OWORD_1(temp, RX_DC_SIZE, RX_DC_ENTRIES_ORDER);
2996 falcon_write(efx, &temp, RX_DC_CFG_REG_KER);
2997 EFX_POPULATE_OWORD_1(temp, RX_DC_PF_LWM, RX_DC_ENTRIES - 8);
2998 falcon_write(efx, &temp, RX_DC_PF_WM_REG_KER);
2999
3000 /* Clear the parity enables on the TX data fifos as
3001 * they produce false parity errors because of timing issues
3002 */
3003 if (EFX_WORKAROUND_5129(efx)) {
3004 falcon_read(efx, &temp, SPARE_REG_KER);
3005 EFX_SET_OWORD_FIELD(temp, MEM_PERR_EN_TX_DATA, 0);
3006 falcon_write(efx, &temp, SPARE_REG_KER);
3007 }
3008
3009 /* Enable all the genuinely fatal interrupts. (They are still
3010 * masked by the overall interrupt mask, controlled by
3011 * falcon_interrupts()).
3012 *
3013 * Note: All other fatal interrupts are enabled
3014 */
3015 EFX_POPULATE_OWORD_3(temp,
3016 ILL_ADR_INT_KER_EN, 1,
3017 RBUF_OWN_INT_KER_EN, 1,
3018 TBUF_OWN_INT_KER_EN, 1);
3019 EFX_INVERT_OWORD(temp);
3020 falcon_write(efx, &temp, FATAL_INTR_REG_KER);
3021
3022 if (EFX_WORKAROUND_7244(efx)) {
3023 falcon_read(efx, &temp, RX_FILTER_CTL_REG);
3024 EFX_SET_OWORD_FIELD(temp, UDP_FULL_SRCH_LIMIT, 8);
3025 EFX_SET_OWORD_FIELD(temp, UDP_WILD_SRCH_LIMIT, 8);
3026 EFX_SET_OWORD_FIELD(temp, TCP_FULL_SRCH_LIMIT, 8);
3027 EFX_SET_OWORD_FIELD(temp, TCP_WILD_SRCH_LIMIT, 8);
3028 falcon_write(efx, &temp, RX_FILTER_CTL_REG);
3029 }
3030
3031 falcon_setup_rss_indir_table(efx);
3032
3033 /* Setup RX. Wait for descriptor is broken and must
3034 * be disabled. RXDP recovery shouldn't be needed, but is.
3035 */
3036 falcon_read(efx, &temp, RX_SELF_RST_REG_KER);
3037 EFX_SET_OWORD_FIELD(temp, RX_NODESC_WAIT_DIS, 1);
3038 EFX_SET_OWORD_FIELD(temp, RX_RECOVERY_EN, 1);
3039 if (EFX_WORKAROUND_5583(efx))
3040 EFX_SET_OWORD_FIELD(temp, RX_ISCSI_DIS, 1);
3041 falcon_write(efx, &temp, RX_SELF_RST_REG_KER);
3042
3043 /* Disable the ugly timer-based TX DMA backoff and allow TX DMA to be
3044 * controlled by the RX FIFO fill level. Set arbitration to one pkt/Q.
3045 */
3046 falcon_read(efx, &temp, TX_CFG2_REG_KER);
3047 EFX_SET_OWORD_FIELD(temp, TX_RX_SPACER, 0xfe);
3048 EFX_SET_OWORD_FIELD(temp, TX_RX_SPACER_EN, 1);
3049 EFX_SET_OWORD_FIELD(temp, TX_ONE_PKT_PER_Q, 1);
3050 EFX_SET_OWORD_FIELD(temp, TX_CSR_PUSH_EN, 0);
3051 EFX_SET_OWORD_FIELD(temp, TX_DIS_NON_IP_EV, 1);
3052 /* Enable SW_EV to inherit in char driver - assume harmless here */
3053 EFX_SET_OWORD_FIELD(temp, TX_SW_EV_EN, 1);
3054 /* Prefetch threshold 2 => fetch when descriptor cache half empty */
3055 EFX_SET_OWORD_FIELD(temp, TX_PREF_THRESHOLD, 2);
3056 /* Squash TX of packets of 16 bytes or less */
3057 if (falcon_rev(efx) >= FALCON_REV_B0 && EFX_WORKAROUND_9141(efx))
3058 EFX_SET_OWORD_FIELD(temp, TX_FLUSH_MIN_LEN_EN_B0, 1);
3059 falcon_write(efx, &temp, TX_CFG2_REG_KER);
3060
3061 /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
3062 * descriptors (which is bad).
3063 */
3064 falcon_read(efx, &temp, TX_CFG_REG_KER);
3065 EFX_SET_OWORD_FIELD(temp, TX_NO_EOP_DISC_EN, 0);
3066 falcon_write(efx, &temp, TX_CFG_REG_KER);
3067
3068 /* RX config */
3069 falcon_read(efx, &temp, RX_CFG_REG_KER);
3070 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_DESC_PUSH_EN, 0);
3071 if (EFX_WORKAROUND_7575(efx))
3072 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_USR_BUF_SIZE,
3073 (3 * 4096) / 32);
3074 if (falcon_rev(efx) >= FALCON_REV_B0)
3075 EFX_SET_OWORD_FIELD(temp, RX_INGR_EN_B0, 1);
3076
3077 /* RX FIFO flow control thresholds */
3078 thresh = ((rx_xon_thresh_bytes >= 0) ?
3079 rx_xon_thresh_bytes : efx->type->rx_xon_thresh);
3080 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XON_MAC_TH, thresh / 256);
3081 thresh = ((rx_xoff_thresh_bytes >= 0) ?
3082 rx_xoff_thresh_bytes : efx->type->rx_xoff_thresh);
3083 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XOFF_MAC_TH, thresh / 256);
3084 /* RX control FIFO thresholds [32 entries] */
3085 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XON_TX_TH, 20);
3086 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XOFF_TX_TH, 25);
3087 falcon_write(efx, &temp, RX_CFG_REG_KER);
3088
3089 /* Set destination of both TX and RX Flush events */
3090 if (falcon_rev(efx) >= FALCON_REV_B0) {
3091 EFX_POPULATE_OWORD_1(temp, FLS_EVQ_ID, 0);
3092 falcon_write(efx, &temp, DP_CTRL_REG);
3093 }
3094
3095 return 0;
3096 }
3097
3098 void falcon_remove_nic(struct efx_nic *efx)
3099 {
3100 struct falcon_nic_data *nic_data = efx->nic_data;
3101 int rc;
3102
3103 rc = i2c_del_adapter(&efx->i2c_adap);
3104 BUG_ON(rc);
3105
3106 falcon_remove_spi_devices(efx);
3107 falcon_free_buffer(efx, &efx->irq_status);
3108
3109 falcon_reset_hw(efx, RESET_TYPE_ALL);
3110
3111 /* Release the second function after the reset */
3112 if (nic_data->pci_dev2) {
3113 pci_dev_put(nic_data->pci_dev2);
3114 nic_data->pci_dev2 = NULL;
3115 }
3116
3117 /* Tear down the private nic state */
3118 kfree(efx->nic_data);
3119 efx->nic_data = NULL;
3120 }
3121
3122 void falcon_update_nic_stats(struct efx_nic *efx)
3123 {
3124 efx_oword_t cnt;
3125
3126 falcon_read(efx, &cnt, RX_NODESC_DROP_REG_KER);
3127 efx->n_rx_nodesc_drop_cnt += EFX_OWORD_FIELD(cnt, RX_NODESC_DROP_CNT);
3128 }
3129
3130 /**************************************************************************
3131 *
3132 * Revision-dependent attributes used by efx.c
3133 *
3134 **************************************************************************
3135 */
3136
3137 struct efx_nic_type falcon_a_nic_type = {
3138 .mem_bar = 2,
3139 .mem_map_size = 0x20000,
3140 .txd_ptr_tbl_base = TX_DESC_PTR_TBL_KER_A1,
3141 .rxd_ptr_tbl_base = RX_DESC_PTR_TBL_KER_A1,
3142 .buf_tbl_base = BUF_TBL_KER_A1,
3143 .evq_ptr_tbl_base = EVQ_PTR_TBL_KER_A1,
3144 .evq_rptr_tbl_base = EVQ_RPTR_REG_KER_A1,
3145 .txd_ring_mask = FALCON_TXD_RING_MASK,
3146 .rxd_ring_mask = FALCON_RXD_RING_MASK,
3147 .evq_size = FALCON_EVQ_SIZE,
3148 .max_dma_mask = FALCON_DMA_MASK,
3149 .tx_dma_mask = FALCON_TX_DMA_MASK,
3150 .bug5391_mask = 0xf,
3151 .rx_xoff_thresh = 2048,
3152 .rx_xon_thresh = 512,
3153 .rx_buffer_padding = 0x24,
3154 .max_interrupt_mode = EFX_INT_MODE_MSI,
3155 .phys_addr_channels = 4,
3156 };
3157
3158 struct efx_nic_type falcon_b_nic_type = {
3159 .mem_bar = 2,
3160 /* Map everything up to and including the RSS indirection
3161 * table. Don't map MSI-X table, MSI-X PBA since Linux
3162 * requires that they not be mapped. */
3163 .mem_map_size = RX_RSS_INDIR_TBL_B0 + 0x800,
3164 .txd_ptr_tbl_base = TX_DESC_PTR_TBL_KER_B0,
3165 .rxd_ptr_tbl_base = RX_DESC_PTR_TBL_KER_B0,
3166 .buf_tbl_base = BUF_TBL_KER_B0,
3167 .evq_ptr_tbl_base = EVQ_PTR_TBL_KER_B0,
3168 .evq_rptr_tbl_base = EVQ_RPTR_REG_KER_B0,
3169 .txd_ring_mask = FALCON_TXD_RING_MASK,
3170 .rxd_ring_mask = FALCON_RXD_RING_MASK,
3171 .evq_size = FALCON_EVQ_SIZE,
3172 .max_dma_mask = FALCON_DMA_MASK,
3173 .tx_dma_mask = FALCON_TX_DMA_MASK,
3174 .bug5391_mask = 0,
3175 .rx_xoff_thresh = 54272, /* ~80Kb - 3*max MTU */
3176 .rx_xon_thresh = 27648, /* ~3*max MTU */
3177 .rx_buffer_padding = 0,
3178 .max_interrupt_mode = EFX_INT_MODE_MSIX,
3179 .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy
3180 * interrupt handler only supports 32
3181 * channels */
3182 };
3183
Verdex Pro support