arch/i386/pci/mmconfig.c

   1 /*
   2  * Copyright (C) 2004 Matthew Wilcox <matthew@wil.cx>
   3  * Copyright (C) 2004 Intel Corp.
   4  *
   5  * This code is released under the GNU General Public License version 2.
   6  */
   7
   8 /*
   9  * mmconfig.c - Low-level direct PCI config space access via MMCONFIG
  10  */
  11
  12 #include <linux/pci.h>
  13 #include <linux/init.h>
  14 #include <linux/acpi.h>
  15 #include <asm/e820.h>
  16 #include "pci.h"
  17
  18 /* aperture is up to 256MB but BIOS may reserve less */
  19 #define MMCONFIG_APER_MIN       (2 * 1024*1024)
  20 #define MMCONFIG_APER_MAX       (256 * 1024*1024)
  21
  22 /* Assume systems with more busses have correct MCFG */
  23 #define MAX_CHECK_BUS 16
  24
  25 #define mmcfg_virt_addr ((void __iomem *) fix_to_virt(FIX_PCIE_MCFG))
  26
  27 /* The base address of the last MMCONFIG device accessed */
  28 static u32 mmcfg_last_accessed_device;
  29 static int mmcfg_last_accessed_cpu;
  30
  31 static DECLARE_BITMAP(fallback_slots, MAX_CHECK_BUS*32);
  32
  33 /*
  34  * Functions for accessing PCI configuration space with MMCONFIG accesses
  35  */
  36 static u32 get_base_addr(unsigned int seg, int bus, unsigned devfn)
  37 {
  38         int cfg_num = -1;
  39         struct acpi_mcfg_allocation *cfg;
  40
  41         if (seg == 0 && bus < MAX_CHECK_BUS &&
  42             test_bit(PCI_SLOT(devfn) + 32*bus, fallback_slots))
  43                 return 0;
  44
  45         while (1) {
  46                 ++cfg_num;
  47                 if (cfg_num >= pci_mmcfg_config_num) {
  48                         break;
  49                 }
  50                 cfg = &pci_mmcfg_config[cfg_num];
  51                 if (cfg->pci_segment != seg)
  52                         continue;
  53                 if ((cfg->start_bus_number <= bus) &&
  54                     (cfg->end_bus_number >= bus))
  55                         return cfg->address;
  56         }
  57
  58         /* Handle more broken MCFG tables on Asus etc.
  59            They only contain a single entry for bus 0-0. Assume
  60            this applies to all busses. */
  61         cfg = &pci_mmcfg_config[0];
  62         if (pci_mmcfg_config_num == 1 &&
  63                 cfg->pci_segment == 0 &&
  64                 (cfg->start_bus_number | cfg->end_bus_number) == 0)
  65                 return cfg->address;
  66
  67         /* Fall back to type 0 */
  68         return 0;
  69 }
  70
  71 /*
  72  * This is always called under pci_config_lock
  73  */
  74 static void pci_exp_set_dev_base(unsigned int base, int bus, int devfn)
  75 {
  76         u32 dev_base = base | (bus << 20) | (devfn << 12);
  77         int cpu = smp_processor_id();
  78         if (dev_base != mmcfg_last_accessed_device ||
  79             cpu != mmcfg_last_accessed_cpu) {
  80                 mmcfg_last_accessed_device = dev_base;
  81                 mmcfg_last_accessed_cpu = cpu;
  82                 set_fixmap_nocache(FIX_PCIE_MCFG, dev_base);
  83         }
  84 }
  85
  86 static int pci_mmcfg_read(unsigned int seg, unsigned int bus,
  87                           unsigned int devfn, int reg, int len, u32 *value)
  88 {
  89         unsigned long flags;
  90         u32 base;
  91
  92         if ((bus > 255) || (devfn > 255) || (reg > 4095)) {
  93                 *value = -1;
  94                 return -EINVAL;
  95         }
  96
  97         base = get_base_addr(seg, bus, devfn);
  98         if (!base)
  99                 return pci_conf1_read(seg,bus,devfn,reg,len,value);
 100
 101         spin_lock_irqsave(&pci_config_lock, flags);
 102
 103         pci_exp_set_dev_base(base, bus, devfn);
 104
 105         switch (len) {
 106         case 1:
 107                 *value = readb(mmcfg_virt_addr + reg);
 108                 break;
 109         case 2:
 110                 *value = readw(mmcfg_virt_addr + reg);
 111                 break;
 112         case 4:
 113                 *value = readl(mmcfg_virt_addr + reg);
 114                 break;
 115         }
 116
 117         spin_unlock_irqrestore(&pci_config_lock, flags);
 118
 119         return 0;
 120 }
 121
 122 static int pci_mmcfg_write(unsigned int seg, unsigned int bus,
 123                            unsigned int devfn, int reg, int len, u32 value)
 124 {
 125         unsigned long flags;
 126         u32 base;
 127
 128         if ((bus > 255) || (devfn > 255) || (reg > 4095))
 129                 return -EINVAL;
 130
 131         base = get_base_addr(seg, bus, devfn);
 132         if (!base)
 133                 return pci_conf1_write(seg,bus,devfn,reg,len,value);
 134
 135         spin_lock_irqsave(&pci_config_lock, flags);
 136
 137         pci_exp_set_dev_base(base, bus, devfn);
 138
 139         switch (len) {
 140         case 1:
 141                 writeb(value, mmcfg_virt_addr + reg);
 142                 break;
 143         case 2:
 144                 writew(value, mmcfg_virt_addr + reg);
 145                 break;
 146         case 4:
 147                 writel(value, mmcfg_virt_addr + reg);
 148                 break;
 149         }
 150
 151         spin_unlock_irqrestore(&pci_config_lock, flags);
 152
 153         return 0;
 154 }
 155
 156 static struct pci_raw_ops pci_mmcfg = {
 157         .read =         pci_mmcfg_read,
 158         .write =        pci_mmcfg_write,
 159 };
 160
 161 /* K8 systems have some devices (typically in the builtin northbridge)
 162    that are only accessible using type1
 163    Normally this can be expressed in the MCFG by not listing them
 164    and assigning suitable _SEGs, but this isn't implemented in some BIOS.
 165    Instead try to discover all devices on bus 0 that are unreachable using MM
 166    and fallback for them. */
 167 static __init void unreachable_devices(void)
 168 {
 169         int i, k;
 170         unsigned long flags;
 171
 172         for (k = 0; k < MAX_CHECK_BUS; k++) {
 173                 for (i = 0; i < 32; i++) {
 174                         u32 val1;
 175                         u32 addr;
 176
 177                         pci_conf1_read(0, k, PCI_DEVFN(i, 0), 0, 4, &val1);
 178                         if (val1 == 0xffffffff)
 179                                 continue;
 180
 181                         /* Locking probably not needed, but safer */
 182                         spin_lock_irqsave(&pci_config_lock, flags);
 183                         addr = get_base_addr(0, k, PCI_DEVFN(i, 0));
 184                         if (addr != 0)
 185                                 pci_exp_set_dev_base(addr, k, PCI_DEVFN(i, 0));
 186                         if (addr == 0 ||
 187                             readl((u32 __iomem *)mmcfg_virt_addr) != val1) {
 188                                 set_bit(i + 32*k, fallback_slots);
 189                                 printk(KERN_NOTICE
 190                         "PCI: No mmconfig possible on %x:%x\n", k, i);
 191                         }
 192                         spin_unlock_irqrestore(&pci_config_lock, flags);
 193                 }
 194         }
 195 }
 196
 197 void __init pci_mmcfg_init(int type)
 198 {
 199         if ((pci_probe & PCI_PROBE_MMCONF) == 0)
 200                 return;
 201
 202         acpi_table_parse(ACPI_SIG_MCFG, acpi_parse_mcfg);
 203         if ((pci_mmcfg_config_num == 0) ||
 204             (pci_mmcfg_config == NULL) ||
 205             (pci_mmcfg_config[0].address == 0))
 206                 return;
 207
 208         /* Only do this check when type 1 works. If it doesn't work
 209            assume we run on a Mac and always use MCFG */
 210         if (type == 1 && !e820_all_mapped(pci_mmcfg_config[0].address,
 211                         pci_mmcfg_config[0].address + MMCONFIG_APER_MIN,
 212                         E820_RESERVED)) {
 213                 printk(KERN_ERR "PCI: BIOS Bug: MCFG area at %lx is not E820-reserved\n",
 214                                 (unsigned long)pci_mmcfg_config[0].address);
 215                 printk(KERN_ERR "PCI: Not using MMCONFIG.\n");
 216                 return;
 217         }
 218
 219         printk(KERN_INFO "PCI: Using MMCONFIG\n");
 220         raw_pci_ops = &pci_mmcfg;
 221         pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF;
 222
 223         unreachable_devices();
 224 }