2 * SuperH Ethernet device driver
4 * Copyright (C) 2006-2008 Nobuhiro Iwamatsu
5 * Copyright (C) 2008-2009 Renesas Solutions Corp.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 * The full GNU General Public License is included in this distribution in
20 * the file called "COPYING".
23 #include <linux/init.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/etherdevice.h>
26 #include <linux/delay.h>
27 #include <linux/platform_device.h>
28 #include <linux/mdio-bitbang.h>
29 #include <linux/netdevice.h>
30 #include <linux/phy.h>
31 #include <linux/cache.h>
36 /* There is CPU dependent code */
37 #if defined(CONFIG_CPU_SUBTYPE_SH7724)
38 #define SH_ETH_RESET_DEFAULT 1
39 static void sh_eth_set_duplex(struct net_device
*ndev
)
41 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
42 u32 ioaddr
= ndev
->base_addr
;
44 if (mdp
->duplex
) /* Full */
45 ctrl_outl(ctrl_inl(ioaddr
+ ECMR
) | ECMR_DM
, ioaddr
+ ECMR
);
47 ctrl_outl(ctrl_inl(ioaddr
+ ECMR
) & ~ECMR_DM
, ioaddr
+ ECMR
);
50 static void sh_eth_set_rate(struct net_device
*ndev
)
52 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
53 u32 ioaddr
= ndev
->base_addr
;
57 ctrl_outl(ctrl_inl(ioaddr
+ ECMR
) & ~ECMR_RTM
, ioaddr
+ ECMR
);
59 case 100:/* 100BASE */
60 ctrl_outl(ctrl_inl(ioaddr
+ ECMR
) | ECMR_RTM
, ioaddr
+ ECMR
);
68 static struct sh_eth_cpu_data sh_eth_my_cpu_data
= {
69 .set_duplex
= sh_eth_set_duplex
,
70 .set_rate
= sh_eth_set_rate
,
72 .ecsr_value
= ECSR_PSRTO
| ECSR_LCHNG
| ECSR_ICD
,
73 .ecsipr_value
= ECSIPR_PSRTOIP
| ECSIPR_LCHNGIP
| ECSIPR_ICDIP
,
74 .eesipr_value
= DMAC_M_RFRMER
| DMAC_M_ECI
| 0x01ff009f,
76 .tx_check
= EESR_FTC
| EESR_CND
| EESR_DLC
| EESR_CD
| EESR_RTO
,
77 .eesr_err_check
= EESR_TWB
| EESR_TABT
| EESR_RABT
| EESR_RDE
|
78 EESR_RFRMER
| EESR_TFE
| EESR_TDE
| EESR_ECI
,
79 .tx_error_check
= EESR_TWB
| EESR_TABT
| EESR_TDE
| EESR_TFE
,
87 #elif defined(CONFIG_CPU_SUBTYPE_SH7763)
88 #define SH_ETH_HAS_TSU 1
89 static void sh_eth_chip_reset(struct net_device
*ndev
)
92 ctrl_outl(ARSTR_ARSTR
, ARSTR
);
96 static void sh_eth_reset(struct net_device
*ndev
)
98 u32 ioaddr
= ndev
->base_addr
;
101 ctrl_outl(EDSR_ENALL
, ioaddr
+ EDSR
);
102 ctrl_outl(ctrl_inl(ioaddr
+ EDMR
) | EDMR_SRST
, ioaddr
+ EDMR
);
104 if (!(ctrl_inl(ioaddr
+ EDMR
) & 0x3))
110 printk(KERN_ERR
"Device reset fail\n");
113 ctrl_outl(0x0, ioaddr
+ TDLAR
);
114 ctrl_outl(0x0, ioaddr
+ TDFAR
);
115 ctrl_outl(0x0, ioaddr
+ TDFXR
);
116 ctrl_outl(0x0, ioaddr
+ TDFFR
);
117 ctrl_outl(0x0, ioaddr
+ RDLAR
);
118 ctrl_outl(0x0, ioaddr
+ RDFAR
);
119 ctrl_outl(0x0, ioaddr
+ RDFXR
);
120 ctrl_outl(0x0, ioaddr
+ RDFFR
);
123 static void sh_eth_set_duplex(struct net_device
*ndev
)
125 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
126 u32 ioaddr
= ndev
->base_addr
;
128 if (mdp
->duplex
) /* Full */
129 ctrl_outl(ctrl_inl(ioaddr
+ ECMR
) | ECMR_DM
, ioaddr
+ ECMR
);
131 ctrl_outl(ctrl_inl(ioaddr
+ ECMR
) & ~ECMR_DM
, ioaddr
+ ECMR
);
134 static void sh_eth_set_rate(struct net_device
*ndev
)
136 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
137 u32 ioaddr
= ndev
->base_addr
;
139 switch (mdp
->speed
) {
140 case 10: /* 10BASE */
141 ctrl_outl(GECMR_10
, ioaddr
+ GECMR
);
143 case 100:/* 100BASE */
144 ctrl_outl(GECMR_100
, ioaddr
+ GECMR
);
146 case 1000: /* 1000BASE */
147 ctrl_outl(GECMR_1000
, ioaddr
+ GECMR
);
155 static struct sh_eth_cpu_data sh_eth_my_cpu_data
= {
156 .chip_reset
= sh_eth_chip_reset
,
157 .set_duplex
= sh_eth_set_duplex
,
158 .set_rate
= sh_eth_set_rate
,
160 .ecsr_value
= ECSR_ICD
| ECSR_MPD
,
161 .ecsipr_value
= ECSIPR_LCHNGIP
| ECSIPR_ICDIP
| ECSIPR_MPDIP
,
162 .eesipr_value
= DMAC_M_RFRMER
| DMAC_M_ECI
| 0x003fffff,
164 .tx_check
= EESR_TC1
| EESR_FTC
,
165 .eesr_err_check
= EESR_TWB1
| EESR_TWB
| EESR_TABT
| EESR_RABT
| \
166 EESR_RDE
| EESR_RFRMER
| EESR_TFE
| EESR_TDE
| \
168 .tx_error_check
= EESR_TWB1
| EESR_TWB
| EESR_TABT
| EESR_TDE
| \
181 #elif defined(CONFIG_CPU_SUBTYPE_SH7619)
182 #define SH_ETH_RESET_DEFAULT 1
183 static struct sh_eth_cpu_data sh_eth_my_cpu_data
= {
184 .eesipr_value
= DMAC_M_RFRMER
| DMAC_M_ECI
| 0x003fffff,
191 #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
192 #define SH_ETH_RESET_DEFAULT 1
193 #define SH_ETH_HAS_TSU 1
194 static struct sh_eth_cpu_data sh_eth_my_cpu_data
= {
195 .eesipr_value
= DMAC_M_RFRMER
| DMAC_M_ECI
| 0x003fffff,
199 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data
*cd
)
202 cd
->ecsr_value
= DEFAULT_ECSR_INIT
;
204 if (!cd
->ecsipr_value
)
205 cd
->ecsipr_value
= DEFAULT_ECSIPR_INIT
;
207 if (!cd
->fcftr_value
)
208 cd
->fcftr_value
= DEFAULT_FIFO_F_D_RFF
| \
209 DEFAULT_FIFO_F_D_RFD
;
212 cd
->fdr_value
= DEFAULT_FDR_INIT
;
215 cd
->rmcr_value
= DEFAULT_RMCR_VALUE
;
218 cd
->tx_check
= DEFAULT_TX_CHECK
;
220 if (!cd
->eesr_err_check
)
221 cd
->eesr_err_check
= DEFAULT_EESR_ERR_CHECK
;
223 if (!cd
->tx_error_check
)
224 cd
->tx_error_check
= DEFAULT_TX_ERROR_CHECK
;
227 #if defined(SH_ETH_RESET_DEFAULT)
229 static void sh_eth_reset(struct net_device
*ndev
)
231 u32 ioaddr
= ndev
->base_addr
;
233 ctrl_outl(ctrl_inl(ioaddr
+ EDMR
) | EDMR_SRST
, ioaddr
+ EDMR
);
235 ctrl_outl(ctrl_inl(ioaddr
+ EDMR
) & ~EDMR_SRST
, ioaddr
+ EDMR
);
239 #if defined(CONFIG_CPU_SH4)
240 static void sh_eth_set_receive_align(struct sk_buff
*skb
)
244 reserve
= SH4_SKB_RX_ALIGN
- ((u32
)skb
->data
& (SH4_SKB_RX_ALIGN
- 1));
246 skb_reserve(skb
, reserve
);
249 static void sh_eth_set_receive_align(struct sk_buff
*skb
)
251 skb_reserve(skb
, SH2_SH3_SKB_RX_ALIGN
);
256 /* CPU <-> EDMAC endian convert */
257 static inline __u32
cpu_to_edmac(struct sh_eth_private
*mdp
, u32 x
)
259 switch (mdp
->edmac_endian
) {
260 case EDMAC_LITTLE_ENDIAN
:
261 return cpu_to_le32(x
);
262 case EDMAC_BIG_ENDIAN
:
263 return cpu_to_be32(x
);
268 static inline __u32
edmac_to_cpu(struct sh_eth_private
*mdp
, u32 x
)
270 switch (mdp
->edmac_endian
) {
271 case EDMAC_LITTLE_ENDIAN
:
272 return le32_to_cpu(x
);
273 case EDMAC_BIG_ENDIAN
:
274 return be32_to_cpu(x
);
280 * Program the hardware MAC address from dev->dev_addr.
282 static void update_mac_address(struct net_device
*ndev
)
284 u32 ioaddr
= ndev
->base_addr
;
286 ctrl_outl((ndev
->dev_addr
[0] << 24) | (ndev
->dev_addr
[1] << 16) |
287 (ndev
->dev_addr
[2] << 8) | (ndev
->dev_addr
[3]),
289 ctrl_outl((ndev
->dev_addr
[4] << 8) | (ndev
->dev_addr
[5]),
294 * Get MAC address from SuperH MAC address register
296 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
297 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
298 * When you want use this device, you must set MAC address in bootloader.
301 static void read_mac_address(struct net_device
*ndev
)
303 u32 ioaddr
= ndev
->base_addr
;
305 ndev
->dev_addr
[0] = (ctrl_inl(ioaddr
+ MAHR
) >> 24);
306 ndev
->dev_addr
[1] = (ctrl_inl(ioaddr
+ MAHR
) >> 16) & 0xFF;
307 ndev
->dev_addr
[2] = (ctrl_inl(ioaddr
+ MAHR
) >> 8) & 0xFF;
308 ndev
->dev_addr
[3] = (ctrl_inl(ioaddr
+ MAHR
) & 0xFF);
309 ndev
->dev_addr
[4] = (ctrl_inl(ioaddr
+ MALR
) >> 8) & 0xFF;
310 ndev
->dev_addr
[5] = (ctrl_inl(ioaddr
+ MALR
) & 0xFF);
314 struct mdiobb_ctrl ctrl
;
316 u32 mmd_msk
;/* MMD */
323 static void bb_set(u32 addr
, u32 msk
)
325 ctrl_outl(ctrl_inl(addr
) | msk
, addr
);
329 static void bb_clr(u32 addr
, u32 msk
)
331 ctrl_outl((ctrl_inl(addr
) & ~msk
), addr
);
335 static int bb_read(u32 addr
, u32 msk
)
337 return (ctrl_inl(addr
) & msk
) != 0;
340 /* Data I/O pin control */
341 static void sh_mmd_ctrl(struct mdiobb_ctrl
*ctrl
, int bit
)
343 struct bb_info
*bitbang
= container_of(ctrl
, struct bb_info
, ctrl
);
345 bb_set(bitbang
->addr
, bitbang
->mmd_msk
);
347 bb_clr(bitbang
->addr
, bitbang
->mmd_msk
);
351 static void sh_set_mdio(struct mdiobb_ctrl
*ctrl
, int bit
)
353 struct bb_info
*bitbang
= container_of(ctrl
, struct bb_info
, ctrl
);
356 bb_set(bitbang
->addr
, bitbang
->mdo_msk
);
358 bb_clr(bitbang
->addr
, bitbang
->mdo_msk
);
362 static int sh_get_mdio(struct mdiobb_ctrl
*ctrl
)
364 struct bb_info
*bitbang
= container_of(ctrl
, struct bb_info
, ctrl
);
365 return bb_read(bitbang
->addr
, bitbang
->mdi_msk
);
368 /* MDC pin control */
369 static void sh_mdc_ctrl(struct mdiobb_ctrl
*ctrl
, int bit
)
371 struct bb_info
*bitbang
= container_of(ctrl
, struct bb_info
, ctrl
);
374 bb_set(bitbang
->addr
, bitbang
->mdc_msk
);
376 bb_clr(bitbang
->addr
, bitbang
->mdc_msk
);
379 /* mdio bus control struct */
380 static struct mdiobb_ops bb_ops
= {
381 .owner
= THIS_MODULE
,
382 .set_mdc
= sh_mdc_ctrl
,
383 .set_mdio_dir
= sh_mmd_ctrl
,
384 .set_mdio_data
= sh_set_mdio
,
385 .get_mdio_data
= sh_get_mdio
,
388 /* free skb and descriptor buffer */
389 static void sh_eth_ring_free(struct net_device
*ndev
)
391 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
394 /* Free Rx skb ringbuffer */
395 if (mdp
->rx_skbuff
) {
396 for (i
= 0; i
< RX_RING_SIZE
; i
++) {
397 if (mdp
->rx_skbuff
[i
])
398 dev_kfree_skb(mdp
->rx_skbuff
[i
]);
401 kfree(mdp
->rx_skbuff
);
403 /* Free Tx skb ringbuffer */
404 if (mdp
->tx_skbuff
) {
405 for (i
= 0; i
< TX_RING_SIZE
; i
++) {
406 if (mdp
->tx_skbuff
[i
])
407 dev_kfree_skb(mdp
->tx_skbuff
[i
]);
410 kfree(mdp
->tx_skbuff
);
413 /* format skb and descriptor buffer */
414 static void sh_eth_ring_format(struct net_device
*ndev
)
416 u32 ioaddr
= ndev
->base_addr
;
417 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
420 struct sh_eth_rxdesc
*rxdesc
= NULL
;
421 struct sh_eth_txdesc
*txdesc
= NULL
;
422 int rx_ringsize
= sizeof(*rxdesc
) * RX_RING_SIZE
;
423 int tx_ringsize
= sizeof(*txdesc
) * TX_RING_SIZE
;
425 mdp
->cur_rx
= mdp
->cur_tx
= 0;
426 mdp
->dirty_rx
= mdp
->dirty_tx
= 0;
428 memset(mdp
->rx_ring
, 0, rx_ringsize
);
430 /* build Rx ring buffer */
431 for (i
= 0; i
< RX_RING_SIZE
; i
++) {
433 mdp
->rx_skbuff
[i
] = NULL
;
434 skb
= dev_alloc_skb(mdp
->rx_buf_sz
);
435 mdp
->rx_skbuff
[i
] = skb
;
438 dma_map_single(&ndev
->dev
, skb
->tail
, mdp
->rx_buf_sz
,
440 skb
->dev
= ndev
; /* Mark as being used by this device. */
441 sh_eth_set_receive_align(skb
);
444 rxdesc
= &mdp
->rx_ring
[i
];
445 rxdesc
->addr
= virt_to_phys(PTR_ALIGN(skb
->data
, 4));
446 rxdesc
->status
= cpu_to_edmac(mdp
, RD_RACT
| RD_RFP
);
448 /* The size of the buffer is 16 byte boundary. */
449 rxdesc
->buffer_length
= ALIGN(mdp
->rx_buf_sz
, 16);
450 /* Rx descriptor address set */
452 ctrl_outl(mdp
->rx_desc_dma
, ioaddr
+ RDLAR
);
453 #if defined(CONFIG_CPU_SUBTYPE_SH7763)
454 ctrl_outl(mdp
->rx_desc_dma
, ioaddr
+ RDFAR
);
459 mdp
->dirty_rx
= (u32
) (i
- RX_RING_SIZE
);
461 /* Mark the last entry as wrapping the ring. */
462 rxdesc
->status
|= cpu_to_edmac(mdp
, RD_RDEL
);
464 memset(mdp
->tx_ring
, 0, tx_ringsize
);
466 /* build Tx ring buffer */
467 for (i
= 0; i
< TX_RING_SIZE
; i
++) {
468 mdp
->tx_skbuff
[i
] = NULL
;
469 txdesc
= &mdp
->tx_ring
[i
];
470 txdesc
->status
= cpu_to_edmac(mdp
, TD_TFP
);
471 txdesc
->buffer_length
= 0;
473 /* Tx descriptor address set */
474 ctrl_outl(mdp
->tx_desc_dma
, ioaddr
+ TDLAR
);
475 #if defined(CONFIG_CPU_SUBTYPE_SH7763)
476 ctrl_outl(mdp
->tx_desc_dma
, ioaddr
+ TDFAR
);
481 txdesc
->status
|= cpu_to_edmac(mdp
, TD_TDLE
);
484 /* Get skb and descriptor buffer */
485 static int sh_eth_ring_init(struct net_device
*ndev
)
487 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
488 int rx_ringsize
, tx_ringsize
, ret
= 0;
491 * +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
492 * card needs room to do 8 byte alignment, +2 so we can reserve
493 * the first 2 bytes, and +16 gets room for the status word from the
496 mdp
->rx_buf_sz
= (ndev
->mtu
<= 1492 ? PKT_BUF_SZ
:
497 (((ndev
->mtu
+ 26 + 7) & ~7) + 2 + 16));
499 /* Allocate RX and TX skb rings */
500 mdp
->rx_skbuff
= kmalloc(sizeof(*mdp
->rx_skbuff
) * RX_RING_SIZE
,
502 if (!mdp
->rx_skbuff
) {
503 dev_err(&ndev
->dev
, "Cannot allocate Rx skb\n");
508 mdp
->tx_skbuff
= kmalloc(sizeof(*mdp
->tx_skbuff
) * TX_RING_SIZE
,
510 if (!mdp
->tx_skbuff
) {
511 dev_err(&ndev
->dev
, "Cannot allocate Tx skb\n");
516 /* Allocate all Rx descriptors. */
517 rx_ringsize
= sizeof(struct sh_eth_rxdesc
) * RX_RING_SIZE
;
518 mdp
->rx_ring
= dma_alloc_coherent(NULL
, rx_ringsize
, &mdp
->rx_desc_dma
,
522 dev_err(&ndev
->dev
, "Cannot allocate Rx Ring (size %d bytes)\n",
530 /* Allocate all Tx descriptors. */
531 tx_ringsize
= sizeof(struct sh_eth_txdesc
) * TX_RING_SIZE
;
532 mdp
->tx_ring
= dma_alloc_coherent(NULL
, tx_ringsize
, &mdp
->tx_desc_dma
,
535 dev_err(&ndev
->dev
, "Cannot allocate Tx Ring (size %d bytes)\n",
543 /* free DMA buffer */
544 dma_free_coherent(NULL
, rx_ringsize
, mdp
->rx_ring
, mdp
->rx_desc_dma
);
547 /* Free Rx and Tx skb ring buffer */
548 sh_eth_ring_free(ndev
);
553 static int sh_eth_dev_init(struct net_device
*ndev
)
556 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
557 u32 ioaddr
= ndev
->base_addr
;
558 u_int32_t rx_int_var
, tx_int_var
;
564 /* Descriptor format */
565 sh_eth_ring_format(ndev
);
567 ctrl_outl(mdp
->cd
->rpadir_value
, ioaddr
+ RPADIR
);
569 /* all sh_eth int mask */
570 ctrl_outl(0, ioaddr
+ EESIPR
);
572 #if defined(__LITTLE_ENDIAN__)
573 if (mdp
->cd
->hw_swap
)
574 ctrl_outl(EDMR_EL
, ioaddr
+ EDMR
);
577 ctrl_outl(0, ioaddr
+ EDMR
);
580 ctrl_outl(mdp
->cd
->fdr_value
, ioaddr
+ FDR
);
581 ctrl_outl(0, ioaddr
+ TFTR
);
583 /* Frame recv control */
584 ctrl_outl(mdp
->cd
->rmcr_value
, ioaddr
+ RMCR
);
586 rx_int_var
= mdp
->rx_int_var
= DESC_I_RINT8
| DESC_I_RINT5
;
587 tx_int_var
= mdp
->tx_int_var
= DESC_I_TINT2
;
588 ctrl_outl(rx_int_var
| tx_int_var
, ioaddr
+ TRSCER
);
591 ctrl_outl(0x800, ioaddr
+ BCULR
); /* Burst sycle set */
593 ctrl_outl(mdp
->cd
->fcftr_value
, ioaddr
+ FCFTR
);
595 if (!mdp
->cd
->no_trimd
)
596 ctrl_outl(0, ioaddr
+ TRIMD
);
598 /* Recv frame limit set register */
599 ctrl_outl(RFLR_VALUE
, ioaddr
+ RFLR
);
601 ctrl_outl(ctrl_inl(ioaddr
+ EESR
), ioaddr
+ EESR
);
602 ctrl_outl(mdp
->cd
->eesipr_value
, ioaddr
+ EESIPR
);
604 /* PAUSE Prohibition */
605 val
= (ctrl_inl(ioaddr
+ ECMR
) & ECMR_DM
) |
606 ECMR_ZPF
| (mdp
->duplex
? ECMR_DM
: 0) | ECMR_TE
| ECMR_RE
;
608 ctrl_outl(val
, ioaddr
+ ECMR
);
610 if (mdp
->cd
->set_rate
)
611 mdp
->cd
->set_rate(ndev
);
613 /* E-MAC Status Register clear */
614 ctrl_outl(mdp
->cd
->ecsr_value
, ioaddr
+ ECSR
);
616 /* E-MAC Interrupt Enable register */
617 ctrl_outl(mdp
->cd
->ecsipr_value
, ioaddr
+ ECSIPR
);
619 /* Set MAC address */
620 update_mac_address(ndev
);
624 ctrl_outl(APR_AP
, ioaddr
+ APR
);
626 ctrl_outl(MPR_MP
, ioaddr
+ MPR
);
627 if (mdp
->cd
->tpauser
)
628 ctrl_outl(TPAUSER_UNLIMITED
, ioaddr
+ TPAUSER
);
630 /* Setting the Rx mode will start the Rx process. */
631 ctrl_outl(EDRRR_R
, ioaddr
+ EDRRR
);
633 netif_start_queue(ndev
);
638 /* free Tx skb function */
639 static int sh_eth_txfree(struct net_device
*ndev
)
641 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
642 struct sh_eth_txdesc
*txdesc
;
646 for (; mdp
->cur_tx
- mdp
->dirty_tx
> 0; mdp
->dirty_tx
++) {
647 entry
= mdp
->dirty_tx
% TX_RING_SIZE
;
648 txdesc
= &mdp
->tx_ring
[entry
];
649 if (txdesc
->status
& cpu_to_edmac(mdp
, TD_TACT
))
651 /* Free the original skb. */
652 if (mdp
->tx_skbuff
[entry
]) {
653 dev_kfree_skb_irq(mdp
->tx_skbuff
[entry
]);
654 mdp
->tx_skbuff
[entry
] = NULL
;
657 txdesc
->status
= cpu_to_edmac(mdp
, TD_TFP
);
658 if (entry
>= TX_RING_SIZE
- 1)
659 txdesc
->status
|= cpu_to_edmac(mdp
, TD_TDLE
);
661 mdp
->stats
.tx_packets
++;
662 mdp
->stats
.tx_bytes
+= txdesc
->buffer_length
;
667 /* Packet receive function */
668 static int sh_eth_rx(struct net_device
*ndev
)
670 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
671 struct sh_eth_rxdesc
*rxdesc
;
673 int entry
= mdp
->cur_rx
% RX_RING_SIZE
;
674 int boguscnt
= (mdp
->dirty_rx
+ RX_RING_SIZE
) - mdp
->cur_rx
;
679 rxdesc
= &mdp
->rx_ring
[entry
];
680 while (!(rxdesc
->status
& cpu_to_edmac(mdp
, RD_RACT
))) {
681 desc_status
= edmac_to_cpu(mdp
, rxdesc
->status
);
682 pkt_len
= rxdesc
->frame_length
;
687 if (!(desc_status
& RDFEND
))
688 mdp
->stats
.rx_length_errors
++;
690 if (desc_status
& (RD_RFS1
| RD_RFS2
| RD_RFS3
| RD_RFS4
|
691 RD_RFS5
| RD_RFS6
| RD_RFS10
)) {
692 mdp
->stats
.rx_errors
++;
693 if (desc_status
& RD_RFS1
)
694 mdp
->stats
.rx_crc_errors
++;
695 if (desc_status
& RD_RFS2
)
696 mdp
->stats
.rx_frame_errors
++;
697 if (desc_status
& RD_RFS3
)
698 mdp
->stats
.rx_length_errors
++;
699 if (desc_status
& RD_RFS4
)
700 mdp
->stats
.rx_length_errors
++;
701 if (desc_status
& RD_RFS6
)
702 mdp
->stats
.rx_missed_errors
++;
703 if (desc_status
& RD_RFS10
)
704 mdp
->stats
.rx_over_errors
++;
706 if (!mdp
->cd
->hw_swap
)
708 phys_to_virt(ALIGN(rxdesc
->addr
, 4)),
710 skb
= mdp
->rx_skbuff
[entry
];
711 mdp
->rx_skbuff
[entry
] = NULL
;
712 skb_put(skb
, pkt_len
);
713 skb
->protocol
= eth_type_trans(skb
, ndev
);
715 mdp
->stats
.rx_packets
++;
716 mdp
->stats
.rx_bytes
+= pkt_len
;
718 rxdesc
->status
|= cpu_to_edmac(mdp
, RD_RACT
);
719 entry
= (++mdp
->cur_rx
) % RX_RING_SIZE
;
720 rxdesc
= &mdp
->rx_ring
[entry
];
723 /* Refill the Rx ring buffers. */
724 for (; mdp
->cur_rx
- mdp
->dirty_rx
> 0; mdp
->dirty_rx
++) {
725 entry
= mdp
->dirty_rx
% RX_RING_SIZE
;
726 rxdesc
= &mdp
->rx_ring
[entry
];
727 /* The size of the buffer is 16 byte boundary. */
728 rxdesc
->buffer_length
= ALIGN(mdp
->rx_buf_sz
, 16);
730 if (mdp
->rx_skbuff
[entry
] == NULL
) {
731 skb
= dev_alloc_skb(mdp
->rx_buf_sz
);
732 mdp
->rx_skbuff
[entry
] = skb
;
734 break; /* Better luck next round. */
735 dma_map_single(&ndev
->dev
, skb
->tail
, mdp
->rx_buf_sz
,
738 sh_eth_set_receive_align(skb
);
740 skb
->ip_summed
= CHECKSUM_NONE
;
741 rxdesc
->addr
= virt_to_phys(PTR_ALIGN(skb
->data
, 4));
743 if (entry
>= RX_RING_SIZE
- 1)
745 cpu_to_edmac(mdp
, RD_RACT
| RD_RFP
| RD_RDEL
);
748 cpu_to_edmac(mdp
, RD_RACT
| RD_RFP
);
751 /* Restart Rx engine if stopped. */
752 /* If we don't need to check status, don't. -KDU */
753 if (!(ctrl_inl(ndev
->base_addr
+ EDRRR
) & EDRRR_R
))
754 ctrl_outl(EDRRR_R
, ndev
->base_addr
+ EDRRR
);
759 /* error control function */
760 static void sh_eth_error(struct net_device
*ndev
, int intr_status
)
762 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
763 u32 ioaddr
= ndev
->base_addr
;
768 if (intr_status
& EESR_ECI
) {
769 felic_stat
= ctrl_inl(ioaddr
+ ECSR
);
770 ctrl_outl(felic_stat
, ioaddr
+ ECSR
); /* clear int */
771 if (felic_stat
& ECSR_ICD
)
772 mdp
->stats
.tx_carrier_errors
++;
773 if (felic_stat
& ECSR_LCHNG
) {
775 if (mdp
->cd
->no_psr
) {
776 if (mdp
->link
== PHY_DOWN
)
779 link_stat
= PHY_ST_LINK
;
781 link_stat
= (ctrl_inl(ioaddr
+ PSR
));
783 if (!(link_stat
& PHY_ST_LINK
)) {
784 /* Link Down : disable tx and rx */
785 ctrl_outl(ctrl_inl(ioaddr
+ ECMR
) &
786 ~(ECMR_RE
| ECMR_TE
), ioaddr
+ ECMR
);
789 ctrl_outl(ctrl_inl(ioaddr
+ EESIPR
) &
790 ~DMAC_M_ECI
, ioaddr
+ EESIPR
);
792 ctrl_outl(ctrl_inl(ioaddr
+ ECSR
),
794 ctrl_outl(ctrl_inl(ioaddr
+ EESIPR
) |
795 DMAC_M_ECI
, ioaddr
+ EESIPR
);
796 /* enable tx and rx */
797 ctrl_outl(ctrl_inl(ioaddr
+ ECMR
) |
798 (ECMR_RE
| ECMR_TE
), ioaddr
+ ECMR
);
803 if (intr_status
& EESR_TWB
) {
804 /* Write buck end. unused write back interrupt */
805 if (intr_status
& EESR_TABT
) /* Transmit Abort int */
806 mdp
->stats
.tx_aborted_errors
++;
809 if (intr_status
& EESR_RABT
) {
810 /* Receive Abort int */
811 if (intr_status
& EESR_RFRMER
) {
812 /* Receive Frame Overflow int */
813 mdp
->stats
.rx_frame_errors
++;
814 dev_err(&ndev
->dev
, "Receive Frame Overflow\n");
818 if (!mdp
->cd
->no_ade
) {
819 if (intr_status
& EESR_ADE
&& intr_status
& EESR_TDE
&&
820 intr_status
& EESR_TFE
)
821 mdp
->stats
.tx_fifo_errors
++;
824 if (intr_status
& EESR_RDE
) {
825 /* Receive Descriptor Empty int */
826 mdp
->stats
.rx_over_errors
++;
828 if (ctrl_inl(ioaddr
+ EDRRR
) ^ EDRRR_R
)
829 ctrl_outl(EDRRR_R
, ioaddr
+ EDRRR
);
830 dev_err(&ndev
->dev
, "Receive Descriptor Empty\n");
832 if (intr_status
& EESR_RFE
) {
833 /* Receive FIFO Overflow int */
834 mdp
->stats
.rx_fifo_errors
++;
835 dev_err(&ndev
->dev
, "Receive FIFO Overflow\n");
838 mask
= EESR_TWB
| EESR_TABT
| EESR_ADE
| EESR_TDE
| EESR_TFE
;
841 if (intr_status
& mask
) {
843 u32 edtrr
= ctrl_inl(ndev
->base_addr
+ EDTRR
);
845 dev_err(&ndev
->dev
, "TX error. status=%8.8x cur_tx=%8.8x ",
846 intr_status
, mdp
->cur_tx
);
847 dev_err(&ndev
->dev
, "dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
848 mdp
->dirty_tx
, (u32
) ndev
->state
, edtrr
);
849 /* dirty buffer free */
853 if (edtrr
^ EDTRR_TRNS
) {
855 ctrl_outl(EDTRR_TRNS
, ndev
->base_addr
+ EDTRR
);
858 netif_wake_queue(ndev
);
862 static irqreturn_t
sh_eth_interrupt(int irq
, void *netdev
)
864 struct net_device
*ndev
= netdev
;
865 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
866 struct sh_eth_cpu_data
*cd
= mdp
->cd
;
867 irqreturn_t ret
= IRQ_NONE
;
868 u32 ioaddr
, boguscnt
= RX_RING_SIZE
;
871 ioaddr
= ndev
->base_addr
;
872 spin_lock(&mdp
->lock
);
874 /* Get interrpt stat */
875 intr_status
= ctrl_inl(ioaddr
+ EESR
);
876 /* Clear interrupt */
877 if (intr_status
& (EESR_FRC
| EESR_RMAF
| EESR_RRF
|
878 EESR_RTLF
| EESR_RTSF
| EESR_PRE
| EESR_CERF
|
879 cd
->tx_check
| cd
->eesr_err_check
)) {
880 ctrl_outl(intr_status
, ioaddr
+ EESR
);
885 if (intr_status
& (EESR_FRC
| /* Frame recv*/
886 EESR_RMAF
| /* Multi cast address recv*/
887 EESR_RRF
| /* Bit frame recv */
888 EESR_RTLF
| /* Long frame recv*/
889 EESR_RTSF
| /* short frame recv */
890 EESR_PRE
| /* PHY-LSI recv error */
891 EESR_CERF
)){ /* recv frame CRC error */
896 if (intr_status
& cd
->tx_check
) {
898 netif_wake_queue(ndev
);
901 if (intr_status
& cd
->eesr_err_check
)
902 sh_eth_error(ndev
, intr_status
);
904 if (--boguscnt
< 0) {
906 "%s: Too much work at interrupt, status=0x%4.4x.\n",
907 ndev
->name
, intr_status
);
911 spin_unlock(&mdp
->lock
);
916 static void sh_eth_timer(unsigned long data
)
918 struct net_device
*ndev
= (struct net_device
*)data
;
919 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
921 mod_timer(&mdp
->timer
, jiffies
+ (10 * HZ
));
924 /* PHY state control function */
925 static void sh_eth_adjust_link(struct net_device
*ndev
)
927 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
928 struct phy_device
*phydev
= mdp
->phydev
;
929 u32 ioaddr
= ndev
->base_addr
;
932 if (phydev
->link
!= PHY_DOWN
) {
933 if (phydev
->duplex
!= mdp
->duplex
) {
935 mdp
->duplex
= phydev
->duplex
;
936 if (mdp
->cd
->set_duplex
)
937 mdp
->cd
->set_duplex(ndev
);
940 if (phydev
->speed
!= mdp
->speed
) {
942 mdp
->speed
= phydev
->speed
;
943 if (mdp
->cd
->set_rate
)
944 mdp
->cd
->set_rate(ndev
);
946 if (mdp
->link
== PHY_DOWN
) {
947 ctrl_outl((ctrl_inl(ioaddr
+ ECMR
) & ~ECMR_TXF
)
948 | ECMR_DM
, ioaddr
+ ECMR
);
950 mdp
->link
= phydev
->link
;
952 } else if (mdp
->link
) {
954 mdp
->link
= PHY_DOWN
;
960 phy_print_status(phydev
);
963 /* PHY init function */
964 static int sh_eth_phy_init(struct net_device
*ndev
)
966 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
967 char phy_id
[MII_BUS_ID_SIZE
+ 3];
968 struct phy_device
*phydev
= NULL
;
970 snprintf(phy_id
, sizeof(phy_id
), PHY_ID_FMT
,
971 mdp
->mii_bus
->id
, mdp
->phy_id
);
973 mdp
->link
= PHY_DOWN
;
977 /* Try connect to PHY */
978 phydev
= phy_connect(ndev
, phy_id
, &sh_eth_adjust_link
,
979 0, PHY_INTERFACE_MODE_MII
);
980 if (IS_ERR(phydev
)) {
981 dev_err(&ndev
->dev
, "phy_connect failed\n");
982 return PTR_ERR(phydev
);
985 dev_info(&ndev
->dev
, "attached phy %i to driver %s\n",
986 phydev
->addr
, phydev
->drv
->name
);
988 mdp
->phydev
= phydev
;
993 /* PHY control start function */
994 static int sh_eth_phy_start(struct net_device
*ndev
)
996 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
999 ret
= sh_eth_phy_init(ndev
);
1003 /* reset phy - this also wakes it from PDOWN */
1004 phy_write(mdp
->phydev
, MII_BMCR
, BMCR_RESET
);
1005 phy_start(mdp
->phydev
);
1010 /* network device open function */
1011 static int sh_eth_open(struct net_device
*ndev
)
1014 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1016 ret
= request_irq(ndev
->irq
, &sh_eth_interrupt
,
1017 #if defined(CONFIG_CPU_SUBTYPE_SH7763) || defined(CONFIG_CPU_SUBTYPE_SH7764)
1024 dev_err(&ndev
->dev
, "Can not assign IRQ number\n");
1028 /* Descriptor set */
1029 ret
= sh_eth_ring_init(ndev
);
1034 ret
= sh_eth_dev_init(ndev
);
1038 /* PHY control start*/
1039 ret
= sh_eth_phy_start(ndev
);
1043 /* Set the timer to check for link beat. */
1044 init_timer(&mdp
->timer
);
1045 mdp
->timer
.expires
= (jiffies
+ (24 * HZ
)) / 10;/* 2.4 sec. */
1046 setup_timer(&mdp
->timer
, sh_eth_timer
, (unsigned long)ndev
);
1051 free_irq(ndev
->irq
, ndev
);
1055 /* Timeout function */
1056 static void sh_eth_tx_timeout(struct net_device
*ndev
)
1058 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1059 u32 ioaddr
= ndev
->base_addr
;
1060 struct sh_eth_rxdesc
*rxdesc
;
1063 netif_stop_queue(ndev
);
1065 /* worning message out. */
1066 printk(KERN_WARNING
"%s: transmit timed out, status %8.8x,"
1067 " resetting...\n", ndev
->name
, (int)ctrl_inl(ioaddr
+ EESR
));
1069 /* tx_errors count up */
1070 mdp
->stats
.tx_errors
++;
1073 del_timer_sync(&mdp
->timer
);
1075 /* Free all the skbuffs in the Rx queue. */
1076 for (i
= 0; i
< RX_RING_SIZE
; i
++) {
1077 rxdesc
= &mdp
->rx_ring
[i
];
1079 rxdesc
->addr
= 0xBADF00D0;
1080 if (mdp
->rx_skbuff
[i
])
1081 dev_kfree_skb(mdp
->rx_skbuff
[i
]);
1082 mdp
->rx_skbuff
[i
] = NULL
;
1084 for (i
= 0; i
< TX_RING_SIZE
; i
++) {
1085 if (mdp
->tx_skbuff
[i
])
1086 dev_kfree_skb(mdp
->tx_skbuff
[i
]);
1087 mdp
->tx_skbuff
[i
] = NULL
;
1091 sh_eth_dev_init(ndev
);
1094 mdp
->timer
.expires
= (jiffies
+ (24 * HZ
)) / 10;/* 2.4 sec. */
1095 add_timer(&mdp
->timer
);
1098 /* Packet transmit function */
1099 static int sh_eth_start_xmit(struct sk_buff
*skb
, struct net_device
*ndev
)
1101 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1102 struct sh_eth_txdesc
*txdesc
;
1104 unsigned long flags
;
1106 spin_lock_irqsave(&mdp
->lock
, flags
);
1107 if ((mdp
->cur_tx
- mdp
->dirty_tx
) >= (TX_RING_SIZE
- 4)) {
1108 if (!sh_eth_txfree(ndev
)) {
1109 netif_stop_queue(ndev
);
1110 spin_unlock_irqrestore(&mdp
->lock
, flags
);
1114 spin_unlock_irqrestore(&mdp
->lock
, flags
);
1116 entry
= mdp
->cur_tx
% TX_RING_SIZE
;
1117 mdp
->tx_skbuff
[entry
] = skb
;
1118 txdesc
= &mdp
->tx_ring
[entry
];
1119 txdesc
->addr
= virt_to_phys(skb
->data
);
1121 if (!mdp
->cd
->hw_swap
)
1122 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc
->addr
, 4)),
1125 __flush_purge_region(skb
->data
, skb
->len
);
1126 if (skb
->len
< ETHERSMALL
)
1127 txdesc
->buffer_length
= ETHERSMALL
;
1129 txdesc
->buffer_length
= skb
->len
;
1131 if (entry
>= TX_RING_SIZE
- 1)
1132 txdesc
->status
|= cpu_to_edmac(mdp
, TD_TACT
| TD_TDLE
);
1134 txdesc
->status
|= cpu_to_edmac(mdp
, TD_TACT
);
1138 if (!(ctrl_inl(ndev
->base_addr
+ EDTRR
) & EDTRR_TRNS
))
1139 ctrl_outl(EDTRR_TRNS
, ndev
->base_addr
+ EDTRR
);
1141 ndev
->trans_start
= jiffies
;
1146 /* device close function */
1147 static int sh_eth_close(struct net_device
*ndev
)
1149 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1150 u32 ioaddr
= ndev
->base_addr
;
1153 netif_stop_queue(ndev
);
1155 /* Disable interrupts by clearing the interrupt mask. */
1156 ctrl_outl(0x0000, ioaddr
+ EESIPR
);
1158 /* Stop the chip's Tx and Rx processes. */
1159 ctrl_outl(0, ioaddr
+ EDTRR
);
1160 ctrl_outl(0, ioaddr
+ EDRRR
);
1162 /* PHY Disconnect */
1164 phy_stop(mdp
->phydev
);
1165 phy_disconnect(mdp
->phydev
);
1168 free_irq(ndev
->irq
, ndev
);
1170 del_timer_sync(&mdp
->timer
);
1172 /* Free all the skbuffs in the Rx queue. */
1173 sh_eth_ring_free(ndev
);
1175 /* free DMA buffer */
1176 ringsize
= sizeof(struct sh_eth_rxdesc
) * RX_RING_SIZE
;
1177 dma_free_coherent(NULL
, ringsize
, mdp
->rx_ring
, mdp
->rx_desc_dma
);
1179 /* free DMA buffer */
1180 ringsize
= sizeof(struct sh_eth_txdesc
) * TX_RING_SIZE
;
1181 dma_free_coherent(NULL
, ringsize
, mdp
->tx_ring
, mdp
->tx_desc_dma
);
1186 static struct net_device_stats
*sh_eth_get_stats(struct net_device
*ndev
)
1188 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1189 u32 ioaddr
= ndev
->base_addr
;
1191 mdp
->stats
.tx_dropped
+= ctrl_inl(ioaddr
+ TROCR
);
1192 ctrl_outl(0, ioaddr
+ TROCR
); /* (write clear) */
1193 mdp
->stats
.collisions
+= ctrl_inl(ioaddr
+ CDCR
);
1194 ctrl_outl(0, ioaddr
+ CDCR
); /* (write clear) */
1195 mdp
->stats
.tx_carrier_errors
+= ctrl_inl(ioaddr
+ LCCR
);
1196 ctrl_outl(0, ioaddr
+ LCCR
); /* (write clear) */
1197 #if defined(CONFIG_CPU_SUBTYPE_SH7763)
1198 mdp
->stats
.tx_carrier_errors
+= ctrl_inl(ioaddr
+ CERCR
);/* CERCR */
1199 ctrl_outl(0, ioaddr
+ CERCR
); /* (write clear) */
1200 mdp
->stats
.tx_carrier_errors
+= ctrl_inl(ioaddr
+ CEECR
);/* CEECR */
1201 ctrl_outl(0, ioaddr
+ CEECR
); /* (write clear) */
1203 mdp
->stats
.tx_carrier_errors
+= ctrl_inl(ioaddr
+ CNDCR
);
1204 ctrl_outl(0, ioaddr
+ CNDCR
); /* (write clear) */
1209 /* ioctl to device funciotn*/
1210 static int sh_eth_do_ioctl(struct net_device
*ndev
, struct ifreq
*rq
,
1213 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1214 struct phy_device
*phydev
= mdp
->phydev
;
1216 if (!netif_running(ndev
))
1222 return phy_mii_ioctl(phydev
, if_mii(rq
), cmd
);
1225 #if defined(SH_ETH_HAS_TSU)
1226 /* Multicast reception directions set */
1227 static void sh_eth_set_multicast_list(struct net_device
*ndev
)
1229 u32 ioaddr
= ndev
->base_addr
;
1231 if (ndev
->flags
& IFF_PROMISC
) {
1232 /* Set promiscuous. */
1233 ctrl_outl((ctrl_inl(ioaddr
+ ECMR
) & ~ECMR_MCT
) | ECMR_PRM
,
1236 /* Normal, unicast/broadcast-only mode. */
1237 ctrl_outl((ctrl_inl(ioaddr
+ ECMR
) & ~ECMR_PRM
) | ECMR_MCT
,
1242 /* SuperH's TSU register init function */
1243 static void sh_eth_tsu_init(u32 ioaddr
)
1245 ctrl_outl(0, ioaddr
+ TSU_FWEN0
); /* Disable forward(0->1) */
1246 ctrl_outl(0, ioaddr
+ TSU_FWEN1
); /* Disable forward(1->0) */
1247 ctrl_outl(0, ioaddr
+ TSU_FCM
); /* forward fifo 3k-3k */
1248 ctrl_outl(0xc, ioaddr
+ TSU_BSYSL0
);
1249 ctrl_outl(0xc, ioaddr
+ TSU_BSYSL1
);
1250 ctrl_outl(0, ioaddr
+ TSU_PRISL0
);
1251 ctrl_outl(0, ioaddr
+ TSU_PRISL1
);
1252 ctrl_outl(0, ioaddr
+ TSU_FWSL0
);
1253 ctrl_outl(0, ioaddr
+ TSU_FWSL1
);
1254 ctrl_outl(TSU_FWSLC_POSTENU
| TSU_FWSLC_POSTENL
, ioaddr
+ TSU_FWSLC
);
1255 #if defined(CONFIG_CPU_SUBTYPE_SH7763)
1256 ctrl_outl(0, ioaddr
+ TSU_QTAG0
); /* Disable QTAG(0->1) */
1257 ctrl_outl(0, ioaddr
+ TSU_QTAG1
); /* Disable QTAG(1->0) */
1259 ctrl_outl(0, ioaddr
+ TSU_QTAGM0
); /* Disable QTAG(0->1) */
1260 ctrl_outl(0, ioaddr
+ TSU_QTAGM1
); /* Disable QTAG(1->0) */
1262 ctrl_outl(0, ioaddr
+ TSU_FWSR
); /* all interrupt status clear */
1263 ctrl_outl(0, ioaddr
+ TSU_FWINMK
); /* Disable all interrupt */
1264 ctrl_outl(0, ioaddr
+ TSU_TEN
); /* Disable all CAM entry */
1265 ctrl_outl(0, ioaddr
+ TSU_POST1
); /* Disable CAM entry [ 0- 7] */
1266 ctrl_outl(0, ioaddr
+ TSU_POST2
); /* Disable CAM entry [ 8-15] */
1267 ctrl_outl(0, ioaddr
+ TSU_POST3
); /* Disable CAM entry [16-23] */
1268 ctrl_outl(0, ioaddr
+ TSU_POST4
); /* Disable CAM entry [24-31] */
1270 #endif /* SH_ETH_HAS_TSU */
1272 /* MDIO bus release function */
1273 static int sh_mdio_release(struct net_device
*ndev
)
1275 struct mii_bus
*bus
= dev_get_drvdata(&ndev
->dev
);
1277 /* unregister mdio bus */
1278 mdiobus_unregister(bus
);
1280 /* remove mdio bus info from net_device */
1281 dev_set_drvdata(&ndev
->dev
, NULL
);
1283 /* free bitbang info */
1284 free_mdio_bitbang(bus
);
1289 /* MDIO bus init function */
1290 static int sh_mdio_init(struct net_device
*ndev
, int id
)
1293 struct bb_info
*bitbang
;
1294 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1296 /* create bit control struct for PHY */
1297 bitbang
= kzalloc(sizeof(struct bb_info
), GFP_KERNEL
);
1304 bitbang
->addr
= ndev
->base_addr
+ PIR
;
1305 bitbang
->mdi_msk
= 0x08;
1306 bitbang
->mdo_msk
= 0x04;
1307 bitbang
->mmd_msk
= 0x02;/* MMD */
1308 bitbang
->mdc_msk
= 0x01;
1309 bitbang
->ctrl
.ops
= &bb_ops
;
1311 /* MII contorller setting */
1312 mdp
->mii_bus
= alloc_mdio_bitbang(&bitbang
->ctrl
);
1313 if (!mdp
->mii_bus
) {
1315 goto out_free_bitbang
;
1318 /* Hook up MII support for ethtool */
1319 mdp
->mii_bus
->name
= "sh_mii";
1320 mdp
->mii_bus
->parent
= &ndev
->dev
;
1321 snprintf(mdp
->mii_bus
->id
, MII_BUS_ID_SIZE
, "%x", id
);
1324 mdp
->mii_bus
->irq
= kmalloc(sizeof(int)*PHY_MAX_ADDR
, GFP_KERNEL
);
1325 if (!mdp
->mii_bus
->irq
) {
1330 for (i
= 0; i
< PHY_MAX_ADDR
; i
++)
1331 mdp
->mii_bus
->irq
[i
] = PHY_POLL
;
1333 /* regist mdio bus */
1334 ret
= mdiobus_register(mdp
->mii_bus
);
1338 dev_set_drvdata(&ndev
->dev
, mdp
->mii_bus
);
1343 kfree(mdp
->mii_bus
->irq
);
1346 free_mdio_bitbang(mdp
->mii_bus
);
1355 static const struct net_device_ops sh_eth_netdev_ops
= {
1356 .ndo_open
= sh_eth_open
,
1357 .ndo_stop
= sh_eth_close
,
1358 .ndo_start_xmit
= sh_eth_start_xmit
,
1359 .ndo_get_stats
= sh_eth_get_stats
,
1360 #if defined(SH_ETH_HAS_TSU)
1361 .ndo_set_multicast_list
= sh_eth_set_multicast_list
,
1363 .ndo_tx_timeout
= sh_eth_tx_timeout
,
1364 .ndo_do_ioctl
= sh_eth_do_ioctl
,
1365 .ndo_validate_addr
= eth_validate_addr
,
1366 .ndo_set_mac_address
= eth_mac_addr
,
1367 .ndo_change_mtu
= eth_change_mtu
,
1370 static int sh_eth_drv_probe(struct platform_device
*pdev
)
1372 int ret
, i
, devno
= 0;
1373 struct resource
*res
;
1374 struct net_device
*ndev
= NULL
;
1375 struct sh_eth_private
*mdp
;
1376 struct sh_eth_plat_data
*pd
;
1379 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1380 if (unlikely(res
== NULL
)) {
1381 dev_err(&pdev
->dev
, "invalid resource\n");
1386 ndev
= alloc_etherdev(sizeof(struct sh_eth_private
));
1388 dev_err(&pdev
->dev
, "Could not allocate device.\n");
1393 /* The sh Ether-specific entries in the device structure. */
1394 ndev
->base_addr
= res
->start
;
1400 ret
= platform_get_irq(pdev
, 0);
1407 SET_NETDEV_DEV(ndev
, &pdev
->dev
);
1409 /* Fill in the fields of the device structure with ethernet values. */
1412 mdp
= netdev_priv(ndev
);
1413 spin_lock_init(&mdp
->lock
);
1415 pd
= (struct sh_eth_plat_data
*)(pdev
->dev
.platform_data
);
1417 mdp
->phy_id
= pd
->phy
;
1419 mdp
->edmac_endian
= pd
->edmac_endian
;
1422 mdp
->cd
= &sh_eth_my_cpu_data
;
1423 sh_eth_set_default_cpu_data(mdp
->cd
);
1426 ndev
->netdev_ops
= &sh_eth_netdev_ops
;
1427 ndev
->watchdog_timeo
= TX_TIMEOUT
;
1429 mdp
->post_rx
= POST_RX
>> (devno
<< 1);
1430 mdp
->post_fw
= POST_FW
>> (devno
<< 1);
1432 /* read and set MAC address */
1433 read_mac_address(ndev
);
1435 /* First device only init */
1437 if (mdp
->cd
->chip_reset
)
1438 mdp
->cd
->chip_reset(ndev
);
1440 #if defined(SH_ETH_HAS_TSU)
1441 /* TSU init (Init only)*/
1442 sh_eth_tsu_init(SH_TSU_ADDR
);
1446 /* network device register */
1447 ret
= register_netdev(ndev
);
1452 ret
= sh_mdio_init(ndev
, pdev
->id
);
1454 goto out_unregister
;
1456 /* pritnt device infomation */
1457 pr_info("Base address at 0x%x, ",
1458 (u32
)ndev
->base_addr
);
1460 for (i
= 0; i
< 5; i
++)
1461 printk("%02X:", ndev
->dev_addr
[i
]);
1462 printk("%02X, IRQ %d.\n", ndev
->dev_addr
[i
], ndev
->irq
);
1464 platform_set_drvdata(pdev
, ndev
);
1469 unregister_netdev(ndev
);
1480 static int sh_eth_drv_remove(struct platform_device
*pdev
)
1482 struct net_device
*ndev
= platform_get_drvdata(pdev
);
1484 sh_mdio_release(ndev
);
1485 unregister_netdev(ndev
);
1486 flush_scheduled_work();
1489 platform_set_drvdata(pdev
, NULL
);
1494 static struct platform_driver sh_eth_driver
= {
1495 .probe
= sh_eth_drv_probe
,
1496 .remove
= sh_eth_drv_remove
,
1502 static int __init
sh_eth_init(void)
1504 return platform_driver_register(&sh_eth_driver
);
1507 static void __exit
sh_eth_cleanup(void)
1509 platform_driver_unregister(&sh_eth_driver
);
1512 module_init(sh_eth_init
);
1513 module_exit(sh_eth_cleanup
);
1515 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
1516 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
1517 MODULE_LICENSE("GPL v2");