2 * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
4 * Note: This driver is a cleanroom reimplementation based on reverse
5 * engineered documentation written by Carl-Daniel Hailfinger
6 * and Andrew de Quincey.
8 * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
9 * trademarks of NVIDIA Corporation in the United States and other
12 * Copyright (C) 2003,4,5 Manfred Spraul
13 * Copyright (C) 2004 Andrew de Quincey (wol support)
14 * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
15 * IRQ rate fixes, bigendian fixes, cleanups, verification)
16 * Copyright (c) 2004,2005,2006,2007,2008,2009 NVIDIA Corporation
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License as published by
20 * the Free Software Foundation; either version 2 of the License, or
21 * (at your option) any later version.
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
33 * We suspect that on some hardware no TX done interrupts are generated.
34 * This means recovery from netif_stop_queue only happens if the hw timer
35 * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
36 * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
37 * If your hardware reliably generates tx done interrupts, then you can remove
38 * DEV_NEED_TIMERIRQ from the driver_data flags.
39 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
40 * superfluous timer interrupts from the nic.
42 #define FORCEDETH_VERSION "0.64"
43 #define DRV_NAME "forcedeth"
45 #include <linux/module.h>
46 #include <linux/types.h>
47 #include <linux/pci.h>
48 #include <linux/interrupt.h>
49 #include <linux/netdevice.h>
50 #include <linux/etherdevice.h>
51 #include <linux/delay.h>
52 #include <linux/spinlock.h>
53 #include <linux/ethtool.h>
54 #include <linux/timer.h>
55 #include <linux/skbuff.h>
56 #include <linux/mii.h>
57 #include <linux/random.h>
58 #include <linux/init.h>
59 #include <linux/if_vlan.h>
60 #include <linux/dma-mapping.h>
64 #include <asm/uaccess.h>
65 #include <asm/system.h>
68 #define dprintk printk
70 #define dprintk(x...) do { } while (0)
73 #define TX_WORK_PER_LOOP 64
74 #define RX_WORK_PER_LOOP 64
80 #define DEV_NEED_TIMERIRQ 0x000001 /* set the timer irq flag in the irq mask */
81 #define DEV_NEED_LINKTIMER 0x000002 /* poll link settings. Relies on the timer irq */
82 #define DEV_HAS_LARGEDESC 0x000004 /* device supports jumbo frames and needs packet format 2 */
83 #define DEV_HAS_HIGH_DMA 0x000008 /* device supports 64bit dma */
84 #define DEV_HAS_CHECKSUM 0x000010 /* device supports tx and rx checksum offloads */
85 #define DEV_HAS_VLAN 0x000020 /* device supports vlan tagging and striping */
86 #define DEV_HAS_MSI 0x000040 /* device supports MSI */
87 #define DEV_HAS_MSI_X 0x000080 /* device supports MSI-X */
88 #define DEV_HAS_POWER_CNTRL 0x000100 /* device supports power savings */
89 #define DEV_HAS_STATISTICS_V1 0x000200 /* device supports hw statistics version 1 */
90 #define DEV_HAS_STATISTICS_V2 0x000600 /* device supports hw statistics version 2 */
91 #define DEV_HAS_STATISTICS_V3 0x000e00 /* device supports hw statistics version 3 */
92 #define DEV_HAS_TEST_EXTENDED 0x001000 /* device supports extended diagnostic test */
93 #define DEV_HAS_MGMT_UNIT 0x002000 /* device supports management unit */
94 #define DEV_HAS_CORRECT_MACADDR 0x004000 /* device supports correct mac address order */
95 #define DEV_HAS_COLLISION_FIX 0x008000 /* device supports tx collision fix */
96 #define DEV_HAS_PAUSEFRAME_TX_V1 0x010000 /* device supports tx pause frames version 1 */
97 #define DEV_HAS_PAUSEFRAME_TX_V2 0x020000 /* device supports tx pause frames version 2 */
98 #define DEV_HAS_PAUSEFRAME_TX_V3 0x040000 /* device supports tx pause frames version 3 */
99 #define DEV_NEED_TX_LIMIT 0x080000 /* device needs to limit tx */
100 #define DEV_HAS_GEAR_MODE 0x100000 /* device supports gear mode */
103 NvRegIrqStatus
= 0x000,
104 #define NVREG_IRQSTAT_MIIEVENT 0x040
105 #define NVREG_IRQSTAT_MASK 0x83ff
106 NvRegIrqMask
= 0x004,
107 #define NVREG_IRQ_RX_ERROR 0x0001
108 #define NVREG_IRQ_RX 0x0002
109 #define NVREG_IRQ_RX_NOBUF 0x0004
110 #define NVREG_IRQ_TX_ERR 0x0008
111 #define NVREG_IRQ_TX_OK 0x0010
112 #define NVREG_IRQ_TIMER 0x0020
113 #define NVREG_IRQ_LINK 0x0040
114 #define NVREG_IRQ_RX_FORCED 0x0080
115 #define NVREG_IRQ_TX_FORCED 0x0100
116 #define NVREG_IRQ_RECOVER_ERROR 0x8200
117 #define NVREG_IRQMASK_THROUGHPUT 0x00df
118 #define NVREG_IRQMASK_CPU 0x0060
119 #define NVREG_IRQ_TX_ALL (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
120 #define NVREG_IRQ_RX_ALL (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
121 #define NVREG_IRQ_OTHER (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
123 NvRegUnknownSetupReg6
= 0x008,
124 #define NVREG_UNKSETUP6_VAL 3
127 * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
128 * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
130 NvRegPollingInterval
= 0x00c,
131 #define NVREG_POLL_DEFAULT_THROUGHPUT 65535 /* backup tx cleanup if loop max reached */
132 #define NVREG_POLL_DEFAULT_CPU 13
133 NvRegMSIMap0
= 0x020,
134 NvRegMSIMap1
= 0x024,
135 NvRegMSIIrqMask
= 0x030,
136 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
138 #define NVREG_MISC1_PAUSE_TX 0x01
139 #define NVREG_MISC1_HD 0x02
140 #define NVREG_MISC1_FORCE 0x3b0f3c
142 NvRegMacReset
= 0x34,
143 #define NVREG_MAC_RESET_ASSERT 0x0F3
144 NvRegTransmitterControl
= 0x084,
145 #define NVREG_XMITCTL_START 0x01
146 #define NVREG_XMITCTL_MGMT_ST 0x40000000
147 #define NVREG_XMITCTL_SYNC_MASK 0x000f0000
148 #define NVREG_XMITCTL_SYNC_NOT_READY 0x0
149 #define NVREG_XMITCTL_SYNC_PHY_INIT 0x00040000
150 #define NVREG_XMITCTL_MGMT_SEMA_MASK 0x00000f00
151 #define NVREG_XMITCTL_MGMT_SEMA_FREE 0x0
152 #define NVREG_XMITCTL_HOST_SEMA_MASK 0x0000f000
153 #define NVREG_XMITCTL_HOST_SEMA_ACQ 0x0000f000
154 #define NVREG_XMITCTL_HOST_LOADED 0x00004000
155 #define NVREG_XMITCTL_TX_PATH_EN 0x01000000
156 #define NVREG_XMITCTL_DATA_START 0x00100000
157 #define NVREG_XMITCTL_DATA_READY 0x00010000
158 #define NVREG_XMITCTL_DATA_ERROR 0x00020000
159 NvRegTransmitterStatus
= 0x088,
160 #define NVREG_XMITSTAT_BUSY 0x01
162 NvRegPacketFilterFlags
= 0x8c,
163 #define NVREG_PFF_PAUSE_RX 0x08
164 #define NVREG_PFF_ALWAYS 0x7F0000
165 #define NVREG_PFF_PROMISC 0x80
166 #define NVREG_PFF_MYADDR 0x20
167 #define NVREG_PFF_LOOPBACK 0x10
169 NvRegOffloadConfig
= 0x90,
170 #define NVREG_OFFLOAD_HOMEPHY 0x601
171 #define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE
172 NvRegReceiverControl
= 0x094,
173 #define NVREG_RCVCTL_START 0x01
174 #define NVREG_RCVCTL_RX_PATH_EN 0x01000000
175 NvRegReceiverStatus
= 0x98,
176 #define NVREG_RCVSTAT_BUSY 0x01
178 NvRegSlotTime
= 0x9c,
179 #define NVREG_SLOTTIME_LEGBF_ENABLED 0x80000000
180 #define NVREG_SLOTTIME_10_100_FULL 0x00007f00
181 #define NVREG_SLOTTIME_1000_FULL 0x0003ff00
182 #define NVREG_SLOTTIME_HALF 0x0000ff00
183 #define NVREG_SLOTTIME_DEFAULT 0x00007f00
184 #define NVREG_SLOTTIME_MASK 0x000000ff
186 NvRegTxDeferral
= 0xA0,
187 #define NVREG_TX_DEFERRAL_DEFAULT 0x15050f
188 #define NVREG_TX_DEFERRAL_RGMII_10_100 0x16070f
189 #define NVREG_TX_DEFERRAL_RGMII_1000 0x14050f
190 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_10 0x16190f
191 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_100 0x16300f
192 #define NVREG_TX_DEFERRAL_MII_STRETCH 0x152000
193 NvRegRxDeferral
= 0xA4,
194 #define NVREG_RX_DEFERRAL_DEFAULT 0x16
195 NvRegMacAddrA
= 0xA8,
196 NvRegMacAddrB
= 0xAC,
197 NvRegMulticastAddrA
= 0xB0,
198 #define NVREG_MCASTADDRA_FORCE 0x01
199 NvRegMulticastAddrB
= 0xB4,
200 NvRegMulticastMaskA
= 0xB8,
201 #define NVREG_MCASTMASKA_NONE 0xffffffff
202 NvRegMulticastMaskB
= 0xBC,
203 #define NVREG_MCASTMASKB_NONE 0xffff
205 NvRegPhyInterface
= 0xC0,
206 #define PHY_RGMII 0x10000000
207 NvRegBackOffControl
= 0xC4,
208 #define NVREG_BKOFFCTRL_DEFAULT 0x70000000
209 #define NVREG_BKOFFCTRL_SEED_MASK 0x000003ff
210 #define NVREG_BKOFFCTRL_SELECT 24
211 #define NVREG_BKOFFCTRL_GEAR 12
213 NvRegTxRingPhysAddr
= 0x100,
214 NvRegRxRingPhysAddr
= 0x104,
215 NvRegRingSizes
= 0x108,
216 #define NVREG_RINGSZ_TXSHIFT 0
217 #define NVREG_RINGSZ_RXSHIFT 16
218 NvRegTransmitPoll
= 0x10c,
219 #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
220 NvRegLinkSpeed
= 0x110,
221 #define NVREG_LINKSPEED_FORCE 0x10000
222 #define NVREG_LINKSPEED_10 1000
223 #define NVREG_LINKSPEED_100 100
224 #define NVREG_LINKSPEED_1000 50
225 #define NVREG_LINKSPEED_MASK (0xFFF)
226 NvRegUnknownSetupReg5
= 0x130,
227 #define NVREG_UNKSETUP5_BIT31 (1<<31)
228 NvRegTxWatermark
= 0x13c,
229 #define NVREG_TX_WM_DESC1_DEFAULT 0x0200010
230 #define NVREG_TX_WM_DESC2_3_DEFAULT 0x1e08000
231 #define NVREG_TX_WM_DESC2_3_1000 0xfe08000
232 NvRegTxRxControl
= 0x144,
233 #define NVREG_TXRXCTL_KICK 0x0001
234 #define NVREG_TXRXCTL_BIT1 0x0002
235 #define NVREG_TXRXCTL_BIT2 0x0004
236 #define NVREG_TXRXCTL_IDLE 0x0008
237 #define NVREG_TXRXCTL_RESET 0x0010
238 #define NVREG_TXRXCTL_RXCHECK 0x0400
239 #define NVREG_TXRXCTL_DESC_1 0
240 #define NVREG_TXRXCTL_DESC_2 0x002100
241 #define NVREG_TXRXCTL_DESC_3 0xc02200
242 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
243 #define NVREG_TXRXCTL_VLANINS 0x00080
244 NvRegTxRingPhysAddrHigh
= 0x148,
245 NvRegRxRingPhysAddrHigh
= 0x14C,
246 NvRegTxPauseFrame
= 0x170,
247 #define NVREG_TX_PAUSEFRAME_DISABLE 0x0fff0080
248 #define NVREG_TX_PAUSEFRAME_ENABLE_V1 0x01800010
249 #define NVREG_TX_PAUSEFRAME_ENABLE_V2 0x056003f0
250 #define NVREG_TX_PAUSEFRAME_ENABLE_V3 0x09f00880
251 NvRegTxPauseFrameLimit
= 0x174,
252 #define NVREG_TX_PAUSEFRAMELIMIT_ENABLE 0x00010000
253 NvRegMIIStatus
= 0x180,
254 #define NVREG_MIISTAT_ERROR 0x0001
255 #define NVREG_MIISTAT_LINKCHANGE 0x0008
256 #define NVREG_MIISTAT_MASK_RW 0x0007
257 #define NVREG_MIISTAT_MASK_ALL 0x000f
258 NvRegMIIMask
= 0x184,
259 #define NVREG_MII_LINKCHANGE 0x0008
261 NvRegAdapterControl
= 0x188,
262 #define NVREG_ADAPTCTL_START 0x02
263 #define NVREG_ADAPTCTL_LINKUP 0x04
264 #define NVREG_ADAPTCTL_PHYVALID 0x40000
265 #define NVREG_ADAPTCTL_RUNNING 0x100000
266 #define NVREG_ADAPTCTL_PHYSHIFT 24
267 NvRegMIISpeed
= 0x18c,
268 #define NVREG_MIISPEED_BIT8 (1<<8)
269 #define NVREG_MIIDELAY 5
270 NvRegMIIControl
= 0x190,
271 #define NVREG_MIICTL_INUSE 0x08000
272 #define NVREG_MIICTL_WRITE 0x00400
273 #define NVREG_MIICTL_ADDRSHIFT 5
274 NvRegMIIData
= 0x194,
275 NvRegTxUnicast
= 0x1a0,
276 NvRegTxMulticast
= 0x1a4,
277 NvRegTxBroadcast
= 0x1a8,
278 NvRegWakeUpFlags
= 0x200,
279 #define NVREG_WAKEUPFLAGS_VAL 0x7770
280 #define NVREG_WAKEUPFLAGS_BUSYSHIFT 24
281 #define NVREG_WAKEUPFLAGS_ENABLESHIFT 16
282 #define NVREG_WAKEUPFLAGS_D3SHIFT 12
283 #define NVREG_WAKEUPFLAGS_D2SHIFT 8
284 #define NVREG_WAKEUPFLAGS_D1SHIFT 4
285 #define NVREG_WAKEUPFLAGS_D0SHIFT 0
286 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01
287 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02
288 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04
289 #define NVREG_WAKEUPFLAGS_ENABLE 0x1111
291 NvRegMgmtUnitGetVersion
= 0x204,
292 #define NVREG_MGMTUNITGETVERSION 0x01
293 NvRegMgmtUnitVersion
= 0x208,
294 #define NVREG_MGMTUNITVERSION 0x08
295 NvRegPowerCap
= 0x268,
296 #define NVREG_POWERCAP_D3SUPP (1<<30)
297 #define NVREG_POWERCAP_D2SUPP (1<<26)
298 #define NVREG_POWERCAP_D1SUPP (1<<25)
299 NvRegPowerState
= 0x26c,
300 #define NVREG_POWERSTATE_POWEREDUP 0x8000
301 #define NVREG_POWERSTATE_VALID 0x0100
302 #define NVREG_POWERSTATE_MASK 0x0003
303 #define NVREG_POWERSTATE_D0 0x0000
304 #define NVREG_POWERSTATE_D1 0x0001
305 #define NVREG_POWERSTATE_D2 0x0002
306 #define NVREG_POWERSTATE_D3 0x0003
307 NvRegMgmtUnitControl
= 0x278,
308 #define NVREG_MGMTUNITCONTROL_INUSE 0x20000
310 NvRegTxZeroReXmt
= 0x284,
311 NvRegTxOneReXmt
= 0x288,
312 NvRegTxManyReXmt
= 0x28c,
313 NvRegTxLateCol
= 0x290,
314 NvRegTxUnderflow
= 0x294,
315 NvRegTxLossCarrier
= 0x298,
316 NvRegTxExcessDef
= 0x29c,
317 NvRegTxRetryErr
= 0x2a0,
318 NvRegRxFrameErr
= 0x2a4,
319 NvRegRxExtraByte
= 0x2a8,
320 NvRegRxLateCol
= 0x2ac,
322 NvRegRxFrameTooLong
= 0x2b4,
323 NvRegRxOverflow
= 0x2b8,
324 NvRegRxFCSErr
= 0x2bc,
325 NvRegRxFrameAlignErr
= 0x2c0,
326 NvRegRxLenErr
= 0x2c4,
327 NvRegRxUnicast
= 0x2c8,
328 NvRegRxMulticast
= 0x2cc,
329 NvRegRxBroadcast
= 0x2d0,
331 NvRegTxFrame
= 0x2d8,
333 NvRegTxPause
= 0x2e0,
334 NvRegRxPause
= 0x2e4,
335 NvRegRxDropFrame
= 0x2e8,
336 NvRegVlanControl
= 0x300,
337 #define NVREG_VLANCONTROL_ENABLE 0x2000
338 NvRegMSIXMap0
= 0x3e0,
339 NvRegMSIXMap1
= 0x3e4,
340 NvRegMSIXIrqStatus
= 0x3f0,
342 NvRegPowerState2
= 0x600,
343 #define NVREG_POWERSTATE2_POWERUP_MASK 0x0F15
344 #define NVREG_POWERSTATE2_POWERUP_REV_A3 0x0001
345 #define NVREG_POWERSTATE2_PHY_RESET 0x0004
346 #define NVREG_POWERSTATE2_GATE_CLOCKS 0x0F00
349 /* Big endian: should work, but is untested */
355 struct ring_desc_ex
{
363 struct ring_desc
* orig
;
364 struct ring_desc_ex
* ex
;
367 #define FLAG_MASK_V1 0xffff0000
368 #define FLAG_MASK_V2 0xffffc000
369 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
370 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
372 #define NV_TX_LASTPACKET (1<<16)
373 #define NV_TX_RETRYERROR (1<<19)
374 #define NV_TX_RETRYCOUNT_MASK (0xF<<20)
375 #define NV_TX_FORCED_INTERRUPT (1<<24)
376 #define NV_TX_DEFERRED (1<<26)
377 #define NV_TX_CARRIERLOST (1<<27)
378 #define NV_TX_LATECOLLISION (1<<28)
379 #define NV_TX_UNDERFLOW (1<<29)
380 #define NV_TX_ERROR (1<<30)
381 #define NV_TX_VALID (1<<31)
383 #define NV_TX2_LASTPACKET (1<<29)
384 #define NV_TX2_RETRYERROR (1<<18)
385 #define NV_TX2_RETRYCOUNT_MASK (0xF<<19)
386 #define NV_TX2_FORCED_INTERRUPT (1<<30)
387 #define NV_TX2_DEFERRED (1<<25)
388 #define NV_TX2_CARRIERLOST (1<<26)
389 #define NV_TX2_LATECOLLISION (1<<27)
390 #define NV_TX2_UNDERFLOW (1<<28)
391 /* error and valid are the same for both */
392 #define NV_TX2_ERROR (1<<30)
393 #define NV_TX2_VALID (1<<31)
394 #define NV_TX2_TSO (1<<28)
395 #define NV_TX2_TSO_SHIFT 14
396 #define NV_TX2_TSO_MAX_SHIFT 14
397 #define NV_TX2_TSO_MAX_SIZE (1<<NV_TX2_TSO_MAX_SHIFT)
398 #define NV_TX2_CHECKSUM_L3 (1<<27)
399 #define NV_TX2_CHECKSUM_L4 (1<<26)
401 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
403 #define NV_RX_DESCRIPTORVALID (1<<16)
404 #define NV_RX_MISSEDFRAME (1<<17)
405 #define NV_RX_SUBSTRACT1 (1<<18)
406 #define NV_RX_ERROR1 (1<<23)
407 #define NV_RX_ERROR2 (1<<24)
408 #define NV_RX_ERROR3 (1<<25)
409 #define NV_RX_ERROR4 (1<<26)
410 #define NV_RX_CRCERR (1<<27)
411 #define NV_RX_OVERFLOW (1<<28)
412 #define NV_RX_FRAMINGERR (1<<29)
413 #define NV_RX_ERROR (1<<30)
414 #define NV_RX_AVAIL (1<<31)
415 #define NV_RX_ERROR_MASK (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3|NV_RX_ERROR4|NV_RX_CRCERR|NV_RX_OVERFLOW|NV_RX_FRAMINGERR)
417 #define NV_RX2_CHECKSUMMASK (0x1C000000)
418 #define NV_RX2_CHECKSUM_IP (0x10000000)
419 #define NV_RX2_CHECKSUM_IP_TCP (0x14000000)
420 #define NV_RX2_CHECKSUM_IP_UDP (0x18000000)
421 #define NV_RX2_DESCRIPTORVALID (1<<29)
422 #define NV_RX2_SUBSTRACT1 (1<<25)
423 #define NV_RX2_ERROR1 (1<<18)
424 #define NV_RX2_ERROR2 (1<<19)
425 #define NV_RX2_ERROR3 (1<<20)
426 #define NV_RX2_ERROR4 (1<<21)
427 #define NV_RX2_CRCERR (1<<22)
428 #define NV_RX2_OVERFLOW (1<<23)
429 #define NV_RX2_FRAMINGERR (1<<24)
430 /* error and avail are the same for both */
431 #define NV_RX2_ERROR (1<<30)
432 #define NV_RX2_AVAIL (1<<31)
433 #define NV_RX2_ERROR_MASK (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3|NV_RX2_ERROR4|NV_RX2_CRCERR|NV_RX2_OVERFLOW|NV_RX2_FRAMINGERR)
435 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
436 #define NV_RX3_VLAN_TAG_MASK (0x0000FFFF)
438 /* Miscelaneous hardware related defines: */
439 #define NV_PCI_REGSZ_VER1 0x270
440 #define NV_PCI_REGSZ_VER2 0x2d4
441 #define NV_PCI_REGSZ_VER3 0x604
442 #define NV_PCI_REGSZ_MAX 0x604
444 /* various timeout delays: all in usec */
445 #define NV_TXRX_RESET_DELAY 4
446 #define NV_TXSTOP_DELAY1 10
447 #define NV_TXSTOP_DELAY1MAX 500000
448 #define NV_TXSTOP_DELAY2 100
449 #define NV_RXSTOP_DELAY1 10
450 #define NV_RXSTOP_DELAY1MAX 500000
451 #define NV_RXSTOP_DELAY2 100
452 #define NV_SETUP5_DELAY 5
453 #define NV_SETUP5_DELAYMAX 50000
454 #define NV_POWERUP_DELAY 5
455 #define NV_POWERUP_DELAYMAX 5000
456 #define NV_MIIBUSY_DELAY 50
457 #define NV_MIIPHY_DELAY 10
458 #define NV_MIIPHY_DELAYMAX 10000
459 #define NV_MAC_RESET_DELAY 64
461 #define NV_WAKEUPPATTERNS 5
462 #define NV_WAKEUPMASKENTRIES 4
464 /* General driver defaults */
465 #define NV_WATCHDOG_TIMEO (5*HZ)
467 #define RX_RING_DEFAULT 512
468 #define TX_RING_DEFAULT 256
469 #define RX_RING_MIN 128
470 #define TX_RING_MIN 64
471 #define RING_MAX_DESC_VER_1 1024
472 #define RING_MAX_DESC_VER_2_3 16384
474 /* rx/tx mac addr + type + vlan + align + slack*/
475 #define NV_RX_HEADERS (64)
476 /* even more slack. */
477 #define NV_RX_ALLOC_PAD (64)
479 /* maximum mtu size */
480 #define NV_PKTLIMIT_1 ETH_DATA_LEN /* hard limit not known */
481 #define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia: 9202 */
483 #define OOM_REFILL (1+HZ/20)
484 #define POLL_WAIT (1+HZ/100)
485 #define LINK_TIMEOUT (3*HZ)
486 #define STATS_INTERVAL (10*HZ)
490 * The nic supports three different descriptor types:
491 * - DESC_VER_1: Original
492 * - DESC_VER_2: support for jumbo frames.
493 * - DESC_VER_3: 64-bit format.
500 #define PHY_OUI_MARVELL 0x5043
501 #define PHY_OUI_CICADA 0x03f1
502 #define PHY_OUI_VITESSE 0x01c1
503 #define PHY_OUI_REALTEK 0x0732
504 #define PHY_OUI_REALTEK2 0x0020
505 #define PHYID1_OUI_MASK 0x03ff
506 #define PHYID1_OUI_SHFT 6
507 #define PHYID2_OUI_MASK 0xfc00
508 #define PHYID2_OUI_SHFT 10
509 #define PHYID2_MODEL_MASK 0x03f0
510 #define PHY_MODEL_REALTEK_8211 0x0110
511 #define PHY_REV_MASK 0x0001
512 #define PHY_REV_REALTEK_8211B 0x0000
513 #define PHY_REV_REALTEK_8211C 0x0001
514 #define PHY_MODEL_REALTEK_8201 0x0200
515 #define PHY_MODEL_MARVELL_E3016 0x0220
516 #define PHY_MARVELL_E3016_INITMASK 0x0300
517 #define PHY_CICADA_INIT1 0x0f000
518 #define PHY_CICADA_INIT2 0x0e00
519 #define PHY_CICADA_INIT3 0x01000
520 #define PHY_CICADA_INIT4 0x0200
521 #define PHY_CICADA_INIT5 0x0004
522 #define PHY_CICADA_INIT6 0x02000
523 #define PHY_VITESSE_INIT_REG1 0x1f
524 #define PHY_VITESSE_INIT_REG2 0x10
525 #define PHY_VITESSE_INIT_REG3 0x11
526 #define PHY_VITESSE_INIT_REG4 0x12
527 #define PHY_VITESSE_INIT_MSK1 0xc
528 #define PHY_VITESSE_INIT_MSK2 0x0180
529 #define PHY_VITESSE_INIT1 0x52b5
530 #define PHY_VITESSE_INIT2 0xaf8a
531 #define PHY_VITESSE_INIT3 0x8
532 #define PHY_VITESSE_INIT4 0x8f8a
533 #define PHY_VITESSE_INIT5 0xaf86
534 #define PHY_VITESSE_INIT6 0x8f86
535 #define PHY_VITESSE_INIT7 0xaf82
536 #define PHY_VITESSE_INIT8 0x0100
537 #define PHY_VITESSE_INIT9 0x8f82
538 #define PHY_VITESSE_INIT10 0x0
539 #define PHY_REALTEK_INIT_REG1 0x1f
540 #define PHY_REALTEK_INIT_REG2 0x19
541 #define PHY_REALTEK_INIT_REG3 0x13
542 #define PHY_REALTEK_INIT_REG4 0x14
543 #define PHY_REALTEK_INIT_REG5 0x18
544 #define PHY_REALTEK_INIT_REG6 0x11
545 #define PHY_REALTEK_INIT_REG7 0x01
546 #define PHY_REALTEK_INIT1 0x0000
547 #define PHY_REALTEK_INIT2 0x8e00
548 #define PHY_REALTEK_INIT3 0x0001
549 #define PHY_REALTEK_INIT4 0xad17
550 #define PHY_REALTEK_INIT5 0xfb54
551 #define PHY_REALTEK_INIT6 0xf5c7
552 #define PHY_REALTEK_INIT7 0x1000
553 #define PHY_REALTEK_INIT8 0x0003
554 #define PHY_REALTEK_INIT9 0x0008
555 #define PHY_REALTEK_INIT10 0x0005
556 #define PHY_REALTEK_INIT11 0x0200
557 #define PHY_REALTEK_INIT_MSK1 0x0003
559 #define PHY_GIGABIT 0x0100
561 #define PHY_TIMEOUT 0x1
562 #define PHY_ERROR 0x2
566 #define PHY_HALF 0x100
568 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
569 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
570 #define NV_PAUSEFRAME_RX_ENABLE 0x0004
571 #define NV_PAUSEFRAME_TX_ENABLE 0x0008
572 #define NV_PAUSEFRAME_RX_REQ 0x0010
573 #define NV_PAUSEFRAME_TX_REQ 0x0020
574 #define NV_PAUSEFRAME_AUTONEG 0x0040
576 /* MSI/MSI-X defines */
577 #define NV_MSI_X_MAX_VECTORS 8
578 #define NV_MSI_X_VECTORS_MASK 0x000f
579 #define NV_MSI_CAPABLE 0x0010
580 #define NV_MSI_X_CAPABLE 0x0020
581 #define NV_MSI_ENABLED 0x0040
582 #define NV_MSI_X_ENABLED 0x0080
584 #define NV_MSI_X_VECTOR_ALL 0x0
585 #define NV_MSI_X_VECTOR_RX 0x0
586 #define NV_MSI_X_VECTOR_TX 0x1
587 #define NV_MSI_X_VECTOR_OTHER 0x2
589 #define NV_MSI_PRIV_OFFSET 0x68
590 #define NV_MSI_PRIV_VALUE 0xffffffff
592 #define NV_RESTART_TX 0x1
593 #define NV_RESTART_RX 0x2
595 #define NV_TX_LIMIT_COUNT 16
597 #define NV_DYNAMIC_THRESHOLD 4
598 #define NV_DYNAMIC_MAX_QUIET_COUNT 2048
601 struct nv_ethtool_str
{
602 char name
[ETH_GSTRING_LEN
];
605 static const struct nv_ethtool_str nv_estats_str
[] = {
610 { "tx_late_collision" },
611 { "tx_fifo_errors" },
612 { "tx_carrier_errors" },
613 { "tx_excess_deferral" },
614 { "tx_retry_error" },
615 { "rx_frame_error" },
617 { "rx_late_collision" },
619 { "rx_frame_too_long" },
620 { "rx_over_errors" },
622 { "rx_frame_align_error" },
623 { "rx_length_error" },
628 { "rx_errors_total" },
629 { "tx_errors_total" },
631 /* version 2 stats */
639 /* version 3 stats */
645 struct nv_ethtool_stats
{
650 u64 tx_late_collision
;
652 u64 tx_carrier_errors
;
653 u64 tx_excess_deferral
;
657 u64 rx_late_collision
;
659 u64 rx_frame_too_long
;
662 u64 rx_frame_align_error
;
671 /* version 2 stats */
679 /* version 3 stats */
685 #define NV_DEV_STATISTICS_V3_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64))
686 #define NV_DEV_STATISTICS_V2_COUNT (NV_DEV_STATISTICS_V3_COUNT - 3)
687 #define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6)
690 #define NV_TEST_COUNT_BASE 3
691 #define NV_TEST_COUNT_EXTENDED 4
693 static const struct nv_ethtool_str nv_etests_str
[] = {
694 { "link (online/offline)" },
695 { "register (offline) " },
696 { "interrupt (offline) " },
697 { "loopback (offline) " }
700 struct register_test
{
705 static const struct register_test nv_registers_test
[] = {
706 { NvRegUnknownSetupReg6
, 0x01 },
707 { NvRegMisc1
, 0x03c },
708 { NvRegOffloadConfig
, 0x03ff },
709 { NvRegMulticastAddrA
, 0xffffffff },
710 { NvRegTxWatermark
, 0x0ff },
711 { NvRegWakeUpFlags
, 0x07777 },
718 unsigned int dma_len
;
719 struct ring_desc_ex
*first_tx_desc
;
720 struct nv_skb_map
*next_tx_ctx
;
725 * All hardware access under netdev_priv(dev)->lock, except the performance
727 * - rx is (pseudo-) lockless: it relies on the single-threading provided
728 * by the arch code for interrupts.
729 * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
730 * needs netdev_priv(dev)->lock :-(
731 * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
734 /* in dev: base, irq */
738 struct net_device
*dev
;
739 struct napi_struct napi
;
742 * Locking: spin_lock(&np->lock); */
743 struct nv_ethtool_stats estats
;
751 unsigned int phy_oui
;
752 unsigned int phy_model
;
753 unsigned int phy_rev
;
759 /* General data: RO fields */
760 dma_addr_t ring_addr
;
761 struct pci_dev
*pci_dev
;
778 /* rx specific fields.
779 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
781 union ring_type get_rx
, put_rx
, first_rx
, last_rx
;
782 struct nv_skb_map
*get_rx_ctx
, *put_rx_ctx
;
783 struct nv_skb_map
*first_rx_ctx
, *last_rx_ctx
;
784 struct nv_skb_map
*rx_skb
;
786 union ring_type rx_ring
;
787 unsigned int rx_buf_sz
;
788 unsigned int pkt_limit
;
789 struct timer_list oom_kick
;
790 struct timer_list nic_poll
;
791 struct timer_list stats_poll
;
795 /* media detection workaround.
796 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
799 unsigned long link_timeout
;
801 * tx specific fields.
803 union ring_type get_tx
, put_tx
, first_tx
, last_tx
;
804 struct nv_skb_map
*get_tx_ctx
, *put_tx_ctx
;
805 struct nv_skb_map
*first_tx_ctx
, *last_tx_ctx
;
806 struct nv_skb_map
*tx_skb
;
808 union ring_type tx_ring
;
812 u32 tx_pkts_in_progress
;
813 struct nv_skb_map
*tx_change_owner
;
814 struct nv_skb_map
*tx_end_flip
;
818 struct vlan_group
*vlangrp
;
820 /* msi/msi-x fields */
822 struct msix_entry msi_x_entry
[NV_MSI_X_MAX_VECTORS
];
827 /* power saved state */
828 u32 saved_config_space
[NV_PCI_REGSZ_MAX
/4];
830 /* for different msi-x irq type */
831 char name_rx
[IFNAMSIZ
+ 3]; /* -rx */
832 char name_tx
[IFNAMSIZ
+ 3]; /* -tx */
833 char name_other
[IFNAMSIZ
+ 6]; /* -other */
837 * Maximum number of loops until we assume that a bit in the irq mask
838 * is stuck. Overridable with module param.
840 static int max_interrupt_work
= 4;
843 * Optimization can be either throuput mode or cpu mode
845 * Throughput Mode: Every tx and rx packet will generate an interrupt.
846 * CPU Mode: Interrupts are controlled by a timer.
849 NV_OPTIMIZATION_MODE_THROUGHPUT
,
850 NV_OPTIMIZATION_MODE_CPU
,
851 NV_OPTIMIZATION_MODE_DYNAMIC
853 static int optimization_mode
= NV_OPTIMIZATION_MODE_DYNAMIC
;
856 * Poll interval for timer irq
858 * This interval determines how frequent an interrupt is generated.
859 * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
860 * Min = 0, and Max = 65535
862 static int poll_interval
= -1;
871 static int msi
= NV_MSI_INT_ENABLED
;
877 NV_MSIX_INT_DISABLED
,
880 static int msix
= NV_MSIX_INT_ENABLED
;
886 NV_DMA_64BIT_DISABLED
,
889 static int dma_64bit
= NV_DMA_64BIT_ENABLED
;
892 * Crossover Detection
893 * Realtek 8201 phy + some OEM boards do not work properly.
896 NV_CROSSOVER_DETECTION_DISABLED
,
897 NV_CROSSOVER_DETECTION_ENABLED
899 static int phy_cross
= NV_CROSSOVER_DETECTION_DISABLED
;
902 * Power down phy when interface is down (persists through reboot;
903 * older Linux and other OSes may not power it up again)
905 static int phy_power_down
= 0;
907 static inline struct fe_priv
*get_nvpriv(struct net_device
*dev
)
909 return netdev_priv(dev
);
912 static inline u8 __iomem
*get_hwbase(struct net_device
*dev
)
914 return ((struct fe_priv
*)netdev_priv(dev
))->base
;
917 static inline void pci_push(u8 __iomem
*base
)
919 /* force out pending posted writes */
923 static inline u32
nv_descr_getlength(struct ring_desc
*prd
, u32 v
)
925 return le32_to_cpu(prd
->flaglen
)
926 & ((v
== DESC_VER_1
) ? LEN_MASK_V1
: LEN_MASK_V2
);
929 static inline u32
nv_descr_getlength_ex(struct ring_desc_ex
*prd
, u32 v
)
931 return le32_to_cpu(prd
->flaglen
) & LEN_MASK_V2
;
934 static bool nv_optimized(struct fe_priv
*np
)
936 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
)
941 static int reg_delay(struct net_device
*dev
, int offset
, u32 mask
, u32 target
,
942 int delay
, int delaymax
, const char *msg
)
944 u8 __iomem
*base
= get_hwbase(dev
);
955 } while ((readl(base
+ offset
) & mask
) != target
);
959 #define NV_SETUP_RX_RING 0x01
960 #define NV_SETUP_TX_RING 0x02
962 static inline u32
dma_low(dma_addr_t addr
)
967 static inline u32
dma_high(dma_addr_t addr
)
969 return addr
>>31>>1; /* 0 if 32bit, shift down by 32 if 64bit */
972 static void setup_hw_rings(struct net_device
*dev
, int rxtx_flags
)
974 struct fe_priv
*np
= get_nvpriv(dev
);
975 u8 __iomem
*base
= get_hwbase(dev
);
977 if (!nv_optimized(np
)) {
978 if (rxtx_flags
& NV_SETUP_RX_RING
) {
979 writel(dma_low(np
->ring_addr
), base
+ NvRegRxRingPhysAddr
);
981 if (rxtx_flags
& NV_SETUP_TX_RING
) {
982 writel(dma_low(np
->ring_addr
+ np
->rx_ring_size
*sizeof(struct ring_desc
)), base
+ NvRegTxRingPhysAddr
);
985 if (rxtx_flags
& NV_SETUP_RX_RING
) {
986 writel(dma_low(np
->ring_addr
), base
+ NvRegRxRingPhysAddr
);
987 writel(dma_high(np
->ring_addr
), base
+ NvRegRxRingPhysAddrHigh
);
989 if (rxtx_flags
& NV_SETUP_TX_RING
) {
990 writel(dma_low(np
->ring_addr
+ np
->rx_ring_size
*sizeof(struct ring_desc_ex
)), base
+ NvRegTxRingPhysAddr
);
991 writel(dma_high(np
->ring_addr
+ np
->rx_ring_size
*sizeof(struct ring_desc_ex
)), base
+ NvRegTxRingPhysAddrHigh
);
996 static void free_rings(struct net_device
*dev
)
998 struct fe_priv
*np
= get_nvpriv(dev
);
1000 if (!nv_optimized(np
)) {
1001 if (np
->rx_ring
.orig
)
1002 pci_free_consistent(np
->pci_dev
, sizeof(struct ring_desc
) * (np
->rx_ring_size
+ np
->tx_ring_size
),
1003 np
->rx_ring
.orig
, np
->ring_addr
);
1006 pci_free_consistent(np
->pci_dev
, sizeof(struct ring_desc_ex
) * (np
->rx_ring_size
+ np
->tx_ring_size
),
1007 np
->rx_ring
.ex
, np
->ring_addr
);
1015 static int using_multi_irqs(struct net_device
*dev
)
1017 struct fe_priv
*np
= get_nvpriv(dev
);
1019 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
) ||
1020 ((np
->msi_flags
& NV_MSI_X_ENABLED
) &&
1021 ((np
->msi_flags
& NV_MSI_X_VECTORS_MASK
) == 0x1)))
1027 static void nv_txrx_gate(struct net_device
*dev
, bool gate
)
1029 struct fe_priv
*np
= get_nvpriv(dev
);
1030 u8 __iomem
*base
= get_hwbase(dev
);
1033 if (!np
->mac_in_use
&&
1034 (np
->driver_data
& DEV_HAS_POWER_CNTRL
)) {
1035 powerstate
= readl(base
+ NvRegPowerState2
);
1037 powerstate
|= NVREG_POWERSTATE2_GATE_CLOCKS
;
1039 powerstate
&= ~NVREG_POWERSTATE2_GATE_CLOCKS
;
1040 writel(powerstate
, base
+ NvRegPowerState2
);
1044 static void nv_enable_irq(struct net_device
*dev
)
1046 struct fe_priv
*np
= get_nvpriv(dev
);
1048 if (!using_multi_irqs(dev
)) {
1049 if (np
->msi_flags
& NV_MSI_X_ENABLED
)
1050 enable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_ALL
].vector
);
1052 enable_irq(np
->pci_dev
->irq
);
1054 enable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
);
1055 enable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_TX
].vector
);
1056 enable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_OTHER
].vector
);
1060 static void nv_disable_irq(struct net_device
*dev
)
1062 struct fe_priv
*np
= get_nvpriv(dev
);
1064 if (!using_multi_irqs(dev
)) {
1065 if (np
->msi_flags
& NV_MSI_X_ENABLED
)
1066 disable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_ALL
].vector
);
1068 disable_irq(np
->pci_dev
->irq
);
1070 disable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
);
1071 disable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_TX
].vector
);
1072 disable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_OTHER
].vector
);
1076 /* In MSIX mode, a write to irqmask behaves as XOR */
1077 static void nv_enable_hw_interrupts(struct net_device
*dev
, u32 mask
)
1079 u8 __iomem
*base
= get_hwbase(dev
);
1081 writel(mask
, base
+ NvRegIrqMask
);
1084 static void nv_disable_hw_interrupts(struct net_device
*dev
, u32 mask
)
1086 struct fe_priv
*np
= get_nvpriv(dev
);
1087 u8 __iomem
*base
= get_hwbase(dev
);
1089 if (np
->msi_flags
& NV_MSI_X_ENABLED
) {
1090 writel(mask
, base
+ NvRegIrqMask
);
1092 if (np
->msi_flags
& NV_MSI_ENABLED
)
1093 writel(0, base
+ NvRegMSIIrqMask
);
1094 writel(0, base
+ NvRegIrqMask
);
1098 static void nv_napi_enable(struct net_device
*dev
)
1100 #ifdef CONFIG_FORCEDETH_NAPI
1101 struct fe_priv
*np
= get_nvpriv(dev
);
1103 napi_enable(&np
->napi
);
1107 static void nv_napi_disable(struct net_device
*dev
)
1109 #ifdef CONFIG_FORCEDETH_NAPI
1110 struct fe_priv
*np
= get_nvpriv(dev
);
1112 napi_disable(&np
->napi
);
1116 #define MII_READ (-1)
1117 /* mii_rw: read/write a register on the PHY.
1119 * Caller must guarantee serialization
1121 static int mii_rw(struct net_device
*dev
, int addr
, int miireg
, int value
)
1123 u8 __iomem
*base
= get_hwbase(dev
);
1127 writel(NVREG_MIISTAT_MASK_RW
, base
+ NvRegMIIStatus
);
1129 reg
= readl(base
+ NvRegMIIControl
);
1130 if (reg
& NVREG_MIICTL_INUSE
) {
1131 writel(NVREG_MIICTL_INUSE
, base
+ NvRegMIIControl
);
1132 udelay(NV_MIIBUSY_DELAY
);
1135 reg
= (addr
<< NVREG_MIICTL_ADDRSHIFT
) | miireg
;
1136 if (value
!= MII_READ
) {
1137 writel(value
, base
+ NvRegMIIData
);
1138 reg
|= NVREG_MIICTL_WRITE
;
1140 writel(reg
, base
+ NvRegMIIControl
);
1142 if (reg_delay(dev
, NvRegMIIControl
, NVREG_MIICTL_INUSE
, 0,
1143 NV_MIIPHY_DELAY
, NV_MIIPHY_DELAYMAX
, NULL
)) {
1144 dprintk(KERN_DEBUG
"%s: mii_rw of reg %d at PHY %d timed out.\n",
1145 dev
->name
, miireg
, addr
);
1147 } else if (value
!= MII_READ
) {
1148 /* it was a write operation - fewer failures are detectable */
1149 dprintk(KERN_DEBUG
"%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
1150 dev
->name
, value
, miireg
, addr
);
1152 } else if (readl(base
+ NvRegMIIStatus
) & NVREG_MIISTAT_ERROR
) {
1153 dprintk(KERN_DEBUG
"%s: mii_rw of reg %d at PHY %d failed.\n",
1154 dev
->name
, miireg
, addr
);
1157 retval
= readl(base
+ NvRegMIIData
);
1158 dprintk(KERN_DEBUG
"%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
1159 dev
->name
, miireg
, addr
, retval
);
1165 static int phy_reset(struct net_device
*dev
, u32 bmcr_setup
)
1167 struct fe_priv
*np
= netdev_priv(dev
);
1169 unsigned int tries
= 0;
1171 miicontrol
= BMCR_RESET
| bmcr_setup
;
1172 if (mii_rw(dev
, np
->phyaddr
, MII_BMCR
, miicontrol
)) {
1176 /* wait for 500ms */
1179 /* must wait till reset is deasserted */
1180 while (miicontrol
& BMCR_RESET
) {
1182 miicontrol
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
1183 /* FIXME: 100 tries seem excessive */
1190 static int phy_init(struct net_device
*dev
)
1192 struct fe_priv
*np
= get_nvpriv(dev
);
1193 u8 __iomem
*base
= get_hwbase(dev
);
1194 u32 phyinterface
, phy_reserved
, mii_status
, mii_control
, mii_control_1000
,reg
;
1196 /* phy errata for E3016 phy */
1197 if (np
->phy_model
== PHY_MODEL_MARVELL_E3016
) {
1198 reg
= mii_rw(dev
, np
->phyaddr
, MII_NCONFIG
, MII_READ
);
1199 reg
&= ~PHY_MARVELL_E3016_INITMASK
;
1200 if (mii_rw(dev
, np
->phyaddr
, MII_NCONFIG
, reg
)) {
1201 printk(KERN_INFO
"%s: phy write to errata reg failed.\n", pci_name(np
->pci_dev
));
1205 if (np
->phy_oui
== PHY_OUI_REALTEK
) {
1206 if (np
->phy_model
== PHY_MODEL_REALTEK_8211
&&
1207 np
->phy_rev
== PHY_REV_REALTEK_8211B
) {
1208 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG1
, PHY_REALTEK_INIT1
)) {
1209 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1212 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG2
, PHY_REALTEK_INIT2
)) {
1213 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1216 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG1
, PHY_REALTEK_INIT3
)) {
1217 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1220 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG3
, PHY_REALTEK_INIT4
)) {
1221 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1224 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG4
, PHY_REALTEK_INIT5
)) {
1225 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1228 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG5
, PHY_REALTEK_INIT6
)) {
1229 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1232 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG1
, PHY_REALTEK_INIT1
)) {
1233 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1237 if (np
->phy_model
== PHY_MODEL_REALTEK_8211
&&
1238 np
->phy_rev
== PHY_REV_REALTEK_8211C
) {
1239 u32 powerstate
= readl(base
+ NvRegPowerState2
);
1241 /* need to perform hw phy reset */
1242 powerstate
|= NVREG_POWERSTATE2_PHY_RESET
;
1243 writel(powerstate
, base
+ NvRegPowerState2
);
1246 powerstate
&= ~NVREG_POWERSTATE2_PHY_RESET
;
1247 writel(powerstate
, base
+ NvRegPowerState2
);
1250 reg
= mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG6
, MII_READ
);
1251 reg
|= PHY_REALTEK_INIT9
;
1252 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG6
, reg
)) {
1253 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1256 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG1
, PHY_REALTEK_INIT10
)) {
1257 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1260 reg
= mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG7
, MII_READ
);
1261 if (!(reg
& PHY_REALTEK_INIT11
)) {
1262 reg
|= PHY_REALTEK_INIT11
;
1263 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG7
, reg
)) {
1264 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1268 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG1
, PHY_REALTEK_INIT1
)) {
1269 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1273 if (np
->phy_model
== PHY_MODEL_REALTEK_8201
) {
1274 if (np
->device_id
== PCI_DEVICE_ID_NVIDIA_NVENET_32
||
1275 np
->device_id
== PCI_DEVICE_ID_NVIDIA_NVENET_33
||
1276 np
->device_id
== PCI_DEVICE_ID_NVIDIA_NVENET_34
||
1277 np
->device_id
== PCI_DEVICE_ID_NVIDIA_NVENET_35
||
1278 np
->device_id
== PCI_DEVICE_ID_NVIDIA_NVENET_36
||
1279 np
->device_id
== PCI_DEVICE_ID_NVIDIA_NVENET_37
||
1280 np
->device_id
== PCI_DEVICE_ID_NVIDIA_NVENET_38
||
1281 np
->device_id
== PCI_DEVICE_ID_NVIDIA_NVENET_39
) {
1282 phy_reserved
= mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG6
, MII_READ
);
1283 phy_reserved
|= PHY_REALTEK_INIT7
;
1284 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG6
, phy_reserved
)) {
1285 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1292 /* set advertise register */
1293 reg
= mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, MII_READ
);
1294 reg
|= (ADVERTISE_10HALF
|ADVERTISE_10FULL
|ADVERTISE_100HALF
|ADVERTISE_100FULL
|ADVERTISE_PAUSE_ASYM
|ADVERTISE_PAUSE_CAP
);
1295 if (mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, reg
)) {
1296 printk(KERN_INFO
"%s: phy write to advertise failed.\n", pci_name(np
->pci_dev
));
1300 /* get phy interface type */
1301 phyinterface
= readl(base
+ NvRegPhyInterface
);
1303 /* see if gigabit phy */
1304 mii_status
= mii_rw(dev
, np
->phyaddr
, MII_BMSR
, MII_READ
);
1305 if (mii_status
& PHY_GIGABIT
) {
1306 np
->gigabit
= PHY_GIGABIT
;
1307 mii_control_1000
= mii_rw(dev
, np
->phyaddr
, MII_CTRL1000
, MII_READ
);
1308 mii_control_1000
&= ~ADVERTISE_1000HALF
;
1309 if (phyinterface
& PHY_RGMII
)
1310 mii_control_1000
|= ADVERTISE_1000FULL
;
1312 mii_control_1000
&= ~ADVERTISE_1000FULL
;
1314 if (mii_rw(dev
, np
->phyaddr
, MII_CTRL1000
, mii_control_1000
)) {
1315 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1322 mii_control
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
1323 mii_control
|= BMCR_ANENABLE
;
1325 if (np
->phy_oui
== PHY_OUI_REALTEK
&&
1326 np
->phy_model
== PHY_MODEL_REALTEK_8211
&&
1327 np
->phy_rev
== PHY_REV_REALTEK_8211C
) {
1328 /* start autoneg since we already performed hw reset above */
1329 mii_control
|= BMCR_ANRESTART
;
1330 if (mii_rw(dev
, np
->phyaddr
, MII_BMCR
, mii_control
)) {
1331 printk(KERN_INFO
"%s: phy init failed\n", pci_name(np
->pci_dev
));
1336 * (certain phys need bmcr to be setup with reset)
1338 if (phy_reset(dev
, mii_control
)) {
1339 printk(KERN_INFO
"%s: phy reset failed\n", pci_name(np
->pci_dev
));
1344 /* phy vendor specific configuration */
1345 if ((np
->phy_oui
== PHY_OUI_CICADA
) && (phyinterface
& PHY_RGMII
) ) {
1346 phy_reserved
= mii_rw(dev
, np
->phyaddr
, MII_RESV1
, MII_READ
);
1347 phy_reserved
&= ~(PHY_CICADA_INIT1
| PHY_CICADA_INIT2
);
1348 phy_reserved
|= (PHY_CICADA_INIT3
| PHY_CICADA_INIT4
);
1349 if (mii_rw(dev
, np
->phyaddr
, MII_RESV1
, phy_reserved
)) {
1350 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1353 phy_reserved
= mii_rw(dev
, np
->phyaddr
, MII_NCONFIG
, MII_READ
);
1354 phy_reserved
|= PHY_CICADA_INIT5
;
1355 if (mii_rw(dev
, np
->phyaddr
, MII_NCONFIG
, phy_reserved
)) {
1356 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1360 if (np
->phy_oui
== PHY_OUI_CICADA
) {
1361 phy_reserved
= mii_rw(dev
, np
->phyaddr
, MII_SREVISION
, MII_READ
);
1362 phy_reserved
|= PHY_CICADA_INIT6
;
1363 if (mii_rw(dev
, np
->phyaddr
, MII_SREVISION
, phy_reserved
)) {
1364 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1368 if (np
->phy_oui
== PHY_OUI_VITESSE
) {
1369 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG1
, PHY_VITESSE_INIT1
)) {
1370 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1373 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG2
, PHY_VITESSE_INIT2
)) {
1374 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1377 phy_reserved
= mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG4
, MII_READ
);
1378 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG4
, phy_reserved
)) {
1379 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1382 phy_reserved
= mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG3
, MII_READ
);
1383 phy_reserved
&= ~PHY_VITESSE_INIT_MSK1
;
1384 phy_reserved
|= PHY_VITESSE_INIT3
;
1385 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG3
, phy_reserved
)) {
1386 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1389 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG2
, PHY_VITESSE_INIT4
)) {
1390 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1393 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG2
, PHY_VITESSE_INIT5
)) {
1394 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1397 phy_reserved
= mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG4
, MII_READ
);
1398 phy_reserved
&= ~PHY_VITESSE_INIT_MSK1
;
1399 phy_reserved
|= PHY_VITESSE_INIT3
;
1400 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG4
, phy_reserved
)) {
1401 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1404 phy_reserved
= mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG3
, MII_READ
);
1405 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG3
, phy_reserved
)) {
1406 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1409 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG2
, PHY_VITESSE_INIT6
)) {
1410 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1413 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG2
, PHY_VITESSE_INIT7
)) {
1414 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1417 phy_reserved
= mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG4
, MII_READ
);
1418 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG4
, phy_reserved
)) {
1419 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1422 phy_reserved
= mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG3
, MII_READ
);
1423 phy_reserved
&= ~PHY_VITESSE_INIT_MSK2
;
1424 phy_reserved
|= PHY_VITESSE_INIT8
;
1425 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG3
, phy_reserved
)) {
1426 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1429 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG2
, PHY_VITESSE_INIT9
)) {
1430 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1433 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG1
, PHY_VITESSE_INIT10
)) {
1434 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1438 if (np
->phy_oui
== PHY_OUI_REALTEK
) {
1439 if (np
->phy_model
== PHY_MODEL_REALTEK_8211
&&
1440 np
->phy_rev
== PHY_REV_REALTEK_8211B
) {
1441 /* reset could have cleared these out, set them back */
1442 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG1
, PHY_REALTEK_INIT1
)) {
1443 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1446 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG2
, PHY_REALTEK_INIT2
)) {
1447 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1450 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG1
, PHY_REALTEK_INIT3
)) {
1451 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1454 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG3
, PHY_REALTEK_INIT4
)) {
1455 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1458 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG4
, PHY_REALTEK_INIT5
)) {
1459 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1462 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG5
, PHY_REALTEK_INIT6
)) {
1463 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1466 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG1
, PHY_REALTEK_INIT1
)) {
1467 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1471 if (np
->phy_model
== PHY_MODEL_REALTEK_8201
) {
1472 if (np
->device_id
== PCI_DEVICE_ID_NVIDIA_NVENET_32
||
1473 np
->device_id
== PCI_DEVICE_ID_NVIDIA_NVENET_33
||
1474 np
->device_id
== PCI_DEVICE_ID_NVIDIA_NVENET_34
||
1475 np
->device_id
== PCI_DEVICE_ID_NVIDIA_NVENET_35
||
1476 np
->device_id
== PCI_DEVICE_ID_NVIDIA_NVENET_36
||
1477 np
->device_id
== PCI_DEVICE_ID_NVIDIA_NVENET_37
||
1478 np
->device_id
== PCI_DEVICE_ID_NVIDIA_NVENET_38
||
1479 np
->device_id
== PCI_DEVICE_ID_NVIDIA_NVENET_39
) {
1480 phy_reserved
= mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG6
, MII_READ
);
1481 phy_reserved
|= PHY_REALTEK_INIT7
;
1482 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG6
, phy_reserved
)) {
1483 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1487 if (phy_cross
== NV_CROSSOVER_DETECTION_DISABLED
) {
1488 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG1
, PHY_REALTEK_INIT3
)) {
1489 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1492 phy_reserved
= mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG2
, MII_READ
);
1493 phy_reserved
&= ~PHY_REALTEK_INIT_MSK1
;
1494 phy_reserved
|= PHY_REALTEK_INIT3
;
1495 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG2
, phy_reserved
)) {
1496 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1499 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG1
, PHY_REALTEK_INIT1
)) {
1500 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1507 /* some phys clear out pause advertisment on reset, set it back */
1508 mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, reg
);
1510 /* restart auto negotiation, power down phy */
1511 mii_control
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
1512 mii_control
|= (BMCR_ANRESTART
| BMCR_ANENABLE
);
1513 if (phy_power_down
) {
1514 mii_control
|= BMCR_PDOWN
;
1516 if (mii_rw(dev
, np
->phyaddr
, MII_BMCR
, mii_control
)) {
1523 static void nv_start_rx(struct net_device
*dev
)
1525 struct fe_priv
*np
= netdev_priv(dev
);
1526 u8 __iomem
*base
= get_hwbase(dev
);
1527 u32 rx_ctrl
= readl(base
+ NvRegReceiverControl
);
1529 dprintk(KERN_DEBUG
"%s: nv_start_rx\n", dev
->name
);
1530 /* Already running? Stop it. */
1531 if ((readl(base
+ NvRegReceiverControl
) & NVREG_RCVCTL_START
) && !np
->mac_in_use
) {
1532 rx_ctrl
&= ~NVREG_RCVCTL_START
;
1533 writel(rx_ctrl
, base
+ NvRegReceiverControl
);
1536 writel(np
->linkspeed
, base
+ NvRegLinkSpeed
);
1538 rx_ctrl
|= NVREG_RCVCTL_START
;
1540 rx_ctrl
&= ~NVREG_RCVCTL_RX_PATH_EN
;
1541 writel(rx_ctrl
, base
+ NvRegReceiverControl
);
1542 dprintk(KERN_DEBUG
"%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
1543 dev
->name
, np
->duplex
, np
->linkspeed
);
1547 static void nv_stop_rx(struct net_device
*dev
)
1549 struct fe_priv
*np
= netdev_priv(dev
);
1550 u8 __iomem
*base
= get_hwbase(dev
);
1551 u32 rx_ctrl
= readl(base
+ NvRegReceiverControl
);
1553 dprintk(KERN_DEBUG
"%s: nv_stop_rx\n", dev
->name
);
1554 if (!np
->mac_in_use
)
1555 rx_ctrl
&= ~NVREG_RCVCTL_START
;
1557 rx_ctrl
|= NVREG_RCVCTL_RX_PATH_EN
;
1558 writel(rx_ctrl
, base
+ NvRegReceiverControl
);
1559 reg_delay(dev
, NvRegReceiverStatus
, NVREG_RCVSTAT_BUSY
, 0,
1560 NV_RXSTOP_DELAY1
, NV_RXSTOP_DELAY1MAX
,
1561 KERN_INFO
"nv_stop_rx: ReceiverStatus remained busy");
1563 udelay(NV_RXSTOP_DELAY2
);
1564 if (!np
->mac_in_use
)
1565 writel(0, base
+ NvRegLinkSpeed
);
1568 static void nv_start_tx(struct net_device
*dev
)
1570 struct fe_priv
*np
= netdev_priv(dev
);
1571 u8 __iomem
*base
= get_hwbase(dev
);
1572 u32 tx_ctrl
= readl(base
+ NvRegTransmitterControl
);
1574 dprintk(KERN_DEBUG
"%s: nv_start_tx\n", dev
->name
);
1575 tx_ctrl
|= NVREG_XMITCTL_START
;
1577 tx_ctrl
&= ~NVREG_XMITCTL_TX_PATH_EN
;
1578 writel(tx_ctrl
, base
+ NvRegTransmitterControl
);
1582 static void nv_stop_tx(struct net_device
*dev
)
1584 struct fe_priv
*np
= netdev_priv(dev
);
1585 u8 __iomem
*base
= get_hwbase(dev
);
1586 u32 tx_ctrl
= readl(base
+ NvRegTransmitterControl
);
1588 dprintk(KERN_DEBUG
"%s: nv_stop_tx\n", dev
->name
);
1589 if (!np
->mac_in_use
)
1590 tx_ctrl
&= ~NVREG_XMITCTL_START
;
1592 tx_ctrl
|= NVREG_XMITCTL_TX_PATH_EN
;
1593 writel(tx_ctrl
, base
+ NvRegTransmitterControl
);
1594 reg_delay(dev
, NvRegTransmitterStatus
, NVREG_XMITSTAT_BUSY
, 0,
1595 NV_TXSTOP_DELAY1
, NV_TXSTOP_DELAY1MAX
,
1596 KERN_INFO
"nv_stop_tx: TransmitterStatus remained busy");
1598 udelay(NV_TXSTOP_DELAY2
);
1599 if (!np
->mac_in_use
)
1600 writel(readl(base
+ NvRegTransmitPoll
) & NVREG_TRANSMITPOLL_MAC_ADDR_REV
,
1601 base
+ NvRegTransmitPoll
);
1604 static void nv_start_rxtx(struct net_device
*dev
)
1610 static void nv_stop_rxtx(struct net_device
*dev
)
1616 static void nv_txrx_reset(struct net_device
*dev
)
1618 struct fe_priv
*np
= netdev_priv(dev
);
1619 u8 __iomem
*base
= get_hwbase(dev
);
1621 dprintk(KERN_DEBUG
"%s: nv_txrx_reset\n", dev
->name
);
1622 writel(NVREG_TXRXCTL_BIT2
| NVREG_TXRXCTL_RESET
| np
->txrxctl_bits
, base
+ NvRegTxRxControl
);
1624 udelay(NV_TXRX_RESET_DELAY
);
1625 writel(NVREG_TXRXCTL_BIT2
| np
->txrxctl_bits
, base
+ NvRegTxRxControl
);
1629 static void nv_mac_reset(struct net_device
*dev
)
1631 struct fe_priv
*np
= netdev_priv(dev
);
1632 u8 __iomem
*base
= get_hwbase(dev
);
1633 u32 temp1
, temp2
, temp3
;
1635 dprintk(KERN_DEBUG
"%s: nv_mac_reset\n", dev
->name
);
1637 writel(NVREG_TXRXCTL_BIT2
| NVREG_TXRXCTL_RESET
| np
->txrxctl_bits
, base
+ NvRegTxRxControl
);
1640 /* save registers since they will be cleared on reset */
1641 temp1
= readl(base
+ NvRegMacAddrA
);
1642 temp2
= readl(base
+ NvRegMacAddrB
);
1643 temp3
= readl(base
+ NvRegTransmitPoll
);
1645 writel(NVREG_MAC_RESET_ASSERT
, base
+ NvRegMacReset
);
1647 udelay(NV_MAC_RESET_DELAY
);
1648 writel(0, base
+ NvRegMacReset
);
1650 udelay(NV_MAC_RESET_DELAY
);
1652 /* restore saved registers */
1653 writel(temp1
, base
+ NvRegMacAddrA
);
1654 writel(temp2
, base
+ NvRegMacAddrB
);
1655 writel(temp3
, base
+ NvRegTransmitPoll
);
1657 writel(NVREG_TXRXCTL_BIT2
| np
->txrxctl_bits
, base
+ NvRegTxRxControl
);
1661 static void nv_get_hw_stats(struct net_device
*dev
)
1663 struct fe_priv
*np
= netdev_priv(dev
);
1664 u8 __iomem
*base
= get_hwbase(dev
);
1666 np
->estats
.tx_bytes
+= readl(base
+ NvRegTxCnt
);
1667 np
->estats
.tx_zero_rexmt
+= readl(base
+ NvRegTxZeroReXmt
);
1668 np
->estats
.tx_one_rexmt
+= readl(base
+ NvRegTxOneReXmt
);
1669 np
->estats
.tx_many_rexmt
+= readl(base
+ NvRegTxManyReXmt
);
1670 np
->estats
.tx_late_collision
+= readl(base
+ NvRegTxLateCol
);
1671 np
->estats
.tx_fifo_errors
+= readl(base
+ NvRegTxUnderflow
);
1672 np
->estats
.tx_carrier_errors
+= readl(base
+ NvRegTxLossCarrier
);
1673 np
->estats
.tx_excess_deferral
+= readl(base
+ NvRegTxExcessDef
);
1674 np
->estats
.tx_retry_error
+= readl(base
+ NvRegTxRetryErr
);
1675 np
->estats
.rx_frame_error
+= readl(base
+ NvRegRxFrameErr
);
1676 np
->estats
.rx_extra_byte
+= readl(base
+ NvRegRxExtraByte
);
1677 np
->estats
.rx_late_collision
+= readl(base
+ NvRegRxLateCol
);
1678 np
->estats
.rx_runt
+= readl(base
+ NvRegRxRunt
);
1679 np
->estats
.rx_frame_too_long
+= readl(base
+ NvRegRxFrameTooLong
);
1680 np
->estats
.rx_over_errors
+= readl(base
+ NvRegRxOverflow
);
1681 np
->estats
.rx_crc_errors
+= readl(base
+ NvRegRxFCSErr
);
1682 np
->estats
.rx_frame_align_error
+= readl(base
+ NvRegRxFrameAlignErr
);
1683 np
->estats
.rx_length_error
+= readl(base
+ NvRegRxLenErr
);
1684 np
->estats
.rx_unicast
+= readl(base
+ NvRegRxUnicast
);
1685 np
->estats
.rx_multicast
+= readl(base
+ NvRegRxMulticast
);
1686 np
->estats
.rx_broadcast
+= readl(base
+ NvRegRxBroadcast
);
1687 np
->estats
.rx_packets
=
1688 np
->estats
.rx_unicast
+
1689 np
->estats
.rx_multicast
+
1690 np
->estats
.rx_broadcast
;
1691 np
->estats
.rx_errors_total
=
1692 np
->estats
.rx_crc_errors
+
1693 np
->estats
.rx_over_errors
+
1694 np
->estats
.rx_frame_error
+
1695 (np
->estats
.rx_frame_align_error
- np
->estats
.rx_extra_byte
) +
1696 np
->estats
.rx_late_collision
+
1697 np
->estats
.rx_runt
+
1698 np
->estats
.rx_frame_too_long
;
1699 np
->estats
.tx_errors_total
=
1700 np
->estats
.tx_late_collision
+
1701 np
->estats
.tx_fifo_errors
+
1702 np
->estats
.tx_carrier_errors
+
1703 np
->estats
.tx_excess_deferral
+
1704 np
->estats
.tx_retry_error
;
1706 if (np
->driver_data
& DEV_HAS_STATISTICS_V2
) {
1707 np
->estats
.tx_deferral
+= readl(base
+ NvRegTxDef
);
1708 np
->estats
.tx_packets
+= readl(base
+ NvRegTxFrame
);
1709 np
->estats
.rx_bytes
+= readl(base
+ NvRegRxCnt
);
1710 np
->estats
.tx_pause
+= readl(base
+ NvRegTxPause
);
1711 np
->estats
.rx_pause
+= readl(base
+ NvRegRxPause
);
1712 np
->estats
.rx_drop_frame
+= readl(base
+ NvRegRxDropFrame
);
1715 if (np
->driver_data
& DEV_HAS_STATISTICS_V3
) {
1716 np
->estats
.tx_unicast
+= readl(base
+ NvRegTxUnicast
);
1717 np
->estats
.tx_multicast
+= readl(base
+ NvRegTxMulticast
);
1718 np
->estats
.tx_broadcast
+= readl(base
+ NvRegTxBroadcast
);
1723 * nv_get_stats: dev->get_stats function
1724 * Get latest stats value from the nic.
1725 * Called with read_lock(&dev_base_lock) held for read -
1726 * only synchronized against unregister_netdevice.
1728 static struct net_device_stats
*nv_get_stats(struct net_device
*dev
)
1730 struct fe_priv
*np
= netdev_priv(dev
);
1732 /* If the nic supports hw counters then retrieve latest values */
1733 if (np
->driver_data
& (DEV_HAS_STATISTICS_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_STATISTICS_V3
)) {
1734 nv_get_hw_stats(dev
);
1736 /* copy to net_device stats */
1737 dev
->stats
.tx_bytes
= np
->estats
.tx_bytes
;
1738 dev
->stats
.tx_fifo_errors
= np
->estats
.tx_fifo_errors
;
1739 dev
->stats
.tx_carrier_errors
= np
->estats
.tx_carrier_errors
;
1740 dev
->stats
.rx_crc_errors
= np
->estats
.rx_crc_errors
;
1741 dev
->stats
.rx_over_errors
= np
->estats
.rx_over_errors
;
1742 dev
->stats
.rx_errors
= np
->estats
.rx_errors_total
;
1743 dev
->stats
.tx_errors
= np
->estats
.tx_errors_total
;
1750 * nv_alloc_rx: fill rx ring entries.
1751 * Return 1 if the allocations for the skbs failed and the
1752 * rx engine is without Available descriptors
1754 static int nv_alloc_rx(struct net_device
*dev
)
1756 struct fe_priv
*np
= netdev_priv(dev
);
1757 struct ring_desc
* less_rx
;
1759 less_rx
= np
->get_rx
.orig
;
1760 if (less_rx
-- == np
->first_rx
.orig
)
1761 less_rx
= np
->last_rx
.orig
;
1763 while (np
->put_rx
.orig
!= less_rx
) {
1764 struct sk_buff
*skb
= dev_alloc_skb(np
->rx_buf_sz
+ NV_RX_ALLOC_PAD
);
1766 np
->put_rx_ctx
->skb
= skb
;
1767 np
->put_rx_ctx
->dma
= pci_map_single(np
->pci_dev
,
1770 PCI_DMA_FROMDEVICE
);
1771 np
->put_rx_ctx
->dma_len
= skb_tailroom(skb
);
1772 np
->put_rx
.orig
->buf
= cpu_to_le32(np
->put_rx_ctx
->dma
);
1774 np
->put_rx
.orig
->flaglen
= cpu_to_le32(np
->rx_buf_sz
| NV_RX_AVAIL
);
1775 if (unlikely(np
->put_rx
.orig
++ == np
->last_rx
.orig
))
1776 np
->put_rx
.orig
= np
->first_rx
.orig
;
1777 if (unlikely(np
->put_rx_ctx
++ == np
->last_rx_ctx
))
1778 np
->put_rx_ctx
= np
->first_rx_ctx
;
1786 static int nv_alloc_rx_optimized(struct net_device
*dev
)
1788 struct fe_priv
*np
= netdev_priv(dev
);
1789 struct ring_desc_ex
* less_rx
;
1791 less_rx
= np
->get_rx
.ex
;
1792 if (less_rx
-- == np
->first_rx
.ex
)
1793 less_rx
= np
->last_rx
.ex
;
1795 while (np
->put_rx
.ex
!= less_rx
) {
1796 struct sk_buff
*skb
= dev_alloc_skb(np
->rx_buf_sz
+ NV_RX_ALLOC_PAD
);
1798 np
->put_rx_ctx
->skb
= skb
;
1799 np
->put_rx_ctx
->dma
= pci_map_single(np
->pci_dev
,
1802 PCI_DMA_FROMDEVICE
);
1803 np
->put_rx_ctx
->dma_len
= skb_tailroom(skb
);
1804 np
->put_rx
.ex
->bufhigh
= cpu_to_le32(dma_high(np
->put_rx_ctx
->dma
));
1805 np
->put_rx
.ex
->buflow
= cpu_to_le32(dma_low(np
->put_rx_ctx
->dma
));
1807 np
->put_rx
.ex
->flaglen
= cpu_to_le32(np
->rx_buf_sz
| NV_RX2_AVAIL
);
1808 if (unlikely(np
->put_rx
.ex
++ == np
->last_rx
.ex
))
1809 np
->put_rx
.ex
= np
->first_rx
.ex
;
1810 if (unlikely(np
->put_rx_ctx
++ == np
->last_rx_ctx
))
1811 np
->put_rx_ctx
= np
->first_rx_ctx
;
1819 /* If rx bufs are exhausted called after 50ms to attempt to refresh */
1820 #ifdef CONFIG_FORCEDETH_NAPI
1821 static void nv_do_rx_refill(unsigned long data
)
1823 struct net_device
*dev
= (struct net_device
*) data
;
1824 struct fe_priv
*np
= netdev_priv(dev
);
1826 /* Just reschedule NAPI rx processing */
1827 napi_schedule(&np
->napi
);
1830 static void nv_do_rx_refill(unsigned long data
)
1832 struct net_device
*dev
= (struct net_device
*) data
;
1833 struct fe_priv
*np
= netdev_priv(dev
);
1836 if (!using_multi_irqs(dev
)) {
1837 if (np
->msi_flags
& NV_MSI_X_ENABLED
)
1838 disable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_ALL
].vector
);
1840 disable_irq(np
->pci_dev
->irq
);
1842 disable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
);
1844 if (!nv_optimized(np
))
1845 retcode
= nv_alloc_rx(dev
);
1847 retcode
= nv_alloc_rx_optimized(dev
);
1849 spin_lock_irq(&np
->lock
);
1850 if (!np
->in_shutdown
)
1851 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
1852 spin_unlock_irq(&np
->lock
);
1854 if (!using_multi_irqs(dev
)) {
1855 if (np
->msi_flags
& NV_MSI_X_ENABLED
)
1856 enable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_ALL
].vector
);
1858 enable_irq(np
->pci_dev
->irq
);
1860 enable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
);
1865 static void nv_init_rx(struct net_device
*dev
)
1867 struct fe_priv
*np
= netdev_priv(dev
);
1870 np
->get_rx
= np
->put_rx
= np
->first_rx
= np
->rx_ring
;
1872 if (!nv_optimized(np
))
1873 np
->last_rx
.orig
= &np
->rx_ring
.orig
[np
->rx_ring_size
-1];
1875 np
->last_rx
.ex
= &np
->rx_ring
.ex
[np
->rx_ring_size
-1];
1876 np
->get_rx_ctx
= np
->put_rx_ctx
= np
->first_rx_ctx
= np
->rx_skb
;
1877 np
->last_rx_ctx
= &np
->rx_skb
[np
->rx_ring_size
-1];
1879 for (i
= 0; i
< np
->rx_ring_size
; i
++) {
1880 if (!nv_optimized(np
)) {
1881 np
->rx_ring
.orig
[i
].flaglen
= 0;
1882 np
->rx_ring
.orig
[i
].buf
= 0;
1884 np
->rx_ring
.ex
[i
].flaglen
= 0;
1885 np
->rx_ring
.ex
[i
].txvlan
= 0;
1886 np
->rx_ring
.ex
[i
].bufhigh
= 0;
1887 np
->rx_ring
.ex
[i
].buflow
= 0;
1889 np
->rx_skb
[i
].skb
= NULL
;
1890 np
->rx_skb
[i
].dma
= 0;
1894 static void nv_init_tx(struct net_device
*dev
)
1896 struct fe_priv
*np
= netdev_priv(dev
);
1899 np
->get_tx
= np
->put_tx
= np
->first_tx
= np
->tx_ring
;
1901 if (!nv_optimized(np
))
1902 np
->last_tx
.orig
= &np
->tx_ring
.orig
[np
->tx_ring_size
-1];
1904 np
->last_tx
.ex
= &np
->tx_ring
.ex
[np
->tx_ring_size
-1];
1905 np
->get_tx_ctx
= np
->put_tx_ctx
= np
->first_tx_ctx
= np
->tx_skb
;
1906 np
->last_tx_ctx
= &np
->tx_skb
[np
->tx_ring_size
-1];
1907 np
->tx_pkts_in_progress
= 0;
1908 np
->tx_change_owner
= NULL
;
1909 np
->tx_end_flip
= NULL
;
1912 for (i
= 0; i
< np
->tx_ring_size
; i
++) {
1913 if (!nv_optimized(np
)) {
1914 np
->tx_ring
.orig
[i
].flaglen
= 0;
1915 np
->tx_ring
.orig
[i
].buf
= 0;
1917 np
->tx_ring
.ex
[i
].flaglen
= 0;
1918 np
->tx_ring
.ex
[i
].txvlan
= 0;
1919 np
->tx_ring
.ex
[i
].bufhigh
= 0;
1920 np
->tx_ring
.ex
[i
].buflow
= 0;
1922 np
->tx_skb
[i
].skb
= NULL
;
1923 np
->tx_skb
[i
].dma
= 0;
1924 np
->tx_skb
[i
].dma_len
= 0;
1925 np
->tx_skb
[i
].first_tx_desc
= NULL
;
1926 np
->tx_skb
[i
].next_tx_ctx
= NULL
;
1930 static int nv_init_ring(struct net_device
*dev
)
1932 struct fe_priv
*np
= netdev_priv(dev
);
1937 if (!nv_optimized(np
))
1938 return nv_alloc_rx(dev
);
1940 return nv_alloc_rx_optimized(dev
);
1943 static int nv_release_txskb(struct net_device
*dev
, struct nv_skb_map
* tx_skb
)
1945 struct fe_priv
*np
= netdev_priv(dev
);
1948 pci_unmap_page(np
->pci_dev
, tx_skb
->dma
,
1954 dev_kfree_skb_any(tx_skb
->skb
);
1962 static void nv_drain_tx(struct net_device
*dev
)
1964 struct fe_priv
*np
= netdev_priv(dev
);
1967 for (i
= 0; i
< np
->tx_ring_size
; i
++) {
1968 if (!nv_optimized(np
)) {
1969 np
->tx_ring
.orig
[i
].flaglen
= 0;
1970 np
->tx_ring
.orig
[i
].buf
= 0;
1972 np
->tx_ring
.ex
[i
].flaglen
= 0;
1973 np
->tx_ring
.ex
[i
].txvlan
= 0;
1974 np
->tx_ring
.ex
[i
].bufhigh
= 0;
1975 np
->tx_ring
.ex
[i
].buflow
= 0;
1977 if (nv_release_txskb(dev
, &np
->tx_skb
[i
]))
1978 dev
->stats
.tx_dropped
++;
1979 np
->tx_skb
[i
].dma
= 0;
1980 np
->tx_skb
[i
].dma_len
= 0;
1981 np
->tx_skb
[i
].first_tx_desc
= NULL
;
1982 np
->tx_skb
[i
].next_tx_ctx
= NULL
;
1984 np
->tx_pkts_in_progress
= 0;
1985 np
->tx_change_owner
= NULL
;
1986 np
->tx_end_flip
= NULL
;
1989 static void nv_drain_rx(struct net_device
*dev
)
1991 struct fe_priv
*np
= netdev_priv(dev
);
1994 for (i
= 0; i
< np
->rx_ring_size
; i
++) {
1995 if (!nv_optimized(np
)) {
1996 np
->rx_ring
.orig
[i
].flaglen
= 0;
1997 np
->rx_ring
.orig
[i
].buf
= 0;
1999 np
->rx_ring
.ex
[i
].flaglen
= 0;
2000 np
->rx_ring
.ex
[i
].txvlan
= 0;
2001 np
->rx_ring
.ex
[i
].bufhigh
= 0;
2002 np
->rx_ring
.ex
[i
].buflow
= 0;
2005 if (np
->rx_skb
[i
].skb
) {
2006 pci_unmap_single(np
->pci_dev
, np
->rx_skb
[i
].dma
,
2007 (skb_end_pointer(np
->rx_skb
[i
].skb
) -
2008 np
->rx_skb
[i
].skb
->data
),
2009 PCI_DMA_FROMDEVICE
);
2010 dev_kfree_skb(np
->rx_skb
[i
].skb
);
2011 np
->rx_skb
[i
].skb
= NULL
;
2016 static void nv_drain_rxtx(struct net_device
*dev
)
2022 static inline u32
nv_get_empty_tx_slots(struct fe_priv
*np
)
2024 return (u32
)(np
->tx_ring_size
- ((np
->tx_ring_size
+ (np
->put_tx_ctx
- np
->get_tx_ctx
)) % np
->tx_ring_size
));
2027 static void nv_legacybackoff_reseed(struct net_device
*dev
)
2029 u8 __iomem
*base
= get_hwbase(dev
);
2034 reg
= readl(base
+ NvRegSlotTime
) & ~NVREG_SLOTTIME_MASK
;
2035 get_random_bytes(&low
, sizeof(low
));
2036 reg
|= low
& NVREG_SLOTTIME_MASK
;
2038 /* Need to stop tx before change takes effect.
2039 * Caller has already gained np->lock.
2041 tx_status
= readl(base
+ NvRegTransmitterControl
) & NVREG_XMITCTL_START
;
2045 writel(reg
, base
+ NvRegSlotTime
);
2051 /* Gear Backoff Seeds */
2052 #define BACKOFF_SEEDSET_ROWS 8
2053 #define BACKOFF_SEEDSET_LFSRS 15
2055 /* Known Good seed sets */
2056 static const u32 main_seedset
[BACKOFF_SEEDSET_ROWS
][BACKOFF_SEEDSET_LFSRS
] = {
2057 {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2058 {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 385, 761, 790, 974},
2059 {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2060 {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 386, 761, 790, 974},
2061 {266, 265, 276, 585, 397, 208, 345, 355, 365, 376, 385, 396, 771, 700, 984},
2062 {266, 265, 276, 586, 397, 208, 346, 355, 365, 376, 285, 396, 771, 700, 984},
2063 {366, 365, 376, 686, 497, 308, 447, 455, 466, 476, 485, 496, 871, 800, 84},
2064 {466, 465, 476, 786, 597, 408, 547, 555, 566, 576, 585, 597, 971, 900, 184}};
2066 static const u32 gear_seedset
[BACKOFF_SEEDSET_ROWS
][BACKOFF_SEEDSET_LFSRS
] = {
2067 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
2068 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2069 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 397},
2070 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
2071 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
2072 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2073 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2074 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395}};
2076 static void nv_gear_backoff_reseed(struct net_device
*dev
)
2078 u8 __iomem
*base
= get_hwbase(dev
);
2079 u32 miniseed1
, miniseed2
, miniseed2_reversed
, miniseed3
, miniseed3_reversed
;
2080 u32 temp
, seedset
, combinedSeed
;
2083 /* Setup seed for free running LFSR */
2084 /* We are going to read the time stamp counter 3 times
2085 and swizzle bits around to increase randomness */
2086 get_random_bytes(&miniseed1
, sizeof(miniseed1
));
2087 miniseed1
&= 0x0fff;
2091 get_random_bytes(&miniseed2
, sizeof(miniseed2
));
2092 miniseed2
&= 0x0fff;
2095 miniseed2_reversed
=
2096 ((miniseed2
& 0xF00) >> 8) |
2097 (miniseed2
& 0x0F0) |
2098 ((miniseed2
& 0x00F) << 8);
2100 get_random_bytes(&miniseed3
, sizeof(miniseed3
));
2101 miniseed3
&= 0x0fff;
2104 miniseed3_reversed
=
2105 ((miniseed3
& 0xF00) >> 8) |
2106 (miniseed3
& 0x0F0) |
2107 ((miniseed3
& 0x00F) << 8);
2109 combinedSeed
= ((miniseed1
^ miniseed2_reversed
) << 12) |
2110 (miniseed2
^ miniseed3_reversed
);
2112 /* Seeds can not be zero */
2113 if ((combinedSeed
& NVREG_BKOFFCTRL_SEED_MASK
) == 0)
2114 combinedSeed
|= 0x08;
2115 if ((combinedSeed
& (NVREG_BKOFFCTRL_SEED_MASK
<< NVREG_BKOFFCTRL_GEAR
)) == 0)
2116 combinedSeed
|= 0x8000;
2118 /* No need to disable tx here */
2119 temp
= NVREG_BKOFFCTRL_DEFAULT
| (0 << NVREG_BKOFFCTRL_SELECT
);
2120 temp
|= combinedSeed
& NVREG_BKOFFCTRL_SEED_MASK
;
2121 temp
|= combinedSeed
>> NVREG_BKOFFCTRL_GEAR
;
2122 writel(temp
,base
+ NvRegBackOffControl
);
2124 /* Setup seeds for all gear LFSRs. */
2125 get_random_bytes(&seedset
, sizeof(seedset
));
2126 seedset
= seedset
% BACKOFF_SEEDSET_ROWS
;
2127 for (i
= 1; i
<= BACKOFF_SEEDSET_LFSRS
; i
++)
2129 temp
= NVREG_BKOFFCTRL_DEFAULT
| (i
<< NVREG_BKOFFCTRL_SELECT
);
2130 temp
|= main_seedset
[seedset
][i
-1] & 0x3ff;
2131 temp
|= ((gear_seedset
[seedset
][i
-1] & 0x3ff) << NVREG_BKOFFCTRL_GEAR
);
2132 writel(temp
, base
+ NvRegBackOffControl
);
2137 * nv_start_xmit: dev->hard_start_xmit function
2138 * Called with netif_tx_lock held.
2140 static int nv_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
2142 struct fe_priv
*np
= netdev_priv(dev
);
2144 u32 tx_flags_extra
= (np
->desc_ver
== DESC_VER_1
? NV_TX_LASTPACKET
: NV_TX2_LASTPACKET
);
2145 unsigned int fragments
= skb_shinfo(skb
)->nr_frags
;
2149 u32 size
= skb
->len
-skb
->data_len
;
2150 u32 entries
= (size
>> NV_TX2_TSO_MAX_SHIFT
) + ((size
& (NV_TX2_TSO_MAX_SIZE
-1)) ? 1 : 0);
2152 struct ring_desc
* put_tx
;
2153 struct ring_desc
* start_tx
;
2154 struct ring_desc
* prev_tx
;
2155 struct nv_skb_map
* prev_tx_ctx
;
2156 unsigned long flags
;
2158 /* add fragments to entries count */
2159 for (i
= 0; i
< fragments
; i
++) {
2160 entries
+= (skb_shinfo(skb
)->frags
[i
].size
>> NV_TX2_TSO_MAX_SHIFT
) +
2161 ((skb_shinfo(skb
)->frags
[i
].size
& (NV_TX2_TSO_MAX_SIZE
-1)) ? 1 : 0);
2164 spin_lock_irqsave(&np
->lock
, flags
);
2165 empty_slots
= nv_get_empty_tx_slots(np
);
2166 if (unlikely(empty_slots
<= entries
)) {
2167 netif_stop_queue(dev
);
2169 spin_unlock_irqrestore(&np
->lock
, flags
);
2170 return NETDEV_TX_BUSY
;
2172 spin_unlock_irqrestore(&np
->lock
, flags
);
2174 start_tx
= put_tx
= np
->put_tx
.orig
;
2176 /* setup the header buffer */
2179 prev_tx_ctx
= np
->put_tx_ctx
;
2180 bcnt
= (size
> NV_TX2_TSO_MAX_SIZE
) ? NV_TX2_TSO_MAX_SIZE
: size
;
2181 np
->put_tx_ctx
->dma
= pci_map_single(np
->pci_dev
, skb
->data
+ offset
, bcnt
,
2183 np
->put_tx_ctx
->dma_len
= bcnt
;
2184 put_tx
->buf
= cpu_to_le32(np
->put_tx_ctx
->dma
);
2185 put_tx
->flaglen
= cpu_to_le32((bcnt
-1) | tx_flags
);
2187 tx_flags
= np
->tx_flags
;
2190 if (unlikely(put_tx
++ == np
->last_tx
.orig
))
2191 put_tx
= np
->first_tx
.orig
;
2192 if (unlikely(np
->put_tx_ctx
++ == np
->last_tx_ctx
))
2193 np
->put_tx_ctx
= np
->first_tx_ctx
;
2196 /* setup the fragments */
2197 for (i
= 0; i
< fragments
; i
++) {
2198 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
2199 u32 size
= frag
->size
;
2204 prev_tx_ctx
= np
->put_tx_ctx
;
2205 bcnt
= (size
> NV_TX2_TSO_MAX_SIZE
) ? NV_TX2_TSO_MAX_SIZE
: size
;
2206 np
->put_tx_ctx
->dma
= pci_map_page(np
->pci_dev
, frag
->page
, frag
->page_offset
+offset
, bcnt
,
2208 np
->put_tx_ctx
->dma_len
= bcnt
;
2209 put_tx
->buf
= cpu_to_le32(np
->put_tx_ctx
->dma
);
2210 put_tx
->flaglen
= cpu_to_le32((bcnt
-1) | tx_flags
);
2214 if (unlikely(put_tx
++ == np
->last_tx
.orig
))
2215 put_tx
= np
->first_tx
.orig
;
2216 if (unlikely(np
->put_tx_ctx
++ == np
->last_tx_ctx
))
2217 np
->put_tx_ctx
= np
->first_tx_ctx
;
2221 /* set last fragment flag */
2222 prev_tx
->flaglen
|= cpu_to_le32(tx_flags_extra
);
2224 /* save skb in this slot's context area */
2225 prev_tx_ctx
->skb
= skb
;
2227 if (skb_is_gso(skb
))
2228 tx_flags_extra
= NV_TX2_TSO
| (skb_shinfo(skb
)->gso_size
<< NV_TX2_TSO_SHIFT
);
2230 tx_flags_extra
= skb
->ip_summed
== CHECKSUM_PARTIAL
?
2231 NV_TX2_CHECKSUM_L3
| NV_TX2_CHECKSUM_L4
: 0;
2233 spin_lock_irqsave(&np
->lock
, flags
);
2236 start_tx
->flaglen
|= cpu_to_le32(tx_flags
| tx_flags_extra
);
2237 np
->put_tx
.orig
= put_tx
;
2239 spin_unlock_irqrestore(&np
->lock
, flags
);
2241 dprintk(KERN_DEBUG
"%s: nv_start_xmit: entries %d queued for transmission. tx_flags_extra: %x\n",
2242 dev
->name
, entries
, tx_flags_extra
);
2245 for (j
=0; j
<64; j
++) {
2247 dprintk("\n%03x:", j
);
2248 dprintk(" %02x", ((unsigned char*)skb
->data
)[j
]);
2253 dev
->trans_start
= jiffies
;
2254 writel(NVREG_TXRXCTL_KICK
|np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
2255 return NETDEV_TX_OK
;
2258 static int nv_start_xmit_optimized(struct sk_buff
*skb
, struct net_device
*dev
)
2260 struct fe_priv
*np
= netdev_priv(dev
);
2263 unsigned int fragments
= skb_shinfo(skb
)->nr_frags
;
2267 u32 size
= skb
->len
-skb
->data_len
;
2268 u32 entries
= (size
>> NV_TX2_TSO_MAX_SHIFT
) + ((size
& (NV_TX2_TSO_MAX_SIZE
-1)) ? 1 : 0);
2270 struct ring_desc_ex
* put_tx
;
2271 struct ring_desc_ex
* start_tx
;
2272 struct ring_desc_ex
* prev_tx
;
2273 struct nv_skb_map
* prev_tx_ctx
;
2274 struct nv_skb_map
* start_tx_ctx
;
2275 unsigned long flags
;
2277 /* add fragments to entries count */
2278 for (i
= 0; i
< fragments
; i
++) {
2279 entries
+= (skb_shinfo(skb
)->frags
[i
].size
>> NV_TX2_TSO_MAX_SHIFT
) +
2280 ((skb_shinfo(skb
)->frags
[i
].size
& (NV_TX2_TSO_MAX_SIZE
-1)) ? 1 : 0);
2283 spin_lock_irqsave(&np
->lock
, flags
);
2284 empty_slots
= nv_get_empty_tx_slots(np
);
2285 if (unlikely(empty_slots
<= entries
)) {
2286 netif_stop_queue(dev
);
2288 spin_unlock_irqrestore(&np
->lock
, flags
);
2289 return NETDEV_TX_BUSY
;
2291 spin_unlock_irqrestore(&np
->lock
, flags
);
2293 start_tx
= put_tx
= np
->put_tx
.ex
;
2294 start_tx_ctx
= np
->put_tx_ctx
;
2296 /* setup the header buffer */
2299 prev_tx_ctx
= np
->put_tx_ctx
;
2300 bcnt
= (size
> NV_TX2_TSO_MAX_SIZE
) ? NV_TX2_TSO_MAX_SIZE
: size
;
2301 np
->put_tx_ctx
->dma
= pci_map_single(np
->pci_dev
, skb
->data
+ offset
, bcnt
,
2303 np
->put_tx_ctx
->dma_len
= bcnt
;
2304 put_tx
->bufhigh
= cpu_to_le32(dma_high(np
->put_tx_ctx
->dma
));
2305 put_tx
->buflow
= cpu_to_le32(dma_low(np
->put_tx_ctx
->dma
));
2306 put_tx
->flaglen
= cpu_to_le32((bcnt
-1) | tx_flags
);
2308 tx_flags
= NV_TX2_VALID
;
2311 if (unlikely(put_tx
++ == np
->last_tx
.ex
))
2312 put_tx
= np
->first_tx
.ex
;
2313 if (unlikely(np
->put_tx_ctx
++ == np
->last_tx_ctx
))
2314 np
->put_tx_ctx
= np
->first_tx_ctx
;
2317 /* setup the fragments */
2318 for (i
= 0; i
< fragments
; i
++) {
2319 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
2320 u32 size
= frag
->size
;
2325 prev_tx_ctx
= np
->put_tx_ctx
;
2326 bcnt
= (size
> NV_TX2_TSO_MAX_SIZE
) ? NV_TX2_TSO_MAX_SIZE
: size
;
2327 np
->put_tx_ctx
->dma
= pci_map_page(np
->pci_dev
, frag
->page
, frag
->page_offset
+offset
, bcnt
,
2329 np
->put_tx_ctx
->dma_len
= bcnt
;
2330 put_tx
->bufhigh
= cpu_to_le32(dma_high(np
->put_tx_ctx
->dma
));
2331 put_tx
->buflow
= cpu_to_le32(dma_low(np
->put_tx_ctx
->dma
));
2332 put_tx
->flaglen
= cpu_to_le32((bcnt
-1) | tx_flags
);
2336 if (unlikely(put_tx
++ == np
->last_tx
.ex
))
2337 put_tx
= np
->first_tx
.ex
;
2338 if (unlikely(np
->put_tx_ctx
++ == np
->last_tx_ctx
))
2339 np
->put_tx_ctx
= np
->first_tx_ctx
;
2343 /* set last fragment flag */
2344 prev_tx
->flaglen
|= cpu_to_le32(NV_TX2_LASTPACKET
);
2346 /* save skb in this slot's context area */
2347 prev_tx_ctx
->skb
= skb
;
2349 if (skb_is_gso(skb
))
2350 tx_flags_extra
= NV_TX2_TSO
| (skb_shinfo(skb
)->gso_size
<< NV_TX2_TSO_SHIFT
);
2352 tx_flags_extra
= skb
->ip_summed
== CHECKSUM_PARTIAL
?
2353 NV_TX2_CHECKSUM_L3
| NV_TX2_CHECKSUM_L4
: 0;
2356 if (likely(!np
->vlangrp
)) {
2357 start_tx
->txvlan
= 0;
2359 if (vlan_tx_tag_present(skb
))
2360 start_tx
->txvlan
= cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT
| vlan_tx_tag_get(skb
));
2362 start_tx
->txvlan
= 0;
2365 spin_lock_irqsave(&np
->lock
, flags
);
2368 /* Limit the number of outstanding tx. Setup all fragments, but
2369 * do not set the VALID bit on the first descriptor. Save a pointer
2370 * to that descriptor and also for next skb_map element.
2373 if (np
->tx_pkts_in_progress
== NV_TX_LIMIT_COUNT
) {
2374 if (!np
->tx_change_owner
)
2375 np
->tx_change_owner
= start_tx_ctx
;
2377 /* remove VALID bit */
2378 tx_flags
&= ~NV_TX2_VALID
;
2379 start_tx_ctx
->first_tx_desc
= start_tx
;
2380 start_tx_ctx
->next_tx_ctx
= np
->put_tx_ctx
;
2381 np
->tx_end_flip
= np
->put_tx_ctx
;
2383 np
->tx_pkts_in_progress
++;
2388 start_tx
->flaglen
|= cpu_to_le32(tx_flags
| tx_flags_extra
);
2389 np
->put_tx
.ex
= put_tx
;
2391 spin_unlock_irqrestore(&np
->lock
, flags
);
2393 dprintk(KERN_DEBUG
"%s: nv_start_xmit_optimized: entries %d queued for transmission. tx_flags_extra: %x\n",
2394 dev
->name
, entries
, tx_flags_extra
);
2397 for (j
=0; j
<64; j
++) {
2399 dprintk("\n%03x:", j
);
2400 dprintk(" %02x", ((unsigned char*)skb
->data
)[j
]);
2405 dev
->trans_start
= jiffies
;
2406 writel(NVREG_TXRXCTL_KICK
|np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
2407 return NETDEV_TX_OK
;
2410 static inline void nv_tx_flip_ownership(struct net_device
*dev
)
2412 struct fe_priv
*np
= netdev_priv(dev
);
2414 np
->tx_pkts_in_progress
--;
2415 if (np
->tx_change_owner
) {
2416 np
->tx_change_owner
->first_tx_desc
->flaglen
|=
2417 cpu_to_le32(NV_TX2_VALID
);
2418 np
->tx_pkts_in_progress
++;
2420 np
->tx_change_owner
= np
->tx_change_owner
->next_tx_ctx
;
2421 if (np
->tx_change_owner
== np
->tx_end_flip
)
2422 np
->tx_change_owner
= NULL
;
2424 writel(NVREG_TXRXCTL_KICK
|np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
2429 * nv_tx_done: check for completed packets, release the skbs.
2431 * Caller must own np->lock.
2433 static int nv_tx_done(struct net_device
*dev
, int limit
)
2435 struct fe_priv
*np
= netdev_priv(dev
);
2438 struct ring_desc
* orig_get_tx
= np
->get_tx
.orig
;
2440 while ((np
->get_tx
.orig
!= np
->put_tx
.orig
) &&
2441 !((flags
= le32_to_cpu(np
->get_tx
.orig
->flaglen
)) & NV_TX_VALID
) &&
2442 (tx_work
< limit
)) {
2444 dprintk(KERN_DEBUG
"%s: nv_tx_done: flags 0x%x.\n",
2447 pci_unmap_page(np
->pci_dev
, np
->get_tx_ctx
->dma
,
2448 np
->get_tx_ctx
->dma_len
,
2450 np
->get_tx_ctx
->dma
= 0;
2452 if (np
->desc_ver
== DESC_VER_1
) {
2453 if (flags
& NV_TX_LASTPACKET
) {
2454 if (flags
& NV_TX_ERROR
) {
2455 if (flags
& NV_TX_UNDERFLOW
)
2456 dev
->stats
.tx_fifo_errors
++;
2457 if (flags
& NV_TX_CARRIERLOST
)
2458 dev
->stats
.tx_carrier_errors
++;
2459 if ((flags
& NV_TX_RETRYERROR
) && !(flags
& NV_TX_RETRYCOUNT_MASK
))
2460 nv_legacybackoff_reseed(dev
);
2461 dev
->stats
.tx_errors
++;
2463 dev
->stats
.tx_packets
++;
2464 dev
->stats
.tx_bytes
+= np
->get_tx_ctx
->skb
->len
;
2466 dev_kfree_skb_any(np
->get_tx_ctx
->skb
);
2467 np
->get_tx_ctx
->skb
= NULL
;
2471 if (flags
& NV_TX2_LASTPACKET
) {
2472 if (flags
& NV_TX2_ERROR
) {
2473 if (flags
& NV_TX2_UNDERFLOW
)
2474 dev
->stats
.tx_fifo_errors
++;
2475 if (flags
& NV_TX2_CARRIERLOST
)
2476 dev
->stats
.tx_carrier_errors
++;
2477 if ((flags
& NV_TX2_RETRYERROR
) && !(flags
& NV_TX2_RETRYCOUNT_MASK
))
2478 nv_legacybackoff_reseed(dev
);
2479 dev
->stats
.tx_errors
++;
2481 dev
->stats
.tx_packets
++;
2482 dev
->stats
.tx_bytes
+= np
->get_tx_ctx
->skb
->len
;
2484 dev_kfree_skb_any(np
->get_tx_ctx
->skb
);
2485 np
->get_tx_ctx
->skb
= NULL
;
2489 if (unlikely(np
->get_tx
.orig
++ == np
->last_tx
.orig
))
2490 np
->get_tx
.orig
= np
->first_tx
.orig
;
2491 if (unlikely(np
->get_tx_ctx
++ == np
->last_tx_ctx
))
2492 np
->get_tx_ctx
= np
->first_tx_ctx
;
2494 if (unlikely((np
->tx_stop
== 1) && (np
->get_tx
.orig
!= orig_get_tx
))) {
2496 netif_wake_queue(dev
);
2501 static int nv_tx_done_optimized(struct net_device
*dev
, int limit
)
2503 struct fe_priv
*np
= netdev_priv(dev
);
2506 struct ring_desc_ex
* orig_get_tx
= np
->get_tx
.ex
;
2508 while ((np
->get_tx
.ex
!= np
->put_tx
.ex
) &&
2509 !((flags
= le32_to_cpu(np
->get_tx
.ex
->flaglen
)) & NV_TX_VALID
) &&
2510 (tx_work
< limit
)) {
2512 dprintk(KERN_DEBUG
"%s: nv_tx_done_optimized: flags 0x%x.\n",
2515 pci_unmap_page(np
->pci_dev
, np
->get_tx_ctx
->dma
,
2516 np
->get_tx_ctx
->dma_len
,
2518 np
->get_tx_ctx
->dma
= 0;
2520 if (flags
& NV_TX2_LASTPACKET
) {
2521 if (!(flags
& NV_TX2_ERROR
))
2522 dev
->stats
.tx_packets
++;
2524 if ((flags
& NV_TX2_RETRYERROR
) && !(flags
& NV_TX2_RETRYCOUNT_MASK
)) {
2525 if (np
->driver_data
& DEV_HAS_GEAR_MODE
)
2526 nv_gear_backoff_reseed(dev
);
2528 nv_legacybackoff_reseed(dev
);
2532 dev_kfree_skb_any(np
->get_tx_ctx
->skb
);
2533 np
->get_tx_ctx
->skb
= NULL
;
2537 nv_tx_flip_ownership(dev
);
2540 if (unlikely(np
->get_tx
.ex
++ == np
->last_tx
.ex
))
2541 np
->get_tx
.ex
= np
->first_tx
.ex
;
2542 if (unlikely(np
->get_tx_ctx
++ == np
->last_tx_ctx
))
2543 np
->get_tx_ctx
= np
->first_tx_ctx
;
2545 if (unlikely((np
->tx_stop
== 1) && (np
->get_tx
.ex
!= orig_get_tx
))) {
2547 netif_wake_queue(dev
);
2553 * nv_tx_timeout: dev->tx_timeout function
2554 * Called with netif_tx_lock held.
2556 static void nv_tx_timeout(struct net_device
*dev
)
2558 struct fe_priv
*np
= netdev_priv(dev
);
2559 u8 __iomem
*base
= get_hwbase(dev
);
2561 union ring_type put_tx
;
2564 if (np
->msi_flags
& NV_MSI_X_ENABLED
)
2565 status
= readl(base
+ NvRegMSIXIrqStatus
) & NVREG_IRQSTAT_MASK
;
2567 status
= readl(base
+ NvRegIrqStatus
) & NVREG_IRQSTAT_MASK
;
2569 printk(KERN_INFO
"%s: Got tx_timeout. irq: %08x\n", dev
->name
, status
);
2574 printk(KERN_INFO
"%s: Ring at %lx\n",
2575 dev
->name
, (unsigned long)np
->ring_addr
);
2576 printk(KERN_INFO
"%s: Dumping tx registers\n", dev
->name
);
2577 for (i
=0;i
<=np
->register_size
;i
+= 32) {
2578 printk(KERN_INFO
"%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
2580 readl(base
+ i
+ 0), readl(base
+ i
+ 4),
2581 readl(base
+ i
+ 8), readl(base
+ i
+ 12),
2582 readl(base
+ i
+ 16), readl(base
+ i
+ 20),
2583 readl(base
+ i
+ 24), readl(base
+ i
+ 28));
2585 printk(KERN_INFO
"%s: Dumping tx ring\n", dev
->name
);
2586 for (i
=0;i
<np
->tx_ring_size
;i
+= 4) {
2587 if (!nv_optimized(np
)) {
2588 printk(KERN_INFO
"%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
2590 le32_to_cpu(np
->tx_ring
.orig
[i
].buf
),
2591 le32_to_cpu(np
->tx_ring
.orig
[i
].flaglen
),
2592 le32_to_cpu(np
->tx_ring
.orig
[i
+1].buf
),
2593 le32_to_cpu(np
->tx_ring
.orig
[i
+1].flaglen
),
2594 le32_to_cpu(np
->tx_ring
.orig
[i
+2].buf
),
2595 le32_to_cpu(np
->tx_ring
.orig
[i
+2].flaglen
),
2596 le32_to_cpu(np
->tx_ring
.orig
[i
+3].buf
),
2597 le32_to_cpu(np
->tx_ring
.orig
[i
+3].flaglen
));
2599 printk(KERN_INFO
"%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
2601 le32_to_cpu(np
->tx_ring
.ex
[i
].bufhigh
),
2602 le32_to_cpu(np
->tx_ring
.ex
[i
].buflow
),
2603 le32_to_cpu(np
->tx_ring
.ex
[i
].flaglen
),
2604 le32_to_cpu(np
->tx_ring
.ex
[i
+1].bufhigh
),
2605 le32_to_cpu(np
->tx_ring
.ex
[i
+1].buflow
),
2606 le32_to_cpu(np
->tx_ring
.ex
[i
+1].flaglen
),
2607 le32_to_cpu(np
->tx_ring
.ex
[i
+2].bufhigh
),
2608 le32_to_cpu(np
->tx_ring
.ex
[i
+2].buflow
),
2609 le32_to_cpu(np
->tx_ring
.ex
[i
+2].flaglen
),
2610 le32_to_cpu(np
->tx_ring
.ex
[i
+3].bufhigh
),
2611 le32_to_cpu(np
->tx_ring
.ex
[i
+3].buflow
),
2612 le32_to_cpu(np
->tx_ring
.ex
[i
+3].flaglen
));
2617 spin_lock_irq(&np
->lock
);
2619 /* 1) stop tx engine */
2622 /* 2) complete any outstanding tx and do not give HW any limited tx pkts */
2623 saved_tx_limit
= np
->tx_limit
;
2624 np
->tx_limit
= 0; /* prevent giving HW any limited pkts */
2625 np
->tx_stop
= 0; /* prevent waking tx queue */
2626 if (!nv_optimized(np
))
2627 nv_tx_done(dev
, np
->tx_ring_size
);
2629 nv_tx_done_optimized(dev
, np
->tx_ring_size
);
2631 /* save current HW postion */
2632 if (np
->tx_change_owner
)
2633 put_tx
.ex
= np
->tx_change_owner
->first_tx_desc
;
2635 put_tx
= np
->put_tx
;
2637 /* 3) clear all tx state */
2641 /* 4) restore state to current HW position */
2642 np
->get_tx
= np
->put_tx
= put_tx
;
2643 np
->tx_limit
= saved_tx_limit
;
2645 /* 5) restart tx engine */
2647 netif_wake_queue(dev
);
2648 spin_unlock_irq(&np
->lock
);
2652 * Called when the nic notices a mismatch between the actual data len on the
2653 * wire and the len indicated in the 802 header
2655 static int nv_getlen(struct net_device
*dev
, void *packet
, int datalen
)
2657 int hdrlen
; /* length of the 802 header */
2658 int protolen
; /* length as stored in the proto field */
2660 /* 1) calculate len according to header */
2661 if ( ((struct vlan_ethhdr
*)packet
)->h_vlan_proto
== htons(ETH_P_8021Q
)) {
2662 protolen
= ntohs( ((struct vlan_ethhdr
*)packet
)->h_vlan_encapsulated_proto
);
2665 protolen
= ntohs( ((struct ethhdr
*)packet
)->h_proto
);
2668 dprintk(KERN_DEBUG
"%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
2669 dev
->name
, datalen
, protolen
, hdrlen
);
2670 if (protolen
> ETH_DATA_LEN
)
2671 return datalen
; /* Value in proto field not a len, no checks possible */
2674 /* consistency checks: */
2675 if (datalen
> ETH_ZLEN
) {
2676 if (datalen
>= protolen
) {
2677 /* more data on wire than in 802 header, trim of
2680 dprintk(KERN_DEBUG
"%s: nv_getlen: accepting %d bytes.\n",
2681 dev
->name
, protolen
);
2684 /* less data on wire than mentioned in header.
2685 * Discard the packet.
2687 dprintk(KERN_DEBUG
"%s: nv_getlen: discarding long packet.\n",
2692 /* short packet. Accept only if 802 values are also short */
2693 if (protolen
> ETH_ZLEN
) {
2694 dprintk(KERN_DEBUG
"%s: nv_getlen: discarding short packet.\n",
2698 dprintk(KERN_DEBUG
"%s: nv_getlen: accepting %d bytes.\n",
2699 dev
->name
, datalen
);
2704 static int nv_rx_process(struct net_device
*dev
, int limit
)
2706 struct fe_priv
*np
= netdev_priv(dev
);
2709 struct sk_buff
*skb
;
2712 while((np
->get_rx
.orig
!= np
->put_rx
.orig
) &&
2713 !((flags
= le32_to_cpu(np
->get_rx
.orig
->flaglen
)) & NV_RX_AVAIL
) &&
2714 (rx_work
< limit
)) {
2716 dprintk(KERN_DEBUG
"%s: nv_rx_process: flags 0x%x.\n",
2720 * the packet is for us - immediately tear down the pci mapping.
2721 * TODO: check if a prefetch of the first cacheline improves
2724 pci_unmap_single(np
->pci_dev
, np
->get_rx_ctx
->dma
,
2725 np
->get_rx_ctx
->dma_len
,
2726 PCI_DMA_FROMDEVICE
);
2727 skb
= np
->get_rx_ctx
->skb
;
2728 np
->get_rx_ctx
->skb
= NULL
;
2732 dprintk(KERN_DEBUG
"Dumping packet (flags 0x%x).",flags
);
2733 for (j
=0; j
<64; j
++) {
2735 dprintk("\n%03x:", j
);
2736 dprintk(" %02x", ((unsigned char*)skb
->data
)[j
]);
2740 /* look at what we actually got: */
2741 if (np
->desc_ver
== DESC_VER_1
) {
2742 if (likely(flags
& NV_RX_DESCRIPTORVALID
)) {
2743 len
= flags
& LEN_MASK_V1
;
2744 if (unlikely(flags
& NV_RX_ERROR
)) {
2745 if ((flags
& NV_RX_ERROR_MASK
) == NV_RX_ERROR4
) {
2746 len
= nv_getlen(dev
, skb
->data
, len
);
2748 dev
->stats
.rx_errors
++;
2753 /* framing errors are soft errors */
2754 else if ((flags
& NV_RX_ERROR_MASK
) == NV_RX_FRAMINGERR
) {
2755 if (flags
& NV_RX_SUBSTRACT1
) {
2759 /* the rest are hard errors */
2761 if (flags
& NV_RX_MISSEDFRAME
)
2762 dev
->stats
.rx_missed_errors
++;
2763 if (flags
& NV_RX_CRCERR
)
2764 dev
->stats
.rx_crc_errors
++;
2765 if (flags
& NV_RX_OVERFLOW
)
2766 dev
->stats
.rx_over_errors
++;
2767 dev
->stats
.rx_errors
++;
2777 if (likely(flags
& NV_RX2_DESCRIPTORVALID
)) {
2778 len
= flags
& LEN_MASK_V2
;
2779 if (unlikely(flags
& NV_RX2_ERROR
)) {
2780 if ((flags
& NV_RX2_ERROR_MASK
) == NV_RX2_ERROR4
) {
2781 len
= nv_getlen(dev
, skb
->data
, len
);
2783 dev
->stats
.rx_errors
++;
2788 /* framing errors are soft errors */
2789 else if ((flags
& NV_RX2_ERROR_MASK
) == NV_RX2_FRAMINGERR
) {
2790 if (flags
& NV_RX2_SUBSTRACT1
) {
2794 /* the rest are hard errors */
2796 if (flags
& NV_RX2_CRCERR
)
2797 dev
->stats
.rx_crc_errors
++;
2798 if (flags
& NV_RX2_OVERFLOW
)
2799 dev
->stats
.rx_over_errors
++;
2800 dev
->stats
.rx_errors
++;
2805 if (((flags
& NV_RX2_CHECKSUMMASK
) == NV_RX2_CHECKSUM_IP_TCP
) || /*ip and tcp */
2806 ((flags
& NV_RX2_CHECKSUMMASK
) == NV_RX2_CHECKSUM_IP_UDP
)) /*ip and udp */
2807 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
2813 /* got a valid packet - forward it to the network core */
2815 skb
->protocol
= eth_type_trans(skb
, dev
);
2816 dprintk(KERN_DEBUG
"%s: nv_rx_process: %d bytes, proto %d accepted.\n",
2817 dev
->name
, len
, skb
->protocol
);
2818 #ifdef CONFIG_FORCEDETH_NAPI
2819 netif_receive_skb(skb
);
2823 dev
->stats
.rx_packets
++;
2824 dev
->stats
.rx_bytes
+= len
;
2826 if (unlikely(np
->get_rx
.orig
++ == np
->last_rx
.orig
))
2827 np
->get_rx
.orig
= np
->first_rx
.orig
;
2828 if (unlikely(np
->get_rx_ctx
++ == np
->last_rx_ctx
))
2829 np
->get_rx_ctx
= np
->first_rx_ctx
;
2837 static int nv_rx_process_optimized(struct net_device
*dev
, int limit
)
2839 struct fe_priv
*np
= netdev_priv(dev
);
2843 struct sk_buff
*skb
;
2846 while((np
->get_rx
.ex
!= np
->put_rx
.ex
) &&
2847 !((flags
= le32_to_cpu(np
->get_rx
.ex
->flaglen
)) & NV_RX2_AVAIL
) &&
2848 (rx_work
< limit
)) {
2850 dprintk(KERN_DEBUG
"%s: nv_rx_process_optimized: flags 0x%x.\n",
2854 * the packet is for us - immediately tear down the pci mapping.
2855 * TODO: check if a prefetch of the first cacheline improves
2858 pci_unmap_single(np
->pci_dev
, np
->get_rx_ctx
->dma
,
2859 np
->get_rx_ctx
->dma_len
,
2860 PCI_DMA_FROMDEVICE
);
2861 skb
= np
->get_rx_ctx
->skb
;
2862 np
->get_rx_ctx
->skb
= NULL
;
2866 dprintk(KERN_DEBUG
"Dumping packet (flags 0x%x).",flags
);
2867 for (j
=0; j
<64; j
++) {
2869 dprintk("\n%03x:", j
);
2870 dprintk(" %02x", ((unsigned char*)skb
->data
)[j
]);
2874 /* look at what we actually got: */
2875 if (likely(flags
& NV_RX2_DESCRIPTORVALID
)) {
2876 len
= flags
& LEN_MASK_V2
;
2877 if (unlikely(flags
& NV_RX2_ERROR
)) {
2878 if ((flags
& NV_RX2_ERROR_MASK
) == NV_RX2_ERROR4
) {
2879 len
= nv_getlen(dev
, skb
->data
, len
);
2885 /* framing errors are soft errors */
2886 else if ((flags
& NV_RX2_ERROR_MASK
) == NV_RX2_FRAMINGERR
) {
2887 if (flags
& NV_RX2_SUBSTRACT1
) {
2891 /* the rest are hard errors */
2898 if (((flags
& NV_RX2_CHECKSUMMASK
) == NV_RX2_CHECKSUM_IP_TCP
) || /*ip and tcp */
2899 ((flags
& NV_RX2_CHECKSUMMASK
) == NV_RX2_CHECKSUM_IP_UDP
)) /*ip and udp */
2900 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
2902 /* got a valid packet - forward it to the network core */
2904 skb
->protocol
= eth_type_trans(skb
, dev
);
2905 prefetch(skb
->data
);
2907 dprintk(KERN_DEBUG
"%s: nv_rx_process_optimized: %d bytes, proto %d accepted.\n",
2908 dev
->name
, len
, skb
->protocol
);
2910 if (likely(!np
->vlangrp
)) {
2911 #ifdef CONFIG_FORCEDETH_NAPI
2912 netif_receive_skb(skb
);
2917 vlanflags
= le32_to_cpu(np
->get_rx
.ex
->buflow
);
2918 if (vlanflags
& NV_RX3_VLAN_TAG_PRESENT
) {
2919 #ifdef CONFIG_FORCEDETH_NAPI
2920 vlan_hwaccel_receive_skb(skb
, np
->vlangrp
,
2921 vlanflags
& NV_RX3_VLAN_TAG_MASK
);
2923 vlan_hwaccel_rx(skb
, np
->vlangrp
,
2924 vlanflags
& NV_RX3_VLAN_TAG_MASK
);
2927 #ifdef CONFIG_FORCEDETH_NAPI
2928 netif_receive_skb(skb
);
2935 dev
->stats
.rx_packets
++;
2936 dev
->stats
.rx_bytes
+= len
;
2941 if (unlikely(np
->get_rx
.ex
++ == np
->last_rx
.ex
))
2942 np
->get_rx
.ex
= np
->first_rx
.ex
;
2943 if (unlikely(np
->get_rx_ctx
++ == np
->last_rx_ctx
))
2944 np
->get_rx_ctx
= np
->first_rx_ctx
;
2952 static void set_bufsize(struct net_device
*dev
)
2954 struct fe_priv
*np
= netdev_priv(dev
);
2956 if (dev
->mtu
<= ETH_DATA_LEN
)
2957 np
->rx_buf_sz
= ETH_DATA_LEN
+ NV_RX_HEADERS
;
2959 np
->rx_buf_sz
= dev
->mtu
+ NV_RX_HEADERS
;
2963 * nv_change_mtu: dev->change_mtu function
2964 * Called with dev_base_lock held for read.
2966 static int nv_change_mtu(struct net_device
*dev
, int new_mtu
)
2968 struct fe_priv
*np
= netdev_priv(dev
);
2971 if (new_mtu
< 64 || new_mtu
> np
->pkt_limit
)
2977 /* return early if the buffer sizes will not change */
2978 if (old_mtu
<= ETH_DATA_LEN
&& new_mtu
<= ETH_DATA_LEN
)
2980 if (old_mtu
== new_mtu
)
2983 /* synchronized against open : rtnl_lock() held by caller */
2984 if (netif_running(dev
)) {
2985 u8 __iomem
*base
= get_hwbase(dev
);
2987 * It seems that the nic preloads valid ring entries into an
2988 * internal buffer. The procedure for flushing everything is
2989 * guessed, there is probably a simpler approach.
2990 * Changing the MTU is a rare event, it shouldn't matter.
2992 nv_disable_irq(dev
);
2993 nv_napi_disable(dev
);
2994 netif_tx_lock_bh(dev
);
2995 netif_addr_lock(dev
);
2996 spin_lock(&np
->lock
);
3000 /* drain rx queue */
3002 /* reinit driver view of the rx queue */
3004 if (nv_init_ring(dev
)) {
3005 if (!np
->in_shutdown
)
3006 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
3008 /* reinit nic view of the rx queue */
3009 writel(np
->rx_buf_sz
, base
+ NvRegOffloadConfig
);
3010 setup_hw_rings(dev
, NV_SETUP_RX_RING
| NV_SETUP_TX_RING
);
3011 writel( ((np
->rx_ring_size
-1) << NVREG_RINGSZ_RXSHIFT
) + ((np
->tx_ring_size
-1) << NVREG_RINGSZ_TXSHIFT
),
3012 base
+ NvRegRingSizes
);
3014 writel(NVREG_TXRXCTL_KICK
|np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
3017 /* restart rx engine */
3019 spin_unlock(&np
->lock
);
3020 netif_addr_unlock(dev
);
3021 netif_tx_unlock_bh(dev
);
3022 nv_napi_enable(dev
);
3028 static void nv_copy_mac_to_hw(struct net_device
*dev
)
3030 u8 __iomem
*base
= get_hwbase(dev
);
3033 mac
[0] = (dev
->dev_addr
[0] << 0) + (dev
->dev_addr
[1] << 8) +
3034 (dev
->dev_addr
[2] << 16) + (dev
->dev_addr
[3] << 24);
3035 mac
[1] = (dev
->dev_addr
[4] << 0) + (dev
->dev_addr
[5] << 8);
3037 writel(mac
[0], base
+ NvRegMacAddrA
);
3038 writel(mac
[1], base
+ NvRegMacAddrB
);
3042 * nv_set_mac_address: dev->set_mac_address function
3043 * Called with rtnl_lock() held.
3045 static int nv_set_mac_address(struct net_device
*dev
, void *addr
)
3047 struct fe_priv
*np
= netdev_priv(dev
);
3048 struct sockaddr
*macaddr
= (struct sockaddr
*)addr
;
3050 if (!is_valid_ether_addr(macaddr
->sa_data
))
3051 return -EADDRNOTAVAIL
;
3053 /* synchronized against open : rtnl_lock() held by caller */
3054 memcpy(dev
->dev_addr
, macaddr
->sa_data
, ETH_ALEN
);
3056 if (netif_running(dev
)) {
3057 netif_tx_lock_bh(dev
);
3058 netif_addr_lock(dev
);
3059 spin_lock_irq(&np
->lock
);
3061 /* stop rx engine */
3064 /* set mac address */
3065 nv_copy_mac_to_hw(dev
);
3067 /* restart rx engine */
3069 spin_unlock_irq(&np
->lock
);
3070 netif_addr_unlock(dev
);
3071 netif_tx_unlock_bh(dev
);
3073 nv_copy_mac_to_hw(dev
);
3079 * nv_set_multicast: dev->set_multicast function
3080 * Called with netif_tx_lock held.
3082 static void nv_set_multicast(struct net_device
*dev
)
3084 struct fe_priv
*np
= netdev_priv(dev
);
3085 u8 __iomem
*base
= get_hwbase(dev
);
3088 u32 pff
= readl(base
+ NvRegPacketFilterFlags
) & NVREG_PFF_PAUSE_RX
;
3090 memset(addr
, 0, sizeof(addr
));
3091 memset(mask
, 0, sizeof(mask
));
3093 if (dev
->flags
& IFF_PROMISC
) {
3094 pff
|= NVREG_PFF_PROMISC
;
3096 pff
|= NVREG_PFF_MYADDR
;
3098 if (dev
->flags
& IFF_ALLMULTI
|| dev
->mc_list
) {
3102 alwaysOn
[0] = alwaysOn
[1] = alwaysOff
[0] = alwaysOff
[1] = 0xffffffff;
3103 if (dev
->flags
& IFF_ALLMULTI
) {
3104 alwaysOn
[0] = alwaysOn
[1] = alwaysOff
[0] = alwaysOff
[1] = 0;
3106 struct dev_mc_list
*walk
;
3108 walk
= dev
->mc_list
;
3109 while (walk
!= NULL
) {
3111 a
= le32_to_cpu(*(__le32
*) walk
->dmi_addr
);
3112 b
= le16_to_cpu(*(__le16
*) (&walk
->dmi_addr
[4]));
3120 addr
[0] = alwaysOn
[0];
3121 addr
[1] = alwaysOn
[1];
3122 mask
[0] = alwaysOn
[0] | alwaysOff
[0];
3123 mask
[1] = alwaysOn
[1] | alwaysOff
[1];
3125 mask
[0] = NVREG_MCASTMASKA_NONE
;
3126 mask
[1] = NVREG_MCASTMASKB_NONE
;
3129 addr
[0] |= NVREG_MCASTADDRA_FORCE
;
3130 pff
|= NVREG_PFF_ALWAYS
;
3131 spin_lock_irq(&np
->lock
);
3133 writel(addr
[0], base
+ NvRegMulticastAddrA
);
3134 writel(addr
[1], base
+ NvRegMulticastAddrB
);
3135 writel(mask
[0], base
+ NvRegMulticastMaskA
);
3136 writel(mask
[1], base
+ NvRegMulticastMaskB
);
3137 writel(pff
, base
+ NvRegPacketFilterFlags
);
3138 dprintk(KERN_INFO
"%s: reconfiguration for multicast lists.\n",
3141 spin_unlock_irq(&np
->lock
);
3144 static void nv_update_pause(struct net_device
*dev
, u32 pause_flags
)
3146 struct fe_priv
*np
= netdev_priv(dev
);
3147 u8 __iomem
*base
= get_hwbase(dev
);
3149 np
->pause_flags
&= ~(NV_PAUSEFRAME_TX_ENABLE
| NV_PAUSEFRAME_RX_ENABLE
);
3151 if (np
->pause_flags
& NV_PAUSEFRAME_RX_CAPABLE
) {
3152 u32 pff
= readl(base
+ NvRegPacketFilterFlags
) & ~NVREG_PFF_PAUSE_RX
;
3153 if (pause_flags
& NV_PAUSEFRAME_RX_ENABLE
) {
3154 writel(pff
|NVREG_PFF_PAUSE_RX
, base
+ NvRegPacketFilterFlags
);
3155 np
->pause_flags
|= NV_PAUSEFRAME_RX_ENABLE
;
3157 writel(pff
, base
+ NvRegPacketFilterFlags
);
3160 if (np
->pause_flags
& NV_PAUSEFRAME_TX_CAPABLE
) {
3161 u32 regmisc
= readl(base
+ NvRegMisc1
) & ~NVREG_MISC1_PAUSE_TX
;
3162 if (pause_flags
& NV_PAUSEFRAME_TX_ENABLE
) {
3163 u32 pause_enable
= NVREG_TX_PAUSEFRAME_ENABLE_V1
;
3164 if (np
->driver_data
& DEV_HAS_PAUSEFRAME_TX_V2
)
3165 pause_enable
= NVREG_TX_PAUSEFRAME_ENABLE_V2
;
3166 if (np
->driver_data
& DEV_HAS_PAUSEFRAME_TX_V3
) {
3167 pause_enable
= NVREG_TX_PAUSEFRAME_ENABLE_V3
;
3168 /* limit the number of tx pause frames to a default of 8 */
3169 writel(readl(base
+ NvRegTxPauseFrameLimit
)|NVREG_TX_PAUSEFRAMELIMIT_ENABLE
, base
+ NvRegTxPauseFrameLimit
);
3171 writel(pause_enable
, base
+ NvRegTxPauseFrame
);
3172 writel(regmisc
|NVREG_MISC1_PAUSE_TX
, base
+ NvRegMisc1
);
3173 np
->pause_flags
|= NV_PAUSEFRAME_TX_ENABLE
;
3175 writel(NVREG_TX_PAUSEFRAME_DISABLE
, base
+ NvRegTxPauseFrame
);
3176 writel(regmisc
, base
+ NvRegMisc1
);
3182 * nv_update_linkspeed: Setup the MAC according to the link partner
3183 * @dev: Network device to be configured
3185 * The function queries the PHY and checks if there is a link partner.
3186 * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
3187 * set to 10 MBit HD.
3189 * The function returns 0 if there is no link partner and 1 if there is
3190 * a good link partner.
3192 static int nv_update_linkspeed(struct net_device
*dev
)
3194 struct fe_priv
*np
= netdev_priv(dev
);
3195 u8 __iomem
*base
= get_hwbase(dev
);
3198 int adv_lpa
, adv_pause
, lpa_pause
;
3199 int newls
= np
->linkspeed
;
3200 int newdup
= np
->duplex
;
3203 u32 control_1000
, status_1000
, phyreg
, pause_flags
, txreg
;
3207 /* BMSR_LSTATUS is latched, read it twice:
3208 * we want the current value.
3210 mii_rw(dev
, np
->phyaddr
, MII_BMSR
, MII_READ
);
3211 mii_status
= mii_rw(dev
, np
->phyaddr
, MII_BMSR
, MII_READ
);
3213 if (!(mii_status
& BMSR_LSTATUS
)) {
3214 dprintk(KERN_DEBUG
"%s: no link detected by phy - falling back to 10HD.\n",
3216 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
3222 if (np
->autoneg
== 0) {
3223 dprintk(KERN_DEBUG
"%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
3224 dev
->name
, np
->fixed_mode
);
3225 if (np
->fixed_mode
& LPA_100FULL
) {
3226 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_100
;
3228 } else if (np
->fixed_mode
& LPA_100HALF
) {
3229 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_100
;
3231 } else if (np
->fixed_mode
& LPA_10FULL
) {
3232 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
3235 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
3241 /* check auto negotiation is complete */
3242 if (!(mii_status
& BMSR_ANEGCOMPLETE
)) {
3243 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
3244 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
3247 dprintk(KERN_DEBUG
"%s: autoneg not completed - falling back to 10HD.\n", dev
->name
);
3251 adv
= mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, MII_READ
);
3252 lpa
= mii_rw(dev
, np
->phyaddr
, MII_LPA
, MII_READ
);
3253 dprintk(KERN_DEBUG
"%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
3254 dev
->name
, adv
, lpa
);
3257 if (np
->gigabit
== PHY_GIGABIT
) {
3258 control_1000
= mii_rw(dev
, np
->phyaddr
, MII_CTRL1000
, MII_READ
);
3259 status_1000
= mii_rw(dev
, np
->phyaddr
, MII_STAT1000
, MII_READ
);
3261 if ((control_1000
& ADVERTISE_1000FULL
) &&
3262 (status_1000
& LPA_1000FULL
)) {
3263 dprintk(KERN_DEBUG
"%s: nv_update_linkspeed: GBit ethernet detected.\n",
3265 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_1000
;
3271 /* FIXME: handle parallel detection properly */
3272 adv_lpa
= lpa
& adv
;
3273 if (adv_lpa
& LPA_100FULL
) {
3274 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_100
;
3276 } else if (adv_lpa
& LPA_100HALF
) {
3277 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_100
;
3279 } else if (adv_lpa
& LPA_10FULL
) {
3280 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
3282 } else if (adv_lpa
& LPA_10HALF
) {
3283 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
3286 dprintk(KERN_DEBUG
"%s: bad ability %04x - falling back to 10HD.\n", dev
->name
, adv_lpa
);
3287 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
3292 if (np
->duplex
== newdup
&& np
->linkspeed
== newls
)
3295 dprintk(KERN_INFO
"%s: changing link setting from %d/%d to %d/%d.\n",
3296 dev
->name
, np
->linkspeed
, np
->duplex
, newls
, newdup
);
3298 np
->duplex
= newdup
;
3299 np
->linkspeed
= newls
;
3301 /* The transmitter and receiver must be restarted for safe update */
3302 if (readl(base
+ NvRegTransmitterControl
) & NVREG_XMITCTL_START
) {
3303 txrxFlags
|= NV_RESTART_TX
;
3306 if (readl(base
+ NvRegReceiverControl
) & NVREG_RCVCTL_START
) {
3307 txrxFlags
|= NV_RESTART_RX
;
3311 if (np
->gigabit
== PHY_GIGABIT
) {
3312 phyreg
= readl(base
+ NvRegSlotTime
);
3313 phyreg
&= ~(0x3FF00);
3314 if (((np
->linkspeed
& 0xFFF) == NVREG_LINKSPEED_10
) ||
3315 ((np
->linkspeed
& 0xFFF) == NVREG_LINKSPEED_100
))
3316 phyreg
|= NVREG_SLOTTIME_10_100_FULL
;
3317 else if ((np
->linkspeed
& 0xFFF) == NVREG_LINKSPEED_1000
)
3318 phyreg
|= NVREG_SLOTTIME_1000_FULL
;
3319 writel(phyreg
, base
+ NvRegSlotTime
);
3322 phyreg
= readl(base
+ NvRegPhyInterface
);
3323 phyreg
&= ~(PHY_HALF
|PHY_100
|PHY_1000
);
3324 if (np
->duplex
== 0)
3326 if ((np
->linkspeed
& NVREG_LINKSPEED_MASK
) == NVREG_LINKSPEED_100
)
3328 else if ((np
->linkspeed
& NVREG_LINKSPEED_MASK
) == NVREG_LINKSPEED_1000
)
3330 writel(phyreg
, base
+ NvRegPhyInterface
);
3332 phy_exp
= mii_rw(dev
, np
->phyaddr
, MII_EXPANSION
, MII_READ
) & EXPANSION_NWAY
; /* autoneg capable */
3333 if (phyreg
& PHY_RGMII
) {
3334 if ((np
->linkspeed
& NVREG_LINKSPEED_MASK
) == NVREG_LINKSPEED_1000
) {
3335 txreg
= NVREG_TX_DEFERRAL_RGMII_1000
;
3337 if (!phy_exp
&& !np
->duplex
&& (np
->driver_data
& DEV_HAS_COLLISION_FIX
)) {
3338 if ((np
->linkspeed
& NVREG_LINKSPEED_MASK
) == NVREG_LINKSPEED_10
)
3339 txreg
= NVREG_TX_DEFERRAL_RGMII_STRETCH_10
;
3341 txreg
= NVREG_TX_DEFERRAL_RGMII_STRETCH_100
;
3343 txreg
= NVREG_TX_DEFERRAL_RGMII_10_100
;
3347 if (!phy_exp
&& !np
->duplex
&& (np
->driver_data
& DEV_HAS_COLLISION_FIX
))
3348 txreg
= NVREG_TX_DEFERRAL_MII_STRETCH
;
3350 txreg
= NVREG_TX_DEFERRAL_DEFAULT
;
3352 writel(txreg
, base
+ NvRegTxDeferral
);
3354 if (np
->desc_ver
== DESC_VER_1
) {
3355 txreg
= NVREG_TX_WM_DESC1_DEFAULT
;
3357 if ((np
->linkspeed
& NVREG_LINKSPEED_MASK
) == NVREG_LINKSPEED_1000
)
3358 txreg
= NVREG_TX_WM_DESC2_3_1000
;
3360 txreg
= NVREG_TX_WM_DESC2_3_DEFAULT
;
3362 writel(txreg
, base
+ NvRegTxWatermark
);
3364 writel(NVREG_MISC1_FORCE
| ( np
->duplex
? 0 : NVREG_MISC1_HD
),
3367 writel(np
->linkspeed
, base
+ NvRegLinkSpeed
);
3371 /* setup pause frame */
3372 if (np
->duplex
!= 0) {
3373 if (np
->autoneg
&& np
->pause_flags
& NV_PAUSEFRAME_AUTONEG
) {
3374 adv_pause
= adv
& (ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
3375 lpa_pause
= lpa
& (LPA_PAUSE_CAP
| LPA_PAUSE_ASYM
);
3377 switch (adv_pause
) {
3378 case ADVERTISE_PAUSE_CAP
:
3379 if (lpa_pause
& LPA_PAUSE_CAP
) {
3380 pause_flags
|= NV_PAUSEFRAME_RX_ENABLE
;
3381 if (np
->pause_flags
& NV_PAUSEFRAME_TX_REQ
)
3382 pause_flags
|= NV_PAUSEFRAME_TX_ENABLE
;
3385 case ADVERTISE_PAUSE_ASYM
:
3386 if (lpa_pause
== (LPA_PAUSE_CAP
| LPA_PAUSE_ASYM
))
3388 pause_flags
|= NV_PAUSEFRAME_TX_ENABLE
;
3391 case ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
:
3392 if (lpa_pause
& LPA_PAUSE_CAP
)
3394 pause_flags
|= NV_PAUSEFRAME_RX_ENABLE
;
3395 if (np
->pause_flags
& NV_PAUSEFRAME_TX_REQ
)
3396 pause_flags
|= NV_PAUSEFRAME_TX_ENABLE
;
3398 if (lpa_pause
== LPA_PAUSE_ASYM
)
3400 pause_flags
|= NV_PAUSEFRAME_RX_ENABLE
;
3405 pause_flags
= np
->pause_flags
;
3408 nv_update_pause(dev
, pause_flags
);
3410 if (txrxFlags
& NV_RESTART_TX
)
3412 if (txrxFlags
& NV_RESTART_RX
)
3418 static void nv_linkchange(struct net_device
*dev
)
3420 if (nv_update_linkspeed(dev
)) {
3421 if (!netif_carrier_ok(dev
)) {
3422 netif_carrier_on(dev
);
3423 printk(KERN_INFO
"%s: link up.\n", dev
->name
);
3424 nv_txrx_gate(dev
, false);
3428 if (netif_carrier_ok(dev
)) {
3429 netif_carrier_off(dev
);
3430 printk(KERN_INFO
"%s: link down.\n", dev
->name
);
3431 nv_txrx_gate(dev
, true);
3437 static void nv_link_irq(struct net_device
*dev
)
3439 u8 __iomem
*base
= get_hwbase(dev
);
3442 miistat
= readl(base
+ NvRegMIIStatus
);
3443 writel(NVREG_MIISTAT_LINKCHANGE
, base
+ NvRegMIIStatus
);
3444 dprintk(KERN_INFO
"%s: link change irq, status 0x%x.\n", dev
->name
, miistat
);
3446 if (miistat
& (NVREG_MIISTAT_LINKCHANGE
))
3448 dprintk(KERN_DEBUG
"%s: link change notification done.\n", dev
->name
);
3451 static void nv_msi_workaround(struct fe_priv
*np
)
3454 /* Need to toggle the msi irq mask within the ethernet device,
3455 * otherwise, future interrupts will not be detected.
3457 if (np
->msi_flags
& NV_MSI_ENABLED
) {
3458 u8 __iomem
*base
= np
->base
;
3460 writel(0, base
+ NvRegMSIIrqMask
);
3461 writel(NVREG_MSI_VECTOR_0_ENABLED
, base
+ NvRegMSIIrqMask
);
3465 static inline int nv_change_interrupt_mode(struct net_device
*dev
, int total_work
)
3467 struct fe_priv
*np
= netdev_priv(dev
);
3469 if (optimization_mode
== NV_OPTIMIZATION_MODE_DYNAMIC
) {
3470 if (total_work
> NV_DYNAMIC_THRESHOLD
) {
3471 /* transition to poll based interrupts */
3472 np
->quiet_count
= 0;
3473 if (np
->irqmask
!= NVREG_IRQMASK_CPU
) {
3474 np
->irqmask
= NVREG_IRQMASK_CPU
;
3478 if (np
->quiet_count
< NV_DYNAMIC_MAX_QUIET_COUNT
) {
3481 /* reached a period of low activity, switch
3482 to per tx/rx packet interrupts */
3483 if (np
->irqmask
!= NVREG_IRQMASK_THROUGHPUT
) {
3484 np
->irqmask
= NVREG_IRQMASK_THROUGHPUT
;
3493 static irqreturn_t
nv_nic_irq(int foo
, void *data
)
3495 struct net_device
*dev
= (struct net_device
*) data
;
3496 struct fe_priv
*np
= netdev_priv(dev
);
3497 u8 __iomem
*base
= get_hwbase(dev
);
3498 #ifndef CONFIG_FORCEDETH_NAPI
3503 dprintk(KERN_DEBUG
"%s: nv_nic_irq\n", dev
->name
);
3505 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
)) {
3506 np
->events
= readl(base
+ NvRegIrqStatus
);
3507 writel(np
->events
, base
+ NvRegIrqStatus
);
3509 np
->events
= readl(base
+ NvRegMSIXIrqStatus
);
3510 writel(np
->events
, base
+ NvRegMSIXIrqStatus
);
3512 dprintk(KERN_DEBUG
"%s: irq: %08x\n", dev
->name
, np
->events
);
3513 if (!(np
->events
& np
->irqmask
))
3516 nv_msi_workaround(np
);
3518 #ifdef CONFIG_FORCEDETH_NAPI
3519 napi_schedule(&np
->napi
);
3521 /* Disable furthur irq's
3522 (msix not enabled with napi) */
3523 writel(0, base
+ NvRegIrqMask
);
3529 if ((work
= nv_rx_process(dev
, RX_WORK_PER_LOOP
))) {
3530 if (unlikely(nv_alloc_rx(dev
))) {
3531 spin_lock(&np
->lock
);
3532 if (!np
->in_shutdown
)
3533 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
3534 spin_unlock(&np
->lock
);
3538 spin_lock(&np
->lock
);
3539 work
+= nv_tx_done(dev
, TX_WORK_PER_LOOP
);
3540 spin_unlock(&np
->lock
);
3549 while (loop_count
< max_interrupt_work
);
3551 if (nv_change_interrupt_mode(dev
, total_work
)) {
3552 /* setup new irq mask */
3553 writel(np
->irqmask
, base
+ NvRegIrqMask
);
3556 if (unlikely(np
->events
& NVREG_IRQ_LINK
)) {
3557 spin_lock(&np
->lock
);
3559 spin_unlock(&np
->lock
);
3561 if (unlikely(np
->need_linktimer
&& time_after(jiffies
, np
->link_timeout
))) {
3562 spin_lock(&np
->lock
);
3564 spin_unlock(&np
->lock
);
3565 np
->link_timeout
= jiffies
+ LINK_TIMEOUT
;
3567 if (unlikely(np
->events
& NVREG_IRQ_RECOVER_ERROR
)) {
3568 spin_lock(&np
->lock
);
3569 /* disable interrupts on the nic */
3570 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
))
3571 writel(0, base
+ NvRegIrqMask
);
3573 writel(np
->irqmask
, base
+ NvRegIrqMask
);
3576 if (!np
->in_shutdown
) {
3577 np
->nic_poll_irq
= np
->irqmask
;
3578 np
->recover_error
= 1;
3579 mod_timer(&np
->nic_poll
, jiffies
+ POLL_WAIT
);
3581 spin_unlock(&np
->lock
);
3584 dprintk(KERN_DEBUG
"%s: nv_nic_irq completed\n", dev
->name
);
3590 * All _optimized functions are used to help increase performance
3591 * (reduce CPU and increase throughput). They use descripter version 3,
3592 * compiler directives, and reduce memory accesses.
3594 static irqreturn_t
nv_nic_irq_optimized(int foo
, void *data
)
3596 struct net_device
*dev
= (struct net_device
*) data
;
3597 struct fe_priv
*np
= netdev_priv(dev
);
3598 u8 __iomem
*base
= get_hwbase(dev
);
3599 #ifndef CONFIG_FORCEDETH_NAPI
3604 dprintk(KERN_DEBUG
"%s: nv_nic_irq_optimized\n", dev
->name
);
3606 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
)) {
3607 np
->events
= readl(base
+ NvRegIrqStatus
);
3608 writel(np
->events
, base
+ NvRegIrqStatus
);
3610 np
->events
= readl(base
+ NvRegMSIXIrqStatus
);
3611 writel(np
->events
, base
+ NvRegMSIXIrqStatus
);
3613 dprintk(KERN_DEBUG
"%s: irq: %08x\n", dev
->name
, np
->events
);
3614 if (!(np
->events
& np
->irqmask
))
3617 nv_msi_workaround(np
);
3619 #ifdef CONFIG_FORCEDETH_NAPI
3620 napi_schedule(&np
->napi
);
3622 /* Disable furthur irq's
3623 (msix not enabled with napi) */
3624 writel(0, base
+ NvRegIrqMask
);
3630 if ((work
= nv_rx_process_optimized(dev
, RX_WORK_PER_LOOP
))) {
3631 if (unlikely(nv_alloc_rx_optimized(dev
))) {
3632 spin_lock(&np
->lock
);
3633 if (!np
->in_shutdown
)
3634 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
3635 spin_unlock(&np
->lock
);
3639 spin_lock(&np
->lock
);
3640 work
+= nv_tx_done_optimized(dev
, TX_WORK_PER_LOOP
);
3641 spin_unlock(&np
->lock
);
3650 while (loop_count
< max_interrupt_work
);
3652 if (nv_change_interrupt_mode(dev
, total_work
)) {
3653 /* setup new irq mask */
3654 writel(np
->irqmask
, base
+ NvRegIrqMask
);
3657 if (unlikely(np
->events
& NVREG_IRQ_LINK
)) {
3658 spin_lock(&np
->lock
);
3660 spin_unlock(&np
->lock
);
3662 if (unlikely(np
->need_linktimer
&& time_after(jiffies
, np
->link_timeout
))) {
3663 spin_lock(&np
->lock
);
3665 spin_unlock(&np
->lock
);
3666 np
->link_timeout
= jiffies
+ LINK_TIMEOUT
;
3668 if (unlikely(np
->events
& NVREG_IRQ_RECOVER_ERROR
)) {
3669 spin_lock(&np
->lock
);
3670 /* disable interrupts on the nic */
3671 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
))
3672 writel(0, base
+ NvRegIrqMask
);
3674 writel(np
->irqmask
, base
+ NvRegIrqMask
);
3677 if (!np
->in_shutdown
) {
3678 np
->nic_poll_irq
= np
->irqmask
;
3679 np
->recover_error
= 1;
3680 mod_timer(&np
->nic_poll
, jiffies
+ POLL_WAIT
);
3682 spin_unlock(&np
->lock
);
3686 dprintk(KERN_DEBUG
"%s: nv_nic_irq_optimized completed\n", dev
->name
);
3691 static irqreturn_t
nv_nic_irq_tx(int foo
, void *data
)
3693 struct net_device
*dev
= (struct net_device
*) data
;
3694 struct fe_priv
*np
= netdev_priv(dev
);
3695 u8 __iomem
*base
= get_hwbase(dev
);
3698 unsigned long flags
;
3700 dprintk(KERN_DEBUG
"%s: nv_nic_irq_tx\n", dev
->name
);
3703 events
= readl(base
+ NvRegMSIXIrqStatus
) & NVREG_IRQ_TX_ALL
;
3704 writel(NVREG_IRQ_TX_ALL
, base
+ NvRegMSIXIrqStatus
);
3705 dprintk(KERN_DEBUG
"%s: tx irq: %08x\n", dev
->name
, events
);
3706 if (!(events
& np
->irqmask
))
3709 spin_lock_irqsave(&np
->lock
, flags
);
3710 nv_tx_done_optimized(dev
, TX_WORK_PER_LOOP
);
3711 spin_unlock_irqrestore(&np
->lock
, flags
);
3713 if (unlikely(i
> max_interrupt_work
)) {
3714 spin_lock_irqsave(&np
->lock
, flags
);
3715 /* disable interrupts on the nic */
3716 writel(NVREG_IRQ_TX_ALL
, base
+ NvRegIrqMask
);
3719 if (!np
->in_shutdown
) {
3720 np
->nic_poll_irq
|= NVREG_IRQ_TX_ALL
;
3721 mod_timer(&np
->nic_poll
, jiffies
+ POLL_WAIT
);
3723 spin_unlock_irqrestore(&np
->lock
, flags
);
3724 printk(KERN_DEBUG
"%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev
->name
, i
);
3729 dprintk(KERN_DEBUG
"%s: nv_nic_irq_tx completed\n", dev
->name
);
3731 return IRQ_RETVAL(i
);
3734 #ifdef CONFIG_FORCEDETH_NAPI
3735 static int nv_napi_poll(struct napi_struct
*napi
, int budget
)
3737 struct fe_priv
*np
= container_of(napi
, struct fe_priv
, napi
);
3738 struct net_device
*dev
= np
->dev
;
3739 u8 __iomem
*base
= get_hwbase(dev
);
3740 unsigned long flags
;
3742 int tx_work
, rx_work
;
3744 if (!nv_optimized(np
)) {
3745 spin_lock_irqsave(&np
->lock
, flags
);
3746 tx_work
= nv_tx_done(dev
, np
->tx_ring_size
);
3747 spin_unlock_irqrestore(&np
->lock
, flags
);
3749 rx_work
= nv_rx_process(dev
, budget
);
3750 retcode
= nv_alloc_rx(dev
);
3752 spin_lock_irqsave(&np
->lock
, flags
);
3753 tx_work
= nv_tx_done_optimized(dev
, np
->tx_ring_size
);
3754 spin_unlock_irqrestore(&np
->lock
, flags
);
3756 rx_work
= nv_rx_process_optimized(dev
, budget
);
3757 retcode
= nv_alloc_rx_optimized(dev
);
3761 spin_lock_irqsave(&np
->lock
, flags
);
3762 if (!np
->in_shutdown
)
3763 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
3764 spin_unlock_irqrestore(&np
->lock
, flags
);
3767 nv_change_interrupt_mode(dev
, tx_work
+ rx_work
);
3769 if (unlikely(np
->events
& NVREG_IRQ_LINK
)) {
3770 spin_lock_irqsave(&np
->lock
, flags
);
3772 spin_unlock_irqrestore(&np
->lock
, flags
);
3774 if (unlikely(np
->need_linktimer
&& time_after(jiffies
, np
->link_timeout
))) {
3775 spin_lock_irqsave(&np
->lock
, flags
);
3777 spin_unlock_irqrestore(&np
->lock
, flags
);
3778 np
->link_timeout
= jiffies
+ LINK_TIMEOUT
;
3780 if (unlikely(np
->events
& NVREG_IRQ_RECOVER_ERROR
)) {
3781 spin_lock_irqsave(&np
->lock
, flags
);
3782 if (!np
->in_shutdown
) {
3783 np
->nic_poll_irq
= np
->irqmask
;
3784 np
->recover_error
= 1;
3785 mod_timer(&np
->nic_poll
, jiffies
+ POLL_WAIT
);
3787 spin_unlock_irqrestore(&np
->lock
, flags
);
3788 napi_complete(napi
);
3792 if (rx_work
< budget
) {
3793 /* re-enable interrupts
3794 (msix not enabled in napi) */
3795 napi_complete(napi
);
3797 writel(np
->irqmask
, base
+ NvRegIrqMask
);
3803 static irqreturn_t
nv_nic_irq_rx(int foo
, void *data
)
3805 struct net_device
*dev
= (struct net_device
*) data
;
3806 struct fe_priv
*np
= netdev_priv(dev
);
3807 u8 __iomem
*base
= get_hwbase(dev
);
3810 unsigned long flags
;
3812 dprintk(KERN_DEBUG
"%s: nv_nic_irq_rx\n", dev
->name
);
3815 events
= readl(base
+ NvRegMSIXIrqStatus
) & NVREG_IRQ_RX_ALL
;
3816 writel(NVREG_IRQ_RX_ALL
, base
+ NvRegMSIXIrqStatus
);
3817 dprintk(KERN_DEBUG
"%s: rx irq: %08x\n", dev
->name
, events
);
3818 if (!(events
& np
->irqmask
))
3821 if (nv_rx_process_optimized(dev
, RX_WORK_PER_LOOP
)) {
3822 if (unlikely(nv_alloc_rx_optimized(dev
))) {
3823 spin_lock_irqsave(&np
->lock
, flags
);
3824 if (!np
->in_shutdown
)
3825 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
3826 spin_unlock_irqrestore(&np
->lock
, flags
);
3830 if (unlikely(i
> max_interrupt_work
)) {
3831 spin_lock_irqsave(&np
->lock
, flags
);
3832 /* disable interrupts on the nic */
3833 writel(NVREG_IRQ_RX_ALL
, base
+ NvRegIrqMask
);
3836 if (!np
->in_shutdown
) {
3837 np
->nic_poll_irq
|= NVREG_IRQ_RX_ALL
;
3838 mod_timer(&np
->nic_poll
, jiffies
+ POLL_WAIT
);
3840 spin_unlock_irqrestore(&np
->lock
, flags
);
3841 printk(KERN_DEBUG
"%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev
->name
, i
);
3845 dprintk(KERN_DEBUG
"%s: nv_nic_irq_rx completed\n", dev
->name
);
3847 return IRQ_RETVAL(i
);
3850 static irqreturn_t
nv_nic_irq_other(int foo
, void *data
)
3852 struct net_device
*dev
= (struct net_device
*) data
;
3853 struct fe_priv
*np
= netdev_priv(dev
);
3854 u8 __iomem
*base
= get_hwbase(dev
);
3857 unsigned long flags
;
3859 dprintk(KERN_DEBUG
"%s: nv_nic_irq_other\n", dev
->name
);
3862 events
= readl(base
+ NvRegMSIXIrqStatus
) & NVREG_IRQ_OTHER
;
3863 writel(NVREG_IRQ_OTHER
, base
+ NvRegMSIXIrqStatus
);
3864 dprintk(KERN_DEBUG
"%s: irq: %08x\n", dev
->name
, events
);
3865 if (!(events
& np
->irqmask
))
3868 /* check tx in case we reached max loop limit in tx isr */
3869 spin_lock_irqsave(&np
->lock
, flags
);
3870 nv_tx_done_optimized(dev
, TX_WORK_PER_LOOP
);
3871 spin_unlock_irqrestore(&np
->lock
, flags
);
3873 if (events
& NVREG_IRQ_LINK
) {
3874 spin_lock_irqsave(&np
->lock
, flags
);
3876 spin_unlock_irqrestore(&np
->lock
, flags
);
3878 if (np
->need_linktimer
&& time_after(jiffies
, np
->link_timeout
)) {
3879 spin_lock_irqsave(&np
->lock
, flags
);
3881 spin_unlock_irqrestore(&np
->lock
, flags
);
3882 np
->link_timeout
= jiffies
+ LINK_TIMEOUT
;
3884 if (events
& NVREG_IRQ_RECOVER_ERROR
) {
3885 spin_lock_irq(&np
->lock
);
3886 /* disable interrupts on the nic */
3887 writel(NVREG_IRQ_OTHER
, base
+ NvRegIrqMask
);
3890 if (!np
->in_shutdown
) {
3891 np
->nic_poll_irq
|= NVREG_IRQ_OTHER
;
3892 np
->recover_error
= 1;
3893 mod_timer(&np
->nic_poll
, jiffies
+ POLL_WAIT
);
3895 spin_unlock_irq(&np
->lock
);
3898 if (unlikely(i
> max_interrupt_work
)) {
3899 spin_lock_irqsave(&np
->lock
, flags
);
3900 /* disable interrupts on the nic */
3901 writel(NVREG_IRQ_OTHER
, base
+ NvRegIrqMask
);
3904 if (!np
->in_shutdown
) {
3905 np
->nic_poll_irq
|= NVREG_IRQ_OTHER
;
3906 mod_timer(&np
->nic_poll
, jiffies
+ POLL_WAIT
);
3908 spin_unlock_irqrestore(&np
->lock
, flags
);
3909 printk(KERN_DEBUG
"%s: too many iterations (%d) in nv_nic_irq_other.\n", dev
->name
, i
);
3914 dprintk(KERN_DEBUG
"%s: nv_nic_irq_other completed\n", dev
->name
);
3916 return IRQ_RETVAL(i
);
3919 static irqreturn_t
nv_nic_irq_test(int foo
, void *data
)
3921 struct net_device
*dev
= (struct net_device
*) data
;
3922 struct fe_priv
*np
= netdev_priv(dev
);
3923 u8 __iomem
*base
= get_hwbase(dev
);
3926 dprintk(KERN_DEBUG
"%s: nv_nic_irq_test\n", dev
->name
);
3928 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
)) {
3929 events
= readl(base
+ NvRegIrqStatus
) & NVREG_IRQSTAT_MASK
;
3930 writel(NVREG_IRQ_TIMER
, base
+ NvRegIrqStatus
);
3932 events
= readl(base
+ NvRegMSIXIrqStatus
) & NVREG_IRQSTAT_MASK
;
3933 writel(NVREG_IRQ_TIMER
, base
+ NvRegMSIXIrqStatus
);
3936 dprintk(KERN_DEBUG
"%s: irq: %08x\n", dev
->name
, events
);
3937 if (!(events
& NVREG_IRQ_TIMER
))
3938 return IRQ_RETVAL(0);
3940 nv_msi_workaround(np
);
3942 spin_lock(&np
->lock
);
3944 spin_unlock(&np
->lock
);
3946 dprintk(KERN_DEBUG
"%s: nv_nic_irq_test completed\n", dev
->name
);
3948 return IRQ_RETVAL(1);
3951 static void set_msix_vector_map(struct net_device
*dev
, u32 vector
, u32 irqmask
)
3953 u8 __iomem
*base
= get_hwbase(dev
);
3957 /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
3958 * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
3959 * the remaining 8 interrupts.
3961 for (i
= 0; i
< 8; i
++) {
3962 if ((irqmask
>> i
) & 0x1) {
3963 msixmap
|= vector
<< (i
<< 2);
3966 writel(readl(base
+ NvRegMSIXMap0
) | msixmap
, base
+ NvRegMSIXMap0
);
3969 for (i
= 0; i
< 8; i
++) {
3970 if ((irqmask
>> (i
+ 8)) & 0x1) {
3971 msixmap
|= vector
<< (i
<< 2);
3974 writel(readl(base
+ NvRegMSIXMap1
) | msixmap
, base
+ NvRegMSIXMap1
);
3977 static int nv_request_irq(struct net_device
*dev
, int intr_test
)
3979 struct fe_priv
*np
= get_nvpriv(dev
);
3980 u8 __iomem
*base
= get_hwbase(dev
);
3983 irqreturn_t (*handler
)(int foo
, void *data
);
3986 handler
= nv_nic_irq_test
;
3988 if (nv_optimized(np
))
3989 handler
= nv_nic_irq_optimized
;
3991 handler
= nv_nic_irq
;
3994 if (np
->msi_flags
& NV_MSI_X_CAPABLE
) {
3995 for (i
= 0; i
< (np
->msi_flags
& NV_MSI_X_VECTORS_MASK
); i
++) {
3996 np
->msi_x_entry
[i
].entry
= i
;
3998 if ((ret
= pci_enable_msix(np
->pci_dev
, np
->msi_x_entry
, (np
->msi_flags
& NV_MSI_X_VECTORS_MASK
))) == 0) {
3999 np
->msi_flags
|= NV_MSI_X_ENABLED
;
4000 if (optimization_mode
== NV_OPTIMIZATION_MODE_THROUGHPUT
&& !intr_test
) {
4001 /* Request irq for rx handling */
4002 sprintf(np
->name_rx
, "%s-rx", dev
->name
);
4003 if (request_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
,
4004 &nv_nic_irq_rx
, IRQF_SHARED
, np
->name_rx
, dev
) != 0) {
4005 printk(KERN_INFO
"forcedeth: request_irq failed for rx %d\n", ret
);
4006 pci_disable_msix(np
->pci_dev
);
4007 np
->msi_flags
&= ~NV_MSI_X_ENABLED
;
4010 /* Request irq for tx handling */
4011 sprintf(np
->name_tx
, "%s-tx", dev
->name
);
4012 if (request_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_TX
].vector
,
4013 &nv_nic_irq_tx
, IRQF_SHARED
, np
->name_tx
, dev
) != 0) {
4014 printk(KERN_INFO
"forcedeth: request_irq failed for tx %d\n", ret
);
4015 pci_disable_msix(np
->pci_dev
);
4016 np
->msi_flags
&= ~NV_MSI_X_ENABLED
;
4019 /* Request irq for link and timer handling */
4020 sprintf(np
->name_other
, "%s-other", dev
->name
);
4021 if (request_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_OTHER
].vector
,
4022 &nv_nic_irq_other
, IRQF_SHARED
, np
->name_other
, dev
) != 0) {
4023 printk(KERN_INFO
"forcedeth: request_irq failed for link %d\n", ret
);
4024 pci_disable_msix(np
->pci_dev
);
4025 np
->msi_flags
&= ~NV_MSI_X_ENABLED
;
4028 /* map interrupts to their respective vector */
4029 writel(0, base
+ NvRegMSIXMap0
);
4030 writel(0, base
+ NvRegMSIXMap1
);
4031 set_msix_vector_map(dev
, NV_MSI_X_VECTOR_RX
, NVREG_IRQ_RX_ALL
);
4032 set_msix_vector_map(dev
, NV_MSI_X_VECTOR_TX
, NVREG_IRQ_TX_ALL
);
4033 set_msix_vector_map(dev
, NV_MSI_X_VECTOR_OTHER
, NVREG_IRQ_OTHER
);
4035 /* Request irq for all interrupts */
4036 if (request_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_ALL
].vector
, handler
, IRQF_SHARED
, dev
->name
, dev
) != 0) {
4037 printk(KERN_INFO
"forcedeth: request_irq failed %d\n", ret
);
4038 pci_disable_msix(np
->pci_dev
);
4039 np
->msi_flags
&= ~NV_MSI_X_ENABLED
;
4043 /* map interrupts to vector 0 */
4044 writel(0, base
+ NvRegMSIXMap0
);
4045 writel(0, base
+ NvRegMSIXMap1
);
4049 if (ret
!= 0 && np
->msi_flags
& NV_MSI_CAPABLE
) {
4050 if ((ret
= pci_enable_msi(np
->pci_dev
)) == 0) {
4051 np
->msi_flags
|= NV_MSI_ENABLED
;
4052 dev
->irq
= np
->pci_dev
->irq
;
4053 if (request_irq(np
->pci_dev
->irq
, handler
, IRQF_SHARED
, dev
->name
, dev
) != 0) {
4054 printk(KERN_INFO
"forcedeth: request_irq failed %d\n", ret
);
4055 pci_disable_msi(np
->pci_dev
);
4056 np
->msi_flags
&= ~NV_MSI_ENABLED
;
4057 dev
->irq
= np
->pci_dev
->irq
;
4061 /* map interrupts to vector 0 */
4062 writel(0, base
+ NvRegMSIMap0
);
4063 writel(0, base
+ NvRegMSIMap1
);
4064 /* enable msi vector 0 */
4065 writel(NVREG_MSI_VECTOR_0_ENABLED
, base
+ NvRegMSIIrqMask
);
4069 if (request_irq(np
->pci_dev
->irq
, handler
, IRQF_SHARED
, dev
->name
, dev
) != 0)
4076 free_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_TX
].vector
, dev
);
4078 free_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
, dev
);
4083 static void nv_free_irq(struct net_device
*dev
)
4085 struct fe_priv
*np
= get_nvpriv(dev
);
4088 if (np
->msi_flags
& NV_MSI_X_ENABLED
) {
4089 for (i
= 0; i
< (np
->msi_flags
& NV_MSI_X_VECTORS_MASK
); i
++) {
4090 free_irq(np
->msi_x_entry
[i
].vector
, dev
);
4092 pci_disable_msix(np
->pci_dev
);
4093 np
->msi_flags
&= ~NV_MSI_X_ENABLED
;
4095 free_irq(np
->pci_dev
->irq
, dev
);
4096 if (np
->msi_flags
& NV_MSI_ENABLED
) {
4097 pci_disable_msi(np
->pci_dev
);
4098 np
->msi_flags
&= ~NV_MSI_ENABLED
;
4103 static void nv_do_nic_poll(unsigned long data
)
4105 struct net_device
*dev
= (struct net_device
*) data
;
4106 struct fe_priv
*np
= netdev_priv(dev
);
4107 u8 __iomem
*base
= get_hwbase(dev
);
4111 * First disable irq(s) and then
4112 * reenable interrupts on the nic, we have to do this before calling
4113 * nv_nic_irq because that may decide to do otherwise
4116 if (!using_multi_irqs(dev
)) {
4117 if (np
->msi_flags
& NV_MSI_X_ENABLED
)
4118 disable_irq_lockdep(np
->msi_x_entry
[NV_MSI_X_VECTOR_ALL
].vector
);
4120 disable_irq_lockdep(np
->pci_dev
->irq
);
4123 if (np
->nic_poll_irq
& NVREG_IRQ_RX_ALL
) {
4124 disable_irq_lockdep(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
);
4125 mask
|= NVREG_IRQ_RX_ALL
;
4127 if (np
->nic_poll_irq
& NVREG_IRQ_TX_ALL
) {
4128 disable_irq_lockdep(np
->msi_x_entry
[NV_MSI_X_VECTOR_TX
].vector
);
4129 mask
|= NVREG_IRQ_TX_ALL
;
4131 if (np
->nic_poll_irq
& NVREG_IRQ_OTHER
) {
4132 disable_irq_lockdep(np
->msi_x_entry
[NV_MSI_X_VECTOR_OTHER
].vector
);
4133 mask
|= NVREG_IRQ_OTHER
;
4136 /* disable_irq() contains synchronize_irq, thus no irq handler can run now */
4138 if (np
->recover_error
) {
4139 np
->recover_error
= 0;
4140 printk(KERN_INFO
"%s: MAC in recoverable error state\n", dev
->name
);
4141 if (netif_running(dev
)) {
4142 netif_tx_lock_bh(dev
);
4143 netif_addr_lock(dev
);
4144 spin_lock(&np
->lock
);
4147 if (np
->driver_data
& DEV_HAS_POWER_CNTRL
)
4150 /* drain rx queue */
4152 /* reinit driver view of the rx queue */
4154 if (nv_init_ring(dev
)) {
4155 if (!np
->in_shutdown
)
4156 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
4158 /* reinit nic view of the rx queue */
4159 writel(np
->rx_buf_sz
, base
+ NvRegOffloadConfig
);
4160 setup_hw_rings(dev
, NV_SETUP_RX_RING
| NV_SETUP_TX_RING
);
4161 writel( ((np
->rx_ring_size
-1) << NVREG_RINGSZ_RXSHIFT
) + ((np
->tx_ring_size
-1) << NVREG_RINGSZ_TXSHIFT
),
4162 base
+ NvRegRingSizes
);
4164 writel(NVREG_TXRXCTL_KICK
|np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
4166 /* clear interrupts */
4167 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
))
4168 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegIrqStatus
);
4170 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegMSIXIrqStatus
);
4172 /* restart rx engine */
4174 spin_unlock(&np
->lock
);
4175 netif_addr_unlock(dev
);
4176 netif_tx_unlock_bh(dev
);
4180 writel(mask
, base
+ NvRegIrqMask
);
4183 if (!using_multi_irqs(dev
)) {
4184 np
->nic_poll_irq
= 0;
4185 if (nv_optimized(np
))
4186 nv_nic_irq_optimized(0, dev
);
4189 if (np
->msi_flags
& NV_MSI_X_ENABLED
)
4190 enable_irq_lockdep(np
->msi_x_entry
[NV_MSI_X_VECTOR_ALL
].vector
);
4192 enable_irq_lockdep(np
->pci_dev
->irq
);
4194 if (np
->nic_poll_irq
& NVREG_IRQ_RX_ALL
) {
4195 np
->nic_poll_irq
&= ~NVREG_IRQ_RX_ALL
;
4196 nv_nic_irq_rx(0, dev
);
4197 enable_irq_lockdep(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
);
4199 if (np
->nic_poll_irq
& NVREG_IRQ_TX_ALL
) {
4200 np
->nic_poll_irq
&= ~NVREG_IRQ_TX_ALL
;
4201 nv_nic_irq_tx(0, dev
);
4202 enable_irq_lockdep(np
->msi_x_entry
[NV_MSI_X_VECTOR_TX
].vector
);
4204 if (np
->nic_poll_irq
& NVREG_IRQ_OTHER
) {
4205 np
->nic_poll_irq
&= ~NVREG_IRQ_OTHER
;
4206 nv_nic_irq_other(0, dev
);
4207 enable_irq_lockdep(np
->msi_x_entry
[NV_MSI_X_VECTOR_OTHER
].vector
);
4213 #ifdef CONFIG_NET_POLL_CONTROLLER
4214 static void nv_poll_controller(struct net_device
*dev
)
4216 nv_do_nic_poll((unsigned long) dev
);
4220 static void nv_do_stats_poll(unsigned long data
)
4222 struct net_device
*dev
= (struct net_device
*) data
;
4223 struct fe_priv
*np
= netdev_priv(dev
);
4225 nv_get_hw_stats(dev
);
4227 if (!np
->in_shutdown
)
4228 mod_timer(&np
->stats_poll
,
4229 round_jiffies(jiffies
+ STATS_INTERVAL
));
4232 static void nv_get_drvinfo(struct net_device
*dev
, struct ethtool_drvinfo
*info
)
4234 struct fe_priv
*np
= netdev_priv(dev
);
4235 strcpy(info
->driver
, DRV_NAME
);
4236 strcpy(info
->version
, FORCEDETH_VERSION
);
4237 strcpy(info
->bus_info
, pci_name(np
->pci_dev
));
4240 static void nv_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wolinfo
)
4242 struct fe_priv
*np
= netdev_priv(dev
);
4243 wolinfo
->supported
= WAKE_MAGIC
;
4245 spin_lock_irq(&np
->lock
);
4247 wolinfo
->wolopts
= WAKE_MAGIC
;
4248 spin_unlock_irq(&np
->lock
);
4251 static int nv_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wolinfo
)
4253 struct fe_priv
*np
= netdev_priv(dev
);
4254 u8 __iomem
*base
= get_hwbase(dev
);
4257 if (wolinfo
->wolopts
== 0) {
4259 } else if (wolinfo
->wolopts
& WAKE_MAGIC
) {
4261 flags
= NVREG_WAKEUPFLAGS_ENABLE
;
4263 if (netif_running(dev
)) {
4264 spin_lock_irq(&np
->lock
);
4265 writel(flags
, base
+ NvRegWakeUpFlags
);
4266 spin_unlock_irq(&np
->lock
);
4271 static int nv_get_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
4273 struct fe_priv
*np
= netdev_priv(dev
);
4276 spin_lock_irq(&np
->lock
);
4277 ecmd
->port
= PORT_MII
;
4278 if (!netif_running(dev
)) {
4279 /* We do not track link speed / duplex setting if the
4280 * interface is disabled. Force a link check */
4281 if (nv_update_linkspeed(dev
)) {
4282 if (!netif_carrier_ok(dev
))
4283 netif_carrier_on(dev
);
4285 if (netif_carrier_ok(dev
))
4286 netif_carrier_off(dev
);
4290 if (netif_carrier_ok(dev
)) {
4291 switch(np
->linkspeed
& (NVREG_LINKSPEED_MASK
)) {
4292 case NVREG_LINKSPEED_10
:
4293 ecmd
->speed
= SPEED_10
;
4295 case NVREG_LINKSPEED_100
:
4296 ecmd
->speed
= SPEED_100
;
4298 case NVREG_LINKSPEED_1000
:
4299 ecmd
->speed
= SPEED_1000
;
4302 ecmd
->duplex
= DUPLEX_HALF
;
4304 ecmd
->duplex
= DUPLEX_FULL
;
4310 ecmd
->autoneg
= np
->autoneg
;
4312 ecmd
->advertising
= ADVERTISED_MII
;
4314 ecmd
->advertising
|= ADVERTISED_Autoneg
;
4315 adv
= mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, MII_READ
);
4316 if (adv
& ADVERTISE_10HALF
)
4317 ecmd
->advertising
|= ADVERTISED_10baseT_Half
;
4318 if (adv
& ADVERTISE_10FULL
)
4319 ecmd
->advertising
|= ADVERTISED_10baseT_Full
;
4320 if (adv
& ADVERTISE_100HALF
)
4321 ecmd
->advertising
|= ADVERTISED_100baseT_Half
;
4322 if (adv
& ADVERTISE_100FULL
)
4323 ecmd
->advertising
|= ADVERTISED_100baseT_Full
;
4324 if (np
->gigabit
== PHY_GIGABIT
) {
4325 adv
= mii_rw(dev
, np
->phyaddr
, MII_CTRL1000
, MII_READ
);
4326 if (adv
& ADVERTISE_1000FULL
)
4327 ecmd
->advertising
|= ADVERTISED_1000baseT_Full
;
4330 ecmd
->supported
= (SUPPORTED_Autoneg
|
4331 SUPPORTED_10baseT_Half
| SUPPORTED_10baseT_Full
|
4332 SUPPORTED_100baseT_Half
| SUPPORTED_100baseT_Full
|
4334 if (np
->gigabit
== PHY_GIGABIT
)
4335 ecmd
->supported
|= SUPPORTED_1000baseT_Full
;
4337 ecmd
->phy_address
= np
->phyaddr
;
4338 ecmd
->transceiver
= XCVR_EXTERNAL
;
4340 /* ignore maxtxpkt, maxrxpkt for now */
4341 spin_unlock_irq(&np
->lock
);
4345 static int nv_set_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
4347 struct fe_priv
*np
= netdev_priv(dev
);
4349 if (ecmd
->port
!= PORT_MII
)
4351 if (ecmd
->transceiver
!= XCVR_EXTERNAL
)
4353 if (ecmd
->phy_address
!= np
->phyaddr
) {
4354 /* TODO: support switching between multiple phys. Should be
4355 * trivial, but not enabled due to lack of test hardware. */
4358 if (ecmd
->autoneg
== AUTONEG_ENABLE
) {
4361 mask
= ADVERTISED_10baseT_Half
| ADVERTISED_10baseT_Full
|
4362 ADVERTISED_100baseT_Half
| ADVERTISED_100baseT_Full
;
4363 if (np
->gigabit
== PHY_GIGABIT
)
4364 mask
|= ADVERTISED_1000baseT_Full
;
4366 if ((ecmd
->advertising
& mask
) == 0)
4369 } else if (ecmd
->autoneg
== AUTONEG_DISABLE
) {
4370 /* Note: autonegotiation disable, speed 1000 intentionally
4371 * forbidden - noone should need that. */
4373 if (ecmd
->speed
!= SPEED_10
&& ecmd
->speed
!= SPEED_100
)
4375 if (ecmd
->duplex
!= DUPLEX_HALF
&& ecmd
->duplex
!= DUPLEX_FULL
)
4381 netif_carrier_off(dev
);
4382 if (netif_running(dev
)) {
4383 unsigned long flags
;
4385 nv_disable_irq(dev
);
4386 netif_tx_lock_bh(dev
);
4387 netif_addr_lock(dev
);
4388 /* with plain spinlock lockdep complains */
4389 spin_lock_irqsave(&np
->lock
, flags
);
4392 * this can take some time, and interrupts are disabled
4393 * due to spin_lock_irqsave, but let's hope no daemon
4394 * is going to change the settings very often...
4396 * NV_RXSTOP_DELAY1MAX + NV_TXSTOP_DELAY1MAX
4397 * + some minor delays, which is up to a second approximately
4400 spin_unlock_irqrestore(&np
->lock
, flags
);
4401 netif_addr_unlock(dev
);
4402 netif_tx_unlock_bh(dev
);
4405 if (ecmd
->autoneg
== AUTONEG_ENABLE
) {
4410 /* advertise only what has been requested */
4411 adv
= mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, MII_READ
);
4412 adv
&= ~(ADVERTISE_ALL
| ADVERTISE_100BASE4
| ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
4413 if (ecmd
->advertising
& ADVERTISED_10baseT_Half
)
4414 adv
|= ADVERTISE_10HALF
;
4415 if (ecmd
->advertising
& ADVERTISED_10baseT_Full
)
4416 adv
|= ADVERTISE_10FULL
;
4417 if (ecmd
->advertising
& ADVERTISED_100baseT_Half
)
4418 adv
|= ADVERTISE_100HALF
;
4419 if (ecmd
->advertising
& ADVERTISED_100baseT_Full
)
4420 adv
|= ADVERTISE_100FULL
;
4421 if (np
->pause_flags
& NV_PAUSEFRAME_RX_REQ
) /* for rx we set both advertisments but disable tx pause */
4422 adv
|= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
4423 if (np
->pause_flags
& NV_PAUSEFRAME_TX_REQ
)
4424 adv
|= ADVERTISE_PAUSE_ASYM
;
4425 mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, adv
);
4427 if (np
->gigabit
== PHY_GIGABIT
) {
4428 adv
= mii_rw(dev
, np
->phyaddr
, MII_CTRL1000
, MII_READ
);
4429 adv
&= ~ADVERTISE_1000FULL
;
4430 if (ecmd
->advertising
& ADVERTISED_1000baseT_Full
)
4431 adv
|= ADVERTISE_1000FULL
;
4432 mii_rw(dev
, np
->phyaddr
, MII_CTRL1000
, adv
);
4435 if (netif_running(dev
))
4436 printk(KERN_INFO
"%s: link down.\n", dev
->name
);
4437 bmcr
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
4438 if (np
->phy_model
== PHY_MODEL_MARVELL_E3016
) {
4439 bmcr
|= BMCR_ANENABLE
;
4440 /* reset the phy in order for settings to stick,
4441 * and cause autoneg to start */
4442 if (phy_reset(dev
, bmcr
)) {
4443 printk(KERN_INFO
"%s: phy reset failed\n", dev
->name
);
4447 bmcr
|= (BMCR_ANENABLE
| BMCR_ANRESTART
);
4448 mii_rw(dev
, np
->phyaddr
, MII_BMCR
, bmcr
);
4455 adv
= mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, MII_READ
);
4456 adv
&= ~(ADVERTISE_ALL
| ADVERTISE_100BASE4
| ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
4457 if (ecmd
->speed
== SPEED_10
&& ecmd
->duplex
== DUPLEX_HALF
)
4458 adv
|= ADVERTISE_10HALF
;
4459 if (ecmd
->speed
== SPEED_10
&& ecmd
->duplex
== DUPLEX_FULL
)
4460 adv
|= ADVERTISE_10FULL
;
4461 if (ecmd
->speed
== SPEED_100
&& ecmd
->duplex
== DUPLEX_HALF
)
4462 adv
|= ADVERTISE_100HALF
;
4463 if (ecmd
->speed
== SPEED_100
&& ecmd
->duplex
== DUPLEX_FULL
)
4464 adv
|= ADVERTISE_100FULL
;
4465 np
->pause_flags
&= ~(NV_PAUSEFRAME_AUTONEG
|NV_PAUSEFRAME_RX_ENABLE
|NV_PAUSEFRAME_TX_ENABLE
);
4466 if (np
->pause_flags
& NV_PAUSEFRAME_RX_REQ
) {/* for rx we set both advertisments but disable tx pause */
4467 adv
|= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
4468 np
->pause_flags
|= NV_PAUSEFRAME_RX_ENABLE
;
4470 if (np
->pause_flags
& NV_PAUSEFRAME_TX_REQ
) {
4471 adv
|= ADVERTISE_PAUSE_ASYM
;
4472 np
->pause_flags
|= NV_PAUSEFRAME_TX_ENABLE
;
4474 mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, adv
);
4475 np
->fixed_mode
= adv
;
4477 if (np
->gigabit
== PHY_GIGABIT
) {
4478 adv
= mii_rw(dev
, np
->phyaddr
, MII_CTRL1000
, MII_READ
);
4479 adv
&= ~ADVERTISE_1000FULL
;
4480 mii_rw(dev
, np
->phyaddr
, MII_CTRL1000
, adv
);
4483 bmcr
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
4484 bmcr
&= ~(BMCR_ANENABLE
|BMCR_SPEED100
|BMCR_SPEED1000
|BMCR_FULLDPLX
);
4485 if (np
->fixed_mode
& (ADVERTISE_10FULL
|ADVERTISE_100FULL
))
4486 bmcr
|= BMCR_FULLDPLX
;
4487 if (np
->fixed_mode
& (ADVERTISE_100HALF
|ADVERTISE_100FULL
))
4488 bmcr
|= BMCR_SPEED100
;
4489 if (np
->phy_oui
== PHY_OUI_MARVELL
) {
4490 /* reset the phy in order for forced mode settings to stick */
4491 if (phy_reset(dev
, bmcr
)) {
4492 printk(KERN_INFO
"%s: phy reset failed\n", dev
->name
);
4496 mii_rw(dev
, np
->phyaddr
, MII_BMCR
, bmcr
);
4497 if (netif_running(dev
)) {
4498 /* Wait a bit and then reconfigure the nic. */
4505 if (netif_running(dev
)) {
4513 #define FORCEDETH_REGS_VER 1
4515 static int nv_get_regs_len(struct net_device
*dev
)
4517 struct fe_priv
*np
= netdev_priv(dev
);
4518 return np
->register_size
;
4521 static void nv_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
, void *buf
)
4523 struct fe_priv
*np
= netdev_priv(dev
);
4524 u8 __iomem
*base
= get_hwbase(dev
);
4528 regs
->version
= FORCEDETH_REGS_VER
;
4529 spin_lock_irq(&np
->lock
);
4530 for (i
= 0;i
<= np
->register_size
/sizeof(u32
); i
++)
4531 rbuf
[i
] = readl(base
+ i
*sizeof(u32
));
4532 spin_unlock_irq(&np
->lock
);
4535 static int nv_nway_reset(struct net_device
*dev
)
4537 struct fe_priv
*np
= netdev_priv(dev
);
4543 netif_carrier_off(dev
);
4544 if (netif_running(dev
)) {
4545 nv_disable_irq(dev
);
4546 netif_tx_lock_bh(dev
);
4547 netif_addr_lock(dev
);
4548 spin_lock(&np
->lock
);
4551 spin_unlock(&np
->lock
);
4552 netif_addr_unlock(dev
);
4553 netif_tx_unlock_bh(dev
);
4554 printk(KERN_INFO
"%s: link down.\n", dev
->name
);
4557 bmcr
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
4558 if (np
->phy_model
== PHY_MODEL_MARVELL_E3016
) {
4559 bmcr
|= BMCR_ANENABLE
;
4560 /* reset the phy in order for settings to stick*/
4561 if (phy_reset(dev
, bmcr
)) {
4562 printk(KERN_INFO
"%s: phy reset failed\n", dev
->name
);
4566 bmcr
|= (BMCR_ANENABLE
| BMCR_ANRESTART
);
4567 mii_rw(dev
, np
->phyaddr
, MII_BMCR
, bmcr
);
4570 if (netif_running(dev
)) {
4582 static int nv_set_tso(struct net_device
*dev
, u32 value
)
4584 struct fe_priv
*np
= netdev_priv(dev
);
4586 if ((np
->driver_data
& DEV_HAS_CHECKSUM
))
4587 return ethtool_op_set_tso(dev
, value
);
4592 static void nv_get_ringparam(struct net_device
*dev
, struct ethtool_ringparam
* ring
)
4594 struct fe_priv
*np
= netdev_priv(dev
);
4596 ring
->rx_max_pending
= (np
->desc_ver
== DESC_VER_1
) ? RING_MAX_DESC_VER_1
: RING_MAX_DESC_VER_2_3
;
4597 ring
->rx_mini_max_pending
= 0;
4598 ring
->rx_jumbo_max_pending
= 0;
4599 ring
->tx_max_pending
= (np
->desc_ver
== DESC_VER_1
) ? RING_MAX_DESC_VER_1
: RING_MAX_DESC_VER_2_3
;
4601 ring
->rx_pending
= np
->rx_ring_size
;
4602 ring
->rx_mini_pending
= 0;
4603 ring
->rx_jumbo_pending
= 0;
4604 ring
->tx_pending
= np
->tx_ring_size
;
4607 static int nv_set_ringparam(struct net_device
*dev
, struct ethtool_ringparam
* ring
)
4609 struct fe_priv
*np
= netdev_priv(dev
);
4610 u8 __iomem
*base
= get_hwbase(dev
);
4611 u8
*rxtx_ring
, *rx_skbuff
, *tx_skbuff
;
4612 dma_addr_t ring_addr
;
4614 if (ring
->rx_pending
< RX_RING_MIN
||
4615 ring
->tx_pending
< TX_RING_MIN
||
4616 ring
->rx_mini_pending
!= 0 ||
4617 ring
->rx_jumbo_pending
!= 0 ||
4618 (np
->desc_ver
== DESC_VER_1
&&
4619 (ring
->rx_pending
> RING_MAX_DESC_VER_1
||
4620 ring
->tx_pending
> RING_MAX_DESC_VER_1
)) ||
4621 (np
->desc_ver
!= DESC_VER_1
&&
4622 (ring
->rx_pending
> RING_MAX_DESC_VER_2_3
||
4623 ring
->tx_pending
> RING_MAX_DESC_VER_2_3
))) {
4627 /* allocate new rings */
4628 if (!nv_optimized(np
)) {
4629 rxtx_ring
= pci_alloc_consistent(np
->pci_dev
,
4630 sizeof(struct ring_desc
) * (ring
->rx_pending
+ ring
->tx_pending
),
4633 rxtx_ring
= pci_alloc_consistent(np
->pci_dev
,
4634 sizeof(struct ring_desc_ex
) * (ring
->rx_pending
+ ring
->tx_pending
),
4637 rx_skbuff
= kmalloc(sizeof(struct nv_skb_map
) * ring
->rx_pending
, GFP_KERNEL
);
4638 tx_skbuff
= kmalloc(sizeof(struct nv_skb_map
) * ring
->tx_pending
, GFP_KERNEL
);
4639 if (!rxtx_ring
|| !rx_skbuff
|| !tx_skbuff
) {
4640 /* fall back to old rings */
4641 if (!nv_optimized(np
)) {
4643 pci_free_consistent(np
->pci_dev
, sizeof(struct ring_desc
) * (ring
->rx_pending
+ ring
->tx_pending
),
4644 rxtx_ring
, ring_addr
);
4647 pci_free_consistent(np
->pci_dev
, sizeof(struct ring_desc_ex
) * (ring
->rx_pending
+ ring
->tx_pending
),
4648 rxtx_ring
, ring_addr
);
4657 if (netif_running(dev
)) {
4658 nv_disable_irq(dev
);
4659 nv_napi_disable(dev
);
4660 netif_tx_lock_bh(dev
);
4661 netif_addr_lock(dev
);
4662 spin_lock(&np
->lock
);
4672 /* set new values */
4673 np
->rx_ring_size
= ring
->rx_pending
;
4674 np
->tx_ring_size
= ring
->tx_pending
;
4676 if (!nv_optimized(np
)) {
4677 np
->rx_ring
.orig
= (struct ring_desc
*)rxtx_ring
;
4678 np
->tx_ring
.orig
= &np
->rx_ring
.orig
[np
->rx_ring_size
];
4680 np
->rx_ring
.ex
= (struct ring_desc_ex
*)rxtx_ring
;
4681 np
->tx_ring
.ex
= &np
->rx_ring
.ex
[np
->rx_ring_size
];
4683 np
->rx_skb
= (struct nv_skb_map
*)rx_skbuff
;
4684 np
->tx_skb
= (struct nv_skb_map
*)tx_skbuff
;
4685 np
->ring_addr
= ring_addr
;
4687 memset(np
->rx_skb
, 0, sizeof(struct nv_skb_map
) * np
->rx_ring_size
);
4688 memset(np
->tx_skb
, 0, sizeof(struct nv_skb_map
) * np
->tx_ring_size
);
4690 if (netif_running(dev
)) {
4691 /* reinit driver view of the queues */
4693 if (nv_init_ring(dev
)) {
4694 if (!np
->in_shutdown
)
4695 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
4698 /* reinit nic view of the queues */
4699 writel(np
->rx_buf_sz
, base
+ NvRegOffloadConfig
);
4700 setup_hw_rings(dev
, NV_SETUP_RX_RING
| NV_SETUP_TX_RING
);
4701 writel( ((np
->rx_ring_size
-1) << NVREG_RINGSZ_RXSHIFT
) + ((np
->tx_ring_size
-1) << NVREG_RINGSZ_TXSHIFT
),
4702 base
+ NvRegRingSizes
);
4704 writel(NVREG_TXRXCTL_KICK
|np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
4707 /* restart engines */
4709 spin_unlock(&np
->lock
);
4710 netif_addr_unlock(dev
);
4711 netif_tx_unlock_bh(dev
);
4712 nv_napi_enable(dev
);
4720 static void nv_get_pauseparam(struct net_device
*dev
, struct ethtool_pauseparam
* pause
)
4722 struct fe_priv
*np
= netdev_priv(dev
);
4724 pause
->autoneg
= (np
->pause_flags
& NV_PAUSEFRAME_AUTONEG
) != 0;
4725 pause
->rx_pause
= (np
->pause_flags
& NV_PAUSEFRAME_RX_ENABLE
) != 0;
4726 pause
->tx_pause
= (np
->pause_flags
& NV_PAUSEFRAME_TX_ENABLE
) != 0;
4729 static int nv_set_pauseparam(struct net_device
*dev
, struct ethtool_pauseparam
* pause
)
4731 struct fe_priv
*np
= netdev_priv(dev
);
4734 if ((!np
->autoneg
&& np
->duplex
== 0) ||
4735 (np
->autoneg
&& !pause
->autoneg
&& np
->duplex
== 0)) {
4736 printk(KERN_INFO
"%s: can not set pause settings when forced link is in half duplex.\n",
4740 if (pause
->tx_pause
&& !(np
->pause_flags
& NV_PAUSEFRAME_TX_CAPABLE
)) {
4741 printk(KERN_INFO
"%s: hardware does not support tx pause frames.\n", dev
->name
);
4745 netif_carrier_off(dev
);
4746 if (netif_running(dev
)) {
4747 nv_disable_irq(dev
);
4748 netif_tx_lock_bh(dev
);
4749 netif_addr_lock(dev
);
4750 spin_lock(&np
->lock
);
4753 spin_unlock(&np
->lock
);
4754 netif_addr_unlock(dev
);
4755 netif_tx_unlock_bh(dev
);
4758 np
->pause_flags
&= ~(NV_PAUSEFRAME_RX_REQ
|NV_PAUSEFRAME_TX_REQ
);
4759 if (pause
->rx_pause
)
4760 np
->pause_flags
|= NV_PAUSEFRAME_RX_REQ
;
4761 if (pause
->tx_pause
)
4762 np
->pause_flags
|= NV_PAUSEFRAME_TX_REQ
;
4764 if (np
->autoneg
&& pause
->autoneg
) {
4765 np
->pause_flags
|= NV_PAUSEFRAME_AUTONEG
;
4767 adv
= mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, MII_READ
);
4768 adv
&= ~(ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
4769 if (np
->pause_flags
& NV_PAUSEFRAME_RX_REQ
) /* for rx we set both advertisments but disable tx pause */
4770 adv
|= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
4771 if (np
->pause_flags
& NV_PAUSEFRAME_TX_REQ
)
4772 adv
|= ADVERTISE_PAUSE_ASYM
;
4773 mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, adv
);
4775 if (netif_running(dev
))
4776 printk(KERN_INFO
"%s: link down.\n", dev
->name
);
4777 bmcr
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
4778 bmcr
|= (BMCR_ANENABLE
| BMCR_ANRESTART
);
4779 mii_rw(dev
, np
->phyaddr
, MII_BMCR
, bmcr
);
4781 np
->pause_flags
&= ~(NV_PAUSEFRAME_AUTONEG
|NV_PAUSEFRAME_RX_ENABLE
|NV_PAUSEFRAME_TX_ENABLE
);
4782 if (pause
->rx_pause
)
4783 np
->pause_flags
|= NV_PAUSEFRAME_RX_ENABLE
;
4784 if (pause
->tx_pause
)
4785 np
->pause_flags
|= NV_PAUSEFRAME_TX_ENABLE
;
4787 if (!netif_running(dev
))
4788 nv_update_linkspeed(dev
);
4790 nv_update_pause(dev
, np
->pause_flags
);
4793 if (netif_running(dev
)) {
4800 static u32
nv_get_rx_csum(struct net_device
*dev
)
4802 struct fe_priv
*np
= netdev_priv(dev
);
4803 return (np
->rx_csum
) != 0;
4806 static int nv_set_rx_csum(struct net_device
*dev
, u32 data
)
4808 struct fe_priv
*np
= netdev_priv(dev
);
4809 u8 __iomem
*base
= get_hwbase(dev
);
4812 if (np
->driver_data
& DEV_HAS_CHECKSUM
) {
4815 np
->txrxctl_bits
|= NVREG_TXRXCTL_RXCHECK
;
4818 /* vlan is dependent on rx checksum offload */
4819 if (!(np
->vlanctl_bits
& NVREG_VLANCONTROL_ENABLE
))
4820 np
->txrxctl_bits
&= ~NVREG_TXRXCTL_RXCHECK
;
4822 if (netif_running(dev
)) {
4823 spin_lock_irq(&np
->lock
);
4824 writel(np
->txrxctl_bits
, base
+ NvRegTxRxControl
);
4825 spin_unlock_irq(&np
->lock
);
4834 static int nv_set_tx_csum(struct net_device
*dev
, u32 data
)
4836 struct fe_priv
*np
= netdev_priv(dev
);
4838 if (np
->driver_data
& DEV_HAS_CHECKSUM
)
4839 return ethtool_op_set_tx_csum(dev
, data
);
4844 static int nv_set_sg(struct net_device
*dev
, u32 data
)
4846 struct fe_priv
*np
= netdev_priv(dev
);
4848 if (np
->driver_data
& DEV_HAS_CHECKSUM
)
4849 return ethtool_op_set_sg(dev
, data
);
4854 static int nv_get_sset_count(struct net_device
*dev
, int sset
)
4856 struct fe_priv
*np
= netdev_priv(dev
);
4860 if (np
->driver_data
& DEV_HAS_TEST_EXTENDED
)
4861 return NV_TEST_COUNT_EXTENDED
;
4863 return NV_TEST_COUNT_BASE
;
4865 if (np
->driver_data
& DEV_HAS_STATISTICS_V3
)
4866 return NV_DEV_STATISTICS_V3_COUNT
;
4867 else if (np
->driver_data
& DEV_HAS_STATISTICS_V2
)
4868 return NV_DEV_STATISTICS_V2_COUNT
;
4869 else if (np
->driver_data
& DEV_HAS_STATISTICS_V1
)
4870 return NV_DEV_STATISTICS_V1_COUNT
;
4878 static void nv_get_ethtool_stats(struct net_device
*dev
, struct ethtool_stats
*estats
, u64
*buffer
)
4880 struct fe_priv
*np
= netdev_priv(dev
);
4883 nv_do_stats_poll((unsigned long)dev
);
4885 memcpy(buffer
, &np
->estats
, nv_get_sset_count(dev
, ETH_SS_STATS
)*sizeof(u64
));
4888 static int nv_link_test(struct net_device
*dev
)
4890 struct fe_priv
*np
= netdev_priv(dev
);
4893 mii_rw(dev
, np
->phyaddr
, MII_BMSR
, MII_READ
);
4894 mii_status
= mii_rw(dev
, np
->phyaddr
, MII_BMSR
, MII_READ
);
4896 /* check phy link status */
4897 if (!(mii_status
& BMSR_LSTATUS
))
4903 static int nv_register_test(struct net_device
*dev
)
4905 u8 __iomem
*base
= get_hwbase(dev
);
4907 u32 orig_read
, new_read
;
4910 orig_read
= readl(base
+ nv_registers_test
[i
].reg
);
4912 /* xor with mask to toggle bits */
4913 orig_read
^= nv_registers_test
[i
].mask
;
4915 writel(orig_read
, base
+ nv_registers_test
[i
].reg
);
4917 new_read
= readl(base
+ nv_registers_test
[i
].reg
);
4919 if ((new_read
& nv_registers_test
[i
].mask
) != (orig_read
& nv_registers_test
[i
].mask
))
4922 /* restore original value */
4923 orig_read
^= nv_registers_test
[i
].mask
;
4924 writel(orig_read
, base
+ nv_registers_test
[i
].reg
);
4926 } while (nv_registers_test
[++i
].reg
!= 0);
4931 static int nv_interrupt_test(struct net_device
*dev
)
4933 struct fe_priv
*np
= netdev_priv(dev
);
4934 u8 __iomem
*base
= get_hwbase(dev
);
4937 u32 save_msi_flags
, save_poll_interval
= 0;
4939 if (netif_running(dev
)) {
4940 /* free current irq */
4942 save_poll_interval
= readl(base
+NvRegPollingInterval
);
4945 /* flag to test interrupt handler */
4948 /* setup test irq */
4949 save_msi_flags
= np
->msi_flags
;
4950 np
->msi_flags
&= ~NV_MSI_X_VECTORS_MASK
;
4951 np
->msi_flags
|= 0x001; /* setup 1 vector */
4952 if (nv_request_irq(dev
, 1))
4955 /* setup timer interrupt */
4956 writel(NVREG_POLL_DEFAULT_CPU
, base
+ NvRegPollingInterval
);
4957 writel(NVREG_UNKSETUP6_VAL
, base
+ NvRegUnknownSetupReg6
);
4959 nv_enable_hw_interrupts(dev
, NVREG_IRQ_TIMER
);
4961 /* wait for at least one interrupt */
4964 spin_lock_irq(&np
->lock
);
4966 /* flag should be set within ISR */
4967 testcnt
= np
->intr_test
;
4971 nv_disable_hw_interrupts(dev
, NVREG_IRQ_TIMER
);
4972 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
))
4973 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegIrqStatus
);
4975 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegMSIXIrqStatus
);
4977 spin_unlock_irq(&np
->lock
);
4981 np
->msi_flags
= save_msi_flags
;
4983 if (netif_running(dev
)) {
4984 writel(save_poll_interval
, base
+ NvRegPollingInterval
);
4985 writel(NVREG_UNKSETUP6_VAL
, base
+ NvRegUnknownSetupReg6
);
4986 /* restore original irq */
4987 if (nv_request_irq(dev
, 0))
4994 static int nv_loopback_test(struct net_device
*dev
)
4996 struct fe_priv
*np
= netdev_priv(dev
);
4997 u8 __iomem
*base
= get_hwbase(dev
);
4998 struct sk_buff
*tx_skb
, *rx_skb
;
4999 dma_addr_t test_dma_addr
;
5000 u32 tx_flags_extra
= (np
->desc_ver
== DESC_VER_1
? NV_TX_LASTPACKET
: NV_TX2_LASTPACKET
);
5002 int len
, i
, pkt_len
;
5004 u32 filter_flags
= 0;
5005 u32 misc1_flags
= 0;
5008 if (netif_running(dev
)) {
5009 nv_disable_irq(dev
);
5010 filter_flags
= readl(base
+ NvRegPacketFilterFlags
);
5011 misc1_flags
= readl(base
+ NvRegMisc1
);
5016 /* reinit driver view of the rx queue */
5020 /* setup hardware for loopback */
5021 writel(NVREG_MISC1_FORCE
, base
+ NvRegMisc1
);
5022 writel(NVREG_PFF_ALWAYS
| NVREG_PFF_LOOPBACK
, base
+ NvRegPacketFilterFlags
);
5024 /* reinit nic view of the rx queue */
5025 writel(np
->rx_buf_sz
, base
+ NvRegOffloadConfig
);
5026 setup_hw_rings(dev
, NV_SETUP_RX_RING
| NV_SETUP_TX_RING
);
5027 writel( ((np
->rx_ring_size
-1) << NVREG_RINGSZ_RXSHIFT
) + ((np
->tx_ring_size
-1) << NVREG_RINGSZ_TXSHIFT
),
5028 base
+ NvRegRingSizes
);
5031 /* restart rx engine */
5034 /* setup packet for tx */
5035 pkt_len
= ETH_DATA_LEN
;
5036 tx_skb
= dev_alloc_skb(pkt_len
);
5038 printk(KERN_ERR
"dev_alloc_skb() failed during loopback test"
5039 " of %s\n", dev
->name
);
5043 test_dma_addr
= pci_map_single(np
->pci_dev
, tx_skb
->data
,
5044 skb_tailroom(tx_skb
),
5045 PCI_DMA_FROMDEVICE
);
5046 pkt_data
= skb_put(tx_skb
, pkt_len
);
5047 for (i
= 0; i
< pkt_len
; i
++)
5048 pkt_data
[i
] = (u8
)(i
& 0xff);
5050 if (!nv_optimized(np
)) {
5051 np
->tx_ring
.orig
[0].buf
= cpu_to_le32(test_dma_addr
);
5052 np
->tx_ring
.orig
[0].flaglen
= cpu_to_le32((pkt_len
-1) | np
->tx_flags
| tx_flags_extra
);
5054 np
->tx_ring
.ex
[0].bufhigh
= cpu_to_le32(dma_high(test_dma_addr
));
5055 np
->tx_ring
.ex
[0].buflow
= cpu_to_le32(dma_low(test_dma_addr
));
5056 np
->tx_ring
.ex
[0].flaglen
= cpu_to_le32((pkt_len
-1) | np
->tx_flags
| tx_flags_extra
);
5058 writel(NVREG_TXRXCTL_KICK
|np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
5059 pci_push(get_hwbase(dev
));
5063 /* check for rx of the packet */
5064 if (!nv_optimized(np
)) {
5065 flags
= le32_to_cpu(np
->rx_ring
.orig
[0].flaglen
);
5066 len
= nv_descr_getlength(&np
->rx_ring
.orig
[0], np
->desc_ver
);
5069 flags
= le32_to_cpu(np
->rx_ring
.ex
[0].flaglen
);
5070 len
= nv_descr_getlength_ex(&np
->rx_ring
.ex
[0], np
->desc_ver
);
5073 if (flags
& NV_RX_AVAIL
) {
5075 } else if (np
->desc_ver
== DESC_VER_1
) {
5076 if (flags
& NV_RX_ERROR
)
5079 if (flags
& NV_RX2_ERROR
) {
5085 if (len
!= pkt_len
) {
5087 dprintk(KERN_DEBUG
"%s: loopback len mismatch %d vs %d\n",
5088 dev
->name
, len
, pkt_len
);
5090 rx_skb
= np
->rx_skb
[0].skb
;
5091 for (i
= 0; i
< pkt_len
; i
++) {
5092 if (rx_skb
->data
[i
] != (u8
)(i
& 0xff)) {
5094 dprintk(KERN_DEBUG
"%s: loopback pattern check failed on byte %d\n",
5101 dprintk(KERN_DEBUG
"%s: loopback - did not receive test packet\n", dev
->name
);
5104 pci_unmap_page(np
->pci_dev
, test_dma_addr
,
5105 (skb_end_pointer(tx_skb
) - tx_skb
->data
),
5107 dev_kfree_skb_any(tx_skb
);
5112 /* drain rx queue */
5115 if (netif_running(dev
)) {
5116 writel(misc1_flags
, base
+ NvRegMisc1
);
5117 writel(filter_flags
, base
+ NvRegPacketFilterFlags
);
5124 static void nv_self_test(struct net_device
*dev
, struct ethtool_test
*test
, u64
*buffer
)
5126 struct fe_priv
*np
= netdev_priv(dev
);
5127 u8 __iomem
*base
= get_hwbase(dev
);
5129 memset(buffer
, 0, nv_get_sset_count(dev
, ETH_SS_TEST
)*sizeof(u64
));
5131 if (!nv_link_test(dev
)) {
5132 test
->flags
|= ETH_TEST_FL_FAILED
;
5136 if (test
->flags
& ETH_TEST_FL_OFFLINE
) {
5137 if (netif_running(dev
)) {
5138 netif_stop_queue(dev
);
5139 nv_napi_disable(dev
);
5140 netif_tx_lock_bh(dev
);
5141 netif_addr_lock(dev
);
5142 spin_lock_irq(&np
->lock
);
5143 nv_disable_hw_interrupts(dev
, np
->irqmask
);
5144 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
)) {
5145 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegIrqStatus
);
5147 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegMSIXIrqStatus
);
5152 /* drain rx queue */
5154 spin_unlock_irq(&np
->lock
);
5155 netif_addr_unlock(dev
);
5156 netif_tx_unlock_bh(dev
);
5159 if (!nv_register_test(dev
)) {
5160 test
->flags
|= ETH_TEST_FL_FAILED
;
5164 result
= nv_interrupt_test(dev
);
5166 test
->flags
|= ETH_TEST_FL_FAILED
;
5174 if (!nv_loopback_test(dev
)) {
5175 test
->flags
|= ETH_TEST_FL_FAILED
;
5179 if (netif_running(dev
)) {
5180 /* reinit driver view of the rx queue */
5182 if (nv_init_ring(dev
)) {
5183 if (!np
->in_shutdown
)
5184 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
5186 /* reinit nic view of the rx queue */
5187 writel(np
->rx_buf_sz
, base
+ NvRegOffloadConfig
);
5188 setup_hw_rings(dev
, NV_SETUP_RX_RING
| NV_SETUP_TX_RING
);
5189 writel( ((np
->rx_ring_size
-1) << NVREG_RINGSZ_RXSHIFT
) + ((np
->tx_ring_size
-1) << NVREG_RINGSZ_TXSHIFT
),
5190 base
+ NvRegRingSizes
);
5192 writel(NVREG_TXRXCTL_KICK
|np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
5194 /* restart rx engine */
5196 netif_start_queue(dev
);
5197 nv_napi_enable(dev
);
5198 nv_enable_hw_interrupts(dev
, np
->irqmask
);
5203 static void nv_get_strings(struct net_device
*dev
, u32 stringset
, u8
*buffer
)
5205 switch (stringset
) {
5207 memcpy(buffer
, &nv_estats_str
, nv_get_sset_count(dev
, ETH_SS_STATS
)*sizeof(struct nv_ethtool_str
));
5210 memcpy(buffer
, &nv_etests_str
, nv_get_sset_count(dev
, ETH_SS_TEST
)*sizeof(struct nv_ethtool_str
));
5215 static const struct ethtool_ops ops
= {
5216 .get_drvinfo
= nv_get_drvinfo
,
5217 .get_link
= ethtool_op_get_link
,
5218 .get_wol
= nv_get_wol
,
5219 .set_wol
= nv_set_wol
,
5220 .get_settings
= nv_get_settings
,
5221 .set_settings
= nv_set_settings
,
5222 .get_regs_len
= nv_get_regs_len
,
5223 .get_regs
= nv_get_regs
,
5224 .nway_reset
= nv_nway_reset
,
5225 .set_tso
= nv_set_tso
,
5226 .get_ringparam
= nv_get_ringparam
,
5227 .set_ringparam
= nv_set_ringparam
,
5228 .get_pauseparam
= nv_get_pauseparam
,
5229 .set_pauseparam
= nv_set_pauseparam
,
5230 .get_rx_csum
= nv_get_rx_csum
,
5231 .set_rx_csum
= nv_set_rx_csum
,
5232 .set_tx_csum
= nv_set_tx_csum
,
5233 .set_sg
= nv_set_sg
,
5234 .get_strings
= nv_get_strings
,
5235 .get_ethtool_stats
= nv_get_ethtool_stats
,
5236 .get_sset_count
= nv_get_sset_count
,
5237 .self_test
= nv_self_test
,
5240 static void nv_vlan_rx_register(struct net_device
*dev
, struct vlan_group
*grp
)
5242 struct fe_priv
*np
= get_nvpriv(dev
);
5244 spin_lock_irq(&np
->lock
);
5246 /* save vlan group */
5250 /* enable vlan on MAC */
5251 np
->txrxctl_bits
|= NVREG_TXRXCTL_VLANSTRIP
| NVREG_TXRXCTL_VLANINS
;
5253 /* disable vlan on MAC */
5254 np
->txrxctl_bits
&= ~NVREG_TXRXCTL_VLANSTRIP
;
5255 np
->txrxctl_bits
&= ~NVREG_TXRXCTL_VLANINS
;
5258 writel(np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
5260 spin_unlock_irq(&np
->lock
);
5263 /* The mgmt unit and driver use a semaphore to access the phy during init */
5264 static int nv_mgmt_acquire_sema(struct net_device
*dev
)
5266 struct fe_priv
*np
= netdev_priv(dev
);
5267 u8 __iomem
*base
= get_hwbase(dev
);
5269 u32 tx_ctrl
, mgmt_sema
;
5271 for (i
= 0; i
< 10; i
++) {
5272 mgmt_sema
= readl(base
+ NvRegTransmitterControl
) & NVREG_XMITCTL_MGMT_SEMA_MASK
;
5273 if (mgmt_sema
== NVREG_XMITCTL_MGMT_SEMA_FREE
)
5278 if (mgmt_sema
!= NVREG_XMITCTL_MGMT_SEMA_FREE
)
5281 for (i
= 0; i
< 2; i
++) {
5282 tx_ctrl
= readl(base
+ NvRegTransmitterControl
);
5283 tx_ctrl
|= NVREG_XMITCTL_HOST_SEMA_ACQ
;
5284 writel(tx_ctrl
, base
+ NvRegTransmitterControl
);
5286 /* verify that semaphore was acquired */
5287 tx_ctrl
= readl(base
+ NvRegTransmitterControl
);
5288 if (((tx_ctrl
& NVREG_XMITCTL_HOST_SEMA_MASK
) == NVREG_XMITCTL_HOST_SEMA_ACQ
) &&
5289 ((tx_ctrl
& NVREG_XMITCTL_MGMT_SEMA_MASK
) == NVREG_XMITCTL_MGMT_SEMA_FREE
)) {
5300 static void nv_mgmt_release_sema(struct net_device
*dev
)
5302 struct fe_priv
*np
= netdev_priv(dev
);
5303 u8 __iomem
*base
= get_hwbase(dev
);
5306 if (np
->driver_data
& DEV_HAS_MGMT_UNIT
) {
5307 if (np
->mgmt_sema
) {
5308 tx_ctrl
= readl(base
+ NvRegTransmitterControl
);
5309 tx_ctrl
&= ~NVREG_XMITCTL_HOST_SEMA_ACQ
;
5310 writel(tx_ctrl
, base
+ NvRegTransmitterControl
);
5316 static int nv_mgmt_get_version(struct net_device
*dev
)
5318 struct fe_priv
*np
= netdev_priv(dev
);
5319 u8 __iomem
*base
= get_hwbase(dev
);
5320 u32 data_ready
= readl(base
+ NvRegTransmitterControl
);
5321 u32 data_ready2
= 0;
5322 unsigned long start
;
5325 writel(NVREG_MGMTUNITGETVERSION
, base
+ NvRegMgmtUnitGetVersion
);
5326 writel(data_ready
^ NVREG_XMITCTL_DATA_START
, base
+ NvRegTransmitterControl
);
5328 while (time_before(jiffies
, start
+ 5*HZ
)) {
5329 data_ready2
= readl(base
+ NvRegTransmitterControl
);
5330 if ((data_ready
& NVREG_XMITCTL_DATA_READY
) != (data_ready2
& NVREG_XMITCTL_DATA_READY
)) {
5334 schedule_timeout_uninterruptible(1);
5337 if (!ready
|| (data_ready2
& NVREG_XMITCTL_DATA_ERROR
))
5340 np
->mgmt_version
= readl(base
+ NvRegMgmtUnitVersion
) & NVREG_MGMTUNITVERSION
;
5345 static int nv_open(struct net_device
*dev
)
5347 struct fe_priv
*np
= netdev_priv(dev
);
5348 u8 __iomem
*base
= get_hwbase(dev
);
5353 dprintk(KERN_DEBUG
"nv_open: begin\n");
5356 mii_rw(dev
, np
->phyaddr
, MII_BMCR
,
5357 mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
) & ~BMCR_PDOWN
);
5359 nv_txrx_gate(dev
, false);
5360 /* erase previous misconfiguration */
5361 if (np
->driver_data
& DEV_HAS_POWER_CNTRL
)
5363 writel(NVREG_MCASTADDRA_FORCE
, base
+ NvRegMulticastAddrA
);
5364 writel(0, base
+ NvRegMulticastAddrB
);
5365 writel(NVREG_MCASTMASKA_NONE
, base
+ NvRegMulticastMaskA
);
5366 writel(NVREG_MCASTMASKB_NONE
, base
+ NvRegMulticastMaskB
);
5367 writel(0, base
+ NvRegPacketFilterFlags
);
5369 writel(0, base
+ NvRegTransmitterControl
);
5370 writel(0, base
+ NvRegReceiverControl
);
5372 writel(0, base
+ NvRegAdapterControl
);
5374 if (np
->pause_flags
& NV_PAUSEFRAME_TX_CAPABLE
)
5375 writel(NVREG_TX_PAUSEFRAME_DISABLE
, base
+ NvRegTxPauseFrame
);
5377 /* initialize descriptor rings */
5379 oom
= nv_init_ring(dev
);
5381 writel(0, base
+ NvRegLinkSpeed
);
5382 writel(readl(base
+ NvRegTransmitPoll
) & NVREG_TRANSMITPOLL_MAC_ADDR_REV
, base
+ NvRegTransmitPoll
);
5384 writel(0, base
+ NvRegUnknownSetupReg6
);
5386 np
->in_shutdown
= 0;
5389 setup_hw_rings(dev
, NV_SETUP_RX_RING
| NV_SETUP_TX_RING
);
5390 writel( ((np
->rx_ring_size
-1) << NVREG_RINGSZ_RXSHIFT
) + ((np
->tx_ring_size
-1) << NVREG_RINGSZ_TXSHIFT
),
5391 base
+ NvRegRingSizes
);
5393 writel(np
->linkspeed
, base
+ NvRegLinkSpeed
);
5394 if (np
->desc_ver
== DESC_VER_1
)
5395 writel(NVREG_TX_WM_DESC1_DEFAULT
, base
+ NvRegTxWatermark
);
5397 writel(NVREG_TX_WM_DESC2_3_DEFAULT
, base
+ NvRegTxWatermark
);
5398 writel(np
->txrxctl_bits
, base
+ NvRegTxRxControl
);
5399 writel(np
->vlanctl_bits
, base
+ NvRegVlanControl
);
5401 writel(NVREG_TXRXCTL_BIT1
|np
->txrxctl_bits
, base
+ NvRegTxRxControl
);
5402 reg_delay(dev
, NvRegUnknownSetupReg5
, NVREG_UNKSETUP5_BIT31
, NVREG_UNKSETUP5_BIT31
,
5403 NV_SETUP5_DELAY
, NV_SETUP5_DELAYMAX
,
5404 KERN_INFO
"open: SetupReg5, Bit 31 remained off\n");
5406 writel(0, base
+ NvRegMIIMask
);
5407 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegIrqStatus
);
5408 writel(NVREG_MIISTAT_MASK_ALL
, base
+ NvRegMIIStatus
);
5410 writel(NVREG_MISC1_FORCE
| NVREG_MISC1_HD
, base
+ NvRegMisc1
);
5411 writel(readl(base
+ NvRegTransmitterStatus
), base
+ NvRegTransmitterStatus
);
5412 writel(NVREG_PFF_ALWAYS
, base
+ NvRegPacketFilterFlags
);
5413 writel(np
->rx_buf_sz
, base
+ NvRegOffloadConfig
);
5415 writel(readl(base
+ NvRegReceiverStatus
), base
+ NvRegReceiverStatus
);
5417 get_random_bytes(&low
, sizeof(low
));
5418 low
&= NVREG_SLOTTIME_MASK
;
5419 if (np
->desc_ver
== DESC_VER_1
) {
5420 writel(low
|NVREG_SLOTTIME_DEFAULT
, base
+ NvRegSlotTime
);
5422 if (!(np
->driver_data
& DEV_HAS_GEAR_MODE
)) {
5423 /* setup legacy backoff */
5424 writel(NVREG_SLOTTIME_LEGBF_ENABLED
|NVREG_SLOTTIME_10_100_FULL
|low
, base
+ NvRegSlotTime
);
5426 writel(NVREG_SLOTTIME_10_100_FULL
, base
+ NvRegSlotTime
);
5427 nv_gear_backoff_reseed(dev
);
5430 writel(NVREG_TX_DEFERRAL_DEFAULT
, base
+ NvRegTxDeferral
);
5431 writel(NVREG_RX_DEFERRAL_DEFAULT
, base
+ NvRegRxDeferral
);
5432 if (poll_interval
== -1) {
5433 if (optimization_mode
== NV_OPTIMIZATION_MODE_THROUGHPUT
)
5434 writel(NVREG_POLL_DEFAULT_THROUGHPUT
, base
+ NvRegPollingInterval
);
5436 writel(NVREG_POLL_DEFAULT_CPU
, base
+ NvRegPollingInterval
);
5439 writel(poll_interval
& 0xFFFF, base
+ NvRegPollingInterval
);
5440 writel(NVREG_UNKSETUP6_VAL
, base
+ NvRegUnknownSetupReg6
);
5441 writel((np
->phyaddr
<< NVREG_ADAPTCTL_PHYSHIFT
)|NVREG_ADAPTCTL_PHYVALID
|NVREG_ADAPTCTL_RUNNING
,
5442 base
+ NvRegAdapterControl
);
5443 writel(NVREG_MIISPEED_BIT8
|NVREG_MIIDELAY
, base
+ NvRegMIISpeed
);
5444 writel(NVREG_MII_LINKCHANGE
, base
+ NvRegMIIMask
);
5446 writel(NVREG_WAKEUPFLAGS_ENABLE
, base
+ NvRegWakeUpFlags
);
5448 i
= readl(base
+ NvRegPowerState
);
5449 if ( (i
& NVREG_POWERSTATE_POWEREDUP
) == 0)
5450 writel(NVREG_POWERSTATE_POWEREDUP
|i
, base
+ NvRegPowerState
);
5454 writel(readl(base
+ NvRegPowerState
) | NVREG_POWERSTATE_VALID
, base
+ NvRegPowerState
);
5456 nv_disable_hw_interrupts(dev
, np
->irqmask
);
5458 writel(NVREG_MIISTAT_MASK_ALL
, base
+ NvRegMIIStatus
);
5459 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegIrqStatus
);
5462 if (nv_request_irq(dev
, 0)) {
5466 /* ask for interrupts */
5467 nv_enable_hw_interrupts(dev
, np
->irqmask
);
5469 spin_lock_irq(&np
->lock
);
5470 writel(NVREG_MCASTADDRA_FORCE
, base
+ NvRegMulticastAddrA
);
5471 writel(0, base
+ NvRegMulticastAddrB
);
5472 writel(NVREG_MCASTMASKA_NONE
, base
+ NvRegMulticastMaskA
);
5473 writel(NVREG_MCASTMASKB_NONE
, base
+ NvRegMulticastMaskB
);
5474 writel(NVREG_PFF_ALWAYS
|NVREG_PFF_MYADDR
, base
+ NvRegPacketFilterFlags
);
5475 /* One manual link speed update: Interrupts are enabled, future link
5476 * speed changes cause interrupts and are handled by nv_link_irq().
5480 miistat
= readl(base
+ NvRegMIIStatus
);
5481 writel(NVREG_MIISTAT_MASK_ALL
, base
+ NvRegMIIStatus
);
5482 dprintk(KERN_INFO
"startup: got 0x%08x.\n", miistat
);
5484 /* set linkspeed to invalid value, thus force nv_update_linkspeed
5487 ret
= nv_update_linkspeed(dev
);
5489 netif_start_queue(dev
);
5490 nv_napi_enable(dev
);
5493 netif_carrier_on(dev
);
5495 printk(KERN_INFO
"%s: no link during initialization.\n", dev
->name
);
5496 netif_carrier_off(dev
);
5499 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
5501 /* start statistics timer */
5502 if (np
->driver_data
& (DEV_HAS_STATISTICS_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_STATISTICS_V3
))
5503 mod_timer(&np
->stats_poll
,
5504 round_jiffies(jiffies
+ STATS_INTERVAL
));
5506 spin_unlock_irq(&np
->lock
);
5514 static int nv_close(struct net_device
*dev
)
5516 struct fe_priv
*np
= netdev_priv(dev
);
5519 spin_lock_irq(&np
->lock
);
5520 np
->in_shutdown
= 1;
5521 spin_unlock_irq(&np
->lock
);
5522 nv_napi_disable(dev
);
5523 synchronize_irq(np
->pci_dev
->irq
);
5525 del_timer_sync(&np
->oom_kick
);
5526 del_timer_sync(&np
->nic_poll
);
5527 del_timer_sync(&np
->stats_poll
);
5529 netif_stop_queue(dev
);
5530 spin_lock_irq(&np
->lock
);
5534 /* disable interrupts on the nic or we will lock up */
5535 base
= get_hwbase(dev
);
5536 nv_disable_hw_interrupts(dev
, np
->irqmask
);
5538 dprintk(KERN_INFO
"%s: Irqmask is zero again\n", dev
->name
);
5540 spin_unlock_irq(&np
->lock
);
5546 if (np
->wolenabled
|| !phy_power_down
) {
5547 nv_txrx_gate(dev
, false);
5548 writel(NVREG_PFF_ALWAYS
|NVREG_PFF_MYADDR
, base
+ NvRegPacketFilterFlags
);
5551 /* power down phy */
5552 mii_rw(dev
, np
->phyaddr
, MII_BMCR
,
5553 mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
)|BMCR_PDOWN
);
5554 nv_txrx_gate(dev
, true);
5557 /* FIXME: power down nic */
5562 static const struct net_device_ops nv_netdev_ops
= {
5563 .ndo_open
= nv_open
,
5564 .ndo_stop
= nv_close
,
5565 .ndo_get_stats
= nv_get_stats
,
5566 .ndo_start_xmit
= nv_start_xmit
,
5567 .ndo_tx_timeout
= nv_tx_timeout
,
5568 .ndo_change_mtu
= nv_change_mtu
,
5569 .ndo_validate_addr
= eth_validate_addr
,
5570 .ndo_set_mac_address
= nv_set_mac_address
,
5571 .ndo_set_multicast_list
= nv_set_multicast
,
5572 .ndo_vlan_rx_register
= nv_vlan_rx_register
,
5573 #ifdef CONFIG_NET_POLL_CONTROLLER
5574 .ndo_poll_controller
= nv_poll_controller
,
5578 static const struct net_device_ops nv_netdev_ops_optimized
= {
5579 .ndo_open
= nv_open
,
5580 .ndo_stop
= nv_close
,
5581 .ndo_get_stats
= nv_get_stats
,
5582 .ndo_start_xmit
= nv_start_xmit_optimized
,
5583 .ndo_tx_timeout
= nv_tx_timeout
,
5584 .ndo_change_mtu
= nv_change_mtu
,
5585 .ndo_validate_addr
= eth_validate_addr
,
5586 .ndo_set_mac_address
= nv_set_mac_address
,
5587 .ndo_set_multicast_list
= nv_set_multicast
,
5588 .ndo_vlan_rx_register
= nv_vlan_rx_register
,
5589 #ifdef CONFIG_NET_POLL_CONTROLLER
5590 .ndo_poll_controller
= nv_poll_controller
,
5594 static int __devinit
nv_probe(struct pci_dev
*pci_dev
, const struct pci_device_id
*id
)
5596 struct net_device
*dev
;
5601 u32 powerstate
, txreg
;
5602 u32 phystate_orig
= 0, phystate
;
5603 int phyinitialized
= 0;
5604 static int printed_version
;
5606 if (!printed_version
++)
5607 printk(KERN_INFO
"%s: Reverse Engineered nForce ethernet"
5608 " driver. Version %s.\n", DRV_NAME
, FORCEDETH_VERSION
);
5610 dev
= alloc_etherdev(sizeof(struct fe_priv
));
5615 np
= netdev_priv(dev
);
5617 np
->pci_dev
= pci_dev
;
5618 spin_lock_init(&np
->lock
);
5619 SET_NETDEV_DEV(dev
, &pci_dev
->dev
);
5621 init_timer(&np
->oom_kick
);
5622 np
->oom_kick
.data
= (unsigned long) dev
;
5623 np
->oom_kick
.function
= &nv_do_rx_refill
; /* timer handler */
5624 init_timer(&np
->nic_poll
);
5625 np
->nic_poll
.data
= (unsigned long) dev
;
5626 np
->nic_poll
.function
= &nv_do_nic_poll
; /* timer handler */
5627 init_timer(&np
->stats_poll
);
5628 np
->stats_poll
.data
= (unsigned long) dev
;
5629 np
->stats_poll
.function
= &nv_do_stats_poll
; /* timer handler */
5631 err
= pci_enable_device(pci_dev
);
5635 pci_set_master(pci_dev
);
5637 err
= pci_request_regions(pci_dev
, DRV_NAME
);
5641 if (id
->driver_data
& (DEV_HAS_VLAN
|DEV_HAS_MSI_X
|DEV_HAS_POWER_CNTRL
|DEV_HAS_STATISTICS_V2
|DEV_HAS_STATISTICS_V3
))
5642 np
->register_size
= NV_PCI_REGSZ_VER3
;
5643 else if (id
->driver_data
& DEV_HAS_STATISTICS_V1
)
5644 np
->register_size
= NV_PCI_REGSZ_VER2
;
5646 np
->register_size
= NV_PCI_REGSZ_VER1
;
5650 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++) {
5651 dprintk(KERN_DEBUG
"%s: resource %d start %p len %ld flags 0x%08lx.\n",
5652 pci_name(pci_dev
), i
, (void*)pci_resource_start(pci_dev
, i
),
5653 pci_resource_len(pci_dev
, i
),
5654 pci_resource_flags(pci_dev
, i
));
5655 if (pci_resource_flags(pci_dev
, i
) & IORESOURCE_MEM
&&
5656 pci_resource_len(pci_dev
, i
) >= np
->register_size
) {
5657 addr
= pci_resource_start(pci_dev
, i
);
5661 if (i
== DEVICE_COUNT_RESOURCE
) {
5662 dev_printk(KERN_INFO
, &pci_dev
->dev
,
5663 "Couldn't find register window\n");
5667 /* copy of driver data */
5668 np
->driver_data
= id
->driver_data
;
5669 /* copy of device id */
5670 np
->device_id
= id
->device
;
5672 /* handle different descriptor versions */
5673 if (id
->driver_data
& DEV_HAS_HIGH_DMA
) {
5674 /* packet format 3: supports 40-bit addressing */
5675 np
->desc_ver
= DESC_VER_3
;
5676 np
->txrxctl_bits
= NVREG_TXRXCTL_DESC_3
;
5678 if (pci_set_dma_mask(pci_dev
, DMA_BIT_MASK(39)))
5679 dev_printk(KERN_INFO
, &pci_dev
->dev
,
5680 "64-bit DMA failed, using 32-bit addressing\n");
5682 dev
->features
|= NETIF_F_HIGHDMA
;
5683 if (pci_set_consistent_dma_mask(pci_dev
, DMA_BIT_MASK(39))) {
5684 dev_printk(KERN_INFO
, &pci_dev
->dev
,
5685 "64-bit DMA (consistent) failed, using 32-bit ring buffers\n");
5688 } else if (id
->driver_data
& DEV_HAS_LARGEDESC
) {
5689 /* packet format 2: supports jumbo frames */
5690 np
->desc_ver
= DESC_VER_2
;
5691 np
->txrxctl_bits
= NVREG_TXRXCTL_DESC_2
;
5693 /* original packet format */
5694 np
->desc_ver
= DESC_VER_1
;
5695 np
->txrxctl_bits
= NVREG_TXRXCTL_DESC_1
;
5698 np
->pkt_limit
= NV_PKTLIMIT_1
;
5699 if (id
->driver_data
& DEV_HAS_LARGEDESC
)
5700 np
->pkt_limit
= NV_PKTLIMIT_2
;
5702 if (id
->driver_data
& DEV_HAS_CHECKSUM
) {
5704 np
->txrxctl_bits
|= NVREG_TXRXCTL_RXCHECK
;
5705 dev
->features
|= NETIF_F_IP_CSUM
| NETIF_F_SG
;
5706 dev
->features
|= NETIF_F_TSO
;
5709 np
->vlanctl_bits
= 0;
5710 if (id
->driver_data
& DEV_HAS_VLAN
) {
5711 np
->vlanctl_bits
= NVREG_VLANCONTROL_ENABLE
;
5712 dev
->features
|= NETIF_F_HW_VLAN_RX
| NETIF_F_HW_VLAN_TX
;
5715 np
->pause_flags
= NV_PAUSEFRAME_RX_CAPABLE
| NV_PAUSEFRAME_RX_REQ
| NV_PAUSEFRAME_AUTONEG
;
5716 if ((id
->driver_data
& DEV_HAS_PAUSEFRAME_TX_V1
) ||
5717 (id
->driver_data
& DEV_HAS_PAUSEFRAME_TX_V2
) ||
5718 (id
->driver_data
& DEV_HAS_PAUSEFRAME_TX_V3
)) {
5719 np
->pause_flags
|= NV_PAUSEFRAME_TX_CAPABLE
| NV_PAUSEFRAME_TX_REQ
;
5724 np
->base
= ioremap(addr
, np
->register_size
);
5727 dev
->base_addr
= (unsigned long)np
->base
;
5729 dev
->irq
= pci_dev
->irq
;
5731 np
->rx_ring_size
= RX_RING_DEFAULT
;
5732 np
->tx_ring_size
= TX_RING_DEFAULT
;
5734 if (!nv_optimized(np
)) {
5735 np
->rx_ring
.orig
= pci_alloc_consistent(pci_dev
,
5736 sizeof(struct ring_desc
) * (np
->rx_ring_size
+ np
->tx_ring_size
),
5738 if (!np
->rx_ring
.orig
)
5740 np
->tx_ring
.orig
= &np
->rx_ring
.orig
[np
->rx_ring_size
];
5742 np
->rx_ring
.ex
= pci_alloc_consistent(pci_dev
,
5743 sizeof(struct ring_desc_ex
) * (np
->rx_ring_size
+ np
->tx_ring_size
),
5745 if (!np
->rx_ring
.ex
)
5747 np
->tx_ring
.ex
= &np
->rx_ring
.ex
[np
->rx_ring_size
];
5749 np
->rx_skb
= kcalloc(np
->rx_ring_size
, sizeof(struct nv_skb_map
), GFP_KERNEL
);
5750 np
->tx_skb
= kcalloc(np
->tx_ring_size
, sizeof(struct nv_skb_map
), GFP_KERNEL
);
5751 if (!np
->rx_skb
|| !np
->tx_skb
)
5754 if (!nv_optimized(np
))
5755 dev
->netdev_ops
= &nv_netdev_ops
;
5757 dev
->netdev_ops
= &nv_netdev_ops_optimized
;
5759 #ifdef CONFIG_FORCEDETH_NAPI
5760 netif_napi_add(dev
, &np
->napi
, nv_napi_poll
, RX_WORK_PER_LOOP
);
5762 SET_ETHTOOL_OPS(dev
, &ops
);
5763 dev
->watchdog_timeo
= NV_WATCHDOG_TIMEO
;
5765 pci_set_drvdata(pci_dev
, dev
);
5767 /* read the mac address */
5768 base
= get_hwbase(dev
);
5769 np
->orig_mac
[0] = readl(base
+ NvRegMacAddrA
);
5770 np
->orig_mac
[1] = readl(base
+ NvRegMacAddrB
);
5772 /* check the workaround bit for correct mac address order */
5773 txreg
= readl(base
+ NvRegTransmitPoll
);
5774 if (id
->driver_data
& DEV_HAS_CORRECT_MACADDR
) {
5775 /* mac address is already in correct order */
5776 dev
->dev_addr
[0] = (np
->orig_mac
[0] >> 0) & 0xff;
5777 dev
->dev_addr
[1] = (np
->orig_mac
[0] >> 8) & 0xff;
5778 dev
->dev_addr
[2] = (np
->orig_mac
[0] >> 16) & 0xff;
5779 dev
->dev_addr
[3] = (np
->orig_mac
[0] >> 24) & 0xff;
5780 dev
->dev_addr
[4] = (np
->orig_mac
[1] >> 0) & 0xff;
5781 dev
->dev_addr
[5] = (np
->orig_mac
[1] >> 8) & 0xff;
5782 } else if (txreg
& NVREG_TRANSMITPOLL_MAC_ADDR_REV
) {
5783 /* mac address is already in correct order */
5784 dev
->dev_addr
[0] = (np
->orig_mac
[0] >> 0) & 0xff;
5785 dev
->dev_addr
[1] = (np
->orig_mac
[0] >> 8) & 0xff;
5786 dev
->dev_addr
[2] = (np
->orig_mac
[0] >> 16) & 0xff;
5787 dev
->dev_addr
[3] = (np
->orig_mac
[0] >> 24) & 0xff;
5788 dev
->dev_addr
[4] = (np
->orig_mac
[1] >> 0) & 0xff;
5789 dev
->dev_addr
[5] = (np
->orig_mac
[1] >> 8) & 0xff;
5791 * Set orig mac address back to the reversed version.
5792 * This flag will be cleared during low power transition.
5793 * Therefore, we should always put back the reversed address.
5795 np
->orig_mac
[0] = (dev
->dev_addr
[5] << 0) + (dev
->dev_addr
[4] << 8) +
5796 (dev
->dev_addr
[3] << 16) + (dev
->dev_addr
[2] << 24);
5797 np
->orig_mac
[1] = (dev
->dev_addr
[1] << 0) + (dev
->dev_addr
[0] << 8);
5799 /* need to reverse mac address to correct order */
5800 dev
->dev_addr
[0] = (np
->orig_mac
[1] >> 8) & 0xff;
5801 dev
->dev_addr
[1] = (np
->orig_mac
[1] >> 0) & 0xff;
5802 dev
->dev_addr
[2] = (np
->orig_mac
[0] >> 24) & 0xff;
5803 dev
->dev_addr
[3] = (np
->orig_mac
[0] >> 16) & 0xff;
5804 dev
->dev_addr
[4] = (np
->orig_mac
[0] >> 8) & 0xff;
5805 dev
->dev_addr
[5] = (np
->orig_mac
[0] >> 0) & 0xff;
5806 writel(txreg
|NVREG_TRANSMITPOLL_MAC_ADDR_REV
, base
+ NvRegTransmitPoll
);
5807 printk(KERN_DEBUG
"nv_probe: set workaround bit for reversed mac addr\n");
5809 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
5811 if (!is_valid_ether_addr(dev
->perm_addr
)) {
5813 * Bad mac address. At least one bios sets the mac address
5814 * to 01:23:45:67:89:ab
5816 dev_printk(KERN_ERR
, &pci_dev
->dev
,
5817 "Invalid Mac address detected: %pM\n",
5819 dev_printk(KERN_ERR
, &pci_dev
->dev
,
5820 "Please complain to your hardware vendor. Switching to a random MAC.\n");
5821 dev
->dev_addr
[0] = 0x00;
5822 dev
->dev_addr
[1] = 0x00;
5823 dev
->dev_addr
[2] = 0x6c;
5824 get_random_bytes(&dev
->dev_addr
[3], 3);
5827 dprintk(KERN_DEBUG
"%s: MAC Address %pM\n",
5828 pci_name(pci_dev
), dev
->dev_addr
);
5830 /* set mac address */
5831 nv_copy_mac_to_hw(dev
);
5833 /* Workaround current PCI init glitch: wakeup bits aren't
5834 * being set from PCI PM capability.
5836 device_init_wakeup(&pci_dev
->dev
, 1);
5839 writel(0, base
+ NvRegWakeUpFlags
);
5842 if (id
->driver_data
& DEV_HAS_POWER_CNTRL
) {
5844 /* take phy and nic out of low power mode */
5845 powerstate
= readl(base
+ NvRegPowerState2
);
5846 powerstate
&= ~NVREG_POWERSTATE2_POWERUP_MASK
;
5847 if ((id
->device
== PCI_DEVICE_ID_NVIDIA_NVENET_12
||
5848 id
->device
== PCI_DEVICE_ID_NVIDIA_NVENET_13
) &&
5849 pci_dev
->revision
>= 0xA3)
5850 powerstate
|= NVREG_POWERSTATE2_POWERUP_REV_A3
;
5851 writel(powerstate
, base
+ NvRegPowerState2
);
5854 if (np
->desc_ver
== DESC_VER_1
) {
5855 np
->tx_flags
= NV_TX_VALID
;
5857 np
->tx_flags
= NV_TX2_VALID
;
5861 if ((id
->driver_data
& DEV_HAS_MSI
) && msi
) {
5862 np
->msi_flags
|= NV_MSI_CAPABLE
;
5864 if ((id
->driver_data
& DEV_HAS_MSI_X
) && msix
) {
5865 /* msix has had reported issues when modifying irqmask
5866 as in the case of napi, therefore, disable for now
5868 #ifndef CONFIG_FORCEDETH_NAPI
5869 np
->msi_flags
|= NV_MSI_X_CAPABLE
;
5873 if (optimization_mode
== NV_OPTIMIZATION_MODE_CPU
) {
5874 np
->irqmask
= NVREG_IRQMASK_CPU
;
5875 if (np
->msi_flags
& NV_MSI_X_CAPABLE
) /* set number of vectors */
5876 np
->msi_flags
|= 0x0001;
5877 } else if (optimization_mode
== NV_OPTIMIZATION_MODE_DYNAMIC
&&
5878 !(id
->driver_data
& DEV_NEED_TIMERIRQ
)) {
5879 /* start off in throughput mode */
5880 np
->irqmask
= NVREG_IRQMASK_THROUGHPUT
;
5881 /* remove support for msix mode */
5882 np
->msi_flags
&= ~NV_MSI_X_CAPABLE
;
5884 optimization_mode
= NV_OPTIMIZATION_MODE_THROUGHPUT
;
5885 np
->irqmask
= NVREG_IRQMASK_THROUGHPUT
;
5886 if (np
->msi_flags
& NV_MSI_X_CAPABLE
) /* set number of vectors */
5887 np
->msi_flags
|= 0x0003;
5890 if (id
->driver_data
& DEV_NEED_TIMERIRQ
)
5891 np
->irqmask
|= NVREG_IRQ_TIMER
;
5892 if (id
->driver_data
& DEV_NEED_LINKTIMER
) {
5893 dprintk(KERN_INFO
"%s: link timer on.\n", pci_name(pci_dev
));
5894 np
->need_linktimer
= 1;
5895 np
->link_timeout
= jiffies
+ LINK_TIMEOUT
;
5897 dprintk(KERN_INFO
"%s: link timer off.\n", pci_name(pci_dev
));
5898 np
->need_linktimer
= 0;
5901 /* Limit the number of tx's outstanding for hw bug */
5902 if (id
->driver_data
& DEV_NEED_TX_LIMIT
) {
5904 if ((id
->device
== PCI_DEVICE_ID_NVIDIA_NVENET_32
||
5905 id
->device
== PCI_DEVICE_ID_NVIDIA_NVENET_33
||
5906 id
->device
== PCI_DEVICE_ID_NVIDIA_NVENET_34
||
5907 id
->device
== PCI_DEVICE_ID_NVIDIA_NVENET_35
||
5908 id
->device
== PCI_DEVICE_ID_NVIDIA_NVENET_36
||
5909 id
->device
== PCI_DEVICE_ID_NVIDIA_NVENET_37
||
5910 id
->device
== PCI_DEVICE_ID_NVIDIA_NVENET_38
||
5911 id
->device
== PCI_DEVICE_ID_NVIDIA_NVENET_39
) &&
5912 pci_dev
->revision
>= 0xA2)
5916 /* clear phy state and temporarily halt phy interrupts */
5917 writel(0, base
+ NvRegMIIMask
);
5918 phystate
= readl(base
+ NvRegAdapterControl
);
5919 if (phystate
& NVREG_ADAPTCTL_RUNNING
) {
5921 phystate
&= ~NVREG_ADAPTCTL_RUNNING
;
5922 writel(phystate
, base
+ NvRegAdapterControl
);
5924 writel(NVREG_MIISTAT_MASK_ALL
, base
+ NvRegMIIStatus
);
5926 if (id
->driver_data
& DEV_HAS_MGMT_UNIT
) {
5927 /* management unit running on the mac? */
5928 if ((readl(base
+ NvRegTransmitterControl
) & NVREG_XMITCTL_MGMT_ST
) &&
5929 (readl(base
+ NvRegTransmitterControl
) & NVREG_XMITCTL_SYNC_PHY_INIT
) &&
5930 nv_mgmt_acquire_sema(dev
) &&
5931 nv_mgmt_get_version(dev
)) {
5933 if (np
->mgmt_version
> 0) {
5934 np
->mac_in_use
= readl(base
+ NvRegMgmtUnitControl
) & NVREG_MGMTUNITCONTROL_INUSE
;
5936 dprintk(KERN_INFO
"%s: mgmt unit is running. mac in use %x.\n",
5937 pci_name(pci_dev
), np
->mac_in_use
);
5938 /* management unit setup the phy already? */
5939 if (np
->mac_in_use
&&
5940 ((readl(base
+ NvRegTransmitterControl
) & NVREG_XMITCTL_SYNC_MASK
) ==
5941 NVREG_XMITCTL_SYNC_PHY_INIT
)) {
5942 /* phy is inited by mgmt unit */
5944 dprintk(KERN_INFO
"%s: Phy already initialized by mgmt unit.\n",
5947 /* we need to init the phy */
5952 /* find a suitable phy */
5953 for (i
= 1; i
<= 32; i
++) {
5955 int phyaddr
= i
& 0x1F;
5957 spin_lock_irq(&np
->lock
);
5958 id1
= mii_rw(dev
, phyaddr
, MII_PHYSID1
, MII_READ
);
5959 spin_unlock_irq(&np
->lock
);
5960 if (id1
< 0 || id1
== 0xffff)
5962 spin_lock_irq(&np
->lock
);
5963 id2
= mii_rw(dev
, phyaddr
, MII_PHYSID2
, MII_READ
);
5964 spin_unlock_irq(&np
->lock
);
5965 if (id2
< 0 || id2
== 0xffff)
5968 np
->phy_model
= id2
& PHYID2_MODEL_MASK
;
5969 id1
= (id1
& PHYID1_OUI_MASK
) << PHYID1_OUI_SHFT
;
5970 id2
= (id2
& PHYID2_OUI_MASK
) >> PHYID2_OUI_SHFT
;
5971 dprintk(KERN_DEBUG
"%s: open: Found PHY %04x:%04x at address %d.\n",
5972 pci_name(pci_dev
), id1
, id2
, phyaddr
);
5973 np
->phyaddr
= phyaddr
;
5974 np
->phy_oui
= id1
| id2
;
5976 /* Realtek hardcoded phy id1 to all zero's on certain phys */
5977 if (np
->phy_oui
== PHY_OUI_REALTEK2
)
5978 np
->phy_oui
= PHY_OUI_REALTEK
;
5979 /* Setup phy revision for Realtek */
5980 if (np
->phy_oui
== PHY_OUI_REALTEK
&& np
->phy_model
== PHY_MODEL_REALTEK_8211
)
5981 np
->phy_rev
= mii_rw(dev
, phyaddr
, MII_RESV1
, MII_READ
) & PHY_REV_MASK
;
5986 dev_printk(KERN_INFO
, &pci_dev
->dev
,
5987 "open: Could not find a valid PHY.\n");
5991 if (!phyinitialized
) {
5995 /* see if it is a gigabit phy */
5996 u32 mii_status
= mii_rw(dev
, np
->phyaddr
, MII_BMSR
, MII_READ
);
5997 if (mii_status
& PHY_GIGABIT
) {
5998 np
->gigabit
= PHY_GIGABIT
;
6002 /* set default link speed settings */
6003 np
->linkspeed
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
6007 err
= register_netdev(dev
);
6009 dev_printk(KERN_INFO
, &pci_dev
->dev
,
6010 "unable to register netdev: %d\n", err
);
6014 dev_printk(KERN_INFO
, &pci_dev
->dev
, "ifname %s, PHY OUI 0x%x @ %d, "
6015 "addr %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n",
6026 dev_printk(KERN_INFO
, &pci_dev
->dev
, "%s%s%s%s%s%s%s%s%s%sdesc-v%u\n",
6027 dev
->features
& NETIF_F_HIGHDMA
? "highdma " : "",
6028 dev
->features
& (NETIF_F_IP_CSUM
| NETIF_F_SG
) ?
6030 dev
->features
& (NETIF_F_HW_VLAN_RX
| NETIF_F_HW_VLAN_TX
) ?
6032 id
->driver_data
& DEV_HAS_POWER_CNTRL
? "pwrctl " : "",
6033 id
->driver_data
& DEV_HAS_MGMT_UNIT
? "mgmt " : "",
6034 id
->driver_data
& DEV_NEED_TIMERIRQ
? "timirq " : "",
6035 np
->gigabit
== PHY_GIGABIT
? "gbit " : "",
6036 np
->need_linktimer
? "lnktim " : "",
6037 np
->msi_flags
& NV_MSI_CAPABLE
? "msi " : "",
6038 np
->msi_flags
& NV_MSI_X_CAPABLE
? "msi-x " : "",
6045 writel(phystate
|NVREG_ADAPTCTL_RUNNING
, base
+ NvRegAdapterControl
);
6046 pci_set_drvdata(pci_dev
, NULL
);
6050 iounmap(get_hwbase(dev
));
6052 pci_release_regions(pci_dev
);
6054 pci_disable_device(pci_dev
);
6061 static void nv_restore_phy(struct net_device
*dev
)
6063 struct fe_priv
*np
= netdev_priv(dev
);
6064 u16 phy_reserved
, mii_control
;
6066 if (np
->phy_oui
== PHY_OUI_REALTEK
&&
6067 np
->phy_model
== PHY_MODEL_REALTEK_8201
&&
6068 phy_cross
== NV_CROSSOVER_DETECTION_DISABLED
) {
6069 mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG1
, PHY_REALTEK_INIT3
);
6070 phy_reserved
= mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG2
, MII_READ
);
6071 phy_reserved
&= ~PHY_REALTEK_INIT_MSK1
;
6072 phy_reserved
|= PHY_REALTEK_INIT8
;
6073 mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG2
, phy_reserved
);
6074 mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG1
, PHY_REALTEK_INIT1
);
6076 /* restart auto negotiation */
6077 mii_control
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
6078 mii_control
|= (BMCR_ANRESTART
| BMCR_ANENABLE
);
6079 mii_rw(dev
, np
->phyaddr
, MII_BMCR
, mii_control
);
6083 static void nv_restore_mac_addr(struct pci_dev
*pci_dev
)
6085 struct net_device
*dev
= pci_get_drvdata(pci_dev
);
6086 struct fe_priv
*np
= netdev_priv(dev
);
6087 u8 __iomem
*base
= get_hwbase(dev
);
6089 /* special op: write back the misordered MAC address - otherwise
6090 * the next nv_probe would see a wrong address.
6092 writel(np
->orig_mac
[0], base
+ NvRegMacAddrA
);
6093 writel(np
->orig_mac
[1], base
+ NvRegMacAddrB
);
6094 writel(readl(base
+ NvRegTransmitPoll
) & ~NVREG_TRANSMITPOLL_MAC_ADDR_REV
,
6095 base
+ NvRegTransmitPoll
);
6098 static void __devexit
nv_remove(struct pci_dev
*pci_dev
)
6100 struct net_device
*dev
= pci_get_drvdata(pci_dev
);
6102 unregister_netdev(dev
);
6104 nv_restore_mac_addr(pci_dev
);
6106 /* restore any phy related changes */
6107 nv_restore_phy(dev
);
6109 nv_mgmt_release_sema(dev
);
6111 /* free all structures */
6113 iounmap(get_hwbase(dev
));
6114 pci_release_regions(pci_dev
);
6115 pci_disable_device(pci_dev
);
6117 pci_set_drvdata(pci_dev
, NULL
);
6121 static int nv_suspend(struct pci_dev
*pdev
, pm_message_t state
)
6123 struct net_device
*dev
= pci_get_drvdata(pdev
);
6124 struct fe_priv
*np
= netdev_priv(dev
);
6125 u8 __iomem
*base
= get_hwbase(dev
);
6128 if (netif_running(dev
)) {
6132 netif_device_detach(dev
);
6134 /* save non-pci configuration space */
6135 for (i
= 0;i
<= np
->register_size
/sizeof(u32
); i
++)
6136 np
->saved_config_space
[i
] = readl(base
+ i
*sizeof(u32
));
6138 pci_save_state(pdev
);
6139 pci_enable_wake(pdev
, pci_choose_state(pdev
, state
), np
->wolenabled
);
6140 pci_disable_device(pdev
);
6141 pci_set_power_state(pdev
, pci_choose_state(pdev
, state
));
6145 static int nv_resume(struct pci_dev
*pdev
)
6147 struct net_device
*dev
= pci_get_drvdata(pdev
);
6148 struct fe_priv
*np
= netdev_priv(dev
);
6149 u8 __iomem
*base
= get_hwbase(dev
);
6152 pci_set_power_state(pdev
, PCI_D0
);
6153 pci_restore_state(pdev
);
6154 /* ack any pending wake events, disable PME */
6155 pci_enable_wake(pdev
, PCI_D0
, 0);
6157 /* restore non-pci configuration space */
6158 for (i
= 0;i
<= np
->register_size
/sizeof(u32
); i
++)
6159 writel(np
->saved_config_space
[i
], base
+i
*sizeof(u32
));
6161 pci_write_config_dword(pdev
, NV_MSI_PRIV_OFFSET
, NV_MSI_PRIV_VALUE
);
6163 /* restore phy state, including autoneg */
6166 netif_device_attach(dev
);
6167 if (netif_running(dev
)) {
6169 nv_set_multicast(dev
);
6174 static void nv_shutdown(struct pci_dev
*pdev
)
6176 struct net_device
*dev
= pci_get_drvdata(pdev
);
6177 struct fe_priv
*np
= netdev_priv(dev
);
6179 if (netif_running(dev
))
6183 * Restore the MAC so a kernel started by kexec won't get confused.
6184 * If we really go for poweroff, we must not restore the MAC,
6185 * otherwise the MAC for WOL will be reversed at least on some boards.
6187 if (system_state
!= SYSTEM_POWER_OFF
) {
6188 nv_restore_mac_addr(pdev
);
6191 pci_disable_device(pdev
);
6193 * Apparently it is not possible to reinitialise from D3 hot,
6194 * only put the device into D3 if we really go for poweroff.
6196 if (system_state
== SYSTEM_POWER_OFF
) {
6197 if (pci_enable_wake(pdev
, PCI_D3cold
, np
->wolenabled
))
6198 pci_enable_wake(pdev
, PCI_D3hot
, np
->wolenabled
);
6199 pci_set_power_state(pdev
, PCI_D3hot
);
6203 #define nv_suspend NULL
6204 #define nv_shutdown NULL
6205 #define nv_resume NULL
6206 #endif /* CONFIG_PM */
6208 static struct pci_device_id pci_tbl
[] = {
6209 { /* nForce Ethernet Controller */
6210 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_1
),
6211 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
,
6213 { /* nForce2 Ethernet Controller */
6214 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_2
),
6215 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
,
6217 { /* nForce3 Ethernet Controller */
6218 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_3
),
6219 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
,
6221 { /* nForce3 Ethernet Controller */
6222 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_4
),
6223 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
,
6225 { /* nForce3 Ethernet Controller */
6226 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_5
),
6227 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
,
6229 { /* nForce3 Ethernet Controller */
6230 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_6
),
6231 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
,
6233 { /* nForce3 Ethernet Controller */
6234 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_7
),
6235 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
,
6237 { /* CK804 Ethernet Controller */
6238 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_8
),
6239 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_STATISTICS_V1
|DEV_NEED_TX_LIMIT
,
6241 { /* CK804 Ethernet Controller */
6242 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_9
),
6243 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_STATISTICS_V1
|DEV_NEED_TX_LIMIT
,
6245 { /* MCP04 Ethernet Controller */
6246 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_10
),
6247 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_STATISTICS_V1
|DEV_NEED_TX_LIMIT
,
6249 { /* MCP04 Ethernet Controller */
6250 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_11
),
6251 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_STATISTICS_V1
|DEV_NEED_TX_LIMIT
,
6253 { /* MCP51 Ethernet Controller */
6254 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_12
),
6255 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_STATISTICS_V1
,
6257 { /* MCP51 Ethernet Controller */
6258 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_13
),
6259 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_STATISTICS_V1
,
6261 { /* MCP55 Ethernet Controller */
6262 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_14
),
6263 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_VLAN
|DEV_HAS_MSI
|DEV_HAS_MSI_X
|DEV_HAS_POWER_CNTRL
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_NEED_TX_LIMIT
,
6265 { /* MCP55 Ethernet Controller */
6266 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_15
),
6267 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_VLAN
|DEV_HAS_MSI
|DEV_HAS_MSI_X
|DEV_HAS_POWER_CNTRL
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_NEED_TX_LIMIT
,
6269 { /* MCP61 Ethernet Controller */
6270 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_16
),
6271 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
,
6273 { /* MCP61 Ethernet Controller */
6274 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_17
),
6275 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
,
6277 { /* MCP61 Ethernet Controller */
6278 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_18
),
6279 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
,
6281 { /* MCP61 Ethernet Controller */
6282 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_19
),
6283 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
,
6285 { /* MCP65 Ethernet Controller */
6286 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_20
),
6287 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_NEED_TX_LIMIT
|DEV_NEED_TX_LIMIT
|DEV_HAS_GEAR_MODE
,
6289 { /* MCP65 Ethernet Controller */
6290 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_21
),
6291 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_NEED_TX_LIMIT
|DEV_HAS_GEAR_MODE
,
6293 { /* MCP65 Ethernet Controller */
6294 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_22
),
6295 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_NEED_TX_LIMIT
|DEV_HAS_GEAR_MODE
,
6297 { /* MCP65 Ethernet Controller */
6298 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_23
),
6299 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_NEED_TX_LIMIT
|DEV_HAS_GEAR_MODE
,
6301 { /* MCP67 Ethernet Controller */
6302 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_24
),
6303 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_GEAR_MODE
,
6305 { /* MCP67 Ethernet Controller */
6306 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_25
),
6307 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_GEAR_MODE
,
6309 { /* MCP67 Ethernet Controller */
6310 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_26
),
6311 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_GEAR_MODE
,
6313 { /* MCP67 Ethernet Controller */
6314 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_27
),
6315 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_GEAR_MODE
,
6317 { /* MCP73 Ethernet Controller */
6318 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_28
),
6319 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_HAS_GEAR_MODE
,
6321 { /* MCP73 Ethernet Controller */
6322 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_29
),
6323 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_HAS_GEAR_MODE
,
6325 { /* MCP73 Ethernet Controller */
6326 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_30
),
6327 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_HAS_GEAR_MODE
,
6329 { /* MCP73 Ethernet Controller */
6330 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_31
),
6331 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_HAS_GEAR_MODE
,
6333 { /* MCP77 Ethernet Controller */
6334 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_32
),
6335 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_MSI
|DEV_HAS_POWER_CNTRL
|DEV_HAS_PAUSEFRAME_TX_V2
|DEV_HAS_STATISTICS_V3
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_NEED_TX_LIMIT
|DEV_HAS_GEAR_MODE
,
6337 { /* MCP77 Ethernet Controller */
6338 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_33
),
6339 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_MSI
|DEV_HAS_POWER_CNTRL
|DEV_HAS_PAUSEFRAME_TX_V2
|DEV_HAS_STATISTICS_V3
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_NEED_TX_LIMIT
|DEV_HAS_GEAR_MODE
,
6341 { /* MCP77 Ethernet Controller */
6342 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_34
),
6343 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_MSI
|DEV_HAS_POWER_CNTRL
|DEV_HAS_PAUSEFRAME_TX_V2
|DEV_HAS_STATISTICS_V3
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_NEED_TX_LIMIT
|DEV_HAS_GEAR_MODE
,
6345 { /* MCP77 Ethernet Controller */
6346 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_35
),
6347 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_MSI
|DEV_HAS_POWER_CNTRL
|DEV_HAS_PAUSEFRAME_TX_V2
|DEV_HAS_STATISTICS_V3
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_NEED_TX_LIMIT
|DEV_HAS_GEAR_MODE
,
6349 { /* MCP79 Ethernet Controller */
6350 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_36
),
6351 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_MSI
|DEV_HAS_POWER_CNTRL
|DEV_HAS_PAUSEFRAME_TX_V3
|DEV_HAS_STATISTICS_V3
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_NEED_TX_LIMIT
|DEV_HAS_GEAR_MODE
,
6353 { /* MCP79 Ethernet Controller */
6354 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_37
),
6355 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_MSI
|DEV_HAS_POWER_CNTRL
|DEV_HAS_PAUSEFRAME_TX_V3
|DEV_HAS_STATISTICS_V3
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_NEED_TX_LIMIT
|DEV_HAS_GEAR_MODE
,
6357 { /* MCP79 Ethernet Controller */
6358 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_38
),
6359 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_MSI
|DEV_HAS_POWER_CNTRL
|DEV_HAS_PAUSEFRAME_TX_V3
|DEV_HAS_STATISTICS_V3
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_NEED_TX_LIMIT
|DEV_HAS_GEAR_MODE
,
6361 { /* MCP79 Ethernet Controller */
6362 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_39
),
6363 .driver_data
= DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_MSI
|DEV_HAS_POWER_CNTRL
|DEV_HAS_PAUSEFRAME_TX_V3
|DEV_HAS_STATISTICS_V3
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_NEED_TX_LIMIT
|DEV_HAS_GEAR_MODE
,
6368 static struct pci_driver driver
= {
6370 .id_table
= pci_tbl
,
6372 .remove
= __devexit_p(nv_remove
),
6373 .suspend
= nv_suspend
,
6374 .resume
= nv_resume
,
6375 .shutdown
= nv_shutdown
,
6378 static int __init
init_nic(void)
6380 return pci_register_driver(&driver
);
6383 static void __exit
exit_nic(void)
6385 pci_unregister_driver(&driver
);
6388 module_param(max_interrupt_work
, int, 0);
6389 MODULE_PARM_DESC(max_interrupt_work
, "forcedeth maximum events handled per interrupt");
6390 module_param(optimization_mode
, int, 0);
6391 MODULE_PARM_DESC(optimization_mode
, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer. In dynamic mode (2), the mode toggles between throughput and CPU mode based on network load.");
6392 module_param(poll_interval
, int, 0);
6393 MODULE_PARM_DESC(poll_interval
, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
6394 module_param(msi
, int, 0);
6395 MODULE_PARM_DESC(msi
, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
6396 module_param(msix
, int, 0);
6397 MODULE_PARM_DESC(msix
, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
6398 module_param(dma_64bit
, int, 0);
6399 MODULE_PARM_DESC(dma_64bit
, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
6400 module_param(phy_cross
, int, 0);
6401 MODULE_PARM_DESC(phy_cross
, "Phy crossover detection for Realtek 8201 phy is enabled by setting to 1 and disabled by setting to 0.");
6402 module_param(phy_power_down
, int, 0);
6403 MODULE_PARM_DESC(phy_power_down
, "Power down phy and disable link when interface is down (1), or leave phy powered up (0).");
6405 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
6406 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
6407 MODULE_LICENSE("GPL");
6409 MODULE_DEVICE_TABLE(pci
, pci_tbl
);
6411 module_init(init_nic
);
6412 module_exit(exit_nic
);