2 * V4L2 Driver for PXA camera host
4 * Copyright (C) 2006, Sascha Hauer, Pengutronix
5 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
13 #include <linux/init.h>
14 #include <linux/module.h>
16 #include <linux/delay.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/errno.h>
20 #include <linux/interrupt.h>
21 #include <linux/kernel.h>
23 #include <linux/moduleparam.h>
24 #include <linux/time.h>
25 #include <linux/version.h>
26 #include <linux/device.h>
27 #include <linux/platform_device.h>
28 #include <linux/clk.h>
30 #include <media/v4l2-common.h>
31 #include <media/v4l2-dev.h>
32 #include <media/videobuf-dma-sg.h>
33 #include <media/soc_camera.h>
35 #include <linux/videodev2.h>
38 #include <mach/pxa-regs.h>
39 #include <mach/camera.h>
41 #define PXA_CAM_VERSION_CODE KERNEL_VERSION(0, 0, 5)
42 #define PXA_CAM_DRV_NAME "pxa27x-camera"
44 /* Camera Interface */
57 #define CICR0_DMAEN (1 << 31) /* DMA request enable */
58 #define CICR0_PAR_EN (1 << 30) /* Parity enable */
59 #define CICR0_SL_CAP_EN (1 << 29) /* Capture enable for slave mode */
60 #define CICR0_ENB (1 << 28) /* Camera interface enable */
61 #define CICR0_DIS (1 << 27) /* Camera interface disable */
62 #define CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */
63 #define CICR0_TOM (1 << 9) /* Time-out mask */
64 #define CICR0_RDAVM (1 << 8) /* Receive-data-available mask */
65 #define CICR0_FEM (1 << 7) /* FIFO-empty mask */
66 #define CICR0_EOLM (1 << 6) /* End-of-line mask */
67 #define CICR0_PERRM (1 << 5) /* Parity-error mask */
68 #define CICR0_QDM (1 << 4) /* Quick-disable mask */
69 #define CICR0_CDM (1 << 3) /* Disable-done mask */
70 #define CICR0_SOFM (1 << 2) /* Start-of-frame mask */
71 #define CICR0_EOFM (1 << 1) /* End-of-frame mask */
72 #define CICR0_FOM (1 << 0) /* FIFO-overrun mask */
74 #define CICR1_TBIT (1 << 31) /* Transparency bit */
75 #define CICR1_RGBT_CONV (0x3 << 29) /* RGBT conversion mask */
76 #define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */
77 #define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */
78 #define CICR1_RGB_F (1 << 11) /* RGB format */
79 #define CICR1_YCBCR_F (1 << 10) /* YCbCr format */
80 #define CICR1_RGB_BPP (0x7 << 7) /* RGB bis per pixel mask */
81 #define CICR1_RAW_BPP (0x3 << 5) /* Raw bis per pixel mask */
82 #define CICR1_COLOR_SP (0x3 << 3) /* Color space mask */
83 #define CICR1_DW (0x7 << 0) /* Data width mask */
85 #define CICR2_BLW (0xff << 24) /* Beginning-of-line pixel clock
87 #define CICR2_ELW (0xff << 16) /* End-of-line pixel clock
89 #define CICR2_HSW (0x3f << 10) /* Horizontal sync pulse width mask */
90 #define CICR2_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
92 #define CICR2_FSW (0x7 << 0) /* Frame stabilization
95 #define CICR3_BFW (0xff << 24) /* Beginning-of-frame line clock
97 #define CICR3_EFW (0xff << 16) /* End-of-frame line clock
99 #define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */
100 #define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
102 #define CICR3_LPF (0x7ff << 0) /* Lines per frame mask */
104 #define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */
105 #define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */
106 #define CICR4_PCP (1 << 22) /* Pixel clock polarity */
107 #define CICR4_HSP (1 << 21) /* Horizontal sync polarity */
108 #define CICR4_VSP (1 << 20) /* Vertical sync polarity */
109 #define CICR4_MCLK_EN (1 << 19) /* MCLK enable */
110 #define CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */
111 #define CICR4_DIV (0xff << 0) /* Clock divisor mask */
113 #define CISR_FTO (1 << 15) /* FIFO time-out */
114 #define CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */
115 #define CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */
116 #define CISR_RDAV_0 (1 << 12) /* Channel 0 receive data available */
117 #define CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO empty */
118 #define CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO empty */
119 #define CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO empty */
120 #define CISR_EOL (1 << 8) /* End of line */
121 #define CISR_PAR_ERR (1 << 7) /* Parity error */
122 #define CISR_CQD (1 << 6) /* Camera interface quick disable */
123 #define CISR_CDD (1 << 5) /* Camera interface disable done */
124 #define CISR_SOF (1 << 4) /* Start of frame */
125 #define CISR_EOF (1 << 3) /* End of frame */
126 #define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */
127 #define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */
128 #define CISR_IFO_0 (1 << 0) /* FIFO overrun for Channel 0 */
130 #define CIFR_FLVL2 (0x7f << 23) /* FIFO 2 level mask */
131 #define CIFR_FLVL1 (0x7f << 16) /* FIFO 1 level mask */
132 #define CIFR_FLVL0 (0xff << 8) /* FIFO 0 level mask */
133 #define CIFR_THL_0 (0x3 << 4) /* Threshold Level for Channel 0 FIFO */
134 #define CIFR_RESET_F (1 << 3) /* Reset input FIFOs */
135 #define CIFR_FEN2 (1 << 2) /* FIFO enable for channel 2 */
136 #define CIFR_FEN1 (1 << 1) /* FIFO enable for channel 1 */
137 #define CIFR_FEN0 (1 << 0) /* FIFO enable for channel 0 */
139 #define CICR0_SIM_MP (0 << 24)
140 #define CICR0_SIM_SP (1 << 24)
141 #define CICR0_SIM_MS (2 << 24)
142 #define CICR0_SIM_EP (3 << 24)
143 #define CICR0_SIM_ES (4 << 24)
145 #define CICR1_DW_VAL(x) ((x) & CICR1_DW) /* Data bus width */
146 #define CICR1_PPL_VAL(x) (((x) << 15) & CICR1_PPL) /* Pixels per line */
147 #define CICR1_COLOR_SP_VAL(x) (((x) << 3) & CICR1_COLOR_SP) /* color space */
148 #define CICR1_RGB_BPP_VAL(x) (((x) << 7) & CICR1_RGB_BPP) /* bpp for rgb */
149 #define CICR1_RGBT_CONV_VAL(x) (((x) << 29) & CICR1_RGBT_CONV) /* rgbt conv */
151 #define CICR2_BLW_VAL(x) (((x) << 24) & CICR2_BLW) /* Beginning-of-line pixel clock wait count */
152 #define CICR2_ELW_VAL(x) (((x) << 16) & CICR2_ELW) /* End-of-line pixel clock wait count */
153 #define CICR2_HSW_VAL(x) (((x) << 10) & CICR2_HSW) /* Horizontal sync pulse width */
154 #define CICR2_BFPW_VAL(x) (((x) << 3) & CICR2_BFPW) /* Beginning-of-frame pixel clock wait count */
155 #define CICR2_FSW_VAL(x) (((x) << 0) & CICR2_FSW) /* Frame stabilization wait count */
157 #define CICR3_BFW_VAL(x) (((x) << 24) & CICR3_BFW) /* Beginning-of-frame line clock wait count */
158 #define CICR3_EFW_VAL(x) (((x) << 16) & CICR3_EFW) /* End-of-frame line clock wait count */
159 #define CICR3_VSW_VAL(x) (((x) << 11) & CICR3_VSW) /* Vertical sync pulse width */
160 #define CICR3_LPF_VAL(x) (((x) << 0) & CICR3_LPF) /* Lines per frame */
162 #define CICR0_IRQ_MASK (CICR0_TOM | CICR0_RDAVM | CICR0_FEM | CICR0_EOLM | \
163 CICR0_PERRM | CICR0_QDM | CICR0_CDM | CICR0_SOFM | \
164 CICR0_EOFM | CICR0_FOM)
169 enum pxa_camera_active_dma
{
175 /* descriptor needed for the PXA DMA engine */
178 struct pxa_dma_desc
*sg_cpu
;
183 /* buffer for one video frame */
185 /* common v4l buffer stuff -- must be first */
186 struct videobuf_buffer vb
;
188 const struct soc_camera_data_format
*fmt
;
190 /* our descriptor lists for Y, U and V channels */
191 struct pxa_cam_dma dmas
[3];
195 enum pxa_camera_active_dma active_dma
;
198 struct pxa_camera_dev
{
200 /* PXA27x is only supposed to handle one camera on its Quick Capture
201 * interface. If anyone ever builds hardware to enable more than
202 * one camera, they will have to modify this driver too */
203 struct soc_camera_device
*icd
;
210 unsigned int dma_chans
[3];
212 struct pxacamera_platform_data
*pdata
;
213 struct resource
*res
;
214 unsigned long platform_flags
;
219 struct list_head capture
;
223 struct pxa_buffer
*active
;
224 struct pxa_dma_desc
*sg_tail
[3];
229 static const char *pxa_cam_driver_description
= "PXA_Camera";
231 static unsigned int vid_limit
= 16; /* Video memory limit, in Mb */
234 * Videobuf operations
236 static int pxa_videobuf_setup(struct videobuf_queue
*vq
, unsigned int *count
,
239 struct soc_camera_device
*icd
= vq
->priv_data
;
240 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->dev
.parent
);
241 struct pxa_camera_dev
*pcdev
= ici
->priv
;
243 dev_dbg(&icd
->dev
, "count=%d, size=%d\n", *count
, *size
);
245 /* planar capture requires Y, U and V buffers to be page aligned */
246 if (pcdev
->channels
== 3) {
247 *size
= PAGE_ALIGN(icd
->width
* icd
->height
); /* Y pages */
248 *size
+= PAGE_ALIGN(icd
->width
* icd
->height
/ 2); /* U pages */
249 *size
+= PAGE_ALIGN(icd
->width
* icd
->height
/ 2); /* V pages */
251 *size
= icd
->width
* icd
->height
*
252 ((icd
->current_fmt
->depth
+ 7) >> 3);
257 while (*size
* *count
> vid_limit
* 1024 * 1024)
263 static void free_buffer(struct videobuf_queue
*vq
, struct pxa_buffer
*buf
)
265 struct soc_camera_device
*icd
= vq
->priv_data
;
266 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->dev
.parent
);
267 struct pxa_camera_dev
*pcdev
= ici
->priv
;
268 struct videobuf_dmabuf
*dma
= videobuf_to_dma(&buf
->vb
);
271 BUG_ON(in_interrupt());
273 dev_dbg(&icd
->dev
, "%s (vb=0x%p) 0x%08lx %d\n", __func__
,
274 &buf
->vb
, buf
->vb
.baddr
, buf
->vb
.bsize
);
276 /* This waits until this buffer is out of danger, i.e., until it is no
277 * longer in STATE_QUEUED or STATE_ACTIVE */
278 videobuf_waiton(&buf
->vb
, 0, 0);
279 videobuf_dma_unmap(vq
, dma
);
280 videobuf_dma_free(dma
);
282 for (i
= 0; i
< ARRAY_SIZE(buf
->dmas
); i
++) {
283 if (buf
->dmas
[i
].sg_cpu
)
284 dma_free_coherent(pcdev
->dev
, buf
->dmas
[i
].sg_size
,
286 buf
->dmas
[i
].sg_dma
);
287 buf
->dmas
[i
].sg_cpu
= NULL
;
290 buf
->vb
.state
= VIDEOBUF_NEEDS_INIT
;
293 static int pxa_init_dma_channel(struct pxa_camera_dev
*pcdev
,
294 struct pxa_buffer
*buf
,
295 struct videobuf_dmabuf
*dma
, int channel
,
296 int sglen
, int sg_start
, int cibr
,
299 struct pxa_cam_dma
*pxa_dma
= &buf
->dmas
[channel
];
303 dma_free_coherent(pcdev
->dev
, pxa_dma
->sg_size
,
304 pxa_dma
->sg_cpu
, pxa_dma
->sg_dma
);
306 pxa_dma
->sg_size
= (sglen
+ 1) * sizeof(struct pxa_dma_desc
);
307 pxa_dma
->sg_cpu
= dma_alloc_coherent(pcdev
->dev
, pxa_dma
->sg_size
,
308 &pxa_dma
->sg_dma
, GFP_KERNEL
);
309 if (!pxa_dma
->sg_cpu
)
312 pxa_dma
->sglen
= sglen
;
314 for (i
= 0; i
< sglen
; i
++) {
315 int sg_i
= sg_start
+ i
;
316 struct scatterlist
*sg
= dma
->sglist
;
317 unsigned int dma_len
= sg_dma_len(&sg
[sg_i
]), xfer_len
;
319 pxa_dma
->sg_cpu
[i
].dsadr
= pcdev
->res
->start
+ cibr
;
320 pxa_dma
->sg_cpu
[i
].dtadr
= sg_dma_address(&sg
[sg_i
]);
322 /* PXA27x Developer's Manual 27.4.4.1: round up to 8 bytes */
323 xfer_len
= (min(dma_len
, size
) + 7) & ~7;
325 pxa_dma
->sg_cpu
[i
].dcmd
=
326 DCMD_FLOWSRC
| DCMD_BURST8
| DCMD_INCTRGADDR
| xfer_len
;
328 pxa_dma
->sg_cpu
[i
].ddadr
=
329 pxa_dma
->sg_dma
+ (i
+ 1) * sizeof(struct pxa_dma_desc
);
332 pxa_dma
->sg_cpu
[sglen
- 1].ddadr
= DDADR_STOP
;
333 pxa_dma
->sg_cpu
[sglen
- 1].dcmd
|= DCMD_ENDIRQEN
;
338 static int pxa_videobuf_prepare(struct videobuf_queue
*vq
,
339 struct videobuf_buffer
*vb
, enum v4l2_field field
)
341 struct soc_camera_device
*icd
= vq
->priv_data
;
342 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->dev
.parent
);
343 struct pxa_camera_dev
*pcdev
= ici
->priv
;
344 struct pxa_buffer
*buf
= container_of(vb
, struct pxa_buffer
, vb
);
346 int sglen_y
, sglen_yu
= 0, sglen_u
= 0, sglen_v
= 0;
347 int size_y
, size_u
= 0, size_v
= 0;
349 dev_dbg(&icd
->dev
, "%s (vb=0x%p) 0x%08lx %d\n", __func__
,
350 vb
, vb
->baddr
, vb
->bsize
);
352 /* Added list head initialization on alloc */
353 WARN_ON(!list_empty(&vb
->queue
));
356 /* This can be useful if you want to see if we actually fill
357 * the buffer with something */
358 memset((void *)vb
->baddr
, 0xaa, vb
->bsize
);
361 BUG_ON(NULL
== icd
->current_fmt
);
363 /* I think, in buf_prepare you only have to protect global data,
364 * the actual buffer is yours */
367 if (buf
->fmt
!= icd
->current_fmt
||
368 vb
->width
!= icd
->width
||
369 vb
->height
!= icd
->height
||
370 vb
->field
!= field
) {
371 buf
->fmt
= icd
->current_fmt
;
372 vb
->width
= icd
->width
;
373 vb
->height
= icd
->height
;
375 vb
->state
= VIDEOBUF_NEEDS_INIT
;
378 vb
->size
= vb
->width
* vb
->height
* ((buf
->fmt
->depth
+ 7) >> 3);
379 if (0 != vb
->baddr
&& vb
->bsize
< vb
->size
) {
384 if (vb
->state
== VIDEOBUF_NEEDS_INIT
) {
385 unsigned int size
= vb
->size
;
386 struct videobuf_dmabuf
*dma
= videobuf_to_dma(vb
);
388 ret
= videobuf_iolock(vq
, vb
, NULL
);
392 if (pcdev
->channels
== 3) {
393 /* FIXME the calculations should be more precise */
394 sglen_y
= dma
->sglen
/ 2;
395 sglen_u
= sglen_v
= dma
->sglen
/ 4 + 1;
396 sglen_yu
= sglen_y
+ sglen_u
;
398 size_u
= size_v
= size
/ 4;
400 sglen_y
= dma
->sglen
;
404 /* init DMA for Y channel */
405 ret
= pxa_init_dma_channel(pcdev
, buf
, dma
, 0, sglen_y
,
410 "DMA initialization for Y/RGB failed\n");
414 if (pcdev
->channels
== 3) {
415 /* init DMA for U channel */
416 ret
= pxa_init_dma_channel(pcdev
, buf
, dma
, 1, sglen_u
,
417 sglen_y
, 0x30, size_u
);
420 "DMA initialization for U failed\n");
424 /* init DMA for V channel */
425 ret
= pxa_init_dma_channel(pcdev
, buf
, dma
, 2, sglen_v
,
426 sglen_yu
, 0x38, size_v
);
429 "DMA initialization for V failed\n");
434 vb
->state
= VIDEOBUF_PREPARED
;
438 buf
->active_dma
= DMA_Y
;
439 if (pcdev
->channels
== 3)
440 buf
->active_dma
|= DMA_U
| DMA_V
;
445 dma_free_coherent(pcdev
->dev
, buf
->dmas
[1].sg_size
,
446 buf
->dmas
[1].sg_cpu
, buf
->dmas
[1].sg_dma
);
448 dma_free_coherent(pcdev
->dev
, buf
->dmas
[0].sg_size
,
449 buf
->dmas
[0].sg_cpu
, buf
->dmas
[0].sg_dma
);
451 free_buffer(vq
, buf
);
457 static void pxa_videobuf_queue(struct videobuf_queue
*vq
,
458 struct videobuf_buffer
*vb
)
460 struct soc_camera_device
*icd
= vq
->priv_data
;
461 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->dev
.parent
);
462 struct pxa_camera_dev
*pcdev
= ici
->priv
;
463 struct pxa_buffer
*buf
= container_of(vb
, struct pxa_buffer
, vb
);
464 struct pxa_buffer
*active
;
468 dev_dbg(&icd
->dev
, "%s (vb=0x%p) 0x%08lx %d\n", __func__
,
469 vb
, vb
->baddr
, vb
->bsize
);
470 spin_lock_irqsave(&pcdev
->lock
, flags
);
472 list_add_tail(&vb
->queue
, &pcdev
->capture
);
474 vb
->state
= VIDEOBUF_ACTIVE
;
475 active
= pcdev
->active
;
478 unsigned long cifr
, cicr0
;
480 cifr
= __raw_readl(pcdev
->base
+ CIFR
) | CIFR_RESET_F
;
481 __raw_writel(cifr
, pcdev
->base
+ CIFR
);
483 for (i
= 0; i
< pcdev
->channels
; i
++) {
484 DDADR(pcdev
->dma_chans
[i
]) = buf
->dmas
[i
].sg_dma
;
485 DCSR(pcdev
->dma_chans
[i
]) = DCSR_RUN
;
486 pcdev
->sg_tail
[i
] = buf
->dmas
[i
].sg_cpu
+ buf
->dmas
[i
].sglen
- 1;
491 cicr0
= __raw_readl(pcdev
->base
+ CICR0
) | CICR0_ENB
;
492 __raw_writel(cicr0
, pcdev
->base
+ CICR0
);
494 struct pxa_cam_dma
*buf_dma
;
495 struct pxa_cam_dma
*act_dma
;
498 for (i
= 0; i
< pcdev
->channels
; i
++) {
499 buf_dma
= &buf
->dmas
[i
];
500 act_dma
= &active
->dmas
[i
];
501 nents
= buf_dma
->sglen
;
503 /* Stop DMA engine */
504 DCSR(pcdev
->dma_chans
[i
]) = 0;
506 /* Add the descriptors we just initialized to
507 the currently running chain */
508 pcdev
->sg_tail
[i
]->ddadr
= buf_dma
->sg_dma
;
509 pcdev
->sg_tail
[i
] = buf_dma
->sg_cpu
+ buf_dma
->sglen
- 1;
511 /* Setup a dummy descriptor with the DMA engines current
514 buf_dma
->sg_cpu
[nents
].dsadr
=
515 pcdev
->res
->start
+ 0x28 + i
*8; /* CIBRx */
516 buf_dma
->sg_cpu
[nents
].dtadr
=
517 DTADR(pcdev
->dma_chans
[i
]);
518 buf_dma
->sg_cpu
[nents
].dcmd
=
519 DCMD(pcdev
->dma_chans
[i
]);
521 if (DDADR(pcdev
->dma_chans
[i
]) == DDADR_STOP
) {
522 /* The DMA engine is on the last
523 descriptor, set the next descriptors
524 address to the descriptors we just
526 buf_dma
->sg_cpu
[nents
].ddadr
= buf_dma
->sg_dma
;
528 buf_dma
->sg_cpu
[nents
].ddadr
=
529 DDADR(pcdev
->dma_chans
[i
]);
532 /* The next descriptor is the dummy descriptor */
533 DDADR(pcdev
->dma_chans
[i
]) = buf_dma
->sg_dma
+ nents
*
534 sizeof(struct pxa_dma_desc
);
536 DCSR(pcdev
->dma_chans
[i
]) = DCSR_RUN
;
540 spin_unlock_irqrestore(&pcdev
->lock
, flags
);
543 static void pxa_videobuf_release(struct videobuf_queue
*vq
,
544 struct videobuf_buffer
*vb
)
546 struct pxa_buffer
*buf
= container_of(vb
, struct pxa_buffer
, vb
);
548 struct soc_camera_device
*icd
= vq
->priv_data
;
550 dev_dbg(&icd
->dev
, "%s (vb=0x%p) 0x%08lx %d\n", __func__
,
551 vb
, vb
->baddr
, vb
->bsize
);
554 case VIDEOBUF_ACTIVE
:
555 dev_dbg(&icd
->dev
, "%s (active)\n", __func__
);
557 case VIDEOBUF_QUEUED
:
558 dev_dbg(&icd
->dev
, "%s (queued)\n", __func__
);
560 case VIDEOBUF_PREPARED
:
561 dev_dbg(&icd
->dev
, "%s (prepared)\n", __func__
);
564 dev_dbg(&icd
->dev
, "%s (unknown)\n", __func__
);
569 free_buffer(vq
, buf
);
572 static void pxa_camera_wakeup(struct pxa_camera_dev
*pcdev
,
573 struct videobuf_buffer
*vb
,
574 struct pxa_buffer
*buf
)
578 /* _init is used to debug races, see comment in pxa_camera_reqbufs() */
579 list_del_init(&vb
->queue
);
580 vb
->state
= VIDEOBUF_DONE
;
581 do_gettimeofday(&vb
->ts
);
585 if (list_empty(&pcdev
->capture
)) {
586 pcdev
->active
= NULL
;
587 DCSR(pcdev
->dma_chans
[0]) = 0;
588 DCSR(pcdev
->dma_chans
[1]) = 0;
589 DCSR(pcdev
->dma_chans
[2]) = 0;
591 cicr0
= __raw_readl(pcdev
->base
+ CICR0
) & ~CICR0_ENB
;
592 __raw_writel(cicr0
, pcdev
->base
+ CICR0
);
596 pcdev
->active
= list_entry(pcdev
->capture
.next
,
597 struct pxa_buffer
, vb
.queue
);
600 static void pxa_camera_dma_irq(int channel
, struct pxa_camera_dev
*pcdev
,
601 enum pxa_camera_active_dma act_dma
)
603 struct pxa_buffer
*buf
;
605 u32 status
, camera_status
, overrun
;
606 struct videobuf_buffer
*vb
;
607 unsigned long cifr
, cicr0
;
609 spin_lock_irqsave(&pcdev
->lock
, flags
);
611 status
= DCSR(channel
);
612 DCSR(channel
) = status
| DCSR_ENDINTR
;
614 if (status
& DCSR_BUSERR
) {
615 dev_err(pcdev
->dev
, "DMA Bus Error IRQ!\n");
619 if (!(status
& DCSR_ENDINTR
)) {
620 dev_err(pcdev
->dev
, "Unknown DMA IRQ source, "
621 "status: 0x%08x\n", status
);
625 if (!pcdev
->active
) {
626 dev_err(pcdev
->dev
, "DMA End IRQ with no active buffer!\n");
630 camera_status
= __raw_readl(pcdev
->base
+ CISR
);
631 overrun
= CISR_IFO_0
;
632 if (pcdev
->channels
== 3)
633 overrun
|= CISR_IFO_1
| CISR_IFO_2
;
634 if (camera_status
& overrun
) {
635 dev_dbg(pcdev
->dev
, "FIFO overrun! CISR: %x\n", camera_status
);
636 /* Stop the Capture Interface */
637 cicr0
= __raw_readl(pcdev
->base
+ CICR0
) & ~CICR0_ENB
;
638 __raw_writel(cicr0
, pcdev
->base
+ CICR0
);
642 /* Reset the FIFOs */
643 cifr
= __raw_readl(pcdev
->base
+ CIFR
) | CIFR_RESET_F
;
644 __raw_writel(cifr
, pcdev
->base
+ CIFR
);
645 /* Enable End-Of-Frame Interrupt */
646 cicr0
&= ~CICR0_EOFM
;
647 __raw_writel(cicr0
, pcdev
->base
+ CICR0
);
648 /* Restart the Capture Interface */
649 __raw_writel(cicr0
| CICR0_ENB
, pcdev
->base
+ CICR0
);
653 vb
= &pcdev
->active
->vb
;
654 buf
= container_of(vb
, struct pxa_buffer
, vb
);
655 WARN_ON(buf
->inwork
|| list_empty(&vb
->queue
));
656 dev_dbg(pcdev
->dev
, "%s (vb=0x%p) 0x%08lx %d\n", __func__
,
657 vb
, vb
->baddr
, vb
->bsize
);
659 buf
->active_dma
&= ~act_dma
;
660 if (!buf
->active_dma
)
661 pxa_camera_wakeup(pcdev
, vb
, buf
);
664 spin_unlock_irqrestore(&pcdev
->lock
, flags
);
667 static void pxa_camera_dma_irq_y(int channel
, void *data
)
669 struct pxa_camera_dev
*pcdev
= data
;
670 pxa_camera_dma_irq(channel
, pcdev
, DMA_Y
);
673 static void pxa_camera_dma_irq_u(int channel
, void *data
)
675 struct pxa_camera_dev
*pcdev
= data
;
676 pxa_camera_dma_irq(channel
, pcdev
, DMA_U
);
679 static void pxa_camera_dma_irq_v(int channel
, void *data
)
681 struct pxa_camera_dev
*pcdev
= data
;
682 pxa_camera_dma_irq(channel
, pcdev
, DMA_V
);
685 static struct videobuf_queue_ops pxa_videobuf_ops
= {
686 .buf_setup
= pxa_videobuf_setup
,
687 .buf_prepare
= pxa_videobuf_prepare
,
688 .buf_queue
= pxa_videobuf_queue
,
689 .buf_release
= pxa_videobuf_release
,
692 static void pxa_camera_init_videobuf(struct videobuf_queue
*q
,
693 struct soc_camera_device
*icd
)
695 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->dev
.parent
);
696 struct pxa_camera_dev
*pcdev
= ici
->priv
;
698 /* We must pass NULL as dev pointer, then all pci_* dma operations
699 * transform to normal dma_* ones. */
700 videobuf_queue_sg_init(q
, &pxa_videobuf_ops
, NULL
, &pcdev
->lock
,
701 V4L2_BUF_TYPE_VIDEO_CAPTURE
, V4L2_FIELD_NONE
,
702 sizeof(struct pxa_buffer
), icd
);
705 static u32
mclk_get_divisor(struct pxa_camera_dev
*pcdev
)
707 unsigned long mclk
= pcdev
->mclk
;
709 unsigned long lcdclk
;
711 lcdclk
= clk_get_rate(pcdev
->clk
);
712 pcdev
->ciclk
= lcdclk
;
714 /* mclk <= ciclk / 4 (27.4.2) */
715 if (mclk
> lcdclk
/ 4) {
717 dev_warn(pcdev
->dev
, "Limiting master clock to %lu\n", mclk
);
720 /* We verify mclk != 0, so if anyone breaks it, here comes their Oops */
721 div
= (lcdclk
+ 2 * mclk
- 1) / (2 * mclk
) - 1;
723 /* If we're not supplying MCLK, leave it at 0 */
724 if (pcdev
->platform_flags
& PXA_CAMERA_MCLK_EN
)
725 pcdev
->mclk
= lcdclk
/ (2 * (div
+ 1));
727 dev_dbg(pcdev
->dev
, "LCD clock %luHz, target freq %luHz, "
728 "divisor %u\n", lcdclk
, mclk
, div
);
733 static void recalculate_fifo_timeout(struct pxa_camera_dev
*pcdev
,
736 /* We want a timeout > 1 pixel time, not ">=" */
737 u32 ciclk_per_pixel
= pcdev
->ciclk
/ pclk
+ 1;
739 __raw_writel(ciclk_per_pixel
, pcdev
->base
+ CITOR
);
742 static void pxa_camera_activate(struct pxa_camera_dev
*pcdev
)
744 struct pxacamera_platform_data
*pdata
= pcdev
->pdata
;
747 dev_dbg(pcdev
->dev
, "Registered platform device at %p data %p\n",
750 if (pdata
&& pdata
->init
) {
751 dev_dbg(pcdev
->dev
, "%s: Init gpios\n", __func__
);
752 pdata
->init(pcdev
->dev
);
755 /* disable all interrupts */
756 __raw_writel(0x3ff, pcdev
->base
+ CICR0
);
758 if (pcdev
->platform_flags
& PXA_CAMERA_PCLK_EN
)
759 cicr4
|= CICR4_PCLK_EN
;
760 if (pcdev
->platform_flags
& PXA_CAMERA_MCLK_EN
)
761 cicr4
|= CICR4_MCLK_EN
;
762 if (pcdev
->platform_flags
& PXA_CAMERA_PCP
)
764 if (pcdev
->platform_flags
& PXA_CAMERA_HSP
)
766 if (pcdev
->platform_flags
& PXA_CAMERA_VSP
)
769 __raw_writel(pcdev
->mclk_divisor
| cicr4
, pcdev
->base
+ CICR4
);
771 if (pcdev
->platform_flags
& PXA_CAMERA_MCLK_EN
)
772 /* Initialise the timeout under the assumption pclk = mclk */
773 recalculate_fifo_timeout(pcdev
, pcdev
->mclk
);
775 /* "Safe default" - 13MHz */
776 recalculate_fifo_timeout(pcdev
, 13000000);
778 clk_enable(pcdev
->clk
);
781 static void pxa_camera_deactivate(struct pxa_camera_dev
*pcdev
)
783 clk_disable(pcdev
->clk
);
786 static irqreturn_t
pxa_camera_irq(int irq
, void *data
)
788 struct pxa_camera_dev
*pcdev
= data
;
789 unsigned long status
, cicr0
;
791 status
= __raw_readl(pcdev
->base
+ CISR
);
792 dev_dbg(pcdev
->dev
, "Camera interrupt status 0x%lx\n", status
);
797 __raw_writel(status
, pcdev
->base
+ CISR
);
799 if (status
& CISR_EOF
) {
801 for (i
= 0; i
< pcdev
->channels
; i
++) {
802 DDADR(pcdev
->dma_chans
[i
]) =
803 pcdev
->active
->dmas
[i
].sg_dma
;
804 DCSR(pcdev
->dma_chans
[i
]) = DCSR_RUN
;
806 cicr0
= __raw_readl(pcdev
->base
+ CICR0
) | CICR0_EOFM
;
807 __raw_writel(cicr0
, pcdev
->base
+ CICR0
);
814 * The following two functions absolutely depend on the fact, that
815 * there can be only one camera on PXA quick capture interface
816 * Called with .video_lock held
818 static int pxa_camera_add_device(struct soc_camera_device
*icd
)
820 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->dev
.parent
);
821 struct pxa_camera_dev
*pcdev
= ici
->priv
;
829 dev_info(&icd
->dev
, "PXA Camera driver attached to camera %d\n",
832 pxa_camera_activate(pcdev
);
833 ret
= icd
->ops
->init(icd
);
842 /* Called with .video_lock held */
843 static void pxa_camera_remove_device(struct soc_camera_device
*icd
)
845 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->dev
.parent
);
846 struct pxa_camera_dev
*pcdev
= ici
->priv
;
848 BUG_ON(icd
!= pcdev
->icd
);
850 dev_info(&icd
->dev
, "PXA Camera driver detached from camera %d\n",
853 /* disable capture, disable interrupts */
854 __raw_writel(0x3ff, pcdev
->base
+ CICR0
);
856 /* Stop DMA engine */
857 DCSR(pcdev
->dma_chans
[0]) = 0;
858 DCSR(pcdev
->dma_chans
[1]) = 0;
859 DCSR(pcdev
->dma_chans
[2]) = 0;
861 icd
->ops
->release(icd
);
863 pxa_camera_deactivate(pcdev
);
868 static int test_platform_param(struct pxa_camera_dev
*pcdev
,
869 unsigned char buswidth
, unsigned long *flags
)
872 * Platform specified synchronization and pixel clock polarities are
873 * only a recommendation and are only used during probing. The PXA270
874 * quick capture interface supports both.
876 *flags
= (pcdev
->platform_flags
& PXA_CAMERA_MASTER
?
877 SOCAM_MASTER
: SOCAM_SLAVE
) |
878 SOCAM_HSYNC_ACTIVE_HIGH
|
879 SOCAM_HSYNC_ACTIVE_LOW
|
880 SOCAM_VSYNC_ACTIVE_HIGH
|
881 SOCAM_VSYNC_ACTIVE_LOW
|
882 SOCAM_PCLK_SAMPLE_RISING
|
883 SOCAM_PCLK_SAMPLE_FALLING
;
885 /* If requested data width is supported by the platform, use it */
888 if (!(pcdev
->platform_flags
& PXA_CAMERA_DATAWIDTH_10
))
890 *flags
|= SOCAM_DATAWIDTH_10
;
893 if (!(pcdev
->platform_flags
& PXA_CAMERA_DATAWIDTH_9
))
895 *flags
|= SOCAM_DATAWIDTH_9
;
898 if (!(pcdev
->platform_flags
& PXA_CAMERA_DATAWIDTH_8
))
900 *flags
|= SOCAM_DATAWIDTH_8
;
909 static int pxa_camera_set_bus_param(struct soc_camera_device
*icd
, __u32 pixfmt
)
911 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->dev
.parent
);
912 struct pxa_camera_dev
*pcdev
= ici
->priv
;
913 unsigned long dw
, bpp
, bus_flags
, camera_flags
, common_flags
;
914 u32 cicr0
, cicr1
, cicr2
, cicr3
, cicr4
= 0;
915 int ret
= test_platform_param(pcdev
, icd
->buswidth
, &bus_flags
);
920 camera_flags
= icd
->ops
->query_bus_param(icd
);
922 common_flags
= soc_camera_bus_param_compatible(camera_flags
, bus_flags
);
928 /* Make choises, based on platform preferences */
929 if ((common_flags
& SOCAM_HSYNC_ACTIVE_HIGH
) &&
930 (common_flags
& SOCAM_HSYNC_ACTIVE_LOW
)) {
931 if (pcdev
->platform_flags
& PXA_CAMERA_HSP
)
932 common_flags
&= ~SOCAM_HSYNC_ACTIVE_HIGH
;
934 common_flags
&= ~SOCAM_HSYNC_ACTIVE_LOW
;
937 if ((common_flags
& SOCAM_VSYNC_ACTIVE_HIGH
) &&
938 (common_flags
& SOCAM_VSYNC_ACTIVE_LOW
)) {
939 if (pcdev
->platform_flags
& PXA_CAMERA_VSP
)
940 common_flags
&= ~SOCAM_VSYNC_ACTIVE_HIGH
;
942 common_flags
&= ~SOCAM_VSYNC_ACTIVE_LOW
;
945 if ((common_flags
& SOCAM_PCLK_SAMPLE_RISING
) &&
946 (common_flags
& SOCAM_PCLK_SAMPLE_FALLING
)) {
947 if (pcdev
->platform_flags
& PXA_CAMERA_PCP
)
948 common_flags
&= ~SOCAM_PCLK_SAMPLE_RISING
;
950 common_flags
&= ~SOCAM_PCLK_SAMPLE_FALLING
;
953 ret
= icd
->ops
->set_bus_param(icd
, common_flags
);
957 /* Datawidth is now guaranteed to be equal to one of the three values.
958 * We fix bit-per-pixel equal to data-width... */
959 switch (common_flags
& SOCAM_DATAWIDTH_MASK
) {
960 case SOCAM_DATAWIDTH_10
:
964 case SOCAM_DATAWIDTH_9
:
969 /* Actually it can only be 8 now,
970 * default is just to silence compiler warnings */
971 case SOCAM_DATAWIDTH_8
:
976 if (pcdev
->platform_flags
& PXA_CAMERA_PCLK_EN
)
977 cicr4
|= CICR4_PCLK_EN
;
978 if (pcdev
->platform_flags
& PXA_CAMERA_MCLK_EN
)
979 cicr4
|= CICR4_MCLK_EN
;
980 if (common_flags
& SOCAM_PCLK_SAMPLE_FALLING
)
982 if (common_flags
& SOCAM_HSYNC_ACTIVE_LOW
)
984 if (common_flags
& SOCAM_VSYNC_ACTIVE_LOW
)
987 cicr0
= __raw_readl(pcdev
->base
+ CICR0
);
988 if (cicr0
& CICR0_ENB
)
989 __raw_writel(cicr0
& ~CICR0_ENB
, pcdev
->base
+ CICR0
);
991 cicr1
= CICR1_PPL_VAL(icd
->width
- 1) | bpp
| dw
;
994 case V4L2_PIX_FMT_YUV422P
:
996 cicr1
|= CICR1_YCBCR_F
;
998 * Normally, pxa bus wants as input UYVY format. We allow all
999 * reorderings of the YUV422 format, as no processing is done,
1000 * and the YUV stream is just passed through without any
1001 * transformation. Note that UYVY is the only format that
1002 * should be used if pxa framebuffer Overlay2 is used.
1004 case V4L2_PIX_FMT_UYVY
:
1005 case V4L2_PIX_FMT_VYUY
:
1006 case V4L2_PIX_FMT_YUYV
:
1007 case V4L2_PIX_FMT_YVYU
:
1008 cicr1
|= CICR1_COLOR_SP_VAL(2);
1010 case V4L2_PIX_FMT_RGB555
:
1011 cicr1
|= CICR1_RGB_BPP_VAL(1) | CICR1_RGBT_CONV_VAL(2) |
1012 CICR1_TBIT
| CICR1_COLOR_SP_VAL(1);
1014 case V4L2_PIX_FMT_RGB565
:
1015 cicr1
|= CICR1_COLOR_SP_VAL(1) | CICR1_RGB_BPP_VAL(2);
1020 cicr3
= CICR3_LPF_VAL(icd
->height
- 1) |
1021 CICR3_BFW_VAL(min((unsigned short)255, icd
->y_skip_top
));
1022 cicr4
|= pcdev
->mclk_divisor
;
1024 __raw_writel(cicr1
, pcdev
->base
+ CICR1
);
1025 __raw_writel(cicr2
, pcdev
->base
+ CICR2
);
1026 __raw_writel(cicr3
, pcdev
->base
+ CICR3
);
1027 __raw_writel(cicr4
, pcdev
->base
+ CICR4
);
1029 /* CIF interrupts are not used, only DMA */
1030 cicr0
= (cicr0
& CICR0_ENB
) | (pcdev
->platform_flags
& PXA_CAMERA_MASTER
?
1031 CICR0_SIM_MP
: (CICR0_SL_CAP_EN
| CICR0_SIM_SP
));
1032 cicr0
|= CICR0_DMAEN
| CICR0_IRQ_MASK
;
1033 __raw_writel(cicr0
, pcdev
->base
+ CICR0
);
1038 static int pxa_camera_try_bus_param(struct soc_camera_device
*icd
,
1039 unsigned char buswidth
)
1041 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->dev
.parent
);
1042 struct pxa_camera_dev
*pcdev
= ici
->priv
;
1043 unsigned long bus_flags
, camera_flags
;
1044 int ret
= test_platform_param(pcdev
, buswidth
, &bus_flags
);
1049 camera_flags
= icd
->ops
->query_bus_param(icd
);
1051 return soc_camera_bus_param_compatible(camera_flags
, bus_flags
) ? 0 : -EINVAL
;
1054 static const struct soc_camera_data_format pxa_camera_formats
[] = {
1056 .name
= "Planar YUV422 16 bit",
1058 .fourcc
= V4L2_PIX_FMT_YUV422P
,
1059 .colorspace
= V4L2_COLORSPACE_JPEG
,
1063 static bool buswidth_supported(struct soc_camera_device
*icd
, int depth
)
1065 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->dev
.parent
);
1066 struct pxa_camera_dev
*pcdev
= ici
->priv
;
1070 return !!(pcdev
->platform_flags
& PXA_CAMERA_DATAWIDTH_8
);
1072 return !!(pcdev
->platform_flags
& PXA_CAMERA_DATAWIDTH_9
);
1074 return !!(pcdev
->platform_flags
& PXA_CAMERA_DATAWIDTH_10
);
1079 static int required_buswidth(const struct soc_camera_data_format
*fmt
)
1081 switch (fmt
->fourcc
) {
1082 case V4L2_PIX_FMT_UYVY
:
1083 case V4L2_PIX_FMT_VYUY
:
1084 case V4L2_PIX_FMT_YUYV
:
1085 case V4L2_PIX_FMT_YVYU
:
1086 case V4L2_PIX_FMT_RGB565
:
1087 case V4L2_PIX_FMT_RGB555
:
1094 static int pxa_camera_get_formats(struct soc_camera_device
*icd
, int idx
,
1095 struct soc_camera_format_xlate
*xlate
)
1097 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->dev
.parent
);
1098 int formats
= 0, buswidth
, ret
;
1100 buswidth
= required_buswidth(icd
->formats
+ idx
);
1102 if (!buswidth_supported(icd
, buswidth
))
1105 ret
= pxa_camera_try_bus_param(icd
, buswidth
);
1109 switch (icd
->formats
[idx
].fourcc
) {
1110 case V4L2_PIX_FMT_UYVY
:
1113 xlate
->host_fmt
= &pxa_camera_formats
[0];
1114 xlate
->cam_fmt
= icd
->formats
+ idx
;
1115 xlate
->buswidth
= buswidth
;
1117 dev_dbg(&ici
->dev
, "Providing format %s using %s\n",
1118 pxa_camera_formats
[0].name
,
1119 icd
->formats
[idx
].name
);
1121 case V4L2_PIX_FMT_VYUY
:
1122 case V4L2_PIX_FMT_YUYV
:
1123 case V4L2_PIX_FMT_YVYU
:
1124 case V4L2_PIX_FMT_RGB565
:
1125 case V4L2_PIX_FMT_RGB555
:
1128 xlate
->host_fmt
= icd
->formats
+ idx
;
1129 xlate
->cam_fmt
= icd
->formats
+ idx
;
1130 xlate
->buswidth
= buswidth
;
1132 dev_dbg(&ici
->dev
, "Providing format %s packed\n",
1133 icd
->formats
[idx
].name
);
1137 /* Generic pass-through */
1140 xlate
->host_fmt
= icd
->formats
+ idx
;
1141 xlate
->cam_fmt
= icd
->formats
+ idx
;
1142 xlate
->buswidth
= icd
->formats
[idx
].depth
;
1145 "Providing format %s in pass-through mode\n",
1146 icd
->formats
[idx
].name
);
1153 static int pxa_camera_set_fmt(struct soc_camera_device
*icd
,
1154 __u32 pixfmt
, struct v4l2_rect
*rect
)
1156 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->dev
.parent
);
1157 struct pxa_camera_dev
*pcdev
= ici
->priv
;
1158 const struct soc_camera_data_format
*cam_fmt
= NULL
;
1159 const struct soc_camera_format_xlate
*xlate
= NULL
;
1160 struct soc_camera_sense sense
= {
1161 .master_clock
= pcdev
->mclk
,
1162 .pixel_clock_max
= pcdev
->ciclk
/ 4,
1167 xlate
= soc_camera_xlate_by_fourcc(icd
, pixfmt
);
1169 dev_warn(&ici
->dev
, "Format %x not found\n", pixfmt
);
1173 cam_fmt
= xlate
->cam_fmt
;
1176 /* If PCLK is used to latch data from the sensor, check sense */
1177 if (pcdev
->platform_flags
& PXA_CAMERA_PCLK_EN
)
1178 icd
->sense
= &sense
;
1181 case 0: /* Only geometry change */
1182 ret
= icd
->ops
->set_fmt(icd
, pixfmt
, rect
);
1185 ret
= icd
->ops
->set_fmt(icd
, cam_fmt
->fourcc
, rect
);
1191 dev_warn(&ici
->dev
, "Failed to configure for format %x\n",
1193 } else if (sense
.flags
& SOCAM_SENSE_PCLK_CHANGED
) {
1194 if (sense
.pixel_clock
> sense
.pixel_clock_max
) {
1196 "pixel clock %lu set by the camera too high!",
1200 recalculate_fifo_timeout(pcdev
, sense
.pixel_clock
);
1203 if (pixfmt
&& !ret
) {
1204 icd
->buswidth
= xlate
->buswidth
;
1205 icd
->current_fmt
= xlate
->host_fmt
;
1211 static int pxa_camera_try_fmt(struct soc_camera_device
*icd
,
1212 struct v4l2_format
*f
)
1214 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->dev
.parent
);
1215 const struct soc_camera_format_xlate
*xlate
;
1216 struct v4l2_pix_format
*pix
= &f
->fmt
.pix
;
1217 __u32 pixfmt
= pix
->pixelformat
;
1218 enum v4l2_field field
;
1221 xlate
= soc_camera_xlate_by_fourcc(icd
, pixfmt
);
1223 dev_warn(&ici
->dev
, "Format %x not found\n", pixfmt
);
1227 /* limit to pxa hardware capabilities */
1228 if (pix
->height
< 32)
1230 if (pix
->height
> 2048)
1232 if (pix
->width
< 48)
1234 if (pix
->width
> 2048)
1236 pix
->width
&= ~0x01;
1238 pix
->bytesperline
= pix
->width
*
1239 DIV_ROUND_UP(xlate
->host_fmt
->depth
, 8);
1240 pix
->sizeimage
= pix
->height
* pix
->bytesperline
;
1242 /* camera has to see its format, but the user the original one */
1243 pix
->pixelformat
= xlate
->cam_fmt
->fourcc
;
1244 /* limit to sensor capabilities */
1245 ret
= icd
->ops
->try_fmt(icd
, f
);
1246 pix
->pixelformat
= xlate
->host_fmt
->fourcc
;
1250 if (field
== V4L2_FIELD_ANY
) {
1251 pix
->field
= V4L2_FIELD_NONE
;
1252 } else if (field
!= V4L2_FIELD_NONE
) {
1253 dev_err(&icd
->dev
, "Field type %d unsupported.\n", field
);
1260 static int pxa_camera_reqbufs(struct soc_camera_file
*icf
,
1261 struct v4l2_requestbuffers
*p
)
1265 /* This is for locking debugging only. I removed spinlocks and now I
1266 * check whether .prepare is ever called on a linked buffer, or whether
1267 * a dma IRQ can occur for an in-work or unlinked buffer. Until now
1268 * it hadn't triggered */
1269 for (i
= 0; i
< p
->count
; i
++) {
1270 struct pxa_buffer
*buf
= container_of(icf
->vb_vidq
.bufs
[i
],
1271 struct pxa_buffer
, vb
);
1273 INIT_LIST_HEAD(&buf
->vb
.queue
);
1279 static unsigned int pxa_camera_poll(struct file
*file
, poll_table
*pt
)
1281 struct soc_camera_file
*icf
= file
->private_data
;
1282 struct pxa_buffer
*buf
;
1284 buf
= list_entry(icf
->vb_vidq
.stream
.next
, struct pxa_buffer
,
1287 poll_wait(file
, &buf
->vb
.done
, pt
);
1289 if (buf
->vb
.state
== VIDEOBUF_DONE
||
1290 buf
->vb
.state
== VIDEOBUF_ERROR
)
1291 return POLLIN
|POLLRDNORM
;
1296 static int pxa_camera_querycap(struct soc_camera_host
*ici
,
1297 struct v4l2_capability
*cap
)
1299 /* cap->name is set by the firendly caller:-> */
1300 strlcpy(cap
->card
, pxa_cam_driver_description
, sizeof(cap
->card
));
1301 cap
->version
= PXA_CAM_VERSION_CODE
;
1302 cap
->capabilities
= V4L2_CAP_VIDEO_CAPTURE
| V4L2_CAP_STREAMING
;
1307 static int pxa_camera_suspend(struct soc_camera_device
*icd
, pm_message_t state
)
1309 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->dev
.parent
);
1310 struct pxa_camera_dev
*pcdev
= ici
->priv
;
1313 pcdev
->save_cicr
[i
++] = __raw_readl(pcdev
->base
+ CICR0
);
1314 pcdev
->save_cicr
[i
++] = __raw_readl(pcdev
->base
+ CICR1
);
1315 pcdev
->save_cicr
[i
++] = __raw_readl(pcdev
->base
+ CICR2
);
1316 pcdev
->save_cicr
[i
++] = __raw_readl(pcdev
->base
+ CICR3
);
1317 pcdev
->save_cicr
[i
++] = __raw_readl(pcdev
->base
+ CICR4
);
1319 if ((pcdev
->icd
) && (pcdev
->icd
->ops
->suspend
))
1320 ret
= pcdev
->icd
->ops
->suspend(pcdev
->icd
, state
);
1325 static int pxa_camera_resume(struct soc_camera_device
*icd
)
1327 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->dev
.parent
);
1328 struct pxa_camera_dev
*pcdev
= ici
->priv
;
1331 DRCMR(68) = pcdev
->dma_chans
[0] | DRCMR_MAPVLD
;
1332 DRCMR(69) = pcdev
->dma_chans
[1] | DRCMR_MAPVLD
;
1333 DRCMR(70) = pcdev
->dma_chans
[2] | DRCMR_MAPVLD
;
1335 __raw_writel(pcdev
->save_cicr
[i
++] & ~CICR0_ENB
, pcdev
->base
+ CICR0
);
1336 __raw_writel(pcdev
->save_cicr
[i
++], pcdev
->base
+ CICR1
);
1337 __raw_writel(pcdev
->save_cicr
[i
++], pcdev
->base
+ CICR2
);
1338 __raw_writel(pcdev
->save_cicr
[i
++], pcdev
->base
+ CICR3
);
1339 __raw_writel(pcdev
->save_cicr
[i
++], pcdev
->base
+ CICR4
);
1341 if ((pcdev
->icd
) && (pcdev
->icd
->ops
->resume
))
1342 ret
= pcdev
->icd
->ops
->resume(pcdev
->icd
);
1344 /* Restart frame capture if active buffer exists */
1345 if (!ret
&& pcdev
->active
) {
1346 unsigned long cifr
, cicr0
;
1348 /* Reset the FIFOs */
1349 cifr
= __raw_readl(pcdev
->base
+ CIFR
) | CIFR_RESET_F
;
1350 __raw_writel(cifr
, pcdev
->base
+ CIFR
);
1352 cicr0
= __raw_readl(pcdev
->base
+ CICR0
);
1353 cicr0
&= ~CICR0_EOFM
; /* Enable End-Of-Frame Interrupt */
1354 cicr0
|= CICR0_ENB
; /* Restart the Capture Interface */
1355 __raw_writel(cicr0
, pcdev
->base
+ CICR0
);
1361 static struct soc_camera_host_ops pxa_soc_camera_host_ops
= {
1362 .owner
= THIS_MODULE
,
1363 .add
= pxa_camera_add_device
,
1364 .remove
= pxa_camera_remove_device
,
1365 .suspend
= pxa_camera_suspend
,
1366 .resume
= pxa_camera_resume
,
1367 .get_formats
= pxa_camera_get_formats
,
1368 .set_fmt
= pxa_camera_set_fmt
,
1369 .try_fmt
= pxa_camera_try_fmt
,
1370 .init_videobuf
= pxa_camera_init_videobuf
,
1371 .reqbufs
= pxa_camera_reqbufs
,
1372 .poll
= pxa_camera_poll
,
1373 .querycap
= pxa_camera_querycap
,
1374 .set_bus_param
= pxa_camera_set_bus_param
,
1377 /* Should be allocated dynamically too, but we have only one. */
1378 static struct soc_camera_host pxa_soc_camera_host
= {
1379 .drv_name
= PXA_CAM_DRV_NAME
,
1380 .ops
= &pxa_soc_camera_host_ops
,
1383 static int pxa_camera_probe(struct platform_device
*pdev
)
1385 struct pxa_camera_dev
*pcdev
;
1386 struct resource
*res
;
1391 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1392 irq
= platform_get_irq(pdev
, 0);
1393 if (!res
|| irq
< 0) {
1398 pcdev
= kzalloc(sizeof(*pcdev
), GFP_KERNEL
);
1400 dev_err(&pdev
->dev
, "Could not allocate pcdev\n");
1405 pcdev
->clk
= clk_get(&pdev
->dev
, NULL
);
1406 if (IS_ERR(pcdev
->clk
)) {
1407 err
= PTR_ERR(pcdev
->clk
);
1411 dev_set_drvdata(&pdev
->dev
, pcdev
);
1414 pcdev
->pdata
= pdev
->dev
.platform_data
;
1415 pcdev
->platform_flags
= pcdev
->pdata
->flags
;
1416 if (!(pcdev
->platform_flags
& (PXA_CAMERA_DATAWIDTH_8
|
1417 PXA_CAMERA_DATAWIDTH_9
| PXA_CAMERA_DATAWIDTH_10
))) {
1418 /* Platform hasn't set available data widths. This is bad.
1419 * Warn and use a default. */
1420 dev_warn(&pdev
->dev
, "WARNING! Platform hasn't set available "
1421 "data widths, using default 10 bit\n");
1422 pcdev
->platform_flags
|= PXA_CAMERA_DATAWIDTH_10
;
1424 pcdev
->mclk
= pcdev
->pdata
->mclk_10khz
* 10000;
1426 dev_warn(&pdev
->dev
,
1427 "mclk == 0! Please, fix your platform data. "
1428 "Using default 20MHz\n");
1429 pcdev
->mclk
= 20000000;
1432 pcdev
->dev
= &pdev
->dev
;
1433 pcdev
->mclk_divisor
= mclk_get_divisor(pcdev
);
1435 INIT_LIST_HEAD(&pcdev
->capture
);
1436 spin_lock_init(&pcdev
->lock
);
1439 * Request the regions.
1441 if (!request_mem_region(res
->start
, res
->end
- res
->start
+ 1,
1442 PXA_CAM_DRV_NAME
)) {
1447 base
= ioremap(res
->start
, res
->end
- res
->start
+ 1);
1456 err
= pxa_request_dma("CI_Y", DMA_PRIO_HIGH
,
1457 pxa_camera_dma_irq_y
, pcdev
);
1459 dev_err(pcdev
->dev
, "Can't request DMA for Y\n");
1462 pcdev
->dma_chans
[0] = err
;
1463 dev_dbg(pcdev
->dev
, "got DMA channel %d\n", pcdev
->dma_chans
[0]);
1465 err
= pxa_request_dma("CI_U", DMA_PRIO_HIGH
,
1466 pxa_camera_dma_irq_u
, pcdev
);
1468 dev_err(pcdev
->dev
, "Can't request DMA for U\n");
1469 goto exit_free_dma_y
;
1471 pcdev
->dma_chans
[1] = err
;
1472 dev_dbg(pcdev
->dev
, "got DMA channel (U) %d\n", pcdev
->dma_chans
[1]);
1474 err
= pxa_request_dma("CI_V", DMA_PRIO_HIGH
,
1475 pxa_camera_dma_irq_v
, pcdev
);
1477 dev_err(pcdev
->dev
, "Can't request DMA for V\n");
1478 goto exit_free_dma_u
;
1480 pcdev
->dma_chans
[2] = err
;
1481 dev_dbg(pcdev
->dev
, "got DMA channel (V) %d\n", pcdev
->dma_chans
[2]);
1483 DRCMR(68) = pcdev
->dma_chans
[0] | DRCMR_MAPVLD
;
1484 DRCMR(69) = pcdev
->dma_chans
[1] | DRCMR_MAPVLD
;
1485 DRCMR(70) = pcdev
->dma_chans
[2] | DRCMR_MAPVLD
;
1488 err
= request_irq(pcdev
->irq
, pxa_camera_irq
, 0, PXA_CAM_DRV_NAME
,
1491 dev_err(pcdev
->dev
, "Camera interrupt register failed \n");
1495 pxa_soc_camera_host
.priv
= pcdev
;
1496 pxa_soc_camera_host
.dev
.parent
= &pdev
->dev
;
1497 pxa_soc_camera_host
.nr
= pdev
->id
;
1498 err
= soc_camera_host_register(&pxa_soc_camera_host
);
1505 free_irq(pcdev
->irq
, pcdev
);
1507 pxa_free_dma(pcdev
->dma_chans
[2]);
1509 pxa_free_dma(pcdev
->dma_chans
[1]);
1511 pxa_free_dma(pcdev
->dma_chans
[0]);
1515 release_mem_region(res
->start
, res
->end
- res
->start
+ 1);
1517 clk_put(pcdev
->clk
);
1524 static int __devexit
pxa_camera_remove(struct platform_device
*pdev
)
1526 struct pxa_camera_dev
*pcdev
= platform_get_drvdata(pdev
);
1527 struct resource
*res
;
1529 clk_put(pcdev
->clk
);
1531 pxa_free_dma(pcdev
->dma_chans
[0]);
1532 pxa_free_dma(pcdev
->dma_chans
[1]);
1533 pxa_free_dma(pcdev
->dma_chans
[2]);
1534 free_irq(pcdev
->irq
, pcdev
);
1536 soc_camera_host_unregister(&pxa_soc_camera_host
);
1538 iounmap(pcdev
->base
);
1541 release_mem_region(res
->start
, res
->end
- res
->start
+ 1);
1545 dev_info(&pdev
->dev
, "PXA Camera driver unloaded\n");
1550 static struct platform_driver pxa_camera_driver
= {
1552 .name
= PXA_CAM_DRV_NAME
,
1554 .probe
= pxa_camera_probe
,
1555 .remove
= __exit_p(pxa_camera_remove
),
1559 static int __devinit
pxa_camera_init(void)
1561 return platform_driver_register(&pxa_camera_driver
);
1564 static void __exit
pxa_camera_exit(void)
1566 platform_driver_unregister(&pxa_camera_driver
);
1569 module_init(pxa_camera_init
);
1570 module_exit(pxa_camera_exit
);
1572 MODULE_DESCRIPTION("PXA27x SoC Camera Host driver");
1573 MODULE_AUTHOR("Guennadi Liakhovetski <kernel@pengutronix.de>");
1574 MODULE_LICENSE("GPL");