1 #ifndef __ASM_ARCH_REGS_SSP_H
2 #define __ASM_ARCH_REGS_SSP_H
5 * SSP Serial Port Registers
6 * PXA250, PXA255, PXA26x and PXA27x SSP controllers are all slightly different.
7 * PXA255, PXA26x and PXA27x have extra ports, registers and bits.
10 /* Common PXA2xx bits first */
11 #define SSCR0_DSS (0x0000000f) /* Data Size Select (mask) */
12 #define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] */
13 #define SSCR0_FRF (0x00000030) /* FRame Format (mask) */
14 #define SSCR0_Motorola (0x0 << 4) /* Motorola's Serial Peripheral Interface (SPI) */
15 #define SSCR0_TI (0x1 << 4) /* Texas Instruments' Synchronous Serial Protocol (SSP) */
16 #define SSCR0_National (0x2 << 4) /* National Microwire */
17 #define SSCR0_ECS (1 << 6) /* External clock select */
18 #define SSCR0_SSE (1 << 7) /* Synchronous Serial Port Enable */
19 #if defined(CONFIG_PXA25x)
20 #define SSCR0_SCR (0x0000ff00) /* Serial Clock Rate (mask) */
21 #define SSCR0_SerClkDiv(x) ((((x) - 2)/2) << 8) /* Divisor [2..512] */
22 #elif defined(CONFIG_PXA27x)
23 #define SSCR0_SCR (0x000fff00) /* Serial Clock Rate (mask) */
24 #define SSCR0_SerClkDiv(x) (((x) - 1) << 8) /* Divisor [1..4096] */
25 #define SSCR0_EDSS (1 << 20) /* Extended data size select */
26 #define SSCR0_NCS (1 << 21) /* Network clock select */
27 #define SSCR0_RIM (1 << 22) /* Receive FIFO overrrun interrupt mask */
28 #define SSCR0_TUM (1 << 23) /* Transmit FIFO underrun interrupt mask */
29 #define SSCR0_FRDC (0x07000000) /* Frame rate divider control (mask) */
30 #define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24) /* Time slots per frame [1..8] */
31 #define SSCR0_ADC (1 << 30) /* Audio clock select */
32 #define SSCR0_MOD (1 << 31) /* Mode (normal or network) */
35 #define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */
36 #define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */
37 #define SSCR1_LBM (1 << 2) /* Loop-Back Mode */
38 #define SSCR1_SPO (1 << 3) /* Motorola SPI SSPSCLK polarity setting */
39 #define SSCR1_SPH (1 << 4) /* Motorola SPI SSPSCLK phase setting */
40 #define SSCR1_MWDS (1 << 5) /* Microwire Transmit Data Size */
41 #define SSCR1_TFT (0x000003c0) /* Transmit FIFO Threshold (mask) */
42 #define SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..16] */
43 #define SSCR1_RFT (0x00003c00) /* Receive FIFO Threshold (mask) */
44 #define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..16] */
46 #define SSSR_TNF (1 << 2) /* Transmit FIFO Not Full */
47 #define SSSR_RNE (1 << 3) /* Receive FIFO Not Empty */
48 #define SSSR_BSY (1 << 4) /* SSP Busy */
49 #define SSSR_TFS (1 << 5) /* Transmit FIFO Service Request */
50 #define SSSR_RFS (1 << 6) /* Receive FIFO Service Request */
51 #define SSSR_ROR (1 << 7) /* Receive FIFO Overrun */
53 #define SSCR0_TIM (1 << 23) /* Transmit FIFO Under Run Interrupt Mask */
54 #define SSCR0_RIM (1 << 22) /* Receive FIFO Over Run interrupt Mask */
55 #define SSCR0_NCS (1 << 21) /* Network Clock Select */
56 #define SSCR0_EDSS (1 << 20) /* Extended Data Size Select */
58 /* extra bits in PXA255, PXA26x and PXA27x SSP ports */
59 #define SSCR0_TISSP (1 << 4) /* TI Sync Serial Protocol */
60 #define SSCR0_PSP (3 << 4) /* PSP - Programmable Serial Protocol */
61 #define SSCR1_TTELP (1 << 31) /* TXD Tristate Enable Last Phase */
62 #define SSCR1_TTE (1 << 30) /* TXD Tristate Enable */
63 #define SSCR1_EBCEI (1 << 29) /* Enable Bit Count Error interrupt */
64 #define SSCR1_SCFR (1 << 28) /* Slave Clock free Running */
65 #define SSCR1_ECRA (1 << 27) /* Enable Clock Request A */
66 #define SSCR1_ECRB (1 << 26) /* Enable Clock request B */
67 #define SSCR1_SCLKDIR (1 << 25) /* Serial Bit Rate Clock Direction */
68 #define SSCR1_SFRMDIR (1 << 24) /* Frame Direction */
69 #define SSCR1_RWOT (1 << 23) /* Receive Without Transmit */
70 #define SSCR1_TRAIL (1 << 22) /* Trailing Byte */
71 #define SSCR1_TSRE (1 << 21) /* Transmit Service Request Enable */
72 #define SSCR1_RSRE (1 << 20) /* Receive Service Request Enable */
73 #define SSCR1_TINTE (1 << 19) /* Receiver Time-out Interrupt enable */
74 #define SSCR1_PINTE (1 << 18) /* Peripheral Trailing Byte Interupt Enable */
75 #define SSCR1_STRF (1 << 15) /* Select FIFO or EFWR */
76 #define SSCR1_EFWR (1 << 14) /* Enable FIFO Write/Read */
78 #define SSSR_BCE (1 << 23) /* Bit Count Error */
79 #define SSSR_CSS (1 << 22) /* Clock Synchronisation Status */
80 #define SSSR_TUR (1 << 21) /* Transmit FIFO Under Run */
81 #define SSSR_EOC (1 << 20) /* End Of Chain */
82 #define SSSR_TINT (1 << 19) /* Receiver Time-out Interrupt */
83 #define SSSR_PINT (1 << 18) /* Peripheral Trailing Byte Interrupt */
85 #define SSPSP_FSRT (1 << 25) /* Frame Sync Relative Timing */
86 #define SSPSP_DMYSTOP(x) ((x) << 23) /* Dummy Stop */
87 #define SSPSP_SFRMWDTH(x) ((x) << 16) /* Serial Frame Width */
88 #define SSPSP_SFRMDLY(x) ((x) << 9) /* Serial Frame Delay */
89 #define SSPSP_DMYSTRT(x) ((x) << 7) /* Dummy Start */
90 #define SSPSP_STRTDLY(x) ((x) << 4) /* Start Delay */
91 #define SSPSP_ETDS (1 << 3) /* End of Transfer data State */
92 #define SSPSP_SFRMP (1 << 2) /* Serial Frame Polarity */
93 #define SSPSP_SCMODE(x) ((x) << 0) /* Serial Bit Rate Clock Mode */
95 #define SSACD_SCDB (1 << 3) /* SSPSYSCLK Divider Bypass */
96 #define SSACD_ACPS(x) ((x) << 4) /* Audio clock PLL select */
97 #define SSACD_ACDS(x) ((x) << 0) /* Audio clock divider select */
99 #define SSCR0_P1 __REG(0x41000000) /* SSP Port 1 Control Register 0 */
100 #define SSCR1_P1 __REG(0x41000004) /* SSP Port 1 Control Register 1 */
101 #define SSSR_P1 __REG(0x41000008) /* SSP Port 1 Status Register */
102 #define SSITR_P1 __REG(0x4100000C) /* SSP Port 1 Interrupt Test Register */
103 #define SSDR_P1 __REG(0x41000010) /* (Write / Read) SSP Port 1 Data Write Register/SSP Data Read Register */
105 /* Support existing PXA25x drivers */
106 #define SSCR0 SSCR0_P1 /* SSP Control Register 0 */
107 #define SSCR1 SSCR1_P1 /* SSP Control Register 1 */
108 #define SSSR SSSR_P1 /* SSP Status Register */
109 #define SSITR SSITR_P1 /* SSP Interrupt Test Register */
110 #define SSDR SSDR_P1 /* (Write / Read) SSP Data Write Register/SSP Data Read Register */
113 #if defined (CONFIG_PXA27x)
114 #define SSTO_P1 __REG(0x41000028) /* SSP Port 1 Time Out Register */
115 #define SSPSP_P1 __REG(0x4100002C) /* SSP Port 1 Programmable Serial Protocol */
116 #define SSTSA_P1 __REG(0x41000030) /* SSP Port 1 Tx Timeslot Active */
117 #define SSRSA_P1 __REG(0x41000034) /* SSP Port 1 Rx Timeslot Active */
118 #define SSTSS_P1 __REG(0x41000038) /* SSP Port 1 Timeslot Status */
119 #define SSACD_P1 __REG(0x4100003C) /* SSP Port 1 Audio Clock Divider */
120 #define SSCR0_P2 __REG(0x41700000) /* SSP Port 2 Control Register 0 */
121 #define SSCR1_P2 __REG(0x41700004) /* SSP Port 2 Control Register 1 */
122 #define SSSR_P2 __REG(0x41700008) /* SSP Port 2 Status Register */
123 #define SSITR_P2 __REG(0x4170000C) /* SSP Port 2 Interrupt Test Register */
124 #define SSDR_P2 __REG(0x41700010) /* (Write / Read) SSP Port 2 Data Write Register/SSP Data Read Register */
125 #define SSTO_P2 __REG(0x41700028) /* SSP Port 2 Time Out Register */
126 #define SSPSP_P2 __REG(0x4170002C) /* SSP Port 2 Programmable Serial Protocol */
127 #define SSTSA_P2 __REG(0x41700030) /* SSP Port 2 Tx Timeslot Active */
128 #define SSRSA_P2 __REG(0x41700034) /* SSP Port 2 Rx Timeslot Active */
129 #define SSTSS_P2 __REG(0x41700038) /* SSP Port 2 Timeslot Status */
130 #define SSACD_P2 __REG(0x4170003C) /* SSP Port 2 Audio Clock Divider */
131 #define SSCR0_P3 __REG(0x41900000) /* SSP Port 3 Control Register 0 */
132 #define SSCR1_P3 __REG(0x41900004) /* SSP Port 3 Control Register 1 */
133 #define SSSR_P3 __REG(0x41900008) /* SSP Port 3 Status Register */
134 #define SSITR_P3 __REG(0x4190000C) /* SSP Port 3 Interrupt Test Register */
135 #define SSDR_P3 __REG(0x41900010) /* (Write / Read) SSP Port 3 Data Write Register/SSP Data Read Register */
136 #define SSTO_P3 __REG(0x41900028) /* SSP Port 3 Time Out Register */
137 #define SSPSP_P3 __REG(0x4190002C) /* SSP Port 3 Programmable Serial Protocol */
138 #define SSTSA_P3 __REG(0x41900030) /* SSP Port 3 Tx Timeslot Active */
139 #define SSRSA_P3 __REG(0x41900034) /* SSP Port 3 Rx Timeslot Active */
140 #define SSTSS_P3 __REG(0x41900038) /* SSP Port 3 Timeslot Status */
141 #define SSACD_P3 __REG(0x4190003C) /* SSP Port 3 Audio Clock Divider */
142 #else /* PXA255 (only port 2) and PXA26x ports*/
143 #define SSTO_P1 __REG(0x41000028) /* SSP Port 1 Time Out Register */
144 #define SSPSP_P1 __REG(0x4100002C) /* SSP Port 1 Programmable Serial Protocol */
145 #define SSCR0_P2 __REG(0x41400000) /* SSP Port 2 Control Register 0 */
146 #define SSCR1_P2 __REG(0x41400004) /* SSP Port 2 Control Register 1 */
147 #define SSSR_P2 __REG(0x41400008) /* SSP Port 2 Status Register */
148 #define SSITR_P2 __REG(0x4140000C) /* SSP Port 2 Interrupt Test Register */
149 #define SSDR_P2 __REG(0x41400010) /* (Write / Read) SSP Port 2 Data Write Register/SSP Data Read Register */
150 #define SSTO_P2 __REG(0x41400028) /* SSP Port 2 Time Out Register */
151 #define SSPSP_P2 __REG(0x4140002C) /* SSP Port 2 Programmable Serial Protocol */
152 #define SSCR0_P3 __REG(0x41500000) /* SSP Port 3 Control Register 0 */
153 #define SSCR1_P3 __REG(0x41500004) /* SSP Port 3 Control Register 1 */
154 #define SSSR_P3 __REG(0x41500008) /* SSP Port 3 Status Register */
155 #define SSITR_P3 __REG(0x4150000C) /* SSP Port 3 Interrupt Test Register */
156 #define SSDR_P3 __REG(0x41500010) /* (Write / Read) SSP Port 3 Data Write Register/SSP Data Read Register */
157 #define SSTO_P3 __REG(0x41500028) /* SSP Port 3 Time Out Register */
158 #define SSPSP_P3 __REG(0x4150002C) /* SSP Port 3 Programmable Serial Protocol */
161 #define SSCR0_P(x) (*(((x) == 1) ? &SSCR0_P1 : ((x) == 2) ? &SSCR0_P2 : ((x) == 3) ? &SSCR0_P3 : NULL))
162 #define SSCR1_P(x) (*(((x) == 1) ? &SSCR1_P1 : ((x) == 2) ? &SSCR1_P2 : ((x) == 3) ? &SSCR1_P3 : NULL))
163 #define SSSR_P(x) (*(((x) == 1) ? &SSSR_P1 : ((x) == 2) ? &SSSR_P2 : ((x) == 3) ? &SSSR_P3 : NULL))
164 #define SSITR_P(x) (*(((x) == 1) ? &SSITR_P1 : ((x) == 2) ? &SSITR_P2 : ((x) == 3) ? &SSITR_P3 : NULL))
165 #define SSDR_P(x) (*(((x) == 1) ? &SSDR_P1 : ((x) == 2) ? &SSDR_P2 : ((x) == 3) ? &SSDR_P3 : NULL))
166 #define SSTO_P(x) (*(((x) == 1) ? &SSTO_P1 : ((x) == 2) ? &SSTO_P2 : ((x) == 3) ? &SSTO_P3 : NULL))
167 #define SSPSP_P(x) (*(((x) == 1) ? &SSPSP_P1 : ((x) == 2) ? &SSPSP_P2 : ((x) == 3) ? &SSPSP_P3 : NULL))
168 #define SSTSA_P(x) (*(((x) == 1) ? &SSTSA_P1 : ((x) == 2) ? &SSTSA_P2 : ((x) == 3) ? &SSTSA_P3 : NULL))
169 #define SSRSA_P(x) (*(((x) == 1) ? &SSRSA_P1 : ((x) == 2) ? &SSRSA_P2 : ((x) == 3) ? &SSRSA_P3 : NULL))
170 #define SSTSS_P(x) (*(((x) == 1) ? &SSTSS_P1 : ((x) == 2) ? &SSTSS_P2 : ((x) == 3) ? &SSTSS_P3 : NULL))
171 #define SSACD_P(x) (*(((x) == 1) ? &SSACD_P1 : ((x) == 2) ? &SSACD_P2 : ((x) == 3) ? &SSACD_P3 : NULL))
173 #endif /* __ASM_ARCH_REGS_SSP_H */
