1 #include <linux/linkage.h>
2 #include <linux/errno.h>
3 #include <linux/signal.h>
4 #include <linux/sched.h>
5 #include <linux/ioport.h>
6 #include <linux/interrupt.h>
7 #include <linux/timex.h>
8 #include <linux/slab.h>
9 #include <linux/random.h>
10 #include <linux/init.h>
11 #include <linux/kernel_stat.h>
12 #include <linux/sysdev.h>
13 #include <linux/bitops.h>
16 #include <asm/atomic.h>
17 #include <asm/system.h>
19 #include <asm/hw_irq.h>
20 #include <asm/pgtable.h>
21 #include <asm/delay.h>
24 #include <asm/i8259.h>
27 * Common place to define all x86 IRQ vectors
29 * This builds up the IRQ handler stubs using some ugly macros in irq.h
31 * These macros create the low-level assembly IRQ routines that save
32 * register context and call do_IRQ(). do_IRQ() then does all the
33 * operations that are needed to keep the AT (or SMP IOAPIC)
34 * interrupt-controller happy.
37 #define IRQ_NAME2(nr) nr##_interrupt(void)
38 #define IRQ_NAME(nr) IRQ_NAME2(IRQ##nr)
41 * SMP has a few special interrupts for IPI messages
44 #define BUILD_IRQ(nr) \
45 asmlinkage void IRQ_NAME(nr); \
46 asm("\n.text\n.p2align\n" \
47 "IRQ" #nr "_interrupt:\n\t" \
48 "push $~(" #nr ") ; " \
49 "jmp common_interrupt\n" \
55 #define BUILD_16_IRQS(x) \
56 BI(x,0) BI(x,1) BI(x,2) BI(x,3) \
57 BI(x,4) BI(x,5) BI(x,6) BI(x,7) \
58 BI(x,8) BI(x,9) BI(x,a) BI(x,b) \
59 BI(x,c) BI(x,d) BI(x,e) BI(x,f)
62 * ISA PIC or low IO-APIC triggered (INTA-cycle or APIC) interrupts:
63 * (these are usually mapped to vectors 0x30-0x3f)
67 * The IO-APIC gives us many more interrupt sources. Most of these
68 * are unused but an SMP system is supposed to have enough memory ...
69 * sometimes (mostly wrt. hw bugs) we get corrupted vectors all
70 * across the spectrum, so we really want to be prepared to get all
71 * of these. Plus, more powerful systems might have more than 64
74 * (these are usually mapped into the 0x30-0xff vector range)
76 BUILD_16_IRQS(0x2) BUILD_16_IRQS(0x3)
77 BUILD_16_IRQS(0x4) BUILD_16_IRQS(0x5) BUILD_16_IRQS(0x6) BUILD_16_IRQS(0x7)
78 BUILD_16_IRQS(0x8) BUILD_16_IRQS(0x9) BUILD_16_IRQS(0xa) BUILD_16_IRQS(0xb)
79 BUILD_16_IRQS(0xc) BUILD_16_IRQS(0xd) BUILD_16_IRQS(0xe) BUILD_16_IRQS(0xf)
88 #define IRQLIST_16(x) \
89 IRQ(x,0), IRQ(x,1), IRQ(x,2), IRQ(x,3), \
90 IRQ(x,4), IRQ(x,5), IRQ(x,6), IRQ(x,7), \
91 IRQ(x,8), IRQ(x,9), IRQ(x,a), IRQ(x,b), \
92 IRQ(x,c), IRQ(x,d), IRQ(x,e), IRQ(x,f)
94 /* for the irq vectors */
95 static void (*__initdata interrupt
[NR_VECTORS
- FIRST_EXTERNAL_VECTOR
])(void) = {
96 IRQLIST_16(0x2), IRQLIST_16(0x3),
97 IRQLIST_16(0x4), IRQLIST_16(0x5), IRQLIST_16(0x6), IRQLIST_16(0x7),
98 IRQLIST_16(0x8), IRQLIST_16(0x9), IRQLIST_16(0xa), IRQLIST_16(0xb),
99 IRQLIST_16(0xc), IRQLIST_16(0xd), IRQLIST_16(0xe), IRQLIST_16(0xf)
109 * IRQ2 is cascade interrupt to second interrupt controller
112 static struct irqaction irq2
= {
113 .handler
= no_action
,
114 .mask
= CPU_MASK_NONE
,
117 DEFINE_PER_CPU(vector_irq_t
, vector_irq
) = {
118 [0 ... IRQ0_VECTOR
- 1] = -1,
135 [IRQ15_VECTOR
+ 1 ... NR_VECTORS
- 1] = -1
138 void __init
init_ISA_irqs(void)
145 for (i
= 0; i
< nr_irqs
; i
++) {
146 struct irq_desc
*desc
= irq_to_desc(i
);
148 desc
->status
= IRQ_DISABLED
;
154 * 16 old-style INTA-cycle interrupts:
156 set_irq_chip_and_handler_name(i
, &i8259A_chip
,
157 handle_level_irq
, "XT");
160 * 'high' PCI IRQs filled in on demand
162 desc
->chip
= &no_irq_chip
;
167 void init_IRQ(void) __attribute__((weak
, alias("native_init_IRQ")));
169 static void __init
smp_intr_init(void)
173 * The reschedule interrupt is a CPU-to-CPU reschedule-helper
174 * IPI, driven by wakeup.
176 alloc_intr_gate(RESCHEDULE_VECTOR
, reschedule_interrupt
);
178 /* IPIs for invalidation */
179 alloc_intr_gate(INVALIDATE_TLB_VECTOR_START
+0, invalidate_interrupt0
);
180 alloc_intr_gate(INVALIDATE_TLB_VECTOR_START
+1, invalidate_interrupt1
);
181 alloc_intr_gate(INVALIDATE_TLB_VECTOR_START
+2, invalidate_interrupt2
);
182 alloc_intr_gate(INVALIDATE_TLB_VECTOR_START
+3, invalidate_interrupt3
);
183 alloc_intr_gate(INVALIDATE_TLB_VECTOR_START
+4, invalidate_interrupt4
);
184 alloc_intr_gate(INVALIDATE_TLB_VECTOR_START
+5, invalidate_interrupt5
);
185 alloc_intr_gate(INVALIDATE_TLB_VECTOR_START
+6, invalidate_interrupt6
);
186 alloc_intr_gate(INVALIDATE_TLB_VECTOR_START
+7, invalidate_interrupt7
);
188 /* IPI for generic function call */
189 alloc_intr_gate(CALL_FUNCTION_VECTOR
, call_function_interrupt
);
191 /* IPI for generic single function call */
192 alloc_intr_gate(CALL_FUNCTION_SINGLE_VECTOR
,
193 call_function_single_interrupt
);
195 /* Low priority IPI to cleanup after moving an irq */
196 set_intr_gate(IRQ_MOVE_CLEANUP_VECTOR
, irq_move_cleanup_interrupt
);
200 static void __init
apic_intr_init(void)
204 alloc_intr_gate(THERMAL_APIC_VECTOR
, thermal_interrupt
);
205 alloc_intr_gate(THRESHOLD_APIC_VECTOR
, threshold_interrupt
);
207 /* self generated IPI for local APIC timer */
208 alloc_intr_gate(LOCAL_TIMER_VECTOR
, apic_timer_interrupt
);
210 /* IPI vectors for APIC spurious and error interrupts */
211 alloc_intr_gate(SPURIOUS_APIC_VECTOR
, spurious_interrupt
);
212 alloc_intr_gate(ERROR_APIC_VECTOR
, error_interrupt
);
215 void __init
native_init_IRQ(void)
221 * Cover the whole vector space, no vector can escape
222 * us. (some of these will be overridden and become
223 * 'special' SMP interrupts)
225 for (i
= 0; i
< (NR_VECTORS
- FIRST_EXTERNAL_VECTOR
); i
++) {
226 int vector
= FIRST_EXTERNAL_VECTOR
+ i
;
227 if (vector
!= IA32_SYSCALL_VECTOR
)
228 set_intr_gate(vector
, interrupt
[i
]);