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generic: sparse irqs: use irq_desc() together with dyn_array, instead of irq_desc[]
[linux-2.6/verdex.git] / arch / x86 / kernel / io_apic_64.c
blobcab5a25d81b142959f14854107d3956f6b9cf9be
1 /*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
22
23 #include <linux/mm.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/acpi.h>
31 #include <linux/sysdev.h>
32 #include <linux/msi.h>
33 #include <linux/htirq.h>
34 #include <linux/dmar.h>
35 #include <linux/jiffies.h>
36 #ifdef CONFIG_ACPI
37 #include <acpi/acpi_bus.h>
38 #endif
39 #include <linux/bootmem.h>
40 #include <linux/dmar.h>
41
42 #include <asm/idle.h>
43 #include <asm/io.h>
44 #include <asm/smp.h>
45 #include <asm/desc.h>
46 #include <asm/proto.h>
47 #include <asm/acpi.h>
48 #include <asm/dma.h>
49 #include <asm/i8259.h>
50 #include <asm/nmi.h>
51 #include <asm/msidef.h>
52 #include <asm/hypertransport.h>
53 #include <asm/irq_remapping.h>
54
55 #include <mach_ipi.h>
56 #include <mach_apic.h>
57
58 #define __apicdebuginit(type) static type __init
59
60 struct irq_cfg {
61 cpumask_t domain;
62 cpumask_t old_domain;
63 unsigned move_cleanup_count;
64 u8 vector;
65 u8 move_in_progress : 1;
66 };
67
68 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
69 static struct irq_cfg irq_cfg_legacy[] __initdata = {
70 [0] = { .domain = CPU_MASK_ALL, .vector = IRQ0_VECTOR, },
71 [1] = { .domain = CPU_MASK_ALL, .vector = IRQ1_VECTOR, },
72 [2] = { .domain = CPU_MASK_ALL, .vector = IRQ2_VECTOR, },
73 [3] = { .domain = CPU_MASK_ALL, .vector = IRQ3_VECTOR, },
74 [4] = { .domain = CPU_MASK_ALL, .vector = IRQ4_VECTOR, },
75 [5] = { .domain = CPU_MASK_ALL, .vector = IRQ5_VECTOR, },
76 [6] = { .domain = CPU_MASK_ALL, .vector = IRQ6_VECTOR, },
77 [7] = { .domain = CPU_MASK_ALL, .vector = IRQ7_VECTOR, },
78 [8] = { .domain = CPU_MASK_ALL, .vector = IRQ8_VECTOR, },
79 [9] = { .domain = CPU_MASK_ALL, .vector = IRQ9_VECTOR, },
80 [10] = { .domain = CPU_MASK_ALL, .vector = IRQ10_VECTOR, },
81 [11] = { .domain = CPU_MASK_ALL, .vector = IRQ11_VECTOR, },
82 [12] = { .domain = CPU_MASK_ALL, .vector = IRQ12_VECTOR, },
83 [13] = { .domain = CPU_MASK_ALL, .vector = IRQ13_VECTOR, },
84 [14] = { .domain = CPU_MASK_ALL, .vector = IRQ14_VECTOR, },
85 [15] = { .domain = CPU_MASK_ALL, .vector = IRQ15_VECTOR, },
86 };
87
88 static struct irq_cfg *irq_cfg;
89
90 static void __init init_work(void *data)
91 {
92 struct dyn_array *da = data;
93
94 memcpy(*da->name, irq_cfg_legacy, sizeof(irq_cfg_legacy));
95 }
96
97 DEFINE_DYN_ARRAY(irq_cfg, sizeof(struct irq_cfg), nr_irqs, PAGE_SIZE, init_work);
98
99 static int assign_irq_vector(int irq, cpumask_t mask);
100
101 int first_system_vector = 0xfe;
102
103 char system_vectors[NR_VECTORS] = { [0 ... NR_VECTORS-1] = SYS_VECTOR_FREE};
104
105 int sis_apic_bug; /* not actually supported, dummy for compile */
106
107 static int no_timer_check;
108
109 static int disable_timer_pin_1 __initdata;
110
111 int timer_through_8259 __initdata;
112
113 /* Where if anywhere is the i8259 connect in external int mode */
114 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
115
116 static DEFINE_SPINLOCK(ioapic_lock);
117 static DEFINE_SPINLOCK(vector_lock);
118
119 /*
120 * # of IRQ routing registers
121 */
122 int nr_ioapic_registers[MAX_IO_APICS];
123
124 /* I/O APIC RTE contents at the OS boot up */
125 struct IO_APIC_route_entry *early_ioapic_entries[MAX_IO_APICS];
126
127 /* I/O APIC entries */
128 struct mp_config_ioapic mp_ioapics[MAX_IO_APICS];
129 int nr_ioapics;
130
131 /* MP IRQ source entries */
132 struct mp_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
133
134 /* # of MP IRQ source entries */
135 int mp_irq_entries;
136
137 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
138
139 /*
140 * Rough estimation of how many shared IRQs there are, can
141 * be changed anytime.
142 */
143
144 int pin_map_size;
145
146 /*
147 * This is performance-critical, we want to do it O(1)
148 *
149 * the indexing order of this array favors 1:1 mappings
150 * between pins and IRQs.
151 */
152
153 static struct irq_pin_list {
154 short apic, pin;
155 int next;
156 } *irq_2_pin;
157
158 DEFINE_DYN_ARRAY(irq_2_pin, sizeof(struct irq_pin_list), pin_map_size, sizeof(struct irq_pin_list), NULL);
159
160
161 struct io_apic {
162 unsigned int index;
163 unsigned int unused[3];
164 unsigned int data;
165 };
166
167 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
168 {
169 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
170 + (mp_ioapics[idx].mp_apicaddr & ~PAGE_MASK);
171 }
172
173 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
174 {
175 struct io_apic __iomem *io_apic = io_apic_base(apic);
176 writel(reg, &io_apic->index);
177 return readl(&io_apic->data);
178 }
179
180 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
181 {
182 struct io_apic __iomem *io_apic = io_apic_base(apic);
183 writel(reg, &io_apic->index);
184 writel(value, &io_apic->data);
185 }
186
187 /*
188 * Re-write a value: to be used for read-modify-write
189 * cycles where the read already set up the index register.
190 */
191 static inline void io_apic_modify(unsigned int apic, unsigned int value)
192 {
193 struct io_apic __iomem *io_apic = io_apic_base(apic);
194 writel(value, &io_apic->data);
195 }
196
197 static bool io_apic_level_ack_pending(unsigned int irq)
198 {
199 struct irq_pin_list *entry;
200 unsigned long flags;
201
202 spin_lock_irqsave(&ioapic_lock, flags);
203 entry = irq_2_pin + irq;
204 for (;;) {
205 unsigned int reg;
206 int pin;
207
208 pin = entry->pin;
209 if (pin == -1)
210 break;
211 reg = io_apic_read(entry->apic, 0x10 + pin*2);
212 /* Is the remote IRR bit set? */
213 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
214 spin_unlock_irqrestore(&ioapic_lock, flags);
215 return true;
216 }
217 if (!entry->next)
218 break;
219 entry = irq_2_pin + entry->next;
220 }
221 spin_unlock_irqrestore(&ioapic_lock, flags);
222
223 return false;
224 }
225
226 /*
227 * Synchronize the IO-APIC and the CPU by doing
228 * a dummy read from the IO-APIC
229 */
230 static inline void io_apic_sync(unsigned int apic)
231 {
232 struct io_apic __iomem *io_apic = io_apic_base(apic);
233 readl(&io_apic->data);
234 }
235
236 #define __DO_ACTION(R, ACTION, FINAL) \
237 \
238 { \
239 int pin; \
240 struct irq_pin_list *entry = irq_2_pin + irq; \
241 \
242 BUG_ON(irq >= nr_irqs); \
243 for (;;) { \
244 unsigned int reg; \
245 pin = entry->pin; \
246 if (pin == -1) \
247 break; \
248 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
249 reg ACTION; \
250 io_apic_modify(entry->apic, reg); \
251 FINAL; \
252 if (!entry->next) \
253 break; \
254 entry = irq_2_pin + entry->next; \
255 } \
256 }
257
258 union entry_union {
259 struct { u32 w1, w2; };
260 struct IO_APIC_route_entry entry;
261 };
262
263 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
264 {
265 union entry_union eu;
266 unsigned long flags;
267 spin_lock_irqsave(&ioapic_lock, flags);
268 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
269 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
270 spin_unlock_irqrestore(&ioapic_lock, flags);
271 return eu.entry;
272 }
273
274 /*
275 * When we write a new IO APIC routing entry, we need to write the high
276 * word first! If the mask bit in the low word is clear, we will enable
277 * the interrupt, and we need to make sure the entry is fully populated
278 * before that happens.
279 */
280 static void
281 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
282 {
283 union entry_union eu;
284 eu.entry = e;
285 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
286 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
287 }
288
289 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
290 {
291 unsigned long flags;
292 spin_lock_irqsave(&ioapic_lock, flags);
293 __ioapic_write_entry(apic, pin, e);
294 spin_unlock_irqrestore(&ioapic_lock, flags);
295 }
296
297 /*
298 * When we mask an IO APIC routing entry, we need to write the low
299 * word first, in order to set the mask bit before we change the
300 * high bits!
301 */
302 static void ioapic_mask_entry(int apic, int pin)
303 {
304 unsigned long flags;
305 union entry_union eu = { .entry.mask = 1 };
306
307 spin_lock_irqsave(&ioapic_lock, flags);
308 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
309 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
310 spin_unlock_irqrestore(&ioapic_lock, flags);
311 }
312
313 #ifdef CONFIG_SMP
314 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector)
315 {
316 int apic, pin;
317 struct irq_pin_list *entry = irq_2_pin + irq;
318
319 BUG_ON(irq >= nr_irqs);
320 for (;;) {
321 unsigned int reg;
322 apic = entry->apic;
323 pin = entry->pin;
324 if (pin == -1)
325 break;
326 /*
327 * With interrupt-remapping, destination information comes
328 * from interrupt-remapping table entry.
329 */
330 if (!irq_remapped(irq))
331 io_apic_write(apic, 0x11 + pin*2, dest);
332 reg = io_apic_read(apic, 0x10 + pin*2);
333 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
334 reg |= vector;
335 io_apic_modify(apic, reg);
336 if (!entry->next)
337 break;
338 entry = irq_2_pin + entry->next;
339 }
340 }
341
342 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
343 {
344 struct irq_cfg *cfg = irq_cfg + irq;
345 unsigned long flags;
346 unsigned int dest;
347 cpumask_t tmp;
348 struct irq_desc *desc;
349
350 cpus_and(tmp, mask, cpu_online_map);
351 if (cpus_empty(tmp))
352 return;
353
354 if (assign_irq_vector(irq, mask))
355 return;
356
357 cpus_and(tmp, cfg->domain, mask);
358 dest = cpu_mask_to_apicid(tmp);
359
360 /*
361 * Only the high 8 bits are valid.
362 */
363 dest = SET_APIC_LOGICAL_ID(dest);
364
365 desc = irq_to_desc(irq);
366 spin_lock_irqsave(&ioapic_lock, flags);
367 __target_IO_APIC_irq(irq, dest, cfg->vector);
368 desc->affinity = mask;
369 spin_unlock_irqrestore(&ioapic_lock, flags);
370 }
371 #endif
372
373 /*
374 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
375 * shared ISA-space IRQs, so we have to support them. We are super
376 * fast in the common case, and fast for shared ISA-space IRQs.
377 */
378 int first_free_entry;
379 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
380 {
381 struct irq_pin_list *entry = irq_2_pin + irq;
382
383 BUG_ON(irq >= nr_irqs);
384 while (entry->next)
385 entry = irq_2_pin + entry->next;
386
387 if (entry->pin != -1) {
388 entry->next = first_free_entry;
389 entry = irq_2_pin + entry->next;
390 if (++first_free_entry >= pin_map_size)
391 panic("io_apic.c: ran out of irq_2_pin entries!");
392 }
393 entry->apic = apic;
394 entry->pin = pin;
395 }
396
397 /*
398 * Reroute an IRQ to a different pin.
399 */
400 static void __init replace_pin_at_irq(unsigned int irq,
401 int oldapic, int oldpin,
402 int newapic, int newpin)
403 {
404 struct irq_pin_list *entry = irq_2_pin + irq;
405
406 while (1) {
407 if (entry->apic == oldapic && entry->pin == oldpin) {
408 entry->apic = newapic;
409 entry->pin = newpin;
410 }
411 if (!entry->next)
412 break;
413 entry = irq_2_pin + entry->next;
414 }
415 }
416
417
418 #define DO_ACTION(name,R,ACTION, FINAL) \
419 \
420 static void name##_IO_APIC_irq (unsigned int irq) \
421 __DO_ACTION(R, ACTION, FINAL)
422
423 /* mask = 1 */
424 DO_ACTION(__mask, 0, |= IO_APIC_REDIR_MASKED, io_apic_sync(entry->apic))
425
426 /* mask = 0 */
427 DO_ACTION(__unmask, 0, &= ~IO_APIC_REDIR_MASKED, )
428
429 static void mask_IO_APIC_irq (unsigned int irq)
430 {
431 unsigned long flags;
432
433 spin_lock_irqsave(&ioapic_lock, flags);
434 __mask_IO_APIC_irq(irq);
435 spin_unlock_irqrestore(&ioapic_lock, flags);
436 }
437
438 static void unmask_IO_APIC_irq (unsigned int irq)
439 {
440 unsigned long flags;
441
442 spin_lock_irqsave(&ioapic_lock, flags);
443 __unmask_IO_APIC_irq(irq);
444 spin_unlock_irqrestore(&ioapic_lock, flags);
445 }
446
447 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
448 {
449 struct IO_APIC_route_entry entry;
450
451 /* Check delivery_mode to be sure we're not clearing an SMI pin */
452 entry = ioapic_read_entry(apic, pin);
453 if (entry.delivery_mode == dest_SMI)
454 return;
455 /*
456 * Disable it in the IO-APIC irq-routing table:
457 */
458 ioapic_mask_entry(apic, pin);
459 }
460
461 static void clear_IO_APIC (void)
462 {
463 int apic, pin;
464
465 for (apic = 0; apic < nr_ioapics; apic++)
466 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
467 clear_IO_APIC_pin(apic, pin);
468 }
469
470 /*
471 * Saves and masks all the unmasked IO-APIC RTE's
472 */
473 int save_mask_IO_APIC_setup(void)
474 {
475 union IO_APIC_reg_01 reg_01;
476 unsigned long flags;
477 int apic, pin;
478
479 /*
480 * The number of IO-APIC IRQ registers (== #pins):
481 */
482 for (apic = 0; apic < nr_ioapics; apic++) {
483 spin_lock_irqsave(&ioapic_lock, flags);
484 reg_01.raw = io_apic_read(apic, 1);
485 spin_unlock_irqrestore(&ioapic_lock, flags);
486 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
487 }
488
489 for (apic = 0; apic < nr_ioapics; apic++) {
490 early_ioapic_entries[apic] =
491 kzalloc(sizeof(struct IO_APIC_route_entry) *
492 nr_ioapic_registers[apic], GFP_KERNEL);
493 if (!early_ioapic_entries[apic])
494 return -ENOMEM;
495 }
496
497 for (apic = 0; apic < nr_ioapics; apic++)
498 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
499 struct IO_APIC_route_entry entry;
500
501 entry = early_ioapic_entries[apic][pin] =
502 ioapic_read_entry(apic, pin);
503 if (!entry.mask) {
504 entry.mask = 1;
505 ioapic_write_entry(apic, pin, entry);
506 }
507 }
508 return 0;
509 }
510
511 void restore_IO_APIC_setup(void)
512 {
513 int apic, pin;
514
515 for (apic = 0; apic < nr_ioapics; apic++)
516 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
517 ioapic_write_entry(apic, pin,
518 early_ioapic_entries[apic][pin]);
519 }
520
521 void reinit_intr_remapped_IO_APIC(int intr_remapping)
522 {
523 /*
524 * for now plain restore of previous settings.
525 * TBD: In the case of OS enabling interrupt-remapping,
526 * IO-APIC RTE's need to be setup to point to interrupt-remapping
527 * table entries. for now, do a plain restore, and wait for
528 * the setup_IO_APIC_irqs() to do proper initialization.
529 */
530 restore_IO_APIC_setup();
531 }
532
533 int skip_ioapic_setup;
534 int ioapic_force;
535
536 static int __init parse_noapic(char *str)
537 {
538 disable_ioapic_setup();
539 return 0;
540 }
541 early_param("noapic", parse_noapic);
542
543 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
544 static int __init disable_timer_pin_setup(char *arg)
545 {
546 disable_timer_pin_1 = 1;
547 return 1;
548 }
549 __setup("disable_timer_pin_1", disable_timer_pin_setup);
550
551
552 /*
553 * Find the IRQ entry number of a certain pin.
554 */
555 static int find_irq_entry(int apic, int pin, int type)
556 {
557 int i;
558
559 for (i = 0; i < mp_irq_entries; i++)
560 if (mp_irqs[i].mp_irqtype == type &&
561 (mp_irqs[i].mp_dstapic == mp_ioapics[apic].mp_apicid ||
562 mp_irqs[i].mp_dstapic == MP_APIC_ALL) &&
563 mp_irqs[i].mp_dstirq == pin)
564 return i;
565
566 return -1;
567 }
568
569 /*
570 * Find the pin to which IRQ[irq] (ISA) is connected
571 */
572 static int __init find_isa_irq_pin(int irq, int type)
573 {
574 int i;
575
576 for (i = 0; i < mp_irq_entries; i++) {
577 int lbus = mp_irqs[i].mp_srcbus;
578
579 if (test_bit(lbus, mp_bus_not_pci) &&
580 (mp_irqs[i].mp_irqtype == type) &&
581 (mp_irqs[i].mp_srcbusirq == irq))
582
583 return mp_irqs[i].mp_dstirq;
584 }
585 return -1;
586 }
587
588 static int __init find_isa_irq_apic(int irq, int type)
589 {
590 int i;
591
592 for (i = 0; i < mp_irq_entries; i++) {
593 int lbus = mp_irqs[i].mp_srcbus;
594
595 if (test_bit(lbus, mp_bus_not_pci) &&
596 (mp_irqs[i].mp_irqtype == type) &&
597 (mp_irqs[i].mp_srcbusirq == irq))
598 break;
599 }
600 if (i < mp_irq_entries) {
601 int apic;
602 for(apic = 0; apic < nr_ioapics; apic++) {
603 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic)
604 return apic;
605 }
606 }
607
608 return -1;
609 }
610
611 /*
612 * Find a specific PCI IRQ entry.
613 * Not an __init, possibly needed by modules
614 */
615 static int pin_2_irq(int idx, int apic, int pin);
616
617 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
618 {
619 int apic, i, best_guess = -1;
620
621 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
622 bus, slot, pin);
623 if (test_bit(bus, mp_bus_not_pci)) {
624 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
625 return -1;
626 }
627 for (i = 0; i < mp_irq_entries; i++) {
628 int lbus = mp_irqs[i].mp_srcbus;
629
630 for (apic = 0; apic < nr_ioapics; apic++)
631 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic ||
632 mp_irqs[i].mp_dstapic == MP_APIC_ALL)
633 break;
634
635 if (!test_bit(lbus, mp_bus_not_pci) &&
636 !mp_irqs[i].mp_irqtype &&
637 (bus == lbus) &&
638 (slot == ((mp_irqs[i].mp_srcbusirq >> 2) & 0x1f))) {
639 int irq = pin_2_irq(i,apic,mp_irqs[i].mp_dstirq);
640
641 if (!(apic || IO_APIC_IRQ(irq)))
642 continue;
643
644 if (pin == (mp_irqs[i].mp_srcbusirq & 3))
645 return irq;
646 /*
647 * Use the first all-but-pin matching entry as a
648 * best-guess fuzzy result for broken mptables.
649 */
650 if (best_guess < 0)
651 best_guess = irq;
652 }
653 }
654 BUG_ON(best_guess >= nr_irqs);
655 return best_guess;
656 }
657
658 /* ISA interrupts are always polarity zero edge triggered,
659 * when listed as conforming in the MP table. */
660
661 #define default_ISA_trigger(idx) (0)
662 #define default_ISA_polarity(idx) (0)
663
664 /* PCI interrupts are always polarity one level triggered,
665 * when listed as conforming in the MP table. */
666
667 #define default_PCI_trigger(idx) (1)
668 #define default_PCI_polarity(idx) (1)
669
670 static int MPBIOS_polarity(int idx)
671 {
672 int bus = mp_irqs[idx].mp_srcbus;
673 int polarity;
674
675 /*
676 * Determine IRQ line polarity (high active or low active):
677 */
678 switch (mp_irqs[idx].mp_irqflag & 3)
679 {
680 case 0: /* conforms, ie. bus-type dependent polarity */
681 if (test_bit(bus, mp_bus_not_pci))
682 polarity = default_ISA_polarity(idx);
683 else
684 polarity = default_PCI_polarity(idx);
685 break;
686 case 1: /* high active */
687 {
688 polarity = 0;
689 break;
690 }
691 case 2: /* reserved */
692 {
693 printk(KERN_WARNING "broken BIOS!!\n");
694 polarity = 1;
695 break;
696 }
697 case 3: /* low active */
698 {
699 polarity = 1;
700 break;
701 }
702 default: /* invalid */
703 {
704 printk(KERN_WARNING "broken BIOS!!\n");
705 polarity = 1;
706 break;
707 }
708 }
709 return polarity;
710 }
711
712 static int MPBIOS_trigger(int idx)
713 {
714 int bus = mp_irqs[idx].mp_srcbus;
715 int trigger;
716
717 /*
718 * Determine IRQ trigger mode (edge or level sensitive):
719 */
720 switch ((mp_irqs[idx].mp_irqflag>>2) & 3)
721 {
722 case 0: /* conforms, ie. bus-type dependent */
723 if (test_bit(bus, mp_bus_not_pci))
724 trigger = default_ISA_trigger(idx);
725 else
726 trigger = default_PCI_trigger(idx);
727 break;
728 case 1: /* edge */
729 {
730 trigger = 0;
731 break;
732 }
733 case 2: /* reserved */
734 {
735 printk(KERN_WARNING "broken BIOS!!\n");
736 trigger = 1;
737 break;
738 }
739 case 3: /* level */
740 {
741 trigger = 1;
742 break;
743 }
744 default: /* invalid */
745 {
746 printk(KERN_WARNING "broken BIOS!!\n");
747 trigger = 0;
748 break;
749 }
750 }
751 return trigger;
752 }
753
754 static inline int irq_polarity(int idx)
755 {
756 return MPBIOS_polarity(idx);
757 }
758
759 static inline int irq_trigger(int idx)
760 {
761 return MPBIOS_trigger(idx);
762 }
763
764 static int pin_2_irq(int idx, int apic, int pin)
765 {
766 int irq, i;
767 int bus = mp_irqs[idx].mp_srcbus;
768
769 /*
770 * Debugging check, we are in big trouble if this message pops up!
771 */
772 if (mp_irqs[idx].mp_dstirq != pin)
773 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
774
775 if (test_bit(bus, mp_bus_not_pci)) {
776 irq = mp_irqs[idx].mp_srcbusirq;
777 } else {
778 /*
779 * PCI IRQs are mapped in order
780 */
781 i = irq = 0;
782 while (i < apic)
783 irq += nr_ioapic_registers[i++];
784 irq += pin;
785 }
786 BUG_ON(irq >= nr_irqs);
787 return irq;
788 }
789
790 void lock_vector_lock(void)
791 {
792 /* Used to the online set of cpus does not change
793 * during assign_irq_vector.
794 */
795 spin_lock(&vector_lock);
796 }
797
798 void unlock_vector_lock(void)
799 {
800 spin_unlock(&vector_lock);
801 }
802
803 static int __assign_irq_vector(int irq, cpumask_t mask)
804 {
805 /*
806 * NOTE! The local APIC isn't very good at handling
807 * multiple interrupts at the same interrupt level.
808 * As the interrupt level is determined by taking the
809 * vector number and shifting that right by 4, we
810 * want to spread these out a bit so that they don't
811 * all fall in the same interrupt level.
812 *
813 * Also, we've got to be careful not to trash gate
814 * 0x80, because int 0x80 is hm, kind of importantish. ;)
815 */
816 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
817 unsigned int old_vector;
818 int cpu;
819 struct irq_cfg *cfg;
820
821 BUG_ON((unsigned)irq >= nr_irqs);
822 cfg = &irq_cfg[irq];
823
824 /* Only try and allocate irqs on cpus that are present */
825 cpus_and(mask, mask, cpu_online_map);
826
827 if ((cfg->move_in_progress) || cfg->move_cleanup_count)
828 return -EBUSY;
829
830 old_vector = cfg->vector;
831 if (old_vector) {
832 cpumask_t tmp;
833 cpus_and(tmp, cfg->domain, mask);
834 if (!cpus_empty(tmp))
835 return 0;
836 }
837
838 for_each_cpu_mask_nr(cpu, mask) {
839 cpumask_t domain, new_mask;
840 int new_cpu;
841 int vector, offset;
842
843 domain = vector_allocation_domain(cpu);
844 cpus_and(new_mask, domain, cpu_online_map);
845
846 vector = current_vector;
847 offset = current_offset;
848 next:
849 vector += 8;
850 if (vector >= first_system_vector) {
851 /* If we run out of vectors on large boxen, must share them. */
852 offset = (offset + 1) % 8;
853 vector = FIRST_DEVICE_VECTOR + offset;
854 }
855 if (unlikely(current_vector == vector))
856 continue;
857 if (vector == IA32_SYSCALL_VECTOR)
858 goto next;
859 for_each_cpu_mask_nr(new_cpu, new_mask)
860 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
861 goto next;
862 /* Found one! */
863 current_vector = vector;
864 current_offset = offset;
865 if (old_vector) {
866 cfg->move_in_progress = 1;
867 cfg->old_domain = cfg->domain;
868 }
869 for_each_cpu_mask_nr(new_cpu, new_mask)
870 per_cpu(vector_irq, new_cpu)[vector] = irq;
871 cfg->vector = vector;
872 cfg->domain = domain;
873 return 0;
874 }
875 return -ENOSPC;
876 }
877
878 static int assign_irq_vector(int irq, cpumask_t mask)
879 {
880 int err;
881 unsigned long flags;
882
883 spin_lock_irqsave(&vector_lock, flags);
884 err = __assign_irq_vector(irq, mask);
885 spin_unlock_irqrestore(&vector_lock, flags);
886 return err;
887 }
888
889 static void __clear_irq_vector(int irq)
890 {
891 struct irq_cfg *cfg;
892 cpumask_t mask;
893 int cpu, vector;
894
895 BUG_ON((unsigned)irq >= nr_irqs);
896 cfg = &irq_cfg[irq];
897 BUG_ON(!cfg->vector);
898
899 vector = cfg->vector;
900 cpus_and(mask, cfg->domain, cpu_online_map);
901 for_each_cpu_mask_nr(cpu, mask)
902 per_cpu(vector_irq, cpu)[vector] = -1;
903
904 cfg->vector = 0;
905 cpus_clear(cfg->domain);
906 }
907
908 void __setup_vector_irq(int cpu)
909 {
910 /* Initialize vector_irq on a new cpu */
911 /* This function must be called with vector_lock held */
912 int irq, vector;
913
914 /* Mark the inuse vectors */
915 for (irq = 0; irq < nr_irqs; ++irq) {
916 if (!cpu_isset(cpu, irq_cfg[irq].domain))
917 continue;
918 vector = irq_cfg[irq].vector;
919 per_cpu(vector_irq, cpu)[vector] = irq;
920 }
921 /* Mark the free vectors */
922 for (vector = 0; vector < NR_VECTORS; ++vector) {
923 irq = per_cpu(vector_irq, cpu)[vector];
924 if (irq < 0)
925 continue;
926 if (!cpu_isset(cpu, irq_cfg[irq].domain))
927 per_cpu(vector_irq, cpu)[vector] = -1;
928 }
929 }
930
931 static struct irq_chip ioapic_chip;
932 #ifdef CONFIG_INTR_REMAP
933 static struct irq_chip ir_ioapic_chip;
934 #endif
935
936 static void ioapic_register_intr(int irq, unsigned long trigger)
937 {
938 struct irq_desc *desc;
939
940 desc = irq_to_desc(irq);
941 if (trigger)
942 desc->status |= IRQ_LEVEL;
943 else
944 desc->status &= ~IRQ_LEVEL;
945
946 #ifdef CONFIG_INTR_REMAP
947 if (irq_remapped(irq)) {
948 desc->status |= IRQ_MOVE_PCNTXT;
949 if (trigger)
950 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
951 handle_fasteoi_irq,
952 "fasteoi");
953 else
954 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
955 handle_edge_irq, "edge");
956 return;
957 }
958 #endif
959 if (trigger)
960 set_irq_chip_and_handler_name(irq, &ioapic_chip,
961 handle_fasteoi_irq,
962 "fasteoi");
963 else
964 set_irq_chip_and_handler_name(irq, &ioapic_chip,
965 handle_edge_irq, "edge");
966 }
967
968 static int setup_ioapic_entry(int apic, int irq,
969 struct IO_APIC_route_entry *entry,
970 unsigned int destination, int trigger,
971 int polarity, int vector)
972 {
973 /*
974 * add it to the IO-APIC irq-routing table:
975 */
976 memset(entry,0,sizeof(*entry));
977
978 #ifdef CONFIG_INTR_REMAP
979 if (intr_remapping_enabled) {
980 struct intel_iommu *iommu = map_ioapic_to_ir(apic);
981 struct irte irte;
982 struct IR_IO_APIC_route_entry *ir_entry =
983 (struct IR_IO_APIC_route_entry *) entry;
984 int index;
985
986 if (!iommu)
987 panic("No mapping iommu for ioapic %d\n", apic);
988
989 index = alloc_irte(iommu, irq, 1);
990 if (index < 0)
991 panic("Failed to allocate IRTE for ioapic %d\n", apic);
992
993 memset(&irte, 0, sizeof(irte));
994
995 irte.present = 1;
996 irte.dst_mode = INT_DEST_MODE;
997 irte.trigger_mode = trigger;
998 irte.dlvry_mode = INT_DELIVERY_MODE;
999 irte.vector = vector;
1000 irte.dest_id = IRTE_DEST(destination);
1001
1002 modify_irte(irq, &irte);
1003
1004 ir_entry->index2 = (index >> 15) & 0x1;
1005 ir_entry->zero = 0;
1006 ir_entry->format = 1;
1007 ir_entry->index = (index & 0x7fff);
1008 } else
1009 #endif
1010 {
1011 entry->delivery_mode = INT_DELIVERY_MODE;
1012 entry->dest_mode = INT_DEST_MODE;
1013 entry->dest = destination;
1014 }
1015
1016 entry->mask = 0; /* enable IRQ */
1017 entry->trigger = trigger;
1018 entry->polarity = polarity;
1019 entry->vector = vector;
1020
1021 /* Mask level triggered irqs.
1022 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1023 */
1024 if (trigger)
1025 entry->mask = 1;
1026 return 0;
1027 }
1028
1029 static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq,
1030 int trigger, int polarity)
1031 {
1032 struct irq_cfg *cfg = irq_cfg + irq;
1033 struct IO_APIC_route_entry entry;
1034 cpumask_t mask;
1035
1036 if (!IO_APIC_IRQ(irq))
1037 return;
1038
1039 mask = TARGET_CPUS;
1040 if (assign_irq_vector(irq, mask))
1041 return;
1042
1043 cpus_and(mask, cfg->domain, mask);
1044
1045 apic_printk(APIC_VERBOSE,KERN_DEBUG
1046 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1047 "IRQ %d Mode:%i Active:%i)\n",
1048 apic, mp_ioapics[apic].mp_apicid, pin, cfg->vector,
1049 irq, trigger, polarity);
1050
1051
1052 if (setup_ioapic_entry(mp_ioapics[apic].mp_apicid, irq, &entry,
1053 cpu_mask_to_apicid(mask), trigger, polarity,
1054 cfg->vector)) {
1055 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1056 mp_ioapics[apic].mp_apicid, pin);
1057 __clear_irq_vector(irq);
1058 return;
1059 }
1060
1061 ioapic_register_intr(irq, trigger);
1062 if (irq < 16)
1063 disable_8259A_irq(irq);
1064
1065 ioapic_write_entry(apic, pin, entry);
1066 }
1067
1068 static void __init setup_IO_APIC_irqs(void)
1069 {
1070 int apic, pin, idx, irq, first_notcon = 1;
1071
1072 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1073
1074 for (apic = 0; apic < nr_ioapics; apic++) {
1075 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1076
1077 idx = find_irq_entry(apic,pin,mp_INT);
1078 if (idx == -1) {
1079 if (first_notcon) {
1080 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mp_apicid, pin);
1081 first_notcon = 0;
1082 } else
1083 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mp_apicid, pin);
1084 continue;
1085 }
1086 if (!first_notcon) {
1087 apic_printk(APIC_VERBOSE, " not connected.\n");
1088 first_notcon = 1;
1089 }
1090
1091 irq = pin_2_irq(idx, apic, pin);
1092 add_pin_to_irq(irq, apic, pin);
1093
1094 setup_IO_APIC_irq(apic, pin, irq,
1095 irq_trigger(idx), irq_polarity(idx));
1096 }
1097 }
1098
1099 if (!first_notcon)
1100 apic_printk(APIC_VERBOSE, " not connected.\n");
1101 }
1102
1103 /*
1104 * Set up the timer pin, possibly with the 8259A-master behind.
1105 */
1106 static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin,
1107 int vector)
1108 {
1109 struct IO_APIC_route_entry entry;
1110
1111 if (intr_remapping_enabled)
1112 return;
1113
1114 memset(&entry, 0, sizeof(entry));
1115
1116 /*
1117 * We use logical delivery to get the timer IRQ
1118 * to the first CPU.
1119 */
1120 entry.dest_mode = INT_DEST_MODE;
1121 entry.mask = 1; /* mask IRQ now */
1122 entry.dest = cpu_mask_to_apicid(TARGET_CPUS);
1123 entry.delivery_mode = INT_DELIVERY_MODE;
1124 entry.polarity = 0;
1125 entry.trigger = 0;
1126 entry.vector = vector;
1127
1128 /*
1129 * The timer IRQ doesn't have to know that behind the
1130 * scene we may have a 8259A-master in AEOI mode ...
1131 */
1132 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1133
1134 /*
1135 * Add it to the IO-APIC irq-routing table:
1136 */
1137 ioapic_write_entry(apic, pin, entry);
1138 }
1139
1140
1141 __apicdebuginit(void) print_IO_APIC(void)
1142 {
1143 int apic, i;
1144 union IO_APIC_reg_00 reg_00;
1145 union IO_APIC_reg_01 reg_01;
1146 union IO_APIC_reg_02 reg_02;
1147 unsigned long flags;
1148
1149 if (apic_verbosity == APIC_QUIET)
1150 return;
1151
1152 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1153 for (i = 0; i < nr_ioapics; i++)
1154 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1155 mp_ioapics[i].mp_apicid, nr_ioapic_registers[i]);
1156
1157 /*
1158 * We are a bit conservative about what we expect. We have to
1159 * know about every hardware change ASAP.
1160 */
1161 printk(KERN_INFO "testing the IO APIC.......................\n");
1162
1163 for (apic = 0; apic < nr_ioapics; apic++) {
1164
1165 spin_lock_irqsave(&ioapic_lock, flags);
1166 reg_00.raw = io_apic_read(apic, 0);
1167 reg_01.raw = io_apic_read(apic, 1);
1168 if (reg_01.bits.version >= 0x10)
1169 reg_02.raw = io_apic_read(apic, 2);
1170 spin_unlock_irqrestore(&ioapic_lock, flags);
1171
1172 printk("\n");
1173 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mp_apicid);
1174 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1175 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1176
1177 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
1178 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1179
1180 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1181 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1182
1183 if (reg_01.bits.version >= 0x10) {
1184 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1185 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1186 }
1187
1188 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1189
1190 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1191 " Stat Dmod Deli Vect: \n");
1192
1193 for (i = 0; i <= reg_01.bits.entries; i++) {
1194 struct IO_APIC_route_entry entry;
1195
1196 entry = ioapic_read_entry(apic, i);
1197
1198 printk(KERN_DEBUG " %02x %03X ",
1199 i,
1200 entry.dest
1201 );
1202
1203 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1204 entry.mask,
1205 entry.trigger,
1206 entry.irr,
1207 entry.polarity,
1208 entry.delivery_status,
1209 entry.dest_mode,
1210 entry.delivery_mode,
1211 entry.vector
1212 );
1213 }
1214 }
1215 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1216 for (i = 0; i < nr_irqs; i++) {
1217 struct irq_pin_list *entry = irq_2_pin + i;
1218 if (entry->pin < 0)
1219 continue;
1220 printk(KERN_DEBUG "IRQ%d ", i);
1221 for (;;) {
1222 printk("-> %d:%d", entry->apic, entry->pin);
1223 if (!entry->next)
1224 break;
1225 entry = irq_2_pin + entry->next;
1226 }
1227 printk("\n");
1228 }
1229
1230 printk(KERN_INFO ".................................... done.\n");
1231
1232 return;
1233 }
1234
1235 __apicdebuginit(void) print_APIC_bitfield(int base)
1236 {
1237 unsigned int v;
1238 int i, j;
1239
1240 if (apic_verbosity == APIC_QUIET)
1241 return;
1242
1243 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1244 for (i = 0; i < 8; i++) {
1245 v = apic_read(base + i*0x10);
1246 for (j = 0; j < 32; j++) {
1247 if (v & (1<<j))
1248 printk("1");
1249 else
1250 printk("0");
1251 }
1252 printk("\n");
1253 }
1254 }
1255
1256 __apicdebuginit(void) print_local_APIC(void *dummy)
1257 {
1258 unsigned int v, ver, maxlvt;
1259 unsigned long icr;
1260
1261 if (apic_verbosity == APIC_QUIET)
1262 return;
1263
1264 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1265 smp_processor_id(), hard_smp_processor_id());
1266 v = apic_read(APIC_ID);
1267 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
1268 v = apic_read(APIC_LVR);
1269 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1270 ver = GET_APIC_VERSION(v);
1271 maxlvt = lapic_get_maxlvt();
1272
1273 v = apic_read(APIC_TASKPRI);
1274 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1275
1276 v = apic_read(APIC_ARBPRI);
1277 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1278 v & APIC_ARBPRI_MASK);
1279 v = apic_read(APIC_PROCPRI);
1280 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1281
1282 v = apic_read(APIC_EOI);
1283 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1284 v = apic_read(APIC_RRR);
1285 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1286 v = apic_read(APIC_LDR);
1287 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1288 v = apic_read(APIC_DFR);
1289 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1290 v = apic_read(APIC_SPIV);
1291 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1292
1293 printk(KERN_DEBUG "... APIC ISR field:\n");
1294 print_APIC_bitfield(APIC_ISR);
1295 printk(KERN_DEBUG "... APIC TMR field:\n");
1296 print_APIC_bitfield(APIC_TMR);
1297 printk(KERN_DEBUG "... APIC IRR field:\n");
1298 print_APIC_bitfield(APIC_IRR);
1299
1300 v = apic_read(APIC_ESR);
1301 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1302
1303 icr = apic_icr_read();
1304 printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1305 printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1306
1307 v = apic_read(APIC_LVTT);
1308 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1309
1310 if (maxlvt > 3) { /* PC is LVT#4. */
1311 v = apic_read(APIC_LVTPC);
1312 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1313 }
1314 v = apic_read(APIC_LVT0);
1315 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1316 v = apic_read(APIC_LVT1);
1317 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1318
1319 if (maxlvt > 2) { /* ERR is LVT#3. */
1320 v = apic_read(APIC_LVTERR);
1321 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1322 }
1323
1324 v = apic_read(APIC_TMICT);
1325 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1326 v = apic_read(APIC_TMCCT);
1327 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1328 v = apic_read(APIC_TDCR);
1329 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1330 printk("\n");
1331 }
1332
1333 __apicdebuginit(void) print_all_local_APICs(void)
1334 {
1335 on_each_cpu(print_local_APIC, NULL, 1);
1336 }
1337
1338 __apicdebuginit(void) print_PIC(void)
1339 {
1340 unsigned int v;
1341 unsigned long flags;
1342
1343 if (apic_verbosity == APIC_QUIET)
1344 return;
1345
1346 printk(KERN_DEBUG "\nprinting PIC contents\n");
1347
1348 spin_lock_irqsave(&i8259A_lock, flags);
1349
1350 v = inb(0xa1) << 8 | inb(0x21);
1351 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1352
1353 v = inb(0xa0) << 8 | inb(0x20);
1354 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1355
1356 outb(0x0b,0xa0);
1357 outb(0x0b,0x20);
1358 v = inb(0xa0) << 8 | inb(0x20);
1359 outb(0x0a,0xa0);
1360 outb(0x0a,0x20);
1361
1362 spin_unlock_irqrestore(&i8259A_lock, flags);
1363
1364 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1365
1366 v = inb(0x4d1) << 8 | inb(0x4d0);
1367 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1368 }
1369
1370 __apicdebuginit(int) print_all_ICs(void)
1371 {
1372 print_PIC();
1373 print_all_local_APICs();
1374 print_IO_APIC();
1375
1376 return 0;
1377 }
1378
1379 fs_initcall(print_all_ICs);
1380
1381
1382 void __init enable_IO_APIC(void)
1383 {
1384 union IO_APIC_reg_01 reg_01;
1385 int i8259_apic, i8259_pin;
1386 int i, apic;
1387 unsigned long flags;
1388
1389 for (i = 0; i < pin_map_size; i++) {
1390 irq_2_pin[i].pin = -1;
1391 irq_2_pin[i].next = 0;
1392 }
1393
1394 /*
1395 * The number of IO-APIC IRQ registers (== #pins):
1396 */
1397 for (apic = 0; apic < nr_ioapics; apic++) {
1398 spin_lock_irqsave(&ioapic_lock, flags);
1399 reg_01.raw = io_apic_read(apic, 1);
1400 spin_unlock_irqrestore(&ioapic_lock, flags);
1401 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1402 }
1403 for(apic = 0; apic < nr_ioapics; apic++) {
1404 int pin;
1405 /* See if any of the pins is in ExtINT mode */
1406 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1407 struct IO_APIC_route_entry entry;
1408 entry = ioapic_read_entry(apic, pin);
1409
1410 /* If the interrupt line is enabled and in ExtInt mode
1411 * I have found the pin where the i8259 is connected.
1412 */
1413 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1414 ioapic_i8259.apic = apic;
1415 ioapic_i8259.pin = pin;
1416 goto found_i8259;
1417 }
1418 }
1419 }
1420 found_i8259:
1421 /* Look to see what if the MP table has reported the ExtINT */
1422 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1423 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1424 /* Trust the MP table if nothing is setup in the hardware */
1425 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1426 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1427 ioapic_i8259.pin = i8259_pin;
1428 ioapic_i8259.apic = i8259_apic;
1429 }
1430 /* Complain if the MP table and the hardware disagree */
1431 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1432 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1433 {
1434 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1435 }
1436
1437 /*
1438 * Do not trust the IO-APIC being empty at bootup
1439 */
1440 clear_IO_APIC();
1441 }
1442
1443 /*
1444 * Not an __init, needed by the reboot code
1445 */
1446 void disable_IO_APIC(void)
1447 {
1448 /*
1449 * Clear the IO-APIC before rebooting:
1450 */
1451 clear_IO_APIC();
1452
1453 /*
1454 * If the i8259 is routed through an IOAPIC
1455 * Put that IOAPIC in virtual wire mode
1456 * so legacy interrupts can be delivered.
1457 */
1458 if (ioapic_i8259.pin != -1) {
1459 struct IO_APIC_route_entry entry;
1460
1461 memset(&entry, 0, sizeof(entry));
1462 entry.mask = 0; /* Enabled */
1463 entry.trigger = 0; /* Edge */
1464 entry.irr = 0;
1465 entry.polarity = 0; /* High */
1466 entry.delivery_status = 0;
1467 entry.dest_mode = 0; /* Physical */
1468 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1469 entry.vector = 0;
1470 entry.dest = read_apic_id();
1471
1472 /*
1473 * Add it to the IO-APIC irq-routing table:
1474 */
1475 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1476 }
1477
1478 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1479 }
1480
1481 /*
1482 * There is a nasty bug in some older SMP boards, their mptable lies
1483 * about the timer IRQ. We do the following to work around the situation:
1484 *
1485 * - timer IRQ defaults to IO-APIC IRQ
1486 * - if this function detects that timer IRQs are defunct, then we fall
1487 * back to ISA timer IRQs
1488 */
1489 static int __init timer_irq_works(void)
1490 {
1491 unsigned long t1 = jiffies;
1492 unsigned long flags;
1493
1494 local_save_flags(flags);
1495 local_irq_enable();
1496 /* Let ten ticks pass... */
1497 mdelay((10 * 1000) / HZ);
1498 local_irq_restore(flags);
1499
1500 /*
1501 * Expect a few ticks at least, to be sure some possible
1502 * glue logic does not lock up after one or two first
1503 * ticks in a non-ExtINT mode. Also the local APIC
1504 * might have cached one ExtINT interrupt. Finally, at
1505 * least one tick may be lost due to delays.
1506 */
1507
1508 /* jiffies wrap? */
1509 if (time_after(jiffies, t1 + 4))
1510 return 1;
1511 return 0;
1512 }
1513
1514 /*
1515 * In the SMP+IOAPIC case it might happen that there are an unspecified
1516 * number of pending IRQ events unhandled. These cases are very rare,
1517 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1518 * better to do it this way as thus we do not have to be aware of
1519 * 'pending' interrupts in the IRQ path, except at this point.
1520 */
1521 /*
1522 * Edge triggered needs to resend any interrupt
1523 * that was delayed but this is now handled in the device
1524 * independent code.
1525 */
1526
1527 /*
1528 * Starting up a edge-triggered IO-APIC interrupt is
1529 * nasty - we need to make sure that we get the edge.
1530 * If it is already asserted for some reason, we need
1531 * return 1 to indicate that is was pending.
1532 *
1533 * This is not complete - we should be able to fake
1534 * an edge even if it isn't on the 8259A...
1535 */
1536
1537 static unsigned int startup_ioapic_irq(unsigned int irq)
1538 {
1539 int was_pending = 0;
1540 unsigned long flags;
1541
1542 spin_lock_irqsave(&ioapic_lock, flags);
1543 if (irq < 16) {
1544 disable_8259A_irq(irq);
1545 if (i8259A_irq_pending(irq))
1546 was_pending = 1;
1547 }
1548 __unmask_IO_APIC_irq(irq);
1549 spin_unlock_irqrestore(&ioapic_lock, flags);
1550
1551 return was_pending;
1552 }
1553
1554 static int ioapic_retrigger_irq(unsigned int irq)
1555 {
1556 struct irq_cfg *cfg = &irq_cfg[irq];
1557 unsigned long flags;
1558
1559 spin_lock_irqsave(&vector_lock, flags);
1560 send_IPI_mask(cpumask_of_cpu(first_cpu(cfg->domain)), cfg->vector);
1561 spin_unlock_irqrestore(&vector_lock, flags);
1562
1563 return 1;
1564 }
1565
1566 /*
1567 * Level and edge triggered IO-APIC interrupts need different handling,
1568 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1569 * handled with the level-triggered descriptor, but that one has slightly
1570 * more overhead. Level-triggered interrupts cannot be handled with the
1571 * edge-triggered handler, without risking IRQ storms and other ugly
1572 * races.
1573 */
1574
1575 #ifdef CONFIG_SMP
1576
1577 #ifdef CONFIG_INTR_REMAP
1578 static void ir_irq_migration(struct work_struct *work);
1579
1580 static DECLARE_DELAYED_WORK(ir_migration_work, ir_irq_migration);
1581
1582 /*
1583 * Migrate the IO-APIC irq in the presence of intr-remapping.
1584 *
1585 * For edge triggered, irq migration is a simple atomic update(of vector
1586 * and cpu destination) of IRTE and flush the hardware cache.
1587 *
1588 * For level triggered, we need to modify the io-apic RTE aswell with the update
1589 * vector information, along with modifying IRTE with vector and destination.
1590 * So irq migration for level triggered is little bit more complex compared to
1591 * edge triggered migration. But the good news is, we use the same algorithm
1592 * for level triggered migration as we have today, only difference being,
1593 * we now initiate the irq migration from process context instead of the
1594 * interrupt context.
1595 *
1596 * In future, when we do a directed EOI (combined with cpu EOI broadcast
1597 * suppression) to the IO-APIC, level triggered irq migration will also be
1598 * as simple as edge triggered migration and we can do the irq migration
1599 * with a simple atomic update to IO-APIC RTE.
1600 */
1601 static void migrate_ioapic_irq(int irq, cpumask_t mask)
1602 {
1603 struct irq_cfg *cfg = irq_cfg + irq;
1604 struct irq_desc *desc;
1605 cpumask_t tmp, cleanup_mask;
1606 struct irte irte;
1607 int modify_ioapic_rte;
1608 unsigned int dest;
1609 unsigned long flags;
1610
1611 cpus_and(tmp, mask, cpu_online_map);
1612 if (cpus_empty(tmp))
1613 return;
1614
1615 if (get_irte(irq, &irte))
1616 return;
1617
1618 if (assign_irq_vector(irq, mask))
1619 return;
1620
1621 cpus_and(tmp, cfg->domain, mask);
1622 dest = cpu_mask_to_apicid(tmp);
1623
1624 desc = irq_to_desc(irq);
1625 modify_ioapic_rte = desc->status & IRQ_LEVEL;
1626 if (modify_ioapic_rte) {
1627 spin_lock_irqsave(&ioapic_lock, flags);
1628 __target_IO_APIC_irq(irq, dest, cfg->vector);
1629 spin_unlock_irqrestore(&ioapic_lock, flags);
1630 }
1631
1632 irte.vector = cfg->vector;
1633 irte.dest_id = IRTE_DEST(dest);
1634
1635 /*
1636 * Modified the IRTE and flushes the Interrupt entry cache.
1637 */
1638 modify_irte(irq, &irte);
1639
1640 if (cfg->move_in_progress) {
1641 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
1642 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
1643 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
1644 cfg->move_in_progress = 0;
1645 }
1646
1647 desc->affinity = mask;
1648 }
1649
1650 static int migrate_irq_remapped_level(int irq)
1651 {
1652 int ret = -1;
1653 struct irq_desc *desc = irq_to_desc(irq);
1654
1655 mask_IO_APIC_irq(irq);
1656
1657 if (io_apic_level_ack_pending(irq)) {
1658 /*
1659 * Interrupt in progress. Migrating irq now will change the
1660 * vector information in the IO-APIC RTE and that will confuse
1661 * the EOI broadcast performed by cpu.
1662 * So, delay the irq migration to the next instance.
1663 */
1664 schedule_delayed_work(&ir_migration_work, 1);
1665 goto unmask;
1666 }
1667
1668 /* everthing is clear. we have right of way */
1669 migrate_ioapic_irq(irq, desc->pending_mask);
1670
1671 ret = 0;
1672 desc->status &= ~IRQ_MOVE_PENDING;
1673 cpus_clear(desc->pending_mask);
1674
1675 unmask:
1676 unmask_IO_APIC_irq(irq);
1677 return ret;
1678 }
1679
1680 static void ir_irq_migration(struct work_struct *work)
1681 {
1682 int irq;
1683
1684 for (irq = 0; irq < nr_irqs; irq++) {
1685 struct irq_desc *desc = irq_to_desc(irq);
1686 if (desc->status & IRQ_MOVE_PENDING) {
1687 unsigned long flags;
1688
1689 spin_lock_irqsave(&desc->lock, flags);
1690 if (!desc->chip->set_affinity ||
1691 !(desc->status & IRQ_MOVE_PENDING)) {
1692 desc->status &= ~IRQ_MOVE_PENDING;
1693 spin_unlock_irqrestore(&desc->lock, flags);
1694 continue;
1695 }
1696
1697 desc->chip->set_affinity(irq, desc->pending_mask);
1698 spin_unlock_irqrestore(&desc->lock, flags);
1699 }
1700 }
1701 }
1702
1703 /*
1704 * Migrates the IRQ destination in the process context.
1705 */
1706 static void set_ir_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
1707 {
1708 struct irq_desc *desc = irq_to_desc(irq);
1709
1710 if (desc->status & IRQ_LEVEL) {
1711 desc->status |= IRQ_MOVE_PENDING;
1712 desc->pending_mask = mask;
1713 migrate_irq_remapped_level(irq);
1714 return;
1715 }
1716
1717 migrate_ioapic_irq(irq, mask);
1718 }
1719 #endif
1720
1721 asmlinkage void smp_irq_move_cleanup_interrupt(void)
1722 {
1723 unsigned vector, me;
1724 ack_APIC_irq();
1725 exit_idle();
1726 irq_enter();
1727
1728 me = smp_processor_id();
1729 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
1730 unsigned int irq;
1731 struct irq_desc *desc;
1732 struct irq_cfg *cfg;
1733 irq = __get_cpu_var(vector_irq)[vector];
1734 if (irq >= nr_irqs)
1735 continue;
1736
1737 desc = irq_to_desc(irq);
1738 cfg = irq_cfg + irq;
1739 spin_lock(&desc->lock);
1740 if (!cfg->move_cleanup_count)
1741 goto unlock;
1742
1743 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain))
1744 goto unlock;
1745
1746 __get_cpu_var(vector_irq)[vector] = -1;
1747 cfg->move_cleanup_count--;
1748 unlock:
1749 spin_unlock(&desc->lock);
1750 }
1751
1752 irq_exit();
1753 }
1754
1755 static void irq_complete_move(unsigned int irq)
1756 {
1757 struct irq_cfg *cfg = irq_cfg + irq;
1758 unsigned vector, me;
1759
1760 if (likely(!cfg->move_in_progress))
1761 return;
1762
1763 vector = ~get_irq_regs()->orig_ax;
1764 me = smp_processor_id();
1765 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain)) {
1766 cpumask_t cleanup_mask;
1767
1768 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
1769 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
1770 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
1771 cfg->move_in_progress = 0;
1772 }
1773 }
1774 #else
1775 static inline void irq_complete_move(unsigned int irq) {}
1776 #endif
1777 #ifdef CONFIG_INTR_REMAP
1778 static void ack_x2apic_level(unsigned int irq)
1779 {
1780 ack_x2APIC_irq();
1781 }
1782
1783 static void ack_x2apic_edge(unsigned int irq)
1784 {
1785 ack_x2APIC_irq();
1786 }
1787 #endif
1788
1789 static void ack_apic_edge(unsigned int irq)
1790 {
1791 irq_complete_move(irq);
1792 move_native_irq(irq);
1793 ack_APIC_irq();
1794 }
1795
1796 static void ack_apic_level(unsigned int irq)
1797 {
1798 int do_unmask_irq = 0;
1799
1800 irq_complete_move(irq);
1801 #ifdef CONFIG_GENERIC_PENDING_IRQ
1802 /* If we are moving the irq we need to mask it */
1803 if (unlikely(irq_to_desc(irq)->status & IRQ_MOVE_PENDING)) {
1804 do_unmask_irq = 1;
1805 mask_IO_APIC_irq(irq);
1806 }
1807 #endif
1808
1809 /*
1810 * We must acknowledge the irq before we move it or the acknowledge will
1811 * not propagate properly.
1812 */
1813 ack_APIC_irq();
1814
1815 /* Now we can move and renable the irq */
1816 if (unlikely(do_unmask_irq)) {
1817 /* Only migrate the irq if the ack has been received.
1818 *
1819 * On rare occasions the broadcast level triggered ack gets
1820 * delayed going to ioapics, and if we reprogram the
1821 * vector while Remote IRR is still set the irq will never
1822 * fire again.
1823 *
1824 * To prevent this scenario we read the Remote IRR bit
1825 * of the ioapic. This has two effects.
1826 * - On any sane system the read of the ioapic will
1827 * flush writes (and acks) going to the ioapic from
1828 * this cpu.
1829 * - We get to see if the ACK has actually been delivered.
1830 *
1831 * Based on failed experiments of reprogramming the
1832 * ioapic entry from outside of irq context starting
1833 * with masking the ioapic entry and then polling until
1834 * Remote IRR was clear before reprogramming the
1835 * ioapic I don't trust the Remote IRR bit to be
1836 * completey accurate.
1837 *
1838 * However there appears to be no other way to plug
1839 * this race, so if the Remote IRR bit is not
1840 * accurate and is causing problems then it is a hardware bug
1841 * and you can go talk to the chipset vendor about it.
1842 */
1843 if (!io_apic_level_ack_pending(irq))
1844 move_masked_irq(irq);
1845 unmask_IO_APIC_irq(irq);
1846 }
1847 }
1848
1849 static struct irq_chip ioapic_chip __read_mostly = {
1850 .name = "IO-APIC",
1851 .startup = startup_ioapic_irq,
1852 .mask = mask_IO_APIC_irq,
1853 .unmask = unmask_IO_APIC_irq,
1854 .ack = ack_apic_edge,
1855 .eoi = ack_apic_level,
1856 #ifdef CONFIG_SMP
1857 .set_affinity = set_ioapic_affinity_irq,
1858 #endif
1859 .retrigger = ioapic_retrigger_irq,
1860 };
1861
1862 #ifdef CONFIG_INTR_REMAP
1863 static struct irq_chip ir_ioapic_chip __read_mostly = {
1864 .name = "IR-IO-APIC",
1865 .startup = startup_ioapic_irq,
1866 .mask = mask_IO_APIC_irq,
1867 .unmask = unmask_IO_APIC_irq,
1868 .ack = ack_x2apic_edge,
1869 .eoi = ack_x2apic_level,
1870 #ifdef CONFIG_SMP
1871 .set_affinity = set_ir_ioapic_affinity_irq,
1872 #endif
1873 .retrigger = ioapic_retrigger_irq,
1874 };
1875 #endif
1876
1877 static inline void init_IO_APIC_traps(void)
1878 {
1879 int irq;
1880 struct irq_desc *desc;
1881
1882 /*
1883 * NOTE! The local APIC isn't very good at handling
1884 * multiple interrupts at the same interrupt level.
1885 * As the interrupt level is determined by taking the
1886 * vector number and shifting that right by 4, we
1887 * want to spread these out a bit so that they don't
1888 * all fall in the same interrupt level.
1889 *
1890 * Also, we've got to be careful not to trash gate
1891 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1892 */
1893 for (irq = 0; irq < nr_irqs ; irq++) {
1894 if (IO_APIC_IRQ(irq) && !irq_cfg[irq].vector) {
1895 /*
1896 * Hmm.. We don't have an entry for this,
1897 * so default to an old-fashioned 8259
1898 * interrupt if we can..
1899 */
1900 if (irq < 16)
1901 make_8259A_irq(irq);
1902 else {
1903 desc = irq_to_desc(irq);
1904 /* Strange. Oh, well.. */
1905 desc->chip = &no_irq_chip;
1906 }
1907 }
1908 }
1909 }
1910
1911 static void unmask_lapic_irq(unsigned int irq)
1912 {
1913 unsigned long v;
1914
1915 v = apic_read(APIC_LVT0);
1916 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1917 }
1918
1919 static void mask_lapic_irq(unsigned int irq)
1920 {
1921 unsigned long v;
1922
1923 v = apic_read(APIC_LVT0);
1924 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1925 }
1926
1927 static void ack_lapic_irq (unsigned int irq)
1928 {
1929 ack_APIC_irq();
1930 }
1931
1932 static struct irq_chip lapic_chip __read_mostly = {
1933 .name = "local-APIC",
1934 .mask = mask_lapic_irq,
1935 .unmask = unmask_lapic_irq,
1936 .ack = ack_lapic_irq,
1937 };
1938
1939 static void lapic_register_intr(int irq)
1940 {
1941 struct irq_desc *desc;
1942
1943 desc = irq_to_desc(irq);
1944 desc->status &= ~IRQ_LEVEL;
1945 set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
1946 "edge");
1947 }
1948
1949 static void __init setup_nmi(void)
1950 {
1951 /*
1952 * Dirty trick to enable the NMI watchdog ...
1953 * We put the 8259A master into AEOI mode and
1954 * unmask on all local APICs LVT0 as NMI.
1955 *
1956 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1957 * is from Maciej W. Rozycki - so we do not have to EOI from
1958 * the NMI handler or the timer interrupt.
1959 */
1960 printk(KERN_INFO "activating NMI Watchdog ...");
1961
1962 enable_NMI_through_LVT0();
1963
1964 printk(" done.\n");
1965 }
1966
1967 /*
1968 * This looks a bit hackish but it's about the only one way of sending
1969 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1970 * not support the ExtINT mode, unfortunately. We need to send these
1971 * cycles as some i82489DX-based boards have glue logic that keeps the
1972 * 8259A interrupt line asserted until INTA. --macro
1973 */
1974 static inline void __init unlock_ExtINT_logic(void)
1975 {
1976 int apic, pin, i;
1977 struct IO_APIC_route_entry entry0, entry1;
1978 unsigned char save_control, save_freq_select;
1979
1980 pin = find_isa_irq_pin(8, mp_INT);
1981 apic = find_isa_irq_apic(8, mp_INT);
1982 if (pin == -1)
1983 return;
1984
1985 entry0 = ioapic_read_entry(apic, pin);
1986
1987 clear_IO_APIC_pin(apic, pin);
1988
1989 memset(&entry1, 0, sizeof(entry1));
1990
1991 entry1.dest_mode = 0; /* physical delivery */
1992 entry1.mask = 0; /* unmask IRQ now */
1993 entry1.dest = hard_smp_processor_id();
1994 entry1.delivery_mode = dest_ExtINT;
1995 entry1.polarity = entry0.polarity;
1996 entry1.trigger = 0;
1997 entry1.vector = 0;
1998
1999 ioapic_write_entry(apic, pin, entry1);
2000
2001 save_control = CMOS_READ(RTC_CONTROL);
2002 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2003 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2004 RTC_FREQ_SELECT);
2005 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2006
2007 i = 100;
2008 while (i-- > 0) {
2009 mdelay(10);
2010 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2011 i -= 10;
2012 }
2013
2014 CMOS_WRITE(save_control, RTC_CONTROL);
2015 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2016 clear_IO_APIC_pin(apic, pin);
2017
2018 ioapic_write_entry(apic, pin, entry0);
2019 }
2020
2021 /*
2022 * This code may look a bit paranoid, but it's supposed to cooperate with
2023 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2024 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2025 * fanatically on his truly buggy board.
2026 *
2027 * FIXME: really need to revamp this for modern platforms only.
2028 */
2029 static inline void __init check_timer(void)
2030 {
2031 struct irq_cfg *cfg = irq_cfg + 0;
2032 int apic1, pin1, apic2, pin2;
2033 unsigned long flags;
2034 int no_pin1 = 0;
2035
2036 local_irq_save(flags);
2037
2038 /*
2039 * get/set the timer IRQ vector:
2040 */
2041 disable_8259A_irq(0);
2042 assign_irq_vector(0, TARGET_CPUS);
2043
2044 /*
2045 * As IRQ0 is to be enabled in the 8259A, the virtual
2046 * wire has to be disabled in the local APIC.
2047 */
2048 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2049 init_8259A(1);
2050
2051 pin1 = find_isa_irq_pin(0, mp_INT);
2052 apic1 = find_isa_irq_apic(0, mp_INT);
2053 pin2 = ioapic_i8259.pin;
2054 apic2 = ioapic_i8259.apic;
2055
2056 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2057 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2058 cfg->vector, apic1, pin1, apic2, pin2);
2059
2060 /*
2061 * Some BIOS writers are clueless and report the ExtINTA
2062 * I/O APIC input from the cascaded 8259A as the timer
2063 * interrupt input. So just in case, if only one pin
2064 * was found above, try it both directly and through the
2065 * 8259A.
2066 */
2067 if (pin1 == -1) {
2068 if (intr_remapping_enabled)
2069 panic("BIOS bug: timer not connected to IO-APIC");
2070 pin1 = pin2;
2071 apic1 = apic2;
2072 no_pin1 = 1;
2073 } else if (pin2 == -1) {
2074 pin2 = pin1;
2075 apic2 = apic1;
2076 }
2077
2078 if (pin1 != -1) {
2079 /*
2080 * Ok, does IRQ0 through the IOAPIC work?
2081 */
2082 if (no_pin1) {
2083 add_pin_to_irq(0, apic1, pin1);
2084 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2085 }
2086 unmask_IO_APIC_irq(0);
2087 if (!no_timer_check && timer_irq_works()) {
2088 if (nmi_watchdog == NMI_IO_APIC) {
2089 setup_nmi();
2090 enable_8259A_irq(0);
2091 }
2092 if (disable_timer_pin_1 > 0)
2093 clear_IO_APIC_pin(0, pin1);
2094 goto out;
2095 }
2096 if (intr_remapping_enabled)
2097 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2098 clear_IO_APIC_pin(apic1, pin1);
2099 if (!no_pin1)
2100 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2101 "8254 timer not connected to IO-APIC\n");
2102
2103 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2104 "(IRQ0) through the 8259A ...\n");
2105 apic_printk(APIC_QUIET, KERN_INFO
2106 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2107 /*
2108 * legacy devices should be connected to IO APIC #0
2109 */
2110 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
2111 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
2112 unmask_IO_APIC_irq(0);
2113 enable_8259A_irq(0);
2114 if (timer_irq_works()) {
2115 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2116 timer_through_8259 = 1;
2117 if (nmi_watchdog == NMI_IO_APIC) {
2118 disable_8259A_irq(0);
2119 setup_nmi();
2120 enable_8259A_irq(0);
2121 }
2122 goto out;
2123 }
2124 /*
2125 * Cleanup, just in case ...
2126 */
2127 disable_8259A_irq(0);
2128 clear_IO_APIC_pin(apic2, pin2);
2129 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2130 }
2131
2132 if (nmi_watchdog == NMI_IO_APIC) {
2133 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
2134 "through the IO-APIC - disabling NMI Watchdog!\n");
2135 nmi_watchdog = NMI_NONE;
2136 }
2137
2138 apic_printk(APIC_QUIET, KERN_INFO
2139 "...trying to set up timer as Virtual Wire IRQ...\n");
2140
2141 lapic_register_intr(0);
2142 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
2143 enable_8259A_irq(0);
2144
2145 if (timer_irq_works()) {
2146 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2147 goto out;
2148 }
2149 disable_8259A_irq(0);
2150 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
2151 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
2152
2153 apic_printk(APIC_QUIET, KERN_INFO
2154 "...trying to set up timer as ExtINT IRQ...\n");
2155
2156 init_8259A(0);
2157 make_8259A_irq(0);
2158 apic_write(APIC_LVT0, APIC_DM_EXTINT);
2159
2160 unlock_ExtINT_logic();
2161
2162 if (timer_irq_works()) {
2163 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2164 goto out;
2165 }
2166 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
2167 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2168 "report. Then try booting with the 'noapic' option.\n");
2169 out:
2170 local_irq_restore(flags);
2171 }
2172
2173 static int __init notimercheck(char *s)
2174 {
2175 no_timer_check = 1;
2176 return 1;
2177 }
2178 __setup("no_timer_check", notimercheck);
2179
2180 /*
2181 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2182 * to devices. However there may be an I/O APIC pin available for
2183 * this interrupt regardless. The pin may be left unconnected, but
2184 * typically it will be reused as an ExtINT cascade interrupt for
2185 * the master 8259A. In the MPS case such a pin will normally be
2186 * reported as an ExtINT interrupt in the MP table. With ACPI
2187 * there is no provision for ExtINT interrupts, and in the absence
2188 * of an override it would be treated as an ordinary ISA I/O APIC
2189 * interrupt, that is edge-triggered and unmasked by default. We
2190 * used to do this, but it caused problems on some systems because
2191 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2192 * the same ExtINT cascade interrupt to drive the local APIC of the
2193 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2194 * the I/O APIC in all cases now. No actual device should request
2195 * it anyway. --macro
2196 */
2197 #define PIC_IRQS (1<<2)
2198
2199 void __init setup_IO_APIC(void)
2200 {
2201
2202 /*
2203 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
2204 */
2205
2206 io_apic_irqs = ~PIC_IRQS;
2207
2208 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
2209
2210 sync_Arb_IDs();
2211 setup_IO_APIC_irqs();
2212 init_IO_APIC_traps();
2213 check_timer();
2214 }
2215
2216 struct sysfs_ioapic_data {
2217 struct sys_device dev;
2218 struct IO_APIC_route_entry entry[0];
2219 };
2220 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2221
2222 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2223 {
2224 struct IO_APIC_route_entry *entry;
2225 struct sysfs_ioapic_data *data;
2226 int i;
2227
2228 data = container_of(dev, struct sysfs_ioapic_data, dev);
2229 entry = data->entry;
2230 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
2231 *entry = ioapic_read_entry(dev->id, i);
2232
2233 return 0;
2234 }
2235
2236 static int ioapic_resume(struct sys_device *dev)
2237 {
2238 struct IO_APIC_route_entry *entry;
2239 struct sysfs_ioapic_data *data;
2240 unsigned long flags;
2241 union IO_APIC_reg_00 reg_00;
2242 int i;
2243
2244 data = container_of(dev, struct sysfs_ioapic_data, dev);
2245 entry = data->entry;
2246
2247 spin_lock_irqsave(&ioapic_lock, flags);
2248 reg_00.raw = io_apic_read(dev->id, 0);
2249 if (reg_00.bits.ID != mp_ioapics[dev->id].mp_apicid) {
2250 reg_00.bits.ID = mp_ioapics[dev->id].mp_apicid;
2251 io_apic_write(dev->id, 0, reg_00.raw);
2252 }
2253 spin_unlock_irqrestore(&ioapic_lock, flags);
2254 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
2255 ioapic_write_entry(dev->id, i, entry[i]);
2256
2257 return 0;
2258 }
2259
2260 static struct sysdev_class ioapic_sysdev_class = {
2261 .name = "ioapic",
2262 .suspend = ioapic_suspend,
2263 .resume = ioapic_resume,
2264 };
2265
2266 static int __init ioapic_init_sysfs(void)
2267 {
2268 struct sys_device * dev;
2269 int i, size, error;
2270
2271 error = sysdev_class_register(&ioapic_sysdev_class);
2272 if (error)
2273 return error;
2274
2275 for (i = 0; i < nr_ioapics; i++ ) {
2276 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2277 * sizeof(struct IO_APIC_route_entry);
2278 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
2279 if (!mp_ioapic_data[i]) {
2280 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2281 continue;
2282 }
2283 dev = &mp_ioapic_data[i]->dev;
2284 dev->id = i;
2285 dev->cls = &ioapic_sysdev_class;
2286 error = sysdev_register(dev);
2287 if (error) {
2288 kfree(mp_ioapic_data[i]);
2289 mp_ioapic_data[i] = NULL;
2290 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2291 continue;
2292 }
2293 }
2294
2295 return 0;
2296 }
2297
2298 device_initcall(ioapic_init_sysfs);
2299
2300 /*
2301 * Dynamic irq allocate and deallocation
2302 */
2303 int create_irq(void)
2304 {
2305 /* Allocate an unused irq */
2306 int irq;
2307 int new;
2308 unsigned long flags;
2309
2310 irq = -ENOSPC;
2311 spin_lock_irqsave(&vector_lock, flags);
2312 for (new = (nr_irqs - 1); new >= 0; new--) {
2313 if (platform_legacy_irq(new))
2314 continue;
2315 if (irq_cfg[new].vector != 0)
2316 continue;
2317 if (__assign_irq_vector(new, TARGET_CPUS) == 0)
2318 irq = new;
2319 break;
2320 }
2321 spin_unlock_irqrestore(&vector_lock, flags);
2322
2323 if (irq >= 0) {
2324 dynamic_irq_init(irq);
2325 }
2326 return irq;
2327 }
2328
2329 void destroy_irq(unsigned int irq)
2330 {
2331 unsigned long flags;
2332
2333 dynamic_irq_cleanup(irq);
2334
2335 #ifdef CONFIG_INTR_REMAP
2336 free_irte(irq);
2337 #endif
2338 spin_lock_irqsave(&vector_lock, flags);
2339 __clear_irq_vector(irq);
2340 spin_unlock_irqrestore(&vector_lock, flags);
2341 }
2342
2343 /*
2344 * MSI message composition
2345 */
2346 #ifdef CONFIG_PCI_MSI
2347 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
2348 {
2349 struct irq_cfg *cfg = irq_cfg + irq;
2350 int err;
2351 unsigned dest;
2352 cpumask_t tmp;
2353
2354 tmp = TARGET_CPUS;
2355 err = assign_irq_vector(irq, tmp);
2356 if (err)
2357 return err;
2358
2359 cpus_and(tmp, cfg->domain, tmp);
2360 dest = cpu_mask_to_apicid(tmp);
2361
2362 #ifdef CONFIG_INTR_REMAP
2363 if (irq_remapped(irq)) {
2364 struct irte irte;
2365 int ir_index;
2366 u16 sub_handle;
2367
2368 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
2369 BUG_ON(ir_index == -1);
2370
2371 memset (&irte, 0, sizeof(irte));
2372
2373 irte.present = 1;
2374 irte.dst_mode = INT_DEST_MODE;
2375 irte.trigger_mode = 0; /* edge */
2376 irte.dlvry_mode = INT_DELIVERY_MODE;
2377 irte.vector = cfg->vector;
2378 irte.dest_id = IRTE_DEST(dest);
2379
2380 modify_irte(irq, &irte);
2381
2382 msg->address_hi = MSI_ADDR_BASE_HI;
2383 msg->data = sub_handle;
2384 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
2385 MSI_ADDR_IR_SHV |
2386 MSI_ADDR_IR_INDEX1(ir_index) |
2387 MSI_ADDR_IR_INDEX2(ir_index);
2388 } else
2389 #endif
2390 {
2391 msg->address_hi = MSI_ADDR_BASE_HI;
2392 msg->address_lo =
2393 MSI_ADDR_BASE_LO |
2394 ((INT_DEST_MODE == 0) ?
2395 MSI_ADDR_DEST_MODE_PHYSICAL:
2396 MSI_ADDR_DEST_MODE_LOGICAL) |
2397 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2398 MSI_ADDR_REDIRECTION_CPU:
2399 MSI_ADDR_REDIRECTION_LOWPRI) |
2400 MSI_ADDR_DEST_ID(dest);
2401
2402 msg->data =
2403 MSI_DATA_TRIGGER_EDGE |
2404 MSI_DATA_LEVEL_ASSERT |
2405 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2406 MSI_DATA_DELIVERY_FIXED:
2407 MSI_DATA_DELIVERY_LOWPRI) |
2408 MSI_DATA_VECTOR(cfg->vector);
2409 }
2410 return err;
2411 }
2412
2413 #ifdef CONFIG_SMP
2414 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
2415 {
2416 struct irq_cfg *cfg = irq_cfg + irq;
2417 struct msi_msg msg;
2418 unsigned int dest;
2419 cpumask_t tmp;
2420 struct irq_desc *desc;
2421
2422 cpus_and(tmp, mask, cpu_online_map);
2423 if (cpus_empty(tmp))
2424 return;
2425
2426 if (assign_irq_vector(irq, mask))
2427 return;
2428
2429 cpus_and(tmp, cfg->domain, mask);
2430 dest = cpu_mask_to_apicid(tmp);
2431
2432 read_msi_msg(irq, &msg);
2433
2434 msg.data &= ~MSI_DATA_VECTOR_MASK;
2435 msg.data |= MSI_DATA_VECTOR(cfg->vector);
2436 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2437 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2438
2439 write_msi_msg(irq, &msg);
2440 desc = irq_to_desc(irq);
2441 desc->affinity = mask;
2442 }
2443
2444 #ifdef CONFIG_INTR_REMAP
2445 /*
2446 * Migrate the MSI irq to another cpumask. This migration is
2447 * done in the process context using interrupt-remapping hardware.
2448 */
2449 static void ir_set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
2450 {
2451 struct irq_cfg *cfg = irq_cfg + irq;
2452 unsigned int dest;
2453 cpumask_t tmp, cleanup_mask;
2454 struct irte irte;
2455 struct irq_desc *desc;
2456
2457 cpus_and(tmp, mask, cpu_online_map);
2458 if (cpus_empty(tmp))
2459 return;
2460
2461 if (get_irte(irq, &irte))
2462 return;
2463
2464 if (assign_irq_vector(irq, mask))
2465 return;
2466
2467 cpus_and(tmp, cfg->domain, mask);
2468 dest = cpu_mask_to_apicid(tmp);
2469
2470 irte.vector = cfg->vector;
2471 irte.dest_id = IRTE_DEST(dest);
2472
2473 /*
2474 * atomically update the IRTE with the new destination and vector.
2475 */
2476 modify_irte(irq, &irte);
2477
2478 /*
2479 * After this point, all the interrupts will start arriving
2480 * at the new destination. So, time to cleanup the previous
2481 * vector allocation.
2482 */
2483 if (cfg->move_in_progress) {
2484 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
2485 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
2486 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2487 cfg->move_in_progress = 0;
2488 }
2489
2490 desc = irq_to_desc(irq);
2491 desc->affinity = mask;
2492 }
2493 #endif
2494 #endif /* CONFIG_SMP */
2495
2496 /*
2497 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2498 * which implement the MSI or MSI-X Capability Structure.
2499 */
2500 static struct irq_chip msi_chip = {
2501 .name = "PCI-MSI",
2502 .unmask = unmask_msi_irq,
2503 .mask = mask_msi_irq,
2504 .ack = ack_apic_edge,
2505 #ifdef CONFIG_SMP
2506 .set_affinity = set_msi_irq_affinity,
2507 #endif
2508 .retrigger = ioapic_retrigger_irq,
2509 };
2510
2511 #ifdef CONFIG_INTR_REMAP
2512 static struct irq_chip msi_ir_chip = {
2513 .name = "IR-PCI-MSI",
2514 .unmask = unmask_msi_irq,
2515 .mask = mask_msi_irq,
2516 .ack = ack_x2apic_edge,
2517 #ifdef CONFIG_SMP
2518 .set_affinity = ir_set_msi_irq_affinity,
2519 #endif
2520 .retrigger = ioapic_retrigger_irq,
2521 };
2522
2523 /*
2524 * Map the PCI dev to the corresponding remapping hardware unit
2525 * and allocate 'nvec' consecutive interrupt-remapping table entries
2526 * in it.
2527 */
2528 static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
2529 {
2530 struct intel_iommu *iommu;
2531 int index;
2532
2533 iommu = map_dev_to_ir(dev);
2534 if (!iommu) {
2535 printk(KERN_ERR
2536 "Unable to map PCI %s to iommu\n", pci_name(dev));
2537 return -ENOENT;
2538 }
2539
2540 index = alloc_irte(iommu, irq, nvec);
2541 if (index < 0) {
2542 printk(KERN_ERR
2543 "Unable to allocate %d IRTE for PCI %s\n", nvec,
2544 pci_name(dev));
2545 return -ENOSPC;
2546 }
2547 return index;
2548 }
2549 #endif
2550
2551 static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc, int irq)
2552 {
2553 int ret;
2554 struct msi_msg msg;
2555
2556 ret = msi_compose_msg(dev, irq, &msg);
2557 if (ret < 0)
2558 return ret;
2559
2560 set_irq_msi(irq, desc);
2561 write_msi_msg(irq, &msg);
2562
2563 #ifdef CONFIG_INTR_REMAP
2564 if (irq_remapped(irq)) {
2565 struct irq_desc *desc = irq_to_desc(irq);
2566 /*
2567 * irq migration in process context
2568 */
2569 desc->status |= IRQ_MOVE_PCNTXT;
2570 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
2571 } else
2572 #endif
2573 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
2574
2575 return 0;
2576 }
2577
2578 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
2579 {
2580 int irq, ret;
2581
2582 irq = create_irq();
2583 if (irq < 0)
2584 return irq;
2585
2586 #ifdef CONFIG_INTR_REMAP
2587 if (!intr_remapping_enabled)
2588 goto no_ir;
2589
2590 ret = msi_alloc_irte(dev, irq, 1);
2591 if (ret < 0)
2592 goto error;
2593 no_ir:
2594 #endif
2595 ret = setup_msi_irq(dev, desc, irq);
2596 if (ret < 0) {
2597 destroy_irq(irq);
2598 return ret;
2599 }
2600 return 0;
2601
2602 #ifdef CONFIG_INTR_REMAP
2603 error:
2604 destroy_irq(irq);
2605 return ret;
2606 #endif
2607 }
2608
2609 int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
2610 {
2611 int irq, ret, sub_handle;
2612 struct msi_desc *desc;
2613 #ifdef CONFIG_INTR_REMAP
2614 struct intel_iommu *iommu = 0;
2615 int index = 0;
2616 #endif
2617
2618 sub_handle = 0;
2619 list_for_each_entry(desc, &dev->msi_list, list) {
2620 irq = create_irq();
2621 if (irq < 0)
2622 return irq;
2623 #ifdef CONFIG_INTR_REMAP
2624 if (!intr_remapping_enabled)
2625 goto no_ir;
2626
2627 if (!sub_handle) {
2628 /*
2629 * allocate the consecutive block of IRTE's
2630 * for 'nvec'
2631 */
2632 index = msi_alloc_irte(dev, irq, nvec);
2633 if (index < 0) {
2634 ret = index;
2635 goto error;
2636 }
2637 } else {
2638 iommu = map_dev_to_ir(dev);
2639 if (!iommu) {
2640 ret = -ENOENT;
2641 goto error;
2642 }
2643 /*
2644 * setup the mapping between the irq and the IRTE
2645 * base index, the sub_handle pointing to the
2646 * appropriate interrupt remap table entry.
2647 */
2648 set_irte_irq(irq, iommu, index, sub_handle);
2649 }
2650 no_ir:
2651 #endif
2652 ret = setup_msi_irq(dev, desc, irq);
2653 if (ret < 0)
2654 goto error;
2655 sub_handle++;
2656 }
2657 return 0;
2658
2659 error:
2660 destroy_irq(irq);
2661 return ret;
2662 }
2663
2664 void arch_teardown_msi_irq(unsigned int irq)
2665 {
2666 destroy_irq(irq);
2667 }
2668
2669 #ifdef CONFIG_DMAR
2670 #ifdef CONFIG_SMP
2671 static void dmar_msi_set_affinity(unsigned int irq, cpumask_t mask)
2672 {
2673 struct irq_cfg *cfg = irq_cfg + irq;
2674 struct msi_msg msg;
2675 unsigned int dest;
2676 cpumask_t tmp;
2677 struct irq_desc *desc;
2678
2679 cpus_and(tmp, mask, cpu_online_map);
2680 if (cpus_empty(tmp))
2681 return;
2682
2683 if (assign_irq_vector(irq, mask))
2684 return;
2685
2686 cpus_and(tmp, cfg->domain, mask);
2687 dest = cpu_mask_to_apicid(tmp);
2688
2689 dmar_msi_read(irq, &msg);
2690
2691 msg.data &= ~MSI_DATA_VECTOR_MASK;
2692 msg.data |= MSI_DATA_VECTOR(cfg->vector);
2693 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2694 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2695
2696 dmar_msi_write(irq, &msg);
2697 desc = irq_to_desc(irq);
2698 desc->affinity = mask;
2699 }
2700 #endif /* CONFIG_SMP */
2701
2702 struct irq_chip dmar_msi_type = {
2703 .name = "DMAR_MSI",
2704 .unmask = dmar_msi_unmask,
2705 .mask = dmar_msi_mask,
2706 .ack = ack_apic_edge,
2707 #ifdef CONFIG_SMP
2708 .set_affinity = dmar_msi_set_affinity,
2709 #endif
2710 .retrigger = ioapic_retrigger_irq,
2711 };
2712
2713 int arch_setup_dmar_msi(unsigned int irq)
2714 {
2715 int ret;
2716 struct msi_msg msg;
2717
2718 ret = msi_compose_msg(NULL, irq, &msg);
2719 if (ret < 0)
2720 return ret;
2721 dmar_msi_write(irq, &msg);
2722 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
2723 "edge");
2724 return 0;
2725 }
2726 #endif
2727
2728 #endif /* CONFIG_PCI_MSI */
2729 /*
2730 * Hypertransport interrupt support
2731 */
2732 #ifdef CONFIG_HT_IRQ
2733
2734 #ifdef CONFIG_SMP
2735
2736 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
2737 {
2738 struct ht_irq_msg msg;
2739 fetch_ht_irq_msg(irq, &msg);
2740
2741 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
2742 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
2743
2744 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
2745 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
2746
2747 write_ht_irq_msg(irq, &msg);
2748 }
2749
2750 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
2751 {
2752 struct irq_cfg *cfg = irq_cfg + irq;
2753 unsigned int dest;
2754 cpumask_t tmp;
2755 struct irq_desc *desc;
2756
2757 cpus_and(tmp, mask, cpu_online_map);
2758 if (cpus_empty(tmp))
2759 return;
2760
2761 if (assign_irq_vector(irq, mask))
2762 return;
2763
2764 cpus_and(tmp, cfg->domain, mask);
2765 dest = cpu_mask_to_apicid(tmp);
2766
2767 target_ht_irq(irq, dest, cfg->vector);
2768 desc = irq_to_desc(irq);
2769 desc->affinity = mask;
2770 }
2771 #endif
2772
2773 static struct irq_chip ht_irq_chip = {
2774 .name = "PCI-HT",
2775 .mask = mask_ht_irq,
2776 .unmask = unmask_ht_irq,
2777 .ack = ack_apic_edge,
2778 #ifdef CONFIG_SMP
2779 .set_affinity = set_ht_irq_affinity,
2780 #endif
2781 .retrigger = ioapic_retrigger_irq,
2782 };
2783
2784 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2785 {
2786 struct irq_cfg *cfg = irq_cfg + irq;
2787 int err;
2788 cpumask_t tmp;
2789
2790 tmp = TARGET_CPUS;
2791 err = assign_irq_vector(irq, tmp);
2792 if (!err) {
2793 struct ht_irq_msg msg;
2794 unsigned dest;
2795
2796 cpus_and(tmp, cfg->domain, tmp);
2797 dest = cpu_mask_to_apicid(tmp);
2798
2799 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
2800
2801 msg.address_lo =
2802 HT_IRQ_LOW_BASE |
2803 HT_IRQ_LOW_DEST_ID(dest) |
2804 HT_IRQ_LOW_VECTOR(cfg->vector) |
2805 ((INT_DEST_MODE == 0) ?
2806 HT_IRQ_LOW_DM_PHYSICAL :
2807 HT_IRQ_LOW_DM_LOGICAL) |
2808 HT_IRQ_LOW_RQEOI_EDGE |
2809 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2810 HT_IRQ_LOW_MT_FIXED :
2811 HT_IRQ_LOW_MT_ARBITRATED) |
2812 HT_IRQ_LOW_IRQ_MASKED;
2813
2814 write_ht_irq_msg(irq, &msg);
2815
2816 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2817 handle_edge_irq, "edge");
2818 }
2819 return err;
2820 }
2821 #endif /* CONFIG_HT_IRQ */
2822
2823 /* --------------------------------------------------------------------------
2824 ACPI-based IOAPIC Configuration
2825 -------------------------------------------------------------------------- */
2826
2827 #ifdef CONFIG_ACPI
2828
2829 #define IO_APIC_MAX_ID 0xFE
2830
2831 int __init io_apic_get_redir_entries (int ioapic)
2832 {
2833 union IO_APIC_reg_01 reg_01;
2834 unsigned long flags;
2835
2836 spin_lock_irqsave(&ioapic_lock, flags);
2837 reg_01.raw = io_apic_read(ioapic, 1);
2838 spin_unlock_irqrestore(&ioapic_lock, flags);
2839
2840 return reg_01.bits.entries;
2841 }
2842
2843
2844 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
2845 {
2846 if (!IO_APIC_IRQ(irq)) {
2847 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2848 ioapic);
2849 return -EINVAL;
2850 }
2851
2852 /*
2853 * IRQs < 16 are already in the irq_2_pin[] map
2854 */
2855 if (irq >= 16)
2856 add_pin_to_irq(irq, ioapic, pin);
2857
2858 setup_IO_APIC_irq(ioapic, pin, irq, triggering, polarity);
2859
2860 return 0;
2861 }
2862
2863
2864 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
2865 {
2866 int i;
2867
2868 if (skip_ioapic_setup)
2869 return -1;
2870
2871 for (i = 0; i < mp_irq_entries; i++)
2872 if (mp_irqs[i].mp_irqtype == mp_INT &&
2873 mp_irqs[i].mp_srcbusirq == bus_irq)
2874 break;
2875 if (i >= mp_irq_entries)
2876 return -1;
2877
2878 *trigger = irq_trigger(i);
2879 *polarity = irq_polarity(i);
2880 return 0;
2881 }
2882
2883 #endif /* CONFIG_ACPI */
2884
2885 /*
2886 * This function currently is only a helper for the i386 smp boot process where
2887 * we need to reprogram the ioredtbls to cater for the cpus which have come online
2888 * so mask in all cases should simply be TARGET_CPUS
2889 */
2890 #ifdef CONFIG_SMP
2891 void __init setup_ioapic_dest(void)
2892 {
2893 int pin, ioapic, irq, irq_entry;
2894
2895 if (skip_ioapic_setup == 1)
2896 return;
2897
2898 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
2899 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
2900 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2901 if (irq_entry == -1)
2902 continue;
2903 irq = pin_2_irq(irq_entry, ioapic, pin);
2904
2905 /* setup_IO_APIC_irqs could fail to get vector for some device
2906 * when you have too many devices, because at that time only boot
2907 * cpu is online.
2908 */
2909 if (!irq_cfg[irq].vector)
2910 setup_IO_APIC_irq(ioapic, pin, irq,
2911 irq_trigger(irq_entry),
2912 irq_polarity(irq_entry));
2913 #ifdef CONFIG_INTR_REMAP
2914 else if (intr_remapping_enabled)
2915 set_ir_ioapic_affinity_irq(irq, TARGET_CPUS);
2916 #endif
2917 else
2918 set_ioapic_affinity_irq(irq, TARGET_CPUS);
2919 }
2920
2921 }
2922 }
2923 #endif
2924
2925 #define IOAPIC_RESOURCE_NAME_SIZE 11
2926
2927 static struct resource *ioapic_resources;
2928
2929 static struct resource * __init ioapic_setup_resources(void)
2930 {
2931 unsigned long n;
2932 struct resource *res;
2933 char *mem;
2934 int i;
2935
2936 if (nr_ioapics <= 0)
2937 return NULL;
2938
2939 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
2940 n *= nr_ioapics;
2941
2942 mem = alloc_bootmem(n);
2943 res = (void *)mem;
2944
2945 if (mem != NULL) {
2946 mem += sizeof(struct resource) * nr_ioapics;
2947
2948 for (i = 0; i < nr_ioapics; i++) {
2949 res[i].name = mem;
2950 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
2951 sprintf(mem, "IOAPIC %u", i);
2952 mem += IOAPIC_RESOURCE_NAME_SIZE;
2953 }
2954 }
2955
2956 ioapic_resources = res;
2957
2958 return res;
2959 }
2960
2961 void __init ioapic_init_mappings(void)
2962 {
2963 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
2964 struct resource *ioapic_res;
2965 int i;
2966
2967 ioapic_res = ioapic_setup_resources();
2968 for (i = 0; i < nr_ioapics; i++) {
2969 if (smp_found_config) {
2970 ioapic_phys = mp_ioapics[i].mp_apicaddr;
2971 } else {
2972 ioapic_phys = (unsigned long)
2973 alloc_bootmem_pages(PAGE_SIZE);
2974 ioapic_phys = __pa(ioapic_phys);
2975 }
2976 set_fixmap_nocache(idx, ioapic_phys);
2977 apic_printk(APIC_VERBOSE,
2978 "mapped IOAPIC to %016lx (%016lx)\n",
2979 __fix_to_virt(idx), ioapic_phys);
2980 idx++;
2981
2982 if (ioapic_res != NULL) {
2983 ioapic_res->start = ioapic_phys;
2984 ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
2985 ioapic_res++;
2986 }
2987 }
2988 }
2989
2990 static int __init ioapic_insert_resources(void)
2991 {
2992 int i;
2993 struct resource *r = ioapic_resources;
2994
2995 if (!r) {
2996 printk(KERN_ERR
2997 "IO APIC resources could be not be allocated.\n");
2998 return -1;
2999 }
3000
3001 for (i = 0; i < nr_ioapics; i++) {
3002 insert_resource(&iomem_resource, r);
3003 r++;
3004 }
3005
3006 return 0;
3007 }
3008
3009 /* Insert the IO APIC resources after PCI initialization has occured to handle
3010 * IO APICS that are mapped in on a BAR in PCI space. */
3011 late_initcall(ioapic_insert_resources);
3012
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