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ata/sata_fsl: remove unneeded sata_fsl_hardreset()
[linux-2.6/verdex.git] / drivers / ata / sata_fsl.c
blob03629b687de47b13254dfa803149f8436c18f851
1 /*
2 * drivers/ata/sata_fsl.c
3 *
4 * Freescale 3.0Gbps SATA device driver
5 *
6 * Author: Ashish Kalra <ashish.kalra@freescale.com>
7 * Li Yang <leoli@freescale.com>
8 *
9 * Copyright (c) 2006-2007 Freescale Semiconductor, Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 */
17
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/platform_device.h>
21
22 #include <scsi/scsi_host.h>
23 #include <scsi/scsi_cmnd.h>
24 #include <linux/libata.h>
25 #include <asm/io.h>
26 #include <linux/of_platform.h>
27
28 /* Controller information */
29 enum {
30 SATA_FSL_QUEUE_DEPTH = 16,
31 SATA_FSL_MAX_PRD = 63,
32 SATA_FSL_MAX_PRD_USABLE = SATA_FSL_MAX_PRD - 1,
33 SATA_FSL_MAX_PRD_DIRECT = 16, /* Direct PRDT entries */
34
35 SATA_FSL_HOST_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
36 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
37 ATA_FLAG_NCQ),
38 SATA_FSL_HOST_LFLAGS = ATA_LFLAG_SKIP_D2H_BSY,
39
40 SATA_FSL_MAX_CMDS = SATA_FSL_QUEUE_DEPTH,
41 SATA_FSL_CMD_HDR_SIZE = 16, /* 4 DWORDS */
42 SATA_FSL_CMD_SLOT_SIZE = (SATA_FSL_MAX_CMDS * SATA_FSL_CMD_HDR_SIZE),
43
44 /*
45 * SATA-FSL host controller supports a max. of (15+1) direct PRDEs, and
46 * chained indirect PRDEs upto a max count of 63.
47 * We are allocating an array of 63 PRDEs contigiously, but PRDE#15 will
48 * be setup as an indirect descriptor, pointing to it's next
49 * (contigious) PRDE. Though chained indirect PRDE arrays are
50 * supported,it will be more efficient to use a direct PRDT and
51 * a single chain/link to indirect PRDE array/PRDT.
52 */
53
54 SATA_FSL_CMD_DESC_CFIS_SZ = 32,
55 SATA_FSL_CMD_DESC_SFIS_SZ = 32,
56 SATA_FSL_CMD_DESC_ACMD_SZ = 16,
57 SATA_FSL_CMD_DESC_RSRVD = 16,
58
59 SATA_FSL_CMD_DESC_SIZE = (SATA_FSL_CMD_DESC_CFIS_SZ +
60 SATA_FSL_CMD_DESC_SFIS_SZ +
61 SATA_FSL_CMD_DESC_ACMD_SZ +
62 SATA_FSL_CMD_DESC_RSRVD +
63 SATA_FSL_MAX_PRD * 16),
64
65 SATA_FSL_CMD_DESC_OFFSET_TO_PRDT =
66 (SATA_FSL_CMD_DESC_CFIS_SZ +
67 SATA_FSL_CMD_DESC_SFIS_SZ +
68 SATA_FSL_CMD_DESC_ACMD_SZ +
69 SATA_FSL_CMD_DESC_RSRVD),
70
71 SATA_FSL_CMD_DESC_AR_SZ = (SATA_FSL_CMD_DESC_SIZE * SATA_FSL_MAX_CMDS),
72 SATA_FSL_PORT_PRIV_DMA_SZ = (SATA_FSL_CMD_SLOT_SIZE +
73 SATA_FSL_CMD_DESC_AR_SZ),
74
75 /*
76 * MPC8315 has two SATA controllers, SATA1 & SATA2
77 * (one port per controller)
78 * MPC837x has 2/4 controllers, one port per controller
79 */
80
81 SATA_FSL_MAX_PORTS = 1,
82
83 SATA_FSL_IRQ_FLAG = IRQF_SHARED,
84 };
85
86 /*
87 * Host Controller command register set - per port
88 */
89 enum {
90 CQ = 0,
91 CA = 8,
92 CC = 0x10,
93 CE = 0x18,
94 DE = 0x20,
95 CHBA = 0x24,
96 HSTATUS = 0x28,
97 HCONTROL = 0x2C,
98 CQPMP = 0x30,
99 SIGNATURE = 0x34,
100 ICC = 0x38,
101
102 /*
103 * Host Status Register (HStatus) bitdefs
104 */
105 ONLINE = (1 << 31),
106 GOING_OFFLINE = (1 << 30),
107 BIST_ERR = (1 << 29),
108
109 FATAL_ERR_HC_MASTER_ERR = (1 << 18),
110 FATAL_ERR_PARITY_ERR_TX = (1 << 17),
111 FATAL_ERR_PARITY_ERR_RX = (1 << 16),
112 FATAL_ERR_DATA_UNDERRUN = (1 << 13),
113 FATAL_ERR_DATA_OVERRUN = (1 << 12),
114 FATAL_ERR_CRC_ERR_TX = (1 << 11),
115 FATAL_ERR_CRC_ERR_RX = (1 << 10),
116 FATAL_ERR_FIFO_OVRFL_TX = (1 << 9),
117 FATAL_ERR_FIFO_OVRFL_RX = (1 << 8),
118
119 FATAL_ERROR_DECODE = FATAL_ERR_HC_MASTER_ERR |
120 FATAL_ERR_PARITY_ERR_TX |
121 FATAL_ERR_PARITY_ERR_RX |
122 FATAL_ERR_DATA_UNDERRUN |
123 FATAL_ERR_DATA_OVERRUN |
124 FATAL_ERR_CRC_ERR_TX |
125 FATAL_ERR_CRC_ERR_RX |
126 FATAL_ERR_FIFO_OVRFL_TX | FATAL_ERR_FIFO_OVRFL_RX,
127
128 INT_ON_FATAL_ERR = (1 << 5),
129 INT_ON_PHYRDY_CHG = (1 << 4),
130
131 INT_ON_SIGNATURE_UPDATE = (1 << 3),
132 INT_ON_SNOTIFY_UPDATE = (1 << 2),
133 INT_ON_SINGL_DEVICE_ERR = (1 << 1),
134 INT_ON_CMD_COMPLETE = 1,
135
136 INT_ON_ERROR = INT_ON_FATAL_ERR |
137 INT_ON_PHYRDY_CHG | INT_ON_SINGL_DEVICE_ERR,
138
139 /*
140 * Host Control Register (HControl) bitdefs
141 */
142 HCONTROL_ONLINE_PHY_RST = (1 << 31),
143 HCONTROL_FORCE_OFFLINE = (1 << 30),
144 HCONTROL_PARITY_PROT_MOD = (1 << 14),
145 HCONTROL_DPATH_PARITY = (1 << 12),
146 HCONTROL_SNOOP_ENABLE = (1 << 10),
147 HCONTROL_PMP_ATTACHED = (1 << 9),
148 HCONTROL_COPYOUT_STATFIS = (1 << 8),
149 IE_ON_FATAL_ERR = (1 << 5),
150 IE_ON_PHYRDY_CHG = (1 << 4),
151 IE_ON_SIGNATURE_UPDATE = (1 << 3),
152 IE_ON_SNOTIFY_UPDATE = (1 << 2),
153 IE_ON_SINGL_DEVICE_ERR = (1 << 1),
154 IE_ON_CMD_COMPLETE = 1,
155
156 DEFAULT_PORT_IRQ_ENABLE_MASK = IE_ON_FATAL_ERR | IE_ON_PHYRDY_CHG |
157 IE_ON_SIGNATURE_UPDATE |
158 IE_ON_SINGL_DEVICE_ERR | IE_ON_CMD_COMPLETE,
159
160 EXT_INDIRECT_SEG_PRD_FLAG = (1 << 31),
161 DATA_SNOOP_ENABLE = (1 << 22),
162 };
163
164 /*
165 * SATA Superset Registers
166 */
167 enum {
168 SSTATUS = 0,
169 SERROR = 4,
170 SCONTROL = 8,
171 SNOTIFY = 0xC,
172 };
173
174 /*
175 * Control Status Register Set
176 */
177 enum {
178 TRANSCFG = 0,
179 TRANSSTATUS = 4,
180 LINKCFG = 8,
181 LINKCFG1 = 0xC,
182 LINKCFG2 = 0x10,
183 LINKSTATUS = 0x14,
184 LINKSTATUS1 = 0x18,
185 PHYCTRLCFG = 0x1C,
186 COMMANDSTAT = 0x20,
187 };
188
189 /* PHY (link-layer) configuration control */
190 enum {
191 PHY_BIST_ENABLE = 0x01,
192 };
193
194 /*
195 * Command Header Table entry, i.e, command slot
196 * 4 Dwords per command slot, command header size == 64 Dwords.
197 */
198 struct cmdhdr_tbl_entry {
199 u32 cda;
200 u32 prde_fis_len;
201 u32 ttl;
202 u32 desc_info;
203 };
204
205 /*
206 * Description information bitdefs
207 */
208 enum {
209 VENDOR_SPECIFIC_BIST = (1 << 10),
210 CMD_DESC_SNOOP_ENABLE = (1 << 9),
211 FPDMA_QUEUED_CMD = (1 << 8),
212 SRST_CMD = (1 << 7),
213 BIST = (1 << 6),
214 ATAPI_CMD = (1 << 5),
215 };
216
217 /*
218 * Command Descriptor
219 */
220 struct command_desc {
221 u8 cfis[8 * 4];
222 u8 sfis[8 * 4];
223 u8 acmd[4 * 4];
224 u8 fill[4 * 4];
225 u32 prdt[SATA_FSL_MAX_PRD_DIRECT * 4];
226 u32 prdt_indirect[(SATA_FSL_MAX_PRD - SATA_FSL_MAX_PRD_DIRECT) * 4];
227 };
228
229 /*
230 * Physical region table descriptor(PRD)
231 */
232
233 struct prde {
234 u32 dba;
235 u8 fill[2 * 4];
236 u32 ddc_and_ext;
237 };
238
239 /*
240 * ata_port private data
241 * This is our per-port instance data.
242 */
243 struct sata_fsl_port_priv {
244 struct cmdhdr_tbl_entry *cmdslot;
245 dma_addr_t cmdslot_paddr;
246 struct command_desc *cmdentry;
247 dma_addr_t cmdentry_paddr;
248
249 /*
250 * SATA FSL controller has a Status FIS which should contain the
251 * received D2H FIS & taskfile registers. This SFIS is present in
252 * the command descriptor, and to have a ready reference to it,
253 * we are caching it here, quite similar to what is done in H/W on
254 * AHCI compliant devices by copying taskfile fields to a 32-bit
255 * register.
256 */
257
258 struct ata_taskfile tf;
259 };
260
261 /*
262 * ata_port->host_set private data
263 */
264 struct sata_fsl_host_priv {
265 void __iomem *hcr_base;
266 void __iomem *ssr_base;
267 void __iomem *csr_base;
268 int irq;
269 };
270
271 static inline unsigned int sata_fsl_tag(unsigned int tag,
272 void __iomem * hcr_base)
273 {
274 /* We let libATA core do actual (queue) tag allocation */
275
276 /* all non NCQ/queued commands should have tag#0 */
277 if (ata_tag_internal(tag)) {
278 DPRINTK("mapping internal cmds to tag#0\n");
279 return 0;
280 }
281
282 if (unlikely(tag >= SATA_FSL_QUEUE_DEPTH)) {
283 DPRINTK("tag %d invalid : out of range\n", tag);
284 return 0;
285 }
286
287 if (unlikely((ioread32(hcr_base + CQ)) & (1 << tag))) {
288 DPRINTK("tag %d invalid : in use!!\n", tag);
289 return 0;
290 }
291
292 return tag;
293 }
294
295 static void sata_fsl_setup_cmd_hdr_entry(struct sata_fsl_port_priv *pp,
296 unsigned int tag, u32 desc_info,
297 u32 data_xfer_len, u8 num_prde,
298 u8 fis_len)
299 {
300 dma_addr_t cmd_descriptor_address;
301
302 cmd_descriptor_address = pp->cmdentry_paddr +
303 tag * SATA_FSL_CMD_DESC_SIZE;
304
305 /* NOTE: both data_xfer_len & fis_len are Dword counts */
306
307 pp->cmdslot[tag].cda = cpu_to_le32(cmd_descriptor_address);
308 pp->cmdslot[tag].prde_fis_len =
309 cpu_to_le32((num_prde << 16) | (fis_len << 2));
310 pp->cmdslot[tag].ttl = cpu_to_le32(data_xfer_len & ~0x03);
311 pp->cmdslot[tag].desc_info = cpu_to_le32((desc_info | (tag & 0x1F)));
312
313 VPRINTK("cda=0x%x, prde_fis_len=0x%x, ttl=0x%x, di=0x%x\n",
314 pp->cmdslot[tag].cda,
315 pp->cmdslot[tag].prde_fis_len,
316 pp->cmdslot[tag].ttl, pp->cmdslot[tag].desc_info);
317
318 }
319
320 static unsigned int sata_fsl_fill_sg(struct ata_queued_cmd *qc, void *cmd_desc,
321 u32 * ttl, dma_addr_t cmd_desc_paddr)
322 {
323 struct scatterlist *sg;
324 unsigned int num_prde = 0;
325 u32 ttl_dwords = 0;
326
327 /*
328 * NOTE : direct & indirect prdt's are contigiously allocated
329 */
330 struct prde *prd = (struct prde *)&((struct command_desc *)
331 cmd_desc)->prdt;
332
333 struct prde *prd_ptr_to_indirect_ext = NULL;
334 unsigned indirect_ext_segment_sz = 0;
335 dma_addr_t indirect_ext_segment_paddr;
336
337 VPRINTK("SATA FSL : cd = 0x%x, prd = 0x%x\n", cmd_desc, prd);
338
339 indirect_ext_segment_paddr = cmd_desc_paddr +
340 SATA_FSL_CMD_DESC_OFFSET_TO_PRDT + SATA_FSL_MAX_PRD_DIRECT * 16;
341
342 ata_for_each_sg(sg, qc) {
343 dma_addr_t sg_addr = sg_dma_address(sg);
344 u32 sg_len = sg_dma_len(sg);
345
346 VPRINTK("SATA FSL : fill_sg, sg_addr = 0x%x, sg_len = %d\n",
347 sg_addr, sg_len);
348
349 /* warn if each s/g element is not dword aligned */
350 if (sg_addr & 0x03)
351 ata_port_printk(qc->ap, KERN_ERR,
352 "s/g addr unaligned : 0x%x\n", sg_addr);
353 if (sg_len & 0x03)
354 ata_port_printk(qc->ap, KERN_ERR,
355 "s/g len unaligned : 0x%x\n", sg_len);
356
357 if ((num_prde == (SATA_FSL_MAX_PRD_DIRECT - 1)) &&
358 (qc->n_iter + 1 != qc->n_elem)) {
359 VPRINTK("setting indirect prde\n");
360 prd_ptr_to_indirect_ext = prd;
361 prd->dba = cpu_to_le32(indirect_ext_segment_paddr);
362 indirect_ext_segment_sz = 0;
363 ++prd;
364 ++num_prde;
365 }
366
367 ttl_dwords += sg_len;
368 prd->dba = cpu_to_le32(sg_addr);
369 prd->ddc_and_ext =
370 cpu_to_le32(DATA_SNOOP_ENABLE | (sg_len & ~0x03));
371
372 VPRINTK("sg_fill, ttl=%d, dba=0x%x, ddc=0x%x\n",
373 ttl_dwords, prd->dba, prd->ddc_and_ext);
374
375 ++num_prde;
376 ++prd;
377 if (prd_ptr_to_indirect_ext)
378 indirect_ext_segment_sz += sg_len;
379 }
380
381 if (prd_ptr_to_indirect_ext) {
382 /* set indirect extension flag along with indirect ext. size */
383 prd_ptr_to_indirect_ext->ddc_and_ext =
384 cpu_to_le32((EXT_INDIRECT_SEG_PRD_FLAG |
385 DATA_SNOOP_ENABLE |
386 (indirect_ext_segment_sz & ~0x03)));
387 }
388
389 *ttl = ttl_dwords;
390 return num_prde;
391 }
392
393 static void sata_fsl_qc_prep(struct ata_queued_cmd *qc)
394 {
395 struct ata_port *ap = qc->ap;
396 struct sata_fsl_port_priv *pp = ap->private_data;
397 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
398 void __iomem *hcr_base = host_priv->hcr_base;
399 unsigned int tag = sata_fsl_tag(qc->tag, hcr_base);
400 struct command_desc *cd;
401 u32 desc_info = CMD_DESC_SNOOP_ENABLE;
402 u32 num_prde = 0;
403 u32 ttl_dwords = 0;
404 dma_addr_t cd_paddr;
405
406 cd = (struct command_desc *)pp->cmdentry + tag;
407 cd_paddr = pp->cmdentry_paddr + tag * SATA_FSL_CMD_DESC_SIZE;
408
409 ata_tf_to_fis(&qc->tf, 0, 1, (u8 *) & cd->cfis);
410
411 VPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x\n",
412 cd->cfis[0], cd->cfis[1], cd->cfis[2]);
413
414 if (qc->tf.protocol == ATA_PROT_NCQ) {
415 VPRINTK("FPDMA xfer,Sctor cnt[0:7],[8:15] = %d,%d\n",
416 cd->cfis[3], cd->cfis[11]);
417 }
418
419 /* setup "ACMD - atapi command" in cmd. desc. if this is ATAPI cmd */
420 if (is_atapi_taskfile(&qc->tf)) {
421 desc_info |= ATAPI_CMD;
422 memset((void *)&cd->acmd, 0, 32);
423 memcpy((void *)&cd->acmd, qc->cdb, qc->dev->cdb_len);
424 }
425
426 if (qc->flags & ATA_QCFLAG_DMAMAP)
427 num_prde = sata_fsl_fill_sg(qc, (void *)cd,
428 &ttl_dwords, cd_paddr);
429
430 if (qc->tf.protocol == ATA_PROT_NCQ)
431 desc_info |= FPDMA_QUEUED_CMD;
432
433 sata_fsl_setup_cmd_hdr_entry(pp, tag, desc_info, ttl_dwords,
434 num_prde, 5);
435
436 VPRINTK("SATA FSL : xx_qc_prep, di = 0x%x, ttl = %d, num_prde = %d\n",
437 desc_info, ttl_dwords, num_prde);
438 }
439
440 static unsigned int sata_fsl_qc_issue(struct ata_queued_cmd *qc)
441 {
442 struct ata_port *ap = qc->ap;
443 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
444 void __iomem *hcr_base = host_priv->hcr_base;
445 unsigned int tag = sata_fsl_tag(qc->tag, hcr_base);
446
447 VPRINTK("xx_qc_issue called,CQ=0x%x,CA=0x%x,CE=0x%x,CC=0x%x\n",
448 ioread32(CQ + hcr_base),
449 ioread32(CA + hcr_base),
450 ioread32(CE + hcr_base), ioread32(CC + hcr_base));
451
452 /* Simply queue command to the controller/device */
453 iowrite32(1 << tag, CQ + hcr_base);
454
455 VPRINTK("xx_qc_issue called, tag=%d, CQ=0x%x, CA=0x%x\n",
456 tag, ioread32(CQ + hcr_base), ioread32(CA + hcr_base));
457
458 VPRINTK("CE=0x%x, DE=0x%x, CC=0x%x, CmdStat = 0x%x\n",
459 ioread32(CE + hcr_base),
460 ioread32(DE + hcr_base),
461 ioread32(CC + hcr_base), ioread32(COMMANDSTAT + csr_base));
462
463 return 0;
464 }
465
466 static int sata_fsl_scr_write(struct ata_port *ap, unsigned int sc_reg_in,
467 u32 val)
468 {
469 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
470 void __iomem *ssr_base = host_priv->ssr_base;
471 unsigned int sc_reg;
472
473 switch (sc_reg_in) {
474 case SCR_STATUS:
475 case SCR_ERROR:
476 case SCR_CONTROL:
477 case SCR_ACTIVE:
478 sc_reg = sc_reg_in;
479 break;
480 default:
481 return -EINVAL;
482 }
483
484 VPRINTK("xx_scr_write, reg_in = %d\n", sc_reg);
485
486 iowrite32(val, ssr_base + (sc_reg * 4));
487 return 0;
488 }
489
490 static int sata_fsl_scr_read(struct ata_port *ap, unsigned int sc_reg_in,
491 u32 *val)
492 {
493 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
494 void __iomem *ssr_base = host_priv->ssr_base;
495 unsigned int sc_reg;
496
497 switch (sc_reg_in) {
498 case SCR_STATUS:
499 case SCR_ERROR:
500 case SCR_CONTROL:
501 case SCR_ACTIVE:
502 sc_reg = sc_reg_in;
503 break;
504 default:
505 return -EINVAL;
506 }
507
508 VPRINTK("xx_scr_read, reg_in = %d\n", sc_reg);
509
510 *val = ioread32(ssr_base + (sc_reg * 4));
511 return 0;
512 }
513
514 static void sata_fsl_freeze(struct ata_port *ap)
515 {
516 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
517 void __iomem *hcr_base = host_priv->hcr_base;
518 u32 temp;
519
520 VPRINTK("xx_freeze, CQ=0x%x, CA=0x%x, CE=0x%x, DE=0x%x\n",
521 ioread32(CQ + hcr_base),
522 ioread32(CA + hcr_base),
523 ioread32(CE + hcr_base), ioread32(DE + hcr_base));
524 VPRINTK("CmdStat = 0x%x\n", ioread32(csr_base + COMMANDSTAT));
525
526 /* disable interrupts on the controller/port */
527 temp = ioread32(hcr_base + HCONTROL);
528 iowrite32((temp & ~0x3F), hcr_base + HCONTROL);
529
530 VPRINTK("in xx_freeze : HControl = 0x%x, HStatus = 0x%x\n",
531 ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS));
532 }
533
534 static void sata_fsl_thaw(struct ata_port *ap)
535 {
536 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
537 void __iomem *hcr_base = host_priv->hcr_base;
538 u32 temp;
539
540 /* ack. any pending IRQs for this controller/port */
541 temp = ioread32(hcr_base + HSTATUS);
542
543 VPRINTK("xx_thaw, pending IRQs = 0x%x\n", (temp & 0x3F));
544
545 if (temp & 0x3F)
546 iowrite32((temp & 0x3F), hcr_base + HSTATUS);
547
548 /* enable interrupts on the controller/port */
549 temp = ioread32(hcr_base + HCONTROL);
550 iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL);
551
552 VPRINTK("xx_thaw : HControl = 0x%x, HStatus = 0x%x\n",
553 ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS));
554 }
555
556 /*
557 * NOTE : 1st D2H FIS from device does not update sfis in command descriptor.
558 */
559 static inline void sata_fsl_cache_taskfile_from_d2h_fis(struct ata_queued_cmd
560 *qc,
561 struct ata_port *ap)
562 {
563 struct sata_fsl_port_priv *pp = ap->private_data;
564 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
565 void __iomem *hcr_base = host_priv->hcr_base;
566 unsigned int tag = sata_fsl_tag(qc->tag, hcr_base);
567 struct command_desc *cd;
568
569 cd = pp->cmdentry + tag;
570
571 ata_tf_from_fis(cd->sfis, &pp->tf);
572 }
573
574 static u8 sata_fsl_check_status(struct ata_port *ap)
575 {
576 struct sata_fsl_port_priv *pp = ap->private_data;
577
578 return pp->tf.command;
579 }
580
581 static void sata_fsl_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
582 {
583 struct sata_fsl_port_priv *pp = ap->private_data;
584
585 *tf = pp->tf;
586 }
587
588 static int sata_fsl_port_start(struct ata_port *ap)
589 {
590 struct device *dev = ap->host->dev;
591 struct sata_fsl_port_priv *pp;
592 int retval;
593 void *mem;
594 dma_addr_t mem_dma;
595 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
596 void __iomem *hcr_base = host_priv->hcr_base;
597 u32 temp;
598
599 pp = kzalloc(sizeof(*pp), GFP_KERNEL);
600 if (!pp)
601 return -ENOMEM;
602
603 /*
604 * allocate per command dma alignment pad buffer, which is used
605 * internally by libATA to ensure that all transfers ending on
606 * unaligned boundaries are padded, to align on Dword boundaries
607 */
608 retval = ata_pad_alloc(ap, dev);
609 if (retval) {
610 kfree(pp);
611 return retval;
612 }
613
614 mem = dma_alloc_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ, &mem_dma,
615 GFP_KERNEL);
616 if (!mem) {
617 ata_pad_free(ap, dev);
618 kfree(pp);
619 return -ENOMEM;
620 }
621 memset(mem, 0, SATA_FSL_PORT_PRIV_DMA_SZ);
622
623 pp->cmdslot = mem;
624 pp->cmdslot_paddr = mem_dma;
625
626 mem += SATA_FSL_CMD_SLOT_SIZE;
627 mem_dma += SATA_FSL_CMD_SLOT_SIZE;
628
629 pp->cmdentry = mem;
630 pp->cmdentry_paddr = mem_dma;
631
632 ap->private_data = pp;
633
634 VPRINTK("CHBA = 0x%x, cmdentry_phys = 0x%x\n",
635 pp->cmdslot_paddr, pp->cmdentry_paddr);
636
637 /* Now, update the CHBA register in host controller cmd register set */
638 iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA);
639
640 /*
641 * Now, we can bring the controller on-line & also initiate
642 * the COMINIT sequence, we simply return here and the boot-probing
643 * & device discovery process is re-initiated by libATA using a
644 * Softreset EH (dummy) session. Hence, boot probing and device
645 * discovey will be part of sata_fsl_softreset() callback.
646 */
647
648 temp = ioread32(hcr_base + HCONTROL);
649 iowrite32((temp | HCONTROL_ONLINE_PHY_RST), hcr_base + HCONTROL);
650
651 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
652 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
653 VPRINTK("CHBA = 0x%x\n", ioread32(hcr_base + CHBA));
654
655 /*
656 * Workaround for 8315DS board 3gbps link-up issue,
657 * currently limit SATA port to GEN1 speed
658 */
659 sata_fsl_scr_read(ap, SCR_CONTROL, &temp);
660 temp &= ~(0xF << 4);
661 temp |= (0x1 << 4);
662 sata_fsl_scr_write(ap, SCR_CONTROL, temp);
663
664 sata_fsl_scr_read(ap, SCR_CONTROL, &temp);
665 dev_printk(KERN_WARNING, dev, "scr_control, speed limited to %x\n",
666 temp);
667
668 return 0;
669 }
670
671 static void sata_fsl_port_stop(struct ata_port *ap)
672 {
673 struct device *dev = ap->host->dev;
674 struct sata_fsl_port_priv *pp = ap->private_data;
675 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
676 void __iomem *hcr_base = host_priv->hcr_base;
677 u32 temp;
678
679 /*
680 * Force host controller to go off-line, aborting current operations
681 */
682 temp = ioread32(hcr_base + HCONTROL);
683 temp &= ~HCONTROL_ONLINE_PHY_RST;
684 temp |= HCONTROL_FORCE_OFFLINE;
685 iowrite32(temp, hcr_base + HCONTROL);
686
687 /* Poll for controller to go offline - should happen immediately */
688 ata_wait_register(hcr_base + HSTATUS, ONLINE, ONLINE, 1, 1);
689
690 ap->private_data = NULL;
691 dma_free_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ,
692 pp->cmdslot, pp->cmdslot_paddr);
693
694 ata_pad_free(ap, dev);
695 kfree(pp);
696 }
697
698 static unsigned int sata_fsl_dev_classify(struct ata_port *ap)
699 {
700 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
701 void __iomem *hcr_base = host_priv->hcr_base;
702 struct ata_taskfile tf;
703 u32 temp;
704
705 temp = ioread32(hcr_base + SIGNATURE);
706
707 VPRINTK("raw sig = 0x%x\n", temp);
708 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
709 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
710
711 tf.lbah = (temp >> 24) & 0xff;
712 tf.lbam = (temp >> 16) & 0xff;
713 tf.lbal = (temp >> 8) & 0xff;
714 tf.nsect = temp & 0xff;
715
716 return ata_dev_classify(&tf);
717 }
718
719 static int sata_fsl_softreset(struct ata_link *link, unsigned int *class,
720 unsigned long deadline)
721 {
722 struct ata_port *ap = link->ap;
723 struct sata_fsl_port_priv *pp = ap->private_data;
724 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
725 void __iomem *hcr_base = host_priv->hcr_base;
726 u32 temp;
727 struct ata_taskfile tf;
728 u8 *cfis;
729 u32 Serror;
730 int i = 0;
731 struct ata_queued_cmd qc;
732 u8 *buf;
733 dma_addr_t dma_address;
734 struct scatterlist *sg;
735 unsigned long start_jiffies;
736
737 DPRINTK("in xx_softreset\n");
738
739 try_offline_again:
740 /*
741 * Force host controller to go off-line, aborting current operations
742 */
743 temp = ioread32(hcr_base + HCONTROL);
744 temp &= ~HCONTROL_ONLINE_PHY_RST;
745 iowrite32(temp, hcr_base + HCONTROL);
746
747 /* Poll for controller to go offline */
748 temp = ata_wait_register(hcr_base + HSTATUS, ONLINE, ONLINE, 1, 500);
749
750 if (temp & ONLINE) {
751 ata_port_printk(ap, KERN_ERR,
752 "Softreset failed, not off-lined %d\n", i);
753
754 /*
755 * Try to offline controller atleast twice
756 */
757 i++;
758 if (i == 2)
759 goto err;
760 else
761 goto try_offline_again;
762 }
763
764 DPRINTK("softreset, controller off-lined\n");
765 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
766 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
767
768 /*
769 * PHY reset should remain asserted for atleast 1ms
770 */
771 msleep(1);
772
773 /*
774 * Now, bring the host controller online again, this can take time
775 * as PHY reset and communication establishment, 1st D2H FIS and
776 * device signature update is done, on safe side assume 500ms
777 * NOTE : Host online status may be indicated immediately!!
778 */
779
780 temp = ioread32(hcr_base + HCONTROL);
781 temp |= (HCONTROL_ONLINE_PHY_RST | HCONTROL_SNOOP_ENABLE);
782 iowrite32(temp, hcr_base + HCONTROL);
783
784 temp = ata_wait_register(hcr_base + HSTATUS, ONLINE, 0, 1, 500);
785
786 if (!(temp & ONLINE)) {
787 ata_port_printk(ap, KERN_ERR,
788 "Softreset failed, not on-lined\n");
789 goto err;
790 }
791
792 DPRINTK("softreset, controller off-lined & on-lined\n");
793 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
794 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
795
796 /*
797 * First, wait for the PHYRDY change to occur before waiting for
798 * the signature, and also verify if SStatus indicates device
799 * presence
800 */
801
802 temp = ata_wait_register(hcr_base + HSTATUS, 0xFF, 0, 1, 500);
803 if ((!(temp & 0x10)) || ata_link_offline(link)) {
804 ata_port_printk(ap, KERN_WARNING,
805 "No Device OR PHYRDY change,Hstatus = 0x%x\n",
806 ioread32(hcr_base + HSTATUS));
807 goto err;
808 }
809
810 /*
811 * Wait for the first D2H from device,i.e,signature update notification
812 */
813 start_jiffies = jiffies;
814 temp = ata_wait_register(hcr_base + HSTATUS, 0xFF, 0x10,
815 500, jiffies_to_msecs(deadline - start_jiffies));
816
817 if ((temp & 0xFF) != 0x18) {
818 ata_port_printk(ap, KERN_WARNING, "No Signature Update\n");
819 goto err;
820 } else {
821 ata_port_printk(ap, KERN_INFO,
822 "Signature Update detected @ %d msecs\n",
823 jiffies_to_msecs(jiffies - start_jiffies));
824 }
825
826 /*
827 * Send a device reset (SRST) explicitly on command slot #0
828 * Check : will the command queue (reg) be cleared during offlining ??
829 * Also we will be online only if Phy commn. has been established
830 * and device presence has been detected, therefore if we have
831 * reached here, we can send a command to the target device
832 */
833
834 if (link->sactive)
835 goto skip_srst_do_ncq_error_handling;
836
837 DPRINTK("Sending SRST/device reset\n");
838
839 ata_tf_init(link->device, &tf);
840 cfis = (u8 *) & pp->cmdentry->cfis;
841
842 /* device reset/SRST is a control register update FIS, uses tag0 */
843 sata_fsl_setup_cmd_hdr_entry(pp, 0,
844 SRST_CMD | CMD_DESC_SNOOP_ENABLE, 0, 0, 5);
845
846 tf.ctl |= ATA_SRST; /* setup SRST bit in taskfile control reg */
847 ata_tf_to_fis(&tf, 0, 0, cfis);
848
849 DPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x, 0x%x\n",
850 cfis[0], cfis[1], cfis[2], cfis[3]);
851
852 /*
853 * Queue SRST command to the controller/device, ensure that no
854 * other commands are active on the controller/device
855 */
856
857 DPRINTK("@Softreset, CQ = 0x%x, CA = 0x%x, CC = 0x%x\n",
858 ioread32(CQ + hcr_base),
859 ioread32(CA + hcr_base), ioread32(CC + hcr_base));
860
861 iowrite32(0xFFFF, CC + hcr_base);
862 iowrite32(1, CQ + hcr_base);
863
864 temp = ata_wait_register(CQ + hcr_base, 0x1, 0x1, 1, 5000);
865 if (temp & 0x1) {
866 ata_port_printk(ap, KERN_WARNING, "ATA_SRST issue failed\n");
867
868 DPRINTK("Softreset@5000,CQ=0x%x,CA=0x%x,CC=0x%x\n",
869 ioread32(CQ + hcr_base),
870 ioread32(CA + hcr_base), ioread32(CC + hcr_base));
871
872 sata_fsl_scr_read(ap, SCR_ERROR, &Serror);
873
874 DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
875 DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
876 DPRINTK("Serror = 0x%x\n", Serror);
877 goto err;
878 }
879
880 msleep(1);
881
882 /*
883 * SATA device enters reset state after receving a Control register
884 * FIS with SRST bit asserted and it awaits another H2D Control reg.
885 * FIS with SRST bit cleared, then the device does internal diags &
886 * initialization, followed by indicating it's initialization status
887 * using ATA signature D2H register FIS to the host controller.
888 */
889
890 sata_fsl_setup_cmd_hdr_entry(pp, 0, CMD_DESC_SNOOP_ENABLE, 0, 0, 5);
891
892 tf.ctl &= ~ATA_SRST; /* 2nd H2D Ctl. register FIS */
893 ata_tf_to_fis(&tf, 0, 0, cfis);
894
895 iowrite32(1, CQ + hcr_base);
896 msleep(150); /* ?? */
897
898 /*
899 * The above command would have signalled an interrupt on command
900 * complete, which needs special handling, by clearing the Nth
901 * command bit of the CCreg
902 */
903 iowrite32(0x01, CC + hcr_base); /* We know it will be cmd#0 always */
904 goto check_device_signature;
905
906 skip_srst_do_ncq_error_handling:
907
908 VPRINTK("Sending read log ext(10h) command\n");
909
910 memset(&qc, 0, sizeof(struct ata_queued_cmd));
911 ata_tf_init(link->device, &tf);
912
913 tf.command = ATA_CMD_READ_LOG_EXT;
914 tf.lbal = ATA_LOG_SATA_NCQ;
915 tf.nsect = 1;
916 tf.hob_nsect = 0;
917 tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_LBA48 | ATA_TFLAG_DEVICE;
918 tf.protocol = ATA_PROT_PIO;
919
920 qc.tag = ATA_TAG_INTERNAL;
921 qc.scsicmd = NULL;
922 qc.ap = ap;
923 qc.dev = link->device;
924
925 qc.tf = tf;
926 qc.flags |= ATA_QCFLAG_RESULT_TF;
927 qc.dma_dir = DMA_FROM_DEVICE;
928
929 buf = ap->sector_buf;
930 ata_sg_init_one(&qc, buf, 1 * ATA_SECT_SIZE);
931
932 /*
933 * Need to DMA-map the memory buffer associated with the command
934 */
935
936 sg = qc.__sg;
937 dma_address = dma_map_single(ap->dev, qc.buf_virt,
938 sg->length, DMA_FROM_DEVICE);
939
940 sg_dma_address(sg) = dma_address;
941 sg_dma_len(sg) = sg->length;
942
943 VPRINTK("EH, addr = 0x%x, len = 0x%x\n", dma_address, sg->length);
944
945 sata_fsl_qc_prep(&qc);
946 sata_fsl_qc_issue(&qc);
947
948 temp = ata_wait_register(CQ + hcr_base, 0x1, 0x1, 1, 5000);
949 if (temp & 0x1) {
950 VPRINTK("READ_LOG_EXT_10H issue failed\n");
951
952 VPRINTK("READ_LOG@5000,CQ=0x%x,CA=0x%x,CC=0x%x\n",
953 ioread32(CQ + hcr_base),
954 ioread32(CA + hcr_base), ioread32(CC + hcr_base));
955
956 sata_fsl_scr_read(ap, SCR_ERROR, &Serror);
957
958 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
959 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
960 VPRINTK("Serror = 0x%x\n", Serror);
961 goto err;
962 }
963
964 iowrite32(0x01, CC + hcr_base); /* We know it will be cmd#0 always */
965
966 check_device_signature:
967
968 DPRINTK("SATA FSL : Now checking device signature\n");
969
970 *class = ATA_DEV_NONE;
971
972 /* Verify if SStatus indicates device presence */
973 if (ata_link_online(link)) {
974 /*
975 * if we are here, device presence has been detected,
976 * 1st D2H FIS would have been received, but sfis in
977 * command desc. is not updated, but signature register
978 * would have been updated
979 */
980
981 *class = sata_fsl_dev_classify(ap);
982
983 DPRINTK("class = %d\n", *class);
984 VPRINTK("ccreg = 0x%x\n", ioread32(hcr_base + CC));
985 VPRINTK("cereg = 0x%x\n", ioread32(hcr_base + CE));
986 }
987
988 return 0;
989
990 err:
991 return -EIO;
992 }
993
994 static void sata_fsl_error_handler(struct ata_port *ap)
995 {
996
997 DPRINTK("in xx_error_handler\n");
998
999 /* perform recovery */
1000 ata_do_eh(ap, ata_std_prereset, sata_fsl_softreset, sata_std_hardreset,
1001 ata_std_postreset);
1002 }
1003
1004 static void sata_fsl_post_internal_cmd(struct ata_queued_cmd *qc)
1005 {
1006 if (qc->flags & ATA_QCFLAG_FAILED)
1007 qc->err_mask |= AC_ERR_OTHER;
1008
1009 if (qc->err_mask) {
1010 /* make DMA engine forget about the failed command */
1011
1012 }
1013 }
1014
1015 static void sata_fsl_irq_clear(struct ata_port *ap)
1016 {
1017 /* unused */
1018 }
1019
1020 static void sata_fsl_error_intr(struct ata_port *ap)
1021 {
1022 struct ata_link *link = &ap->link;
1023 struct ata_eh_info *ehi = &link->eh_info;
1024 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
1025 void __iomem *hcr_base = host_priv->hcr_base;
1026 u32 hstatus, dereg, cereg = 0, SError = 0;
1027 unsigned int err_mask = 0, action = 0;
1028 struct ata_queued_cmd *qc;
1029 int freeze = 0;
1030
1031 hstatus = ioread32(hcr_base + HSTATUS);
1032 cereg = ioread32(hcr_base + CE);
1033
1034 ata_ehi_clear_desc(ehi);
1035
1036 /*
1037 * Handle & Clear SError
1038 */
1039
1040 sata_fsl_scr_read(ap, SCR_ERROR, &SError);
1041 if (unlikely(SError & 0xFFFF0000)) {
1042 sata_fsl_scr_write(ap, SCR_ERROR, SError);
1043 err_mask |= AC_ERR_ATA_BUS;
1044 }
1045
1046 DPRINTK("error_intr,hStat=0x%x,CE=0x%x,DE =0x%x,SErr=0x%x\n",
1047 hstatus, cereg, ioread32(hcr_base + DE), SError);
1048
1049 /* handle single device errors */
1050 if (cereg) {
1051 /*
1052 * clear the command error, also clears queue to the device
1053 * in error, and we can (re)issue commands to this device.
1054 * When a device is in error all commands queued into the
1055 * host controller and at the device are considered aborted
1056 * and the queue for that device is stopped. Now, after
1057 * clearing the device error, we can issue commands to the
1058 * device to interrogate it to find the source of the error.
1059 */
1060 dereg = ioread32(hcr_base + DE);
1061 iowrite32(dereg, hcr_base + DE);
1062 iowrite32(cereg, hcr_base + CE);
1063
1064 DPRINTK("single device error, CE=0x%x, DE=0x%x\n",
1065 ioread32(hcr_base + CE), ioread32(hcr_base + DE));
1066 /*
1067 * We should consider this as non fatal error, and TF must
1068 * be updated as done below.
1069 */
1070
1071 err_mask |= AC_ERR_DEV;
1072 }
1073
1074 /* handle fatal errors */
1075 if (hstatus & FATAL_ERROR_DECODE) {
1076 err_mask |= AC_ERR_ATA_BUS;
1077 action |= ATA_EH_SOFTRESET;
1078 /* how will fatal error interrupts be completed ?? */
1079 freeze = 1;
1080 }
1081
1082 /* Handle PHYRDY change notification */
1083 if (hstatus & INT_ON_PHYRDY_CHG) {
1084 DPRINTK("SATA FSL: PHYRDY change indication\n");
1085
1086 /* Setup a soft-reset EH action */
1087 ata_ehi_hotplugged(ehi);
1088 freeze = 1;
1089 }
1090
1091 /* record error info */
1092 qc = ata_qc_from_tag(ap, link->active_tag);
1093
1094 if (qc) {
1095 sata_fsl_cache_taskfile_from_d2h_fis(qc, qc->ap);
1096 qc->err_mask |= err_mask;
1097 } else
1098 ehi->err_mask |= err_mask;
1099
1100 ehi->action |= action;
1101 ehi->serror |= SError;
1102
1103 /* freeze or abort */
1104 if (freeze)
1105 ata_port_freeze(ap);
1106 else
1107 ata_port_abort(ap);
1108 }
1109
1110 static void sata_fsl_qc_complete(struct ata_queued_cmd *qc)
1111 {
1112 if (qc->flags & ATA_QCFLAG_RESULT_TF) {
1113 DPRINTK("xx_qc_complete called\n");
1114 sata_fsl_cache_taskfile_from_d2h_fis(qc, qc->ap);
1115 }
1116 }
1117
1118 static void sata_fsl_host_intr(struct ata_port *ap)
1119 {
1120 struct ata_link *link = &ap->link;
1121 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
1122 void __iomem *hcr_base = host_priv->hcr_base;
1123 u32 hstatus, qc_active = 0;
1124 struct ata_queued_cmd *qc;
1125 u32 SError;
1126
1127 hstatus = ioread32(hcr_base + HSTATUS);
1128
1129 sata_fsl_scr_read(ap, SCR_ERROR, &SError);
1130
1131 if (unlikely(SError & 0xFFFF0000)) {
1132 DPRINTK("serror @host_intr : 0x%x\n", SError);
1133 sata_fsl_error_intr(ap);
1134
1135 }
1136
1137 if (unlikely(hstatus & INT_ON_ERROR)) {
1138 DPRINTK("error interrupt!!\n");
1139 sata_fsl_error_intr(ap);
1140 return;
1141 }
1142
1143 if (link->sactive) { /* only true for NCQ commands */
1144 int i;
1145 /* Read command completed register */
1146 qc_active = ioread32(hcr_base + CC);
1147 /* clear CC bit, this will also complete the interrupt */
1148 iowrite32(qc_active, hcr_base + CC);
1149
1150 DPRINTK("Status of all queues :\n");
1151 DPRINTK("qc_active/CC = 0x%x, CA = 0x%x, CE=0x%x\n",
1152 qc_active, ioread32(hcr_base + CA),
1153 ioread32(hcr_base + CE));
1154
1155 for (i = 0; i < SATA_FSL_QUEUE_DEPTH; i++) {
1156 if (qc_active & (1 << i)) {
1157 qc = ata_qc_from_tag(ap, i);
1158 if (qc) {
1159 sata_fsl_qc_complete(qc);
1160 ata_qc_complete(qc);
1161 }
1162 DPRINTK
1163 ("completing ncq cmd,tag=%d,CC=0x%x,CA=0x%x\n",
1164 i, ioread32(hcr_base + CC),
1165 ioread32(hcr_base + CA));
1166 }
1167 }
1168 return;
1169
1170 } else if (ap->qc_active) {
1171 iowrite32(1, hcr_base + CC);
1172 qc = ata_qc_from_tag(ap, link->active_tag);
1173
1174 DPRINTK("completing non-ncq cmd, tag=%d,CC=0x%x\n",
1175 link->active_tag, ioread32(hcr_base + CC));
1176
1177 if (qc) {
1178 sata_fsl_qc_complete(qc);
1179 ata_qc_complete(qc);
1180 }
1181 } else {
1182 /* Spurious Interrupt!! */
1183 DPRINTK("spurious interrupt!!, CC = 0x%x\n",
1184 ioread32(hcr_base + CC));
1185 return;
1186 }
1187 }
1188
1189 static irqreturn_t sata_fsl_interrupt(int irq, void *dev_instance)
1190 {
1191 struct ata_host *host = dev_instance;
1192 struct sata_fsl_host_priv *host_priv = host->private_data;
1193 void __iomem *hcr_base = host_priv->hcr_base;
1194 u32 interrupt_enables;
1195 unsigned handled = 0;
1196 struct ata_port *ap;
1197
1198 /* ack. any pending IRQs for this controller/port */
1199 interrupt_enables = ioread32(hcr_base + HSTATUS);
1200 interrupt_enables &= 0x3F;
1201
1202 DPRINTK("interrupt status 0x%x\n", interrupt_enables);
1203
1204 if (!interrupt_enables)
1205 return IRQ_NONE;
1206
1207 spin_lock(&host->lock);
1208
1209 /* Assuming one port per host controller */
1210
1211 ap = host->ports[0];
1212 if (ap) {
1213 sata_fsl_host_intr(ap);
1214 } else {
1215 dev_printk(KERN_WARNING, host->dev,
1216 "interrupt on disabled port 0\n");
1217 }
1218
1219 iowrite32(interrupt_enables, hcr_base + HSTATUS);
1220 handled = 1;
1221
1222 spin_unlock(&host->lock);
1223
1224 return IRQ_RETVAL(handled);
1225 }
1226
1227 /*
1228 * Multiple ports are represented by multiple SATA controllers with
1229 * one port per controller
1230 */
1231 static int sata_fsl_init_controller(struct ata_host *host)
1232 {
1233 struct sata_fsl_host_priv *host_priv = host->private_data;
1234 void __iomem *hcr_base = host_priv->hcr_base;
1235 u32 temp;
1236
1237 /*
1238 * NOTE : We cannot bring the controller online before setting
1239 * the CHBA, hence main controller initialization is done as
1240 * part of the port_start() callback
1241 */
1242
1243 /* ack. any pending IRQs for this controller/port */
1244 temp = ioread32(hcr_base + HSTATUS);
1245 if (temp & 0x3F)
1246 iowrite32((temp & 0x3F), hcr_base + HSTATUS);
1247
1248 /* Keep interrupts disabled on the controller */
1249 temp = ioread32(hcr_base + HCONTROL);
1250 iowrite32((temp & ~0x3F), hcr_base + HCONTROL);
1251
1252 /* Disable interrupt coalescing control(icc), for the moment */
1253 DPRINTK("icc = 0x%x\n", ioread32(hcr_base + ICC));
1254 iowrite32(0x01000000, hcr_base + ICC);
1255
1256 /* clear error registers, SError is cleared by libATA */
1257 iowrite32(0x00000FFFF, hcr_base + CE);
1258 iowrite32(0x00000FFFF, hcr_base + DE);
1259
1260 /* initially assuming no Port multiplier, set CQPMP to 0 */
1261 iowrite32(0x0, hcr_base + CQPMP);
1262
1263 /*
1264 * host controller will be brought on-line, during xx_port_start()
1265 * callback, that should also initiate the OOB, COMINIT sequence
1266 */
1267
1268 DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
1269 DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
1270
1271 return 0;
1272 }
1273
1274 /*
1275 * scsi mid-layer and libata interface structures
1276 */
1277 static struct scsi_host_template sata_fsl_sht = {
1278 .module = THIS_MODULE,
1279 .name = "sata_fsl",
1280 .ioctl = ata_scsi_ioctl,
1281 .queuecommand = ata_scsi_queuecmd,
1282 .change_queue_depth = ata_scsi_change_queue_depth,
1283 .can_queue = SATA_FSL_QUEUE_DEPTH,
1284 .this_id = ATA_SHT_THIS_ID,
1285 .sg_tablesize = SATA_FSL_MAX_PRD_USABLE,
1286 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
1287 .emulated = ATA_SHT_EMULATED,
1288 .use_clustering = ATA_SHT_USE_CLUSTERING,
1289 .proc_name = "sata_fsl",
1290 .dma_boundary = ATA_DMA_BOUNDARY,
1291 .slave_configure = ata_scsi_slave_config,
1292 .slave_destroy = ata_scsi_slave_destroy,
1293 .bios_param = ata_std_bios_param,
1294 #ifdef CONFIG_PM
1295 .suspend = ata_scsi_device_suspend,
1296 .resume = ata_scsi_device_resume,
1297 #endif
1298 };
1299
1300 static const struct ata_port_operations sata_fsl_ops = {
1301 .check_status = sata_fsl_check_status,
1302 .check_altstatus = sata_fsl_check_status,
1303 .dev_select = ata_noop_dev_select,
1304
1305 .tf_read = sata_fsl_tf_read,
1306
1307 .qc_prep = sata_fsl_qc_prep,
1308 .qc_issue = sata_fsl_qc_issue,
1309 .irq_clear = sata_fsl_irq_clear,
1310
1311 .scr_read = sata_fsl_scr_read,
1312 .scr_write = sata_fsl_scr_write,
1313
1314 .freeze = sata_fsl_freeze,
1315 .thaw = sata_fsl_thaw,
1316 .error_handler = sata_fsl_error_handler,
1317 .post_internal_cmd = sata_fsl_post_internal_cmd,
1318
1319 .port_start = sata_fsl_port_start,
1320 .port_stop = sata_fsl_port_stop,
1321 };
1322
1323 static const struct ata_port_info sata_fsl_port_info[] = {
1324 {
1325 .flags = SATA_FSL_HOST_FLAGS,
1326 .link_flags = SATA_FSL_HOST_LFLAGS,
1327 .pio_mask = 0x1f, /* pio 0-4 */
1328 .udma_mask = 0x7f, /* udma 0-6 */
1329 .port_ops = &sata_fsl_ops,
1330 },
1331 };
1332
1333 static int sata_fsl_probe(struct of_device *ofdev,
1334 const struct of_device_id *match)
1335 {
1336 int retval = 0;
1337 void __iomem *hcr_base = NULL;
1338 void __iomem *ssr_base = NULL;
1339 void __iomem *csr_base = NULL;
1340 struct sata_fsl_host_priv *host_priv = NULL;
1341 struct resource *r;
1342 int irq;
1343 struct ata_host *host;
1344
1345 struct ata_port_info pi = sata_fsl_port_info[0];
1346 const struct ata_port_info *ppi[] = { &pi, NULL };
1347
1348 dev_printk(KERN_INFO, &ofdev->dev,
1349 "Sata FSL Platform/CSB Driver init\n");
1350
1351 r = kmalloc(sizeof(struct resource), GFP_KERNEL);
1352
1353 hcr_base = of_iomap(ofdev->node, 0);
1354 if (!hcr_base)
1355 goto error_exit_with_cleanup;
1356
1357 ssr_base = hcr_base + 0x100;
1358 csr_base = hcr_base + 0x140;
1359
1360 DPRINTK("@reset i/o = 0x%x\n", ioread32(csr_base + TRANSCFG));
1361 DPRINTK("sizeof(cmd_desc) = %d\n", sizeof(struct command_desc));
1362 DPRINTK("sizeof(#define cmd_desc) = %d\n", SATA_FSL_CMD_DESC_SIZE);
1363
1364 host_priv = kzalloc(sizeof(struct sata_fsl_host_priv), GFP_KERNEL);
1365 if (!host_priv)
1366 goto error_exit_with_cleanup;
1367
1368 host_priv->hcr_base = hcr_base;
1369 host_priv->ssr_base = ssr_base;
1370 host_priv->csr_base = csr_base;
1371
1372 irq = irq_of_parse_and_map(ofdev->node, 0);
1373 if (irq < 0) {
1374 dev_printk(KERN_ERR, &ofdev->dev, "invalid irq from platform\n");
1375 goto error_exit_with_cleanup;
1376 }
1377 host_priv->irq = irq;
1378
1379 /* allocate host structure */
1380 host = ata_host_alloc_pinfo(&ofdev->dev, ppi, SATA_FSL_MAX_PORTS);
1381
1382 /* host->iomap is not used currently */
1383 host->private_data = host_priv;
1384
1385 /* setup port(s) */
1386
1387 host->ports[0]->ioaddr.cmd_addr = host_priv->hcr_base;
1388 host->ports[0]->ioaddr.scr_addr = host_priv->ssr_base;
1389
1390 /* initialize host controller */
1391 sata_fsl_init_controller(host);
1392
1393 /*
1394 * Now, register with libATA core, this will also initiate the
1395 * device discovery process, invoking our port_start() handler &
1396 * error_handler() to execute a dummy Softreset EH session
1397 */
1398 ata_host_activate(host, irq, sata_fsl_interrupt, SATA_FSL_IRQ_FLAG,
1399 &sata_fsl_sht);
1400
1401 dev_set_drvdata(&ofdev->dev, host);
1402
1403 return 0;
1404
1405 error_exit_with_cleanup:
1406
1407 if (hcr_base)
1408 iounmap(hcr_base);
1409 if (host_priv)
1410 kfree(host_priv);
1411
1412 return retval;
1413 }
1414
1415 static int sata_fsl_remove(struct of_device *ofdev)
1416 {
1417 struct ata_host *host = dev_get_drvdata(&ofdev->dev);
1418 struct sata_fsl_host_priv *host_priv = host->private_data;
1419
1420 ata_host_detach(host);
1421
1422 dev_set_drvdata(&ofdev->dev, NULL);
1423
1424 irq_dispose_mapping(host_priv->irq);
1425 iounmap(host_priv->hcr_base);
1426 kfree(host_priv);
1427
1428 return 0;
1429 }
1430
1431 static struct of_device_id fsl_sata_match[] = {
1432 {
1433 .compatible = "fsl,mpc8315-sata",
1434 },
1435 {
1436 .compatible = "fsl,mpc8379-sata",
1437 },
1438 {},
1439 };
1440
1441 MODULE_DEVICE_TABLE(of, fsl_sata_match);
1442
1443 static struct of_platform_driver fsl_sata_driver = {
1444 .name = "fsl-sata",
1445 .match_table = fsl_sata_match,
1446 .probe = sata_fsl_probe,
1447 .remove = sata_fsl_remove,
1448 };
1449
1450 static int __init sata_fsl_init(void)
1451 {
1452 of_register_platform_driver(&fsl_sata_driver);
1453 return 0;
1454 }
1455
1456 static void __exit sata_fsl_exit(void)
1457 {
1458 of_unregister_platform_driver(&fsl_sata_driver);
1459 }
1460
1461 MODULE_LICENSE("GPL");
1462 MODULE_AUTHOR("Ashish Kalra, Freescale Semiconductor");
1463 MODULE_DESCRIPTION("Freescale 3.0Gbps SATA controller low level driver");
1464 MODULE_VERSION("1.10");
1465
1466 module_init(sata_fsl_init);
1467 module_exit(sata_fsl_exit);
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