1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
31 #include <linux/types.h>
32 #include <linux/pci.h>
33 #include <linux/netdevice.h>
34 #include <linux/aer.h>
36 #include "ixgbe_type.h"
37 #include "ixgbe_common.h"
38 #include "ixgbe_dcb.h"
39 #if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE)
41 #include "ixgbe_fcoe.h"
42 #endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */
43 #ifdef CONFIG_IXGBE_DCA
44 #include <linux/dca.h>
48 #define DPRINTK(nlevel, klevel, fmt, args...) \
49 ((void)((NETIF_MSG_##nlevel & adapter->msg_enable) && \
50 printk(KERN_##klevel PFX "%s: %s: " fmt, adapter->netdev->name, \
53 /* TX/RX descriptor defines */
54 #define IXGBE_DEFAULT_TXD 1024
55 #define IXGBE_MAX_TXD 4096
56 #define IXGBE_MIN_TXD 64
58 #define IXGBE_DEFAULT_RXD 1024
59 #define IXGBE_MAX_RXD 4096
60 #define IXGBE_MIN_RXD 64
63 #define IXGBE_DEFAULT_FCRTL 0x10000
64 #define IXGBE_MIN_FCRTL 0x40
65 #define IXGBE_MAX_FCRTL 0x7FF80
66 #define IXGBE_DEFAULT_FCRTH 0x20000
67 #define IXGBE_MIN_FCRTH 0x600
68 #define IXGBE_MAX_FCRTH 0x7FFF0
69 #define IXGBE_DEFAULT_FCPAUSE 0xFFFF
70 #define IXGBE_MIN_FCPAUSE 0
71 #define IXGBE_MAX_FCPAUSE 0xFFFF
73 /* Supported Rx Buffer Sizes */
74 #define IXGBE_RXBUFFER_64 64 /* Used for packet split */
75 #define IXGBE_RXBUFFER_128 128 /* Used for packet split */
76 #define IXGBE_RXBUFFER_256 256 /* Used for packet split */
77 #define IXGBE_RXBUFFER_2048 2048
78 #define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */
80 #define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256
82 #define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
84 /* How many Rx Buffers do we bundle into one write to the hardware ? */
85 #define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */
87 #define IXGBE_TX_FLAGS_CSUM (u32)(1)
88 #define IXGBE_TX_FLAGS_VLAN (u32)(1 << 1)
89 #define IXGBE_TX_FLAGS_TSO (u32)(1 << 2)
90 #define IXGBE_TX_FLAGS_IPV4 (u32)(1 << 3)
91 #define IXGBE_TX_FLAGS_FCOE (u32)(1 << 4)
92 #define IXGBE_TX_FLAGS_FSO (u32)(1 << 5)
93 #define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000
94 #define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0x0000e000
95 #define IXGBE_TX_FLAGS_VLAN_SHIFT 16
97 /* wrapper around a pointer to a socket buffer,
98 * so a DMA handle can be stored along with the buffer */
99 struct ixgbe_tx_buffer
{
102 unsigned long time_stamp
;
107 struct ixgbe_rx_buffer
{
112 unsigned int page_offset
;
115 struct ixgbe_queue_stats
{
121 void *desc
; /* descriptor ring memory */
122 dma_addr_t dma
; /* phys. address of descriptor ring */
123 unsigned int size
; /* length in bytes */
124 unsigned int count
; /* amount of descriptors */
125 unsigned int next_to_use
;
126 unsigned int next_to_clean
;
128 int queue_index
; /* needed for multiqueue queue management */
130 struct ixgbe_tx_buffer
*tx_buffer_info
;
131 struct ixgbe_rx_buffer
*rx_buffer_info
;
137 unsigned int total_bytes
;
138 unsigned int total_packets
;
140 u16 reg_idx
; /* holds the special value that gets the hardware register
141 * offset associated with this ring, which is different
142 * for DCB and RSS modes */
144 #ifdef CONFIG_IXGBE_DCA
145 /* cpu for tx queue */
148 struct ixgbe_queue_stats stats
;
149 u64 v_idx
; /* maps directly to the index for this ring in the hardware
150 * vector array, can also be used for finding the bit in EICR
151 * and friends that represents the vector for this ring */
154 u16 work_limit
; /* max work per interrupt */
156 u64 rsc_count
; /* stat for coalesced packets */
159 enum ixgbe_ring_f_enum
{
166 #endif /* IXGBE_FCOE */
168 RING_F_ARRAY_SIZE
/* must be last in enum set */
171 #define IXGBE_MAX_DCB_INDICES 8
172 #define IXGBE_MAX_RSS_INDICES 16
173 #define IXGBE_MAX_VMDQ_INDICES 16
175 #define IXGBE_MAX_FCOE_INDICES 8
176 #endif /* IXGBE_FCOE */
177 struct ixgbe_ring_feature
{
182 #define MAX_RX_QUEUES 128
183 #define MAX_TX_QUEUES 128
185 #define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \
187 #define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS
189 /* MAX_MSIX_Q_VECTORS of these are allocated,
190 * but we only use one per queue-specific vector.
192 struct ixgbe_q_vector
{
193 struct ixgbe_adapter
*adapter
;
194 struct napi_struct napi
;
195 DECLARE_BITMAP(rxr_idx
, MAX_RX_QUEUES
); /* Rx ring indices */
196 DECLARE_BITMAP(txr_idx
, MAX_TX_QUEUES
); /* Tx ring indices */
197 u8 rxr_count
; /* Rx ring count assigned to this vector */
198 u8 txr_count
; /* Tx ring count assigned to this vector */
202 u32 v_idx
; /* vector index in list */
205 /* Helper macros to switch between ints/sec and what the register uses.
206 * And yes, it's the same math going both ways. The lowest value
207 * supported by all of the ixgbe hardware is 8.
209 #define EITR_INTS_PER_SEC_TO_REG(_eitr) \
210 ((_eitr) ? (1000000000 / ((_eitr) * 256)) : 8)
211 #define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG
213 #define IXGBE_DESC_UNUSED(R) \
214 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
215 (R)->next_to_clean - (R)->next_to_use - 1)
217 #define IXGBE_RX_DESC_ADV(R, i) \
218 (&(((union ixgbe_adv_rx_desc *)((R).desc))[i]))
219 #define IXGBE_TX_DESC_ADV(R, i) \
220 (&(((union ixgbe_adv_tx_desc *)((R).desc))[i]))
221 #define IXGBE_TX_CTXTDESC_ADV(R, i) \
222 (&(((struct ixgbe_adv_tx_context_desc *)((R).desc))[i]))
224 #define IXGBE_MAX_JUMBO_FRAME_SIZE 16128
226 #define OTHER_VECTOR 1
227 #define NON_Q_VECTORS (OTHER_VECTOR)
229 #define MAX_MSIX_VECTORS_82599 64
230 #define MAX_MSIX_Q_VECTORS_82599 64
231 #define MAX_MSIX_VECTORS_82598 18
232 #define MAX_MSIX_Q_VECTORS_82598 16
234 #define MAX_MSIX_Q_VECTORS MAX_MSIX_Q_VECTORS_82599
235 #define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599
237 #define MIN_MSIX_Q_VECTORS 2
238 #define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
240 /* board specific private data structure */
241 struct ixgbe_adapter
{
242 struct timer_list watchdog_timer
;
243 struct vlan_group
*vlgrp
;
245 struct work_struct reset_task
;
246 struct ixgbe_q_vector
*q_vector
[MAX_MSIX_Q_VECTORS
];
247 char name
[MAX_MSIX_COUNT
][IFNAMSIZ
+ 9];
248 struct ixgbe_dcb_config dcb_cfg
;
249 struct ixgbe_dcb_config temp_dcb_cfg
;
252 /* Interrupt Throttle Rate */
258 struct ixgbe_ring
*tx_ring
; /* One per active queue */
265 u32 tx_timeout_count
;
269 struct ixgbe_ring
*rx_ring
; /* One per active queue */
271 u64 hw_csum_rx_error
;
272 u64 hw_rx_no_dma_resources
;
275 int num_msix_vectors
;
276 int max_msix_q_vectors
; /* true count of q_vectors for device */
277 struct ixgbe_ring_feature ring_feature
[RING_F_ARRAY_SIZE
];
278 struct msix_entry
*msix_entries
;
281 u32 alloc_rx_page_failed
;
282 u32 alloc_rx_buff_failed
;
284 /* Some features need tri-state capability,
285 * thus the additional *_CAPABLE flags.
288 #define IXGBE_FLAG_RX_CSUM_ENABLED (u32)(1)
289 #define IXGBE_FLAG_MSI_CAPABLE (u32)(1 << 1)
290 #define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 2)
291 #define IXGBE_FLAG_MSIX_CAPABLE (u32)(1 << 3)
292 #define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 4)
293 #define IXGBE_FLAG_RX_1BUF_CAPABLE (u32)(1 << 6)
294 #define IXGBE_FLAG_RX_PS_CAPABLE (u32)(1 << 7)
295 #define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 8)
296 #define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 9)
297 #define IXGBE_FLAG_DCA_ENABLED (u32)(1 << 10)
298 #define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 11)
299 #define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 12)
300 #define IXGBE_FLAG_MQ_CAPABLE (u32)(1 << 13)
301 #define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 14)
302 #define IXGBE_FLAG_RSS_ENABLED (u32)(1 << 16)
303 #define IXGBE_FLAG_RSS_CAPABLE (u32)(1 << 17)
304 #define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 18)
305 #define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 19)
306 #define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 20)
307 #define IXGBE_FLAG_NEED_LINK_UPDATE (u32)(1 << 22)
308 #define IXGBE_FLAG_IN_WATCHDOG_TASK (u32)(1 << 23)
309 #define IXGBE_FLAG_IN_SFP_LINK_TASK (u32)(1 << 24)
310 #define IXGBE_FLAG_IN_SFP_MOD_TASK (u32)(1 << 25)
311 #define IXGBE_FLAG_RSC_CAPABLE (u32)(1 << 26)
312 #define IXGBE_FLAG_RSC_ENABLED (u32)(1 << 27)
313 #define IXGBE_FLAG_FCOE_ENABLED (u32)(1 << 29)
315 /* default to trying for four seconds */
316 #define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)
318 /* OS defined structs */
319 struct net_device
*netdev
;
320 struct pci_dev
*pdev
;
321 struct net_device_stats net_stats
;
323 /* structs defined in ixgbe_hw.h */
326 struct ixgbe_hw_stats stats
;
328 /* Interrupt Throttle Rate */
333 unsigned int tx_ring_count
;
334 unsigned int rx_ring_count
;
338 unsigned long link_check_timeout
;
340 struct work_struct watchdog_task
;
341 struct work_struct sfp_task
;
342 struct timer_list sfp_timer
;
343 struct work_struct multispeed_fiber_task
;
344 struct work_struct sfp_config_module_task
;
346 struct ixgbe_fcoe fcoe
;
347 #endif /* IXGBE_FCOE */
357 __IXGBE_SFP_MODULE_NOT_FOUND
365 extern struct ixgbe_info ixgbe_82598_info
;
366 extern struct ixgbe_info ixgbe_82599_info
;
367 #ifdef CONFIG_IXGBE_DCB
368 extern struct dcbnl_rtnl_ops dcbnl_ops
;
369 extern int ixgbe_copy_dcb_cfg(struct ixgbe_dcb_config
*src_dcb_cfg
,
370 struct ixgbe_dcb_config
*dst_dcb_cfg
,
374 extern char ixgbe_driver_name
[];
375 extern const char ixgbe_driver_version
[];
377 extern int ixgbe_up(struct ixgbe_adapter
*adapter
);
378 extern void ixgbe_down(struct ixgbe_adapter
*adapter
);
379 extern void ixgbe_reinit_locked(struct ixgbe_adapter
*adapter
);
380 extern void ixgbe_reset(struct ixgbe_adapter
*adapter
);
381 extern void ixgbe_set_ethtool_ops(struct net_device
*netdev
);
382 extern int ixgbe_setup_rx_resources(struct ixgbe_adapter
*, struct ixgbe_ring
*);
383 extern int ixgbe_setup_tx_resources(struct ixgbe_adapter
*, struct ixgbe_ring
*);
384 extern void ixgbe_free_rx_resources(struct ixgbe_adapter
*, struct ixgbe_ring
*);
385 extern void ixgbe_free_tx_resources(struct ixgbe_adapter
*, struct ixgbe_ring
*);
386 extern void ixgbe_update_stats(struct ixgbe_adapter
*adapter
);
387 extern int ixgbe_init_interrupt_scheme(struct ixgbe_adapter
*adapter
);
388 extern void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter
*adapter
);
389 extern void ixgbe_write_eitr(struct ixgbe_adapter
*, int, u32
);
391 extern void ixgbe_configure_fcoe(struct ixgbe_adapter
*adapter
);
392 extern int ixgbe_fso(struct ixgbe_adapter
*adapter
,
393 struct ixgbe_ring
*tx_ring
, struct sk_buff
*skb
,
394 u32 tx_flags
, u8
*hdr_len
);
395 extern void ixgbe_cleanup_fcoe(struct ixgbe_adapter
*adapter
);
396 extern int ixgbe_fcoe_ddp(struct ixgbe_adapter
*adapter
,
397 union ixgbe_adv_rx_desc
*rx_desc
,
398 struct sk_buff
*skb
);
399 extern int ixgbe_fcoe_ddp_get(struct net_device
*netdev
, u16 xid
,
400 struct scatterlist
*sgl
, unsigned int sgc
);
401 extern int ixgbe_fcoe_ddp_put(struct net_device
*netdev
, u16 xid
);
402 #endif /* IXGBE_FCOE */
404 #endif /* _IXGBE_H_ */