1 #include <linux/init.h>
2 #include <linux/kernel.h>
4 #include <linux/string.h>
5 #include <linux/bitops.h>
7 #include <linux/thread_info.h>
8 #include <linux/module.h>
10 #include <asm/processor.h>
11 #include <asm/pgtable.h>
13 #include <asm/uaccess.h>
19 #include <asm/topology.h>
20 #include <asm/numa_64.h>
25 #ifdef CONFIG_X86_LOCAL_APIC
26 #include <asm/mpspec.h>
30 static void __cpuinit
early_init_intel(struct cpuinfo_x86
*c
)
32 /* Unmask CPUID levels if masked: */
33 if (c
->x86
> 6 || (c
->x86
== 6 && c
->x86_model
>= 0xd)) {
36 rdmsrl(MSR_IA32_MISC_ENABLE
, misc_enable
);
38 if (misc_enable
& MSR_IA32_MISC_ENABLE_LIMIT_CPUID
) {
39 misc_enable
&= ~MSR_IA32_MISC_ENABLE_LIMIT_CPUID
;
40 wrmsrl(MSR_IA32_MISC_ENABLE
, misc_enable
);
41 c
->cpuid_level
= cpuid_eax(0);
45 if ((c
->x86
== 0xf && c
->x86_model
>= 0x03) ||
46 (c
->x86
== 0x6 && c
->x86_model
>= 0x0e))
47 set_cpu_cap(c
, X86_FEATURE_CONSTANT_TSC
);
50 set_cpu_cap(c
, X86_FEATURE_SYSENTER32
);
52 /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
53 if (c
->x86
== 15 && c
->x86_cache_alignment
== 64)
54 c
->x86_cache_alignment
= 128;
58 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
59 * with P/T states and does not stop in deep C-states
61 if (c
->x86_power
& (1 << 8)) {
62 set_cpu_cap(c
, X86_FEATURE_CONSTANT_TSC
);
63 set_cpu_cap(c
, X86_FEATURE_NONSTOP_TSC
);
67 * There is a known erratum on Pentium III and Core Solo
69 * " Page with PAT set to WC while associated MTRR is UC
70 * may consolidate to UC "
71 * Because of this erratum, it is better to stick with
72 * setting WC in MTRR rather than using PAT on these CPUs.
74 * Enable PAT WC only on P4, Core 2 or later CPUs.
76 if (c
->x86
== 6 && c
->x86_model
< 15)
77 clear_cpu_cap(c
, X86_FEATURE_PAT
);
82 * Early probe support logic for ppro memory erratum #50
84 * This is called before we do cpu ident work
87 int __cpuinit
ppro_with_ram_bug(void)
89 /* Uses data from early_cpu_detect now */
90 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
&&
91 boot_cpu_data
.x86
== 6 &&
92 boot_cpu_data
.x86_model
== 1 &&
93 boot_cpu_data
.x86_mask
< 8) {
94 printk(KERN_INFO
"Pentium Pro with Errata#50 detected. Taking evasive action.\n");
100 #ifdef CONFIG_X86_F00F_BUG
101 static void __cpuinit
trap_init_f00f_bug(void)
103 __set_fixmap(FIX_F00F_IDT
, __pa(&idt_table
), PAGE_KERNEL_RO
);
106 * Update the IDT descriptor and reload the IDT so that
107 * it uses the read-only mapped virtual address.
109 idt_descr
.address
= fix_to_virt(FIX_F00F_IDT
);
110 load_idt(&idt_descr
);
114 static void __cpuinit
intel_smp_check(struct cpuinfo_x86
*c
)
117 /* calling is from identify_secondary_cpu() ? */
118 if (c
->cpu_index
== boot_cpu_id
)
122 * Mask B, Pentium, but not Pentium MMX
125 c
->x86_mask
>= 1 && c
->x86_mask
<= 4 &&
128 * Remember we have B step Pentia with bugs
130 WARN_ONCE(1, "WARNING: SMP operation may be unreliable"
131 "with B stepping processors.\n");
136 static void __cpuinit
intel_workarounds(struct cpuinfo_x86
*c
)
138 unsigned long lo
, hi
;
140 #ifdef CONFIG_X86_F00F_BUG
142 * All current models of Pentium and Pentium with MMX technology CPUs
143 * have the F0 0F bug, which lets nonprivileged users lock up the system.
144 * Note that the workaround only should be initialized once...
147 if (!paravirt_enabled() && c
->x86
== 5) {
148 static int f00f_workaround_enabled
;
151 if (!f00f_workaround_enabled
) {
152 trap_init_f00f_bug();
153 printk(KERN_NOTICE
"Intel Pentium with F0 0F bug - workaround enabled.\n");
154 f00f_workaround_enabled
= 1;
160 * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until
163 if ((c
->x86
<<8 | c
->x86_model
<<4 | c
->x86_mask
) < 0x633)
164 clear_cpu_cap(c
, X86_FEATURE_SEP
);
167 * P4 Xeon errata 037 workaround.
168 * Hardware prefetcher may cause stale data to be loaded into the cache.
170 if ((c
->x86
== 15) && (c
->x86_model
== 1) && (c
->x86_mask
== 1)) {
171 rdmsr(MSR_IA32_MISC_ENABLE
, lo
, hi
);
172 if ((lo
& MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE
) == 0) {
173 printk (KERN_INFO
"CPU: C0 stepping P4 Xeon detected.\n");
174 printk (KERN_INFO
"CPU: Disabling hardware prefetching (Errata 037)\n");
175 lo
|= MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE
;
176 wrmsr (MSR_IA32_MISC_ENABLE
, lo
, hi
);
181 * See if we have a good local APIC by checking for buggy Pentia,
182 * i.e. all B steppings and the C2 stepping of P54C when using their
183 * integrated APIC (see 11AP erratum in "Pentium Processor
184 * Specification Update").
186 if (cpu_has_apic
&& (c
->x86
<<8 | c
->x86_model
<<4) == 0x520 &&
187 (c
->x86_mask
< 0x6 || c
->x86_mask
== 0xb))
188 set_cpu_cap(c
, X86_FEATURE_11AP
);
191 #ifdef CONFIG_X86_INTEL_USERCOPY
193 * Set up the preferred alignment for movsl bulk memory moves
196 case 4: /* 486: untested */
198 case 5: /* Old Pentia: untested */
200 case 6: /* PII/PIII only like movsl with 8-byte alignment */
203 case 15: /* P4 is OK down to 8-byte alignment */
209 #ifdef CONFIG_X86_NUMAQ
216 static void __cpuinit
intel_workarounds(struct cpuinfo_x86
*c
)
221 static void __cpuinit
srat_detect_node(void)
223 #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64)
225 int cpu
= smp_processor_id();
226 int apicid
= hard_smp_processor_id();
228 /* Don't do the funky fallback heuristics the AMD version employs
230 node
= apicid_to_node
[apicid
];
231 if (node
== NUMA_NO_NODE
|| !node_online(node
))
232 node
= first_node(node_online_map
);
233 numa_set_node(cpu
, node
);
235 printk(KERN_INFO
"CPU %d/0x%x -> Node %d\n", cpu
, apicid
, node
);
240 * find out the number of processor cores on the die
242 static int __cpuinit
intel_num_cpu_cores(struct cpuinfo_x86
*c
)
244 unsigned int eax
, ebx
, ecx
, edx
;
246 if (c
->cpuid_level
< 4)
249 /* Intel has a non-standard dependency on %ecx for this CPUID level. */
250 cpuid_count(4, 0, &eax
, &ebx
, &ecx
, &edx
);
252 return ((eax
>> 26) + 1);
257 static void __cpuinit
detect_vmx_virtcap(struct cpuinfo_x86
*c
)
259 /* Intel VMX MSR indicated features */
260 #define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW 0x00200000
261 #define X86_VMX_FEATURE_PROC_CTLS_VNMI 0x00400000
262 #define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS 0x80000000
263 #define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC 0x00000001
264 #define X86_VMX_FEATURE_PROC_CTLS2_EPT 0x00000002
265 #define X86_VMX_FEATURE_PROC_CTLS2_VPID 0x00000020
267 u32 vmx_msr_low
, vmx_msr_high
, msr_ctl
, msr_ctl2
;
269 clear_cpu_cap(c
, X86_FEATURE_TPR_SHADOW
);
270 clear_cpu_cap(c
, X86_FEATURE_VNMI
);
271 clear_cpu_cap(c
, X86_FEATURE_FLEXPRIORITY
);
272 clear_cpu_cap(c
, X86_FEATURE_EPT
);
273 clear_cpu_cap(c
, X86_FEATURE_VPID
);
275 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS
, vmx_msr_low
, vmx_msr_high
);
276 msr_ctl
= vmx_msr_high
| vmx_msr_low
;
277 if (msr_ctl
& X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW
)
278 set_cpu_cap(c
, X86_FEATURE_TPR_SHADOW
);
279 if (msr_ctl
& X86_VMX_FEATURE_PROC_CTLS_VNMI
)
280 set_cpu_cap(c
, X86_FEATURE_VNMI
);
281 if (msr_ctl
& X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS
) {
282 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2
,
283 vmx_msr_low
, vmx_msr_high
);
284 msr_ctl2
= vmx_msr_high
| vmx_msr_low
;
285 if ((msr_ctl2
& X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC
) &&
286 (msr_ctl
& X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW
))
287 set_cpu_cap(c
, X86_FEATURE_FLEXPRIORITY
);
288 if (msr_ctl2
& X86_VMX_FEATURE_PROC_CTLS2_EPT
)
289 set_cpu_cap(c
, X86_FEATURE_EPT
);
290 if (msr_ctl2
& X86_VMX_FEATURE_PROC_CTLS2_VPID
)
291 set_cpu_cap(c
, X86_FEATURE_VPID
);
295 static void __cpuinit
init_intel(struct cpuinfo_x86
*c
)
301 intel_workarounds(c
);
304 * Detect the extended topology information if available. This
305 * will reinitialise the initial_apicid which will be used
306 * in init_intel_cacheinfo()
308 detect_extended_topology(c
);
310 l2
= init_intel_cacheinfo(c
);
311 if (c
->cpuid_level
> 9) {
312 unsigned eax
= cpuid_eax(10);
313 /* Check for version and the number of counters */
314 if ((eax
& 0xff) && (((eax
>>8) & 0xff) > 1))
315 set_cpu_cap(c
, X86_FEATURE_ARCH_PERFMON
);
319 set_cpu_cap(c
, X86_FEATURE_LFENCE_RDTSC
);
322 rdmsr(MSR_IA32_MISC_ENABLE
, l1
, l2
);
324 set_cpu_cap(c
, X86_FEATURE_BTS
);
326 set_cpu_cap(c
, X86_FEATURE_PEBS
);
330 if (c
->x86
== 6 && c
->x86_model
== 29 && cpu_has_clflush
)
331 set_cpu_cap(c
, X86_FEATURE_CLFLUSH_MONITOR
);
335 c
->x86_cache_alignment
= c
->x86_clflush_size
* 2;
337 set_cpu_cap(c
, X86_FEATURE_REP_GOOD
);
340 * Names for the Pentium II/Celeron processors
341 * detectable only by also checking the cache size.
342 * Dixon is NOT a Celeron.
347 switch (c
->x86_model
) {
349 if (c
->x86_mask
== 0) {
351 p
= "Celeron (Covington)";
353 p
= "Mobile Pentium II (Dixon)";
359 p
= "Celeron (Mendocino)";
360 else if (c
->x86_mask
== 0 || c
->x86_mask
== 5)
366 p
= "Celeron (Coppermine)";
371 strcpy(c
->x86_model_id
, p
);
375 set_cpu_cap(c
, X86_FEATURE_P4
);
377 set_cpu_cap(c
, X86_FEATURE_P3
);
380 if (!cpu_has(c
, X86_FEATURE_XTOPOLOGY
)) {
382 * let's use the legacy cpuid vector 0x1 and 0x4 for topology
385 c
->x86_max_cores
= intel_num_cpu_cores(c
);
391 /* Work around errata */
394 if (cpu_has(c
, X86_FEATURE_VMX
))
395 detect_vmx_virtcap(c
);
399 static unsigned int __cpuinit
intel_size_cache(struct cpuinfo_x86
*c
, unsigned int size
)
402 * Intel PIII Tualatin. This comes in two flavours.
403 * One has 256kb of cache, the other 512. We have no way
404 * to determine which, so we use a boottime override
405 * for the 512kb model, and assume 256 otherwise.
407 if ((c
->x86
== 6) && (c
->x86_model
== 11) && (size
== 0))
413 static const struct cpu_dev __cpuinitconst intel_cpu_dev
= {
415 .c_ident
= { "GenuineIntel" },
418 { .vendor
= X86_VENDOR_INTEL
, .family
= 4, .model_names
=
420 [0] = "486 DX-25/33",
431 { .vendor
= X86_VENDOR_INTEL
, .family
= 5, .model_names
=
433 [0] = "Pentium 60/66 A-step",
434 [1] = "Pentium 60/66",
435 [2] = "Pentium 75 - 200",
436 [3] = "OverDrive PODP5V83",
438 [7] = "Mobile Pentium 75 - 200",
439 [8] = "Mobile Pentium MMX"
442 { .vendor
= X86_VENDOR_INTEL
, .family
= 6, .model_names
=
444 [0] = "Pentium Pro A-step",
446 [3] = "Pentium II (Klamath)",
447 [4] = "Pentium II (Deschutes)",
448 [5] = "Pentium II (Deschutes)",
449 [6] = "Mobile Pentium II",
450 [7] = "Pentium III (Katmai)",
451 [8] = "Pentium III (Coppermine)",
452 [10] = "Pentium III (Cascades)",
453 [11] = "Pentium III (Tualatin)",
456 { .vendor
= X86_VENDOR_INTEL
, .family
= 15, .model_names
=
458 [0] = "Pentium 4 (Unknown)",
459 [1] = "Pentium 4 (Willamette)",
460 [2] = "Pentium 4 (Northwood)",
461 [4] = "Pentium 4 (Foster)",
462 [5] = "Pentium 4 (Foster)",
466 .c_size_cache
= intel_size_cache
,
468 .c_early_init
= early_init_intel
,
469 .c_init
= init_intel
,
470 .c_x86_vendor
= X86_VENDOR_INTEL
,
473 cpu_dev_register(intel_cpu_dev
);