drivers/usb/host/ehci-pci.c

   1 /*
   2  * EHCI HCD (Host Controller Driver) PCI Bus Glue.
   3  *
   4  * Copyright (c) 2000-2004 by David Brownell
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License as published by the
   8  * Free Software Foundation; either version 2 of the License, or (at your
   9  * option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful, but
  12  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  14  * for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software Foundation,
  18  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19  */
  20
  21 #ifndef CONFIG_PCI
  22 #error "This file is PCI bus glue.  CONFIG_PCI must be defined."
  23 #endif
  24
  25 /*-------------------------------------------------------------------------*/
  26
  27 /* EHCI 0.96 (and later) section 5.1 says how to kick BIOS/SMM/...
  28  * off the controller (maybe it can boot from highspeed USB disks).
  29  */
  30 static int bios_handoff (struct ehci_hcd *ehci, int where, u32 cap)
  31 {
  32         struct pci_dev *pdev = to_pci_dev(ehci_to_hcd(ehci)->self.controller);
  33
  34         /* always say Linux will own the hardware */
  35         pci_write_config_byte(pdev, where + 3, 1);
  36
  37         /* maybe wait a while for BIOS to respond */
  38         if (cap & (1 << 16)) {
  39                 int msec = 5000;
  40
  41                 do {
  42                         msleep(10);
  43                         msec -= 10;
  44                         pci_read_config_dword(pdev, where, &cap);
  45                 } while ((cap & (1 << 16)) && msec);
  46                 if (cap & (1 << 16)) {
  47                         ehci_err(ehci, "BIOS handoff failed (%d, %08x)\n",
  48                                 where, cap);
  49                         // some BIOS versions seem buggy...
  50                         // return 1;
  51                         ehci_warn (ehci, "continuing after BIOS bug...\n");
  52                         /* disable all SMIs, and clear "BIOS owns" flag */
  53                         pci_write_config_dword(pdev, where + 4, 0);
  54                         pci_write_config_byte(pdev, where + 2, 0);
  55                 } else
  56                         ehci_dbg(ehci, "BIOS handoff succeeded\n");
  57         }
  58         return 0;
  59 }
  60
  61 /* called by khubd or root hub init threads */
  62 static int ehci_pci_reset (struct usb_hcd *hcd)
  63 {
  64         struct ehci_hcd         *ehci = hcd_to_ehci (hcd);
  65         u32                     temp;
  66         unsigned                count = 256/4;
  67
  68         spin_lock_init (&ehci->lock);
  69
  70         ehci->caps = hcd->regs;
  71         ehci->regs = hcd->regs + HC_LENGTH (readl (&ehci->caps->hc_capbase));
  72         dbg_hcs_params (ehci, "reset");
  73         dbg_hcc_params (ehci, "reset");
  74
  75         /* cache this readonly data; minimize chip reads */
  76         ehci->hcs_params = readl (&ehci->caps->hcs_params);
  77
  78         if (hcd->self.controller->bus == &pci_bus_type) {
  79                 struct pci_dev  *pdev = to_pci_dev(hcd->self.controller);
  80
  81                 switch (pdev->vendor) {
  82                 case PCI_VENDOR_ID_TDI:
  83                         if (pdev->device == PCI_DEVICE_ID_TDI_EHCI) {
  84                                 ehci->is_tdi_rh_tt = 1;
  85                                 tdi_reset (ehci);
  86                         }
  87                         break;
  88                 case PCI_VENDOR_ID_AMD:
  89                         /* AMD8111 EHCI doesn't work, according to AMD errata */
  90                         if (pdev->device == 0x7463) {
  91                                 ehci_info (ehci, "ignoring AMD8111 (errata)\n");
  92                                 return -EIO;
  93                         }
  94                         break;
  95                 case PCI_VENDOR_ID_NVIDIA:
  96                         /* NVidia reports that certain chips don't handle
  97                          * QH, ITD, or SITD addresses above 2GB.  (But TD,
  98                          * data buffer, and periodic schedule are normal.)
  99                          */
 100                         switch (pdev->device) {
 101                         case 0x003c:    /* MCP04 */
 102                         case 0x005b:    /* CK804 */
 103                         case 0x00d8:    /* CK8 */
 104                         case 0x00e8:    /* CK8S */
 105                                 if (pci_set_consistent_dma_mask(pdev,
 106                                                         DMA_31BIT_MASK) < 0)
 107                                         ehci_warn (ehci, "can't enable NVidia "
 108                                                 "workaround for >2GB RAM\n");
 109                                 break;
 110                         }
 111                         break;
 112                 }
 113
 114                 /* optional debug port, normally in the first BAR */
 115                 temp = pci_find_capability (pdev, 0x0a);
 116                 if (temp) {
 117                         pci_read_config_dword(pdev, temp, &temp);
 118                         temp >>= 16;
 119                         if ((temp & (3 << 13)) == (1 << 13)) {
 120                                 temp &= 0x1fff;
 121                                 ehci->debug = hcd->regs + temp;
 122                                 temp = readl (&ehci->debug->control);
 123                                 ehci_info (ehci, "debug port %d%s\n",
 124                                         HCS_DEBUG_PORT(ehci->hcs_params),
 125                                         (temp & DBGP_ENABLED)
 126                                                 ? " IN USE"
 127                                                 : "");
 128                                 if (!(temp & DBGP_ENABLED))
 129                                         ehci->debug = NULL;
 130                         }
 131                 }
 132
 133                 temp = HCC_EXT_CAPS (readl (&ehci->caps->hcc_params));
 134         } else
 135                 temp = 0;
 136
 137         /* EHCI 0.96 and later may have "extended capabilities" */
 138         while (temp && count--) {
 139                 u32             cap;
 140
 141                 pci_read_config_dword (to_pci_dev(hcd->self.controller),
 142                                 temp, &cap);
 143                 ehci_dbg (ehci, "capability %04x at %02x\n", cap, temp);
 144                 switch (cap & 0xff) {
 145                 case 1:                 /* BIOS/SMM/... handoff */
 146                         if (bios_handoff (ehci, temp, cap) != 0)
 147                                 return -EOPNOTSUPP;
 148                         break;
 149                 case 0:                 /* illegal reserved capability */
 150                         ehci_warn (ehci, "illegal capability!\n");
 151                         cap = 0;
 152                         /* FALLTHROUGH */
 153                 default:                /* unknown */
 154                         break;
 155                 }
 156                 temp = (cap >> 8) & 0xff;
 157         }
 158         if (!count) {
 159                 ehci_err (ehci, "bogus capabilities ... PCI problems!\n");
 160                 return -EIO;
 161         }
 162         if (ehci_is_TDI(ehci))
 163                 ehci_reset (ehci);
 164
 165         ehci_port_power (ehci, 0);
 166
 167         /* at least the Genesys GL880S needs fixup here */
 168         temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params);
 169         temp &= 0x0f;
 170         if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) {
 171                 ehci_dbg (ehci, "bogus port configuration: "
 172                         "cc=%d x pcc=%d < ports=%d\n",
 173                         HCS_N_CC(ehci->hcs_params),
 174                         HCS_N_PCC(ehci->hcs_params),
 175                         HCS_N_PORTS(ehci->hcs_params));
 176
 177                 if (hcd->self.controller->bus == &pci_bus_type) {
 178                         struct pci_dev  *pdev;
 179
 180                         pdev = to_pci_dev(hcd->self.controller);
 181                         switch (pdev->vendor) {
 182                         case 0x17a0:            /* GENESYS */
 183                                 /* GL880S: should be PORTS=2 */
 184                                 temp |= (ehci->hcs_params & ~0xf);
 185                                 ehci->hcs_params = temp;
 186                                 break;
 187                         case PCI_VENDOR_ID_NVIDIA:
 188                                 /* NF4: should be PCC=10 */
 189                                 break;
 190                         }
 191                 }
 192         }
 193
 194         /* force HC to halt state */
 195         return ehci_halt (ehci);
 196 }
 197
 198 static int ehci_pci_start (struct usb_hcd *hcd)
 199 {
 200         struct ehci_hcd         *ehci = hcd_to_ehci (hcd);
 201         int result = 0;
 202
 203         if (hcd->self.controller->bus == &pci_bus_type) {
 204                 struct pci_dev          *pdev;
 205                 u16                     port_wake;
 206
 207                 pdev = to_pci_dev(hcd->self.controller);
 208
 209                 /* Serial Bus Release Number is at PCI 0x60 offset */
 210                 pci_read_config_byte(pdev, 0x60, &ehci->sbrn);
 211
 212                 /* port wake capability, reported by boot firmware */
 213                 pci_read_config_word(pdev, 0x62, &port_wake);
 214                 hcd->can_wakeup = (port_wake & 1) != 0;
 215
 216                 /* help hc dma work well with cachelines */
 217                 result = pci_set_mwi(pdev);
 218                 if (result)
 219                         ehci_dbg(ehci, "unable to enable MWI - not fatal.\n");
 220         }
 221
 222         return ehci_run (hcd);
 223 }
 224
 225 /* always called by thread; normally rmmod */
 226
 227 static void ehci_pci_stop (struct usb_hcd *hcd)
 228 {
 229         ehci_stop (hcd);
 230 }
 231
 232 /*-------------------------------------------------------------------------*/
 233
 234 #ifdef  CONFIG_PM
 235
 236 /* suspend/resume, section 4.3 */
 237
 238 /* These routines rely on the bus (pci, platform, etc)
 239  * to handle powerdown and wakeup, and currently also on
 240  * transceivers that don't need any software attention to set up
 241  * the right sort of wakeup.
 242  */
 243
 244 static int ehci_pci_suspend (struct usb_hcd *hcd, pm_message_t message)
 245 {
 246         struct ehci_hcd         *ehci = hcd_to_ehci (hcd);
 247
 248         if (time_before (jiffies, ehci->next_statechange))
 249                 msleep (100);
 250
 251 #ifdef  CONFIG_USB_SUSPEND
 252         (void) usb_suspend_device (hcd->self.root_hub);
 253 #else
 254         usb_lock_device (hcd->self.root_hub);
 255         (void) ehci_hub_suspend (hcd);
 256         usb_unlock_device (hcd->self.root_hub);
 257 #endif
 258
 259         // save (PCI) FLADJ in case of Vaux power loss
 260         // ... we'd only use it to handle clock skew
 261
 262         return 0;
 263 }
 264
 265 static int ehci_pci_resume (struct usb_hcd *hcd)
 266 {
 267         struct ehci_hcd         *ehci = hcd_to_ehci (hcd);
 268         unsigned                port;
 269         struct usb_device       *root = hcd->self.root_hub;
 270         int                     retval = -EINVAL;
 271
 272         // maybe restore (PCI) FLADJ
 273
 274         if (time_before (jiffies, ehci->next_statechange))
 275                 msleep (100);
 276
 277         /* If any port is suspended (or owned by the companion),
 278          * we know we can/must resume the HC (and mustn't reset it).
 279          */
 280         for (port = HCS_N_PORTS (ehci->hcs_params); port > 0; ) {
 281                 u32     status;
 282                 port--;
 283                 status = readl (&ehci->regs->port_status [port]);
 284                 if (!(status & PORT_POWER))
 285                         continue;
 286                 if (status & (PORT_SUSPEND | PORT_OWNER)) {
 287                         down (&hcd->self.root_hub->serialize);
 288                         retval = ehci_hub_resume (hcd);
 289                         up (&hcd->self.root_hub->serialize);
 290                         break;
 291                 }
 292                 if (!root->children [port])
 293                         continue;
 294                 dbg_port (ehci, __FUNCTION__, port + 1, status);
 295                 usb_set_device_state (root->children[port],
 296                                         USB_STATE_NOTATTACHED);
 297         }
 298
 299         /* Else reset, to cope with power loss or flush-to-storage
 300          * style "resume" having activated BIOS during reboot.
 301          */
 302         if (port == 0) {
 303                 (void) ehci_halt (ehci);
 304                 (void) ehci_reset (ehci);
 305                 (void) ehci_pci_reset (hcd);
 306
 307                 /* emptying the schedule aborts any urbs */
 308                 spin_lock_irq (&ehci->lock);
 309                 if (ehci->reclaim)
 310                         ehci->reclaim_ready = 1;
 311                 ehci_work (ehci, NULL);
 312                 spin_unlock_irq (&ehci->lock);
 313
 314                 /* restart; khubd will disconnect devices */
 315                 retval = ehci_run (hcd);
 316
 317                 /* here we "know" root ports should always stay powered;
 318                  * but some controllers may lose all power.
 319                  */
 320                 ehci_port_power (ehci, 1);
 321         }
 322
 323         return retval;
 324 }
 325 #endif
 326
 327 static const struct hc_driver ehci_pci_hc_driver = {
 328         .description =          hcd_name,
 329         .product_desc =         "EHCI Host Controller",
 330         .hcd_priv_size =        sizeof(struct ehci_hcd),
 331
 332         /*
 333          * generic hardware linkage
 334          */
 335         .irq =                  ehci_irq,
 336         .flags =                HCD_MEMORY | HCD_USB2,
 337
 338         /*
 339          * basic lifecycle operations
 340          */
 341         .reset =                ehci_pci_reset,
 342         .start =                ehci_pci_start,
 343 #ifdef  CONFIG_PM
 344         .suspend =              ehci_pci_suspend,
 345         .resume =               ehci_pci_resume,
 346 #endif
 347         .stop =                 ehci_pci_stop,
 348
 349         /*
 350          * managing i/o requests and associated device resources
 351          */
 352         .urb_enqueue =          ehci_urb_enqueue,
 353         .urb_dequeue =          ehci_urb_dequeue,
 354         .endpoint_disable =     ehci_endpoint_disable,
 355
 356         /*
 357          * scheduling support
 358          */
 359         .get_frame_number =     ehci_get_frame,
 360
 361         /*
 362          * root hub support
 363          */
 364         .hub_status_data =      ehci_hub_status_data,
 365         .hub_control =          ehci_hub_control,
 366         .bus_suspend =          ehci_bus_suspend,
 367         .bus_resume =           ehci_bus_resume,
 368 };
 369
 370 /*-------------------------------------------------------------------------*/
 371
 372 /* PCI driver selection metadata; PCI hotplugging uses this */
 373 static const struct pci_device_id pci_ids [] = { {
 374         /* handle any USB 2.0 EHCI controller */
 375         PCI_DEVICE_CLASS(((PCI_CLASS_SERIAL_USB << 8) | 0x20), ~0),
 376         .driver_data =  (unsigned long) &ehci_pci_hc_driver,
 377         },
 378         { /* end: all zeroes */ }
 379 };
 380 MODULE_DEVICE_TABLE (pci, pci_ids);
 381
 382 /* pci driver glue; this is a "new style" PCI driver module */
 383 static struct pci_driver ehci_pci_driver = {
 384         .name =         (char *) hcd_name,
 385         .id_table =     pci_ids,
 386         .owner =        THIS_MODULE,
 387
 388         .probe =        usb_hcd_pci_probe,
 389         .remove =       usb_hcd_pci_remove,
 390
 391 #ifdef  CONFIG_PM
 392         .suspend =      usb_hcd_pci_suspend,
 393         .resume =       usb_hcd_pci_resume,
 394 #endif
 395 };
 396
 397 static int __init ehci_hcd_pci_init (void)
 398 {
 399         if (usb_disabled())
 400                 return -ENODEV;
 401
 402         pr_debug ("%s: block sizes: qh %Zd qtd %Zd itd %Zd sitd %Zd\n",
 403                 hcd_name,
 404                 sizeof (struct ehci_qh), sizeof (struct ehci_qtd),
 405                 sizeof (struct ehci_itd), sizeof (struct ehci_sitd));
 406
 407         return pci_register_driver (&ehci_pci_driver);
 408 }
 409 module_init (ehci_hcd_pci_init);
 410
 411 static void __exit ehci_hcd_pci_cleanup (void)
 412 {
 413         pci_unregister_driver (&ehci_pci_driver);
 414 }
 415 module_exit (ehci_hcd_pci_cleanup);