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Linux 2.6.18.8
[linux-2.6/suspend2-2.6.18.git] / drivers / char / synclinkmp.c
blob66f3754fbbdf443e891b21cdfcf88c799144e6b9
1 /*
2 * $Id: synclinkmp.c,v 4.38 2005/07/15 13:29:44 paulkf Exp $
3 *
4 * Device driver for Microgate SyncLink Multiport
5 * high speed multiprotocol serial adapter.
6 *
7 * written by Paul Fulghum for Microgate Corporation
8 * paulkf@microgate.com
9 *
10 * Microgate and SyncLink are trademarks of Microgate Corporation
11 *
12 * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
13 * This code is released under the GNU General Public License (GPL)
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
25 * OF THE POSSIBILITY OF SUCH DAMAGE.
26 */
27
28 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
29 #if defined(__i386__)
30 # define BREAKPOINT() asm(" int $3");
31 #else
32 # define BREAKPOINT() { }
33 #endif
34
35 #define MAX_DEVICES 12
36
37 #include <linux/module.h>
38 #include <linux/errno.h>
39 #include <linux/signal.h>
40 #include <linux/sched.h>
41 #include <linux/timer.h>
42 #include <linux/interrupt.h>
43 #include <linux/pci.h>
44 #include <linux/tty.h>
45 #include <linux/tty_flip.h>
46 #include <linux/serial.h>
47 #include <linux/major.h>
48 #include <linux/string.h>
49 #include <linux/fcntl.h>
50 #include <linux/ptrace.h>
51 #include <linux/ioport.h>
52 #include <linux/mm.h>
53 #include <linux/slab.h>
54 #include <linux/netdevice.h>
55 #include <linux/vmalloc.h>
56 #include <linux/init.h>
57 #include <linux/delay.h>
58 #include <linux/ioctl.h>
59
60 #include <asm/system.h>
61 #include <asm/io.h>
62 #include <asm/irq.h>
63 #include <asm/dma.h>
64 #include <linux/bitops.h>
65 #include <asm/types.h>
66 #include <linux/termios.h>
67 #include <linux/workqueue.h>
68 #include <linux/hdlc.h>
69
70 #ifdef CONFIG_HDLC_MODULE
71 #define CONFIG_HDLC 1
72 #endif
73
74 #define GET_USER(error,value,addr) error = get_user(value,addr)
75 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
76 #define PUT_USER(error,value,addr) error = put_user(value,addr)
77 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
78
79 #include <asm/uaccess.h>
80
81 #include "linux/synclink.h"
82
83 static MGSL_PARAMS default_params = {
84 MGSL_MODE_HDLC, /* unsigned long mode */
85 0, /* unsigned char loopback; */
86 HDLC_FLAG_UNDERRUN_ABORT15, /* unsigned short flags; */
87 HDLC_ENCODING_NRZI_SPACE, /* unsigned char encoding; */
88 0, /* unsigned long clock_speed; */
89 0xff, /* unsigned char addr_filter; */
90 HDLC_CRC_16_CCITT, /* unsigned short crc_type; */
91 HDLC_PREAMBLE_LENGTH_8BITS, /* unsigned char preamble_length; */
92 HDLC_PREAMBLE_PATTERN_NONE, /* unsigned char preamble; */
93 9600, /* unsigned long data_rate; */
94 8, /* unsigned char data_bits; */
95 1, /* unsigned char stop_bits; */
96 ASYNC_PARITY_NONE /* unsigned char parity; */
97 };
98
99 /* size in bytes of DMA data buffers */
100 #define SCABUFSIZE 1024
101 #define SCA_MEM_SIZE 0x40000
102 #define SCA_BASE_SIZE 512
103 #define SCA_REG_SIZE 16
104 #define SCA_MAX_PORTS 4
105 #define SCAMAXDESC 128
106
107 #define BUFFERLISTSIZE 4096
108
109 /* SCA-I style DMA buffer descriptor */
110 typedef struct _SCADESC
111 {
112 u16 next; /* lower l6 bits of next descriptor addr */
113 u16 buf_ptr; /* lower 16 bits of buffer addr */
114 u8 buf_base; /* upper 8 bits of buffer addr */
115 u8 pad1;
116 u16 length; /* length of buffer */
117 u8 status; /* status of buffer */
118 u8 pad2;
119 } SCADESC, *PSCADESC;
120
121 typedef struct _SCADESC_EX
122 {
123 /* device driver bookkeeping section */
124 char *virt_addr; /* virtual address of data buffer */
125 u16 phys_entry; /* lower 16-bits of physical address of this descriptor */
126 } SCADESC_EX, *PSCADESC_EX;
127
128 /* The queue of BH actions to be performed */
129
130 #define BH_RECEIVE 1
131 #define BH_TRANSMIT 2
132 #define BH_STATUS 4
133
134 #define IO_PIN_SHUTDOWN_LIMIT 100
135
136 #define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
137
138 struct _input_signal_events {
139 int ri_up;
140 int ri_down;
141 int dsr_up;
142 int dsr_down;
143 int dcd_up;
144 int dcd_down;
145 int cts_up;
146 int cts_down;
147 };
148
149 /*
150 * Device instance data structure
151 */
152 typedef struct _synclinkmp_info {
153 void *if_ptr; /* General purpose pointer (used by SPPP) */
154 int magic;
155 int flags;
156 int count; /* count of opens */
157 int line;
158 unsigned short close_delay;
159 unsigned short closing_wait; /* time to wait before closing */
160
161 struct mgsl_icount icount;
162
163 struct tty_struct *tty;
164 int timeout;
165 int x_char; /* xon/xoff character */
166 int blocked_open; /* # of blocked opens */
167 u16 read_status_mask1; /* break detection (SR1 indications) */
168 u16 read_status_mask2; /* parity/framing/overun (SR2 indications) */
169 unsigned char ignore_status_mask1; /* break detection (SR1 indications) */
170 unsigned char ignore_status_mask2; /* parity/framing/overun (SR2 indications) */
171 unsigned char *tx_buf;
172 int tx_put;
173 int tx_get;
174 int tx_count;
175
176 wait_queue_head_t open_wait;
177 wait_queue_head_t close_wait;
178
179 wait_queue_head_t status_event_wait_q;
180 wait_queue_head_t event_wait_q;
181 struct timer_list tx_timer; /* HDLC transmit timeout timer */
182 struct _synclinkmp_info *next_device; /* device list link */
183 struct timer_list status_timer; /* input signal status check timer */
184
185 spinlock_t lock; /* spinlock for synchronizing with ISR */
186 struct work_struct task; /* task structure for scheduling bh */
187
188 u32 max_frame_size; /* as set by device config */
189
190 u32 pending_bh;
191
192 int bh_running; /* Protection from multiple */
193 int isr_overflow;
194 int bh_requested;
195
196 int dcd_chkcount; /* check counts to prevent */
197 int cts_chkcount; /* too many IRQs if a signal */
198 int dsr_chkcount; /* is floating */
199 int ri_chkcount;
200
201 char *buffer_list; /* virtual address of Rx & Tx buffer lists */
202 unsigned long buffer_list_phys;
203
204 unsigned int rx_buf_count; /* count of total allocated Rx buffers */
205 SCADESC *rx_buf_list; /* list of receive buffer entries */
206 SCADESC_EX rx_buf_list_ex[SCAMAXDESC]; /* list of receive buffer entries */
207 unsigned int current_rx_buf;
208
209 unsigned int tx_buf_count; /* count of total allocated Tx buffers */
210 SCADESC *tx_buf_list; /* list of transmit buffer entries */
211 SCADESC_EX tx_buf_list_ex[SCAMAXDESC]; /* list of transmit buffer entries */
212 unsigned int last_tx_buf;
213
214 unsigned char *tmp_rx_buf;
215 unsigned int tmp_rx_buf_count;
216
217 int rx_enabled;
218 int rx_overflow;
219
220 int tx_enabled;
221 int tx_active;
222 u32 idle_mode;
223
224 unsigned char ie0_value;
225 unsigned char ie1_value;
226 unsigned char ie2_value;
227 unsigned char ctrlreg_value;
228 unsigned char old_signals;
229
230 char device_name[25]; /* device instance name */
231
232 int port_count;
233 int adapter_num;
234 int port_num;
235
236 struct _synclinkmp_info *port_array[SCA_MAX_PORTS];
237
238 unsigned int bus_type; /* expansion bus type (ISA,EISA,PCI) */
239
240 unsigned int irq_level; /* interrupt level */
241 unsigned long irq_flags;
242 int irq_requested; /* nonzero if IRQ requested */
243
244 MGSL_PARAMS params; /* communications parameters */
245
246 unsigned char serial_signals; /* current serial signal states */
247
248 int irq_occurred; /* for diagnostics use */
249 unsigned int init_error; /* Initialization startup error */
250
251 u32 last_mem_alloc;
252 unsigned char* memory_base; /* shared memory address (PCI only) */
253 u32 phys_memory_base;
254 int shared_mem_requested;
255
256 unsigned char* sca_base; /* HD64570 SCA Memory address */
257 u32 phys_sca_base;
258 u32 sca_offset;
259 int sca_base_requested;
260
261 unsigned char* lcr_base; /* local config registers (PCI only) */
262 u32 phys_lcr_base;
263 u32 lcr_offset;
264 int lcr_mem_requested;
265
266 unsigned char* statctrl_base; /* status/control register memory */
267 u32 phys_statctrl_base;
268 u32 statctrl_offset;
269 int sca_statctrl_requested;
270
271 u32 misc_ctrl_value;
272 char flag_buf[MAX_ASYNC_BUFFER_SIZE];
273 char char_buf[MAX_ASYNC_BUFFER_SIZE];
274 BOOLEAN drop_rts_on_tx_done;
275
276 struct _input_signal_events input_signal_events;
277
278 /* SPPP/Cisco HDLC device parts */
279 int netcount;
280 int dosyncppp;
281 spinlock_t netlock;
282
283 #ifdef CONFIG_HDLC
284 struct net_device *netdev;
285 #endif
286
287 } SLMP_INFO;
288
289 #define MGSL_MAGIC 0x5401
290
291 /*
292 * define serial signal status change macros
293 */
294 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) /* indicates change in DCD */
295 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) /* indicates change in RI */
296 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) /* indicates change in CTS */
297 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) /* change in DSR */
298
299 /* Common Register macros */
300 #define LPR 0x00
301 #define PABR0 0x02
302 #define PABR1 0x03
303 #define WCRL 0x04
304 #define WCRM 0x05
305 #define WCRH 0x06
306 #define DPCR 0x08
307 #define DMER 0x09
308 #define ISR0 0x10
309 #define ISR1 0x11
310 #define ISR2 0x12
311 #define IER0 0x14
312 #define IER1 0x15
313 #define IER2 0x16
314 #define ITCR 0x18
315 #define INTVR 0x1a
316 #define IMVR 0x1c
317
318 /* MSCI Register macros */
319 #define TRB 0x20
320 #define TRBL 0x20
321 #define TRBH 0x21
322 #define SR0 0x22
323 #define SR1 0x23
324 #define SR2 0x24
325 #define SR3 0x25
326 #define FST 0x26
327 #define IE0 0x28
328 #define IE1 0x29
329 #define IE2 0x2a
330 #define FIE 0x2b
331 #define CMD 0x2c
332 #define MD0 0x2e
333 #define MD1 0x2f
334 #define MD2 0x30
335 #define CTL 0x31
336 #define SA0 0x32
337 #define SA1 0x33
338 #define IDL 0x34
339 #define TMC 0x35
340 #define RXS 0x36
341 #define TXS 0x37
342 #define TRC0 0x38
343 #define TRC1 0x39
344 #define RRC 0x3a
345 #define CST0 0x3c
346 #define CST1 0x3d
347
348 /* Timer Register Macros */
349 #define TCNT 0x60
350 #define TCNTL 0x60
351 #define TCNTH 0x61
352 #define TCONR 0x62
353 #define TCONRL 0x62
354 #define TCONRH 0x63
355 #define TMCS 0x64
356 #define TEPR 0x65
357
358 /* DMA Controller Register macros */
359 #define DARL 0x80
360 #define DARH 0x81
361 #define DARB 0x82
362 #define BAR 0x80
363 #define BARL 0x80
364 #define BARH 0x81
365 #define BARB 0x82
366 #define SAR 0x84
367 #define SARL 0x84
368 #define SARH 0x85
369 #define SARB 0x86
370 #define CPB 0x86
371 #define CDA 0x88
372 #define CDAL 0x88
373 #define CDAH 0x89
374 #define EDA 0x8a
375 #define EDAL 0x8a
376 #define EDAH 0x8b
377 #define BFL 0x8c
378 #define BFLL 0x8c
379 #define BFLH 0x8d
380 #define BCR 0x8e
381 #define BCRL 0x8e
382 #define BCRH 0x8f
383 #define DSR 0x90
384 #define DMR 0x91
385 #define FCT 0x93
386 #define DIR 0x94
387 #define DCMD 0x95
388
389 /* combine with timer or DMA register address */
390 #define TIMER0 0x00
391 #define TIMER1 0x08
392 #define TIMER2 0x10
393 #define TIMER3 0x18
394 #define RXDMA 0x00
395 #define TXDMA 0x20
396
397 /* SCA Command Codes */
398 #define NOOP 0x00
399 #define TXRESET 0x01
400 #define TXENABLE 0x02
401 #define TXDISABLE 0x03
402 #define TXCRCINIT 0x04
403 #define TXCRCEXCL 0x05
404 #define TXEOM 0x06
405 #define TXABORT 0x07
406 #define MPON 0x08
407 #define TXBUFCLR 0x09
408 #define RXRESET 0x11
409 #define RXENABLE 0x12
410 #define RXDISABLE 0x13
411 #define RXCRCINIT 0x14
412 #define RXREJECT 0x15
413 #define SEARCHMP 0x16
414 #define RXCRCEXCL 0x17
415 #define RXCRCCALC 0x18
416 #define CHRESET 0x21
417 #define HUNT 0x31
418
419 /* DMA command codes */
420 #define SWABORT 0x01
421 #define FEICLEAR 0x02
422
423 /* IE0 */
424 #define TXINTE BIT7
425 #define RXINTE BIT6
426 #define TXRDYE BIT1
427 #define RXRDYE BIT0
428
429 /* IE1 & SR1 */
430 #define UDRN BIT7
431 #define IDLE BIT6
432 #define SYNCD BIT4
433 #define FLGD BIT4
434 #define CCTS BIT3
435 #define CDCD BIT2
436 #define BRKD BIT1
437 #define ABTD BIT1
438 #define GAPD BIT1
439 #define BRKE BIT0
440 #define IDLD BIT0
441
442 /* IE2 & SR2 */
443 #define EOM BIT7
444 #define PMP BIT6
445 #define SHRT BIT6
446 #define PE BIT5
447 #define ABT BIT5
448 #define FRME BIT4
449 #define RBIT BIT4
450 #define OVRN BIT3
451 #define CRCE BIT2
452
453
454 /*
455 * Global linked list of SyncLink devices
456 */
457 static SLMP_INFO *synclinkmp_device_list = NULL;
458 static int synclinkmp_adapter_count = -1;
459 static int synclinkmp_device_count = 0;
460
461 /*
462 * Set this param to non-zero to load eax with the
463 * .text section address and breakpoint on module load.
464 * This is useful for use with gdb and add-symbol-file command.
465 */
466 static int break_on_load=0;
467
468 /*
469 * Driver major number, defaults to zero to get auto
470 * assigned major number. May be forced as module parameter.
471 */
472 static int ttymajor=0;
473
474 /*
475 * Array of user specified options for ISA adapters.
476 */
477 static int debug_level = 0;
478 static int maxframe[MAX_DEVICES] = {0,};
479 static int dosyncppp[MAX_DEVICES] = {0,};
480
481 module_param(break_on_load, bool, 0);
482 module_param(ttymajor, int, 0);
483 module_param(debug_level, int, 0);
484 module_param_array(maxframe, int, NULL, 0);
485 module_param_array(dosyncppp, int, NULL, 0);
486
487 static char *driver_name = "SyncLink MultiPort driver";
488 static char *driver_version = "$Revision: 4.38 $";
489
490 static int synclinkmp_init_one(struct pci_dev *dev,const struct pci_device_id *ent);
491 static void synclinkmp_remove_one(struct pci_dev *dev);
492
493 static struct pci_device_id synclinkmp_pci_tbl[] = {
494 { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_SCA, PCI_ANY_ID, PCI_ANY_ID, },
495 { 0, }, /* terminate list */
496 };
497 MODULE_DEVICE_TABLE(pci, synclinkmp_pci_tbl);
498
499 MODULE_LICENSE("GPL");
500
501 static struct pci_driver synclinkmp_pci_driver = {
502 .name = "synclinkmp",
503 .id_table = synclinkmp_pci_tbl,
504 .probe = synclinkmp_init_one,
505 .remove = __devexit_p(synclinkmp_remove_one),
506 };
507
508
509 static struct tty_driver *serial_driver;
510
511 /* number of characters left in xmit buffer before we ask for more */
512 #define WAKEUP_CHARS 256
513
514
515 /* tty callbacks */
516
517 static int open(struct tty_struct *tty, struct file * filp);
518 static void close(struct tty_struct *tty, struct file * filp);
519 static void hangup(struct tty_struct *tty);
520 static void set_termios(struct tty_struct *tty, struct termios *old_termios);
521
522 static int write(struct tty_struct *tty, const unsigned char *buf, int count);
523 static void put_char(struct tty_struct *tty, unsigned char ch);
524 static void send_xchar(struct tty_struct *tty, char ch);
525 static void wait_until_sent(struct tty_struct *tty, int timeout);
526 static int write_room(struct tty_struct *tty);
527 static void flush_chars(struct tty_struct *tty);
528 static void flush_buffer(struct tty_struct *tty);
529 static void tx_hold(struct tty_struct *tty);
530 static void tx_release(struct tty_struct *tty);
531
532 static int ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg);
533 static int read_proc(char *page, char **start, off_t off, int count,int *eof, void *data);
534 static int chars_in_buffer(struct tty_struct *tty);
535 static void throttle(struct tty_struct * tty);
536 static void unthrottle(struct tty_struct * tty);
537 static void set_break(struct tty_struct *tty, int break_state);
538
539 #ifdef CONFIG_HDLC
540 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
541 static void hdlcdev_tx_done(SLMP_INFO *info);
542 static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size);
543 static int hdlcdev_init(SLMP_INFO *info);
544 static void hdlcdev_exit(SLMP_INFO *info);
545 #endif
546
547 /* ioctl handlers */
548
549 static int get_stats(SLMP_INFO *info, struct mgsl_icount __user *user_icount);
550 static int get_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
551 static int set_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
552 static int get_txidle(SLMP_INFO *info, int __user *idle_mode);
553 static int set_txidle(SLMP_INFO *info, int idle_mode);
554 static int tx_enable(SLMP_INFO *info, int enable);
555 static int tx_abort(SLMP_INFO *info);
556 static int rx_enable(SLMP_INFO *info, int enable);
557 static int modem_input_wait(SLMP_INFO *info,int arg);
558 static int wait_mgsl_event(SLMP_INFO *info, int __user *mask_ptr);
559 static int tiocmget(struct tty_struct *tty, struct file *file);
560 static int tiocmset(struct tty_struct *tty, struct file *file,
561 unsigned int set, unsigned int clear);
562 static void set_break(struct tty_struct *tty, int break_state);
563
564 static void add_device(SLMP_INFO *info);
565 static void device_init(int adapter_num, struct pci_dev *pdev);
566 static int claim_resources(SLMP_INFO *info);
567 static void release_resources(SLMP_INFO *info);
568
569 static int startup(SLMP_INFO *info);
570 static int block_til_ready(struct tty_struct *tty, struct file * filp,SLMP_INFO *info);
571 static void shutdown(SLMP_INFO *info);
572 static void program_hw(SLMP_INFO *info);
573 static void change_params(SLMP_INFO *info);
574
575 static int init_adapter(SLMP_INFO *info);
576 static int register_test(SLMP_INFO *info);
577 static int irq_test(SLMP_INFO *info);
578 static int loopback_test(SLMP_INFO *info);
579 static int adapter_test(SLMP_INFO *info);
580 static int memory_test(SLMP_INFO *info);
581
582 static void reset_adapter(SLMP_INFO *info);
583 static void reset_port(SLMP_INFO *info);
584 static void async_mode(SLMP_INFO *info);
585 static void hdlc_mode(SLMP_INFO *info);
586
587 static void rx_stop(SLMP_INFO *info);
588 static void rx_start(SLMP_INFO *info);
589 static void rx_reset_buffers(SLMP_INFO *info);
590 static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last);
591 static int rx_get_frame(SLMP_INFO *info);
592
593 static void tx_start(SLMP_INFO *info);
594 static void tx_stop(SLMP_INFO *info);
595 static void tx_load_fifo(SLMP_INFO *info);
596 static void tx_set_idle(SLMP_INFO *info);
597 static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count);
598
599 static void get_signals(SLMP_INFO *info);
600 static void set_signals(SLMP_INFO *info);
601 static void enable_loopback(SLMP_INFO *info, int enable);
602 static void set_rate(SLMP_INFO *info, u32 data_rate);
603
604 static int bh_action(SLMP_INFO *info);
605 static void bh_handler(void* Context);
606 static void bh_receive(SLMP_INFO *info);
607 static void bh_transmit(SLMP_INFO *info);
608 static void bh_status(SLMP_INFO *info);
609 static void isr_timer(SLMP_INFO *info);
610 static void isr_rxint(SLMP_INFO *info);
611 static void isr_rxrdy(SLMP_INFO *info);
612 static void isr_txint(SLMP_INFO *info);
613 static void isr_txrdy(SLMP_INFO *info);
614 static void isr_rxdmaok(SLMP_INFO *info);
615 static void isr_rxdmaerror(SLMP_INFO *info);
616 static void isr_txdmaok(SLMP_INFO *info);
617 static void isr_txdmaerror(SLMP_INFO *info);
618 static void isr_io_pin(SLMP_INFO *info, u16 status);
619
620 static int alloc_dma_bufs(SLMP_INFO *info);
621 static void free_dma_bufs(SLMP_INFO *info);
622 static int alloc_buf_list(SLMP_INFO *info);
623 static int alloc_frame_bufs(SLMP_INFO *info, SCADESC *list, SCADESC_EX *list_ex,int count);
624 static int alloc_tmp_rx_buf(SLMP_INFO *info);
625 static void free_tmp_rx_buf(SLMP_INFO *info);
626
627 static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count);
628 static void trace_block(SLMP_INFO *info, const char* data, int count, int xmit);
629 static void tx_timeout(unsigned long context);
630 static void status_timeout(unsigned long context);
631
632 static unsigned char read_reg(SLMP_INFO *info, unsigned char addr);
633 static void write_reg(SLMP_INFO *info, unsigned char addr, unsigned char val);
634 static u16 read_reg16(SLMP_INFO *info, unsigned char addr);
635 static void write_reg16(SLMP_INFO *info, unsigned char addr, u16 val);
636 static unsigned char read_status_reg(SLMP_INFO * info);
637 static void write_control_reg(SLMP_INFO * info);
638
639
640 static unsigned char rx_active_fifo_level = 16; // rx request FIFO activation level in bytes
641 static unsigned char tx_active_fifo_level = 16; // tx request FIFO activation level in bytes
642 static unsigned char tx_negate_fifo_level = 32; // tx request FIFO negation level in bytes
643
644 static u32 misc_ctrl_value = 0x007e4040;
645 static u32 lcr1_brdr_value = 0x00800028;
646
647 static u32 read_ahead_count = 8;
648
649 /* DPCR, DMA Priority Control
650 *
651 * 07..05 Not used, must be 0
652 * 04 BRC, bus release condition: 0=all transfers complete
653 * 1=release after 1 xfer on all channels
654 * 03 CCC, channel change condition: 0=every cycle
655 * 1=after each channel completes all xfers
656 * 02..00 PR<2..0>, priority 100=round robin
657 *
658 * 00000100 = 0x00
659 */
660 static unsigned char dma_priority = 0x04;
661
662 // Number of bytes that can be written to shared RAM
663 // in a single write operation
664 static u32 sca_pci_load_interval = 64;
665
666 /*
667 * 1st function defined in .text section. Calling this function in
668 * init_module() followed by a breakpoint allows a remote debugger
669 * (gdb) to get the .text address for the add-symbol-file command.
670 * This allows remote debugging of dynamically loadable modules.
671 */
672 static void* synclinkmp_get_text_ptr(void);
673 static void* synclinkmp_get_text_ptr(void) {return synclinkmp_get_text_ptr;}
674
675 static inline int sanity_check(SLMP_INFO *info,
676 char *name, const char *routine)
677 {
678 #ifdef SANITY_CHECK
679 static const char *badmagic =
680 "Warning: bad magic number for synclinkmp_struct (%s) in %s\n";
681 static const char *badinfo =
682 "Warning: null synclinkmp_struct for (%s) in %s\n";
683
684 if (!info) {
685 printk(badinfo, name, routine);
686 return 1;
687 }
688 if (info->magic != MGSL_MAGIC) {
689 printk(badmagic, name, routine);
690 return 1;
691 }
692 #else
693 if (!info)
694 return 1;
695 #endif
696 return 0;
697 }
698
699 /**
700 * line discipline callback wrappers
701 *
702 * The wrappers maintain line discipline references
703 * while calling into the line discipline.
704 *
705 * ldisc_receive_buf - pass receive data to line discipline
706 */
707
708 static void ldisc_receive_buf(struct tty_struct *tty,
709 const __u8 *data, char *flags, int count)
710 {
711 struct tty_ldisc *ld;
712 if (!tty)
713 return;
714 ld = tty_ldisc_ref(tty);
715 if (ld) {
716 if (ld->receive_buf)
717 ld->receive_buf(tty, data, flags, count);
718 tty_ldisc_deref(ld);
719 }
720 }
721
722 /* tty callbacks */
723
724 /* Called when a port is opened. Init and enable port.
725 */
726 static int open(struct tty_struct *tty, struct file *filp)
727 {
728 SLMP_INFO *info;
729 int retval, line;
730 unsigned long flags;
731
732 line = tty->index;
733 if ((line < 0) || (line >= synclinkmp_device_count)) {
734 printk("%s(%d): open with invalid line #%d.\n",
735 __FILE__,__LINE__,line);
736 return -ENODEV;
737 }
738
739 info = synclinkmp_device_list;
740 while(info && info->line != line)
741 info = info->next_device;
742 if (sanity_check(info, tty->name, "open"))
743 return -ENODEV;
744 if ( info->init_error ) {
745 printk("%s(%d):%s device is not allocated, init error=%d\n",
746 __FILE__,__LINE__,info->device_name,info->init_error);
747 return -ENODEV;
748 }
749
750 tty->driver_data = info;
751 info->tty = tty;
752
753 if (debug_level >= DEBUG_LEVEL_INFO)
754 printk("%s(%d):%s open(), old ref count = %d\n",
755 __FILE__,__LINE__,tty->driver->name, info->count);
756
757 /* If port is closing, signal caller to try again */
758 if (tty_hung_up_p(filp) || info->flags & ASYNC_CLOSING){
759 if (info->flags & ASYNC_CLOSING)
760 interruptible_sleep_on(&info->close_wait);
761 retval = ((info->flags & ASYNC_HUP_NOTIFY) ?
762 -EAGAIN : -ERESTARTSYS);
763 goto cleanup;
764 }
765
766 info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
767
768 spin_lock_irqsave(&info->netlock, flags);
769 if (info->netcount) {
770 retval = -EBUSY;
771 spin_unlock_irqrestore(&info->netlock, flags);
772 goto cleanup;
773 }
774 info->count++;
775 spin_unlock_irqrestore(&info->netlock, flags);
776
777 if (info->count == 1) {
778 /* 1st open on this device, init hardware */
779 retval = startup(info);
780 if (retval < 0)
781 goto cleanup;
782 }
783
784 retval = block_til_ready(tty, filp, info);
785 if (retval) {
786 if (debug_level >= DEBUG_LEVEL_INFO)
787 printk("%s(%d):%s block_til_ready() returned %d\n",
788 __FILE__,__LINE__, info->device_name, retval);
789 goto cleanup;
790 }
791
792 if (debug_level >= DEBUG_LEVEL_INFO)
793 printk("%s(%d):%s open() success\n",
794 __FILE__,__LINE__, info->device_name);
795 retval = 0;
796
797 cleanup:
798 if (retval) {
799 if (tty->count == 1)
800 info->tty = NULL; /* tty layer will release tty struct */
801 if(info->count)
802 info->count--;
803 }
804
805 return retval;
806 }
807
808 /* Called when port is closed. Wait for remaining data to be
809 * sent. Disable port and free resources.
810 */
811 static void close(struct tty_struct *tty, struct file *filp)
812 {
813 SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
814
815 if (sanity_check(info, tty->name, "close"))
816 return;
817
818 if (debug_level >= DEBUG_LEVEL_INFO)
819 printk("%s(%d):%s close() entry, count=%d\n",
820 __FILE__,__LINE__, info->device_name, info->count);
821
822 if (!info->count)
823 return;
824
825 if (tty_hung_up_p(filp))
826 goto cleanup;
827
828 if ((tty->count == 1) && (info->count != 1)) {
829 /*
830 * tty->count is 1 and the tty structure will be freed.
831 * info->count should be one in this case.
832 * if it's not, correct it so that the port is shutdown.
833 */
834 printk("%s(%d):%s close: bad refcount; tty->count is 1, "
835 "info->count is %d\n",
836 __FILE__,__LINE__, info->device_name, info->count);
837 info->count = 1;
838 }
839
840 info->count--;
841
842 /* if at least one open remaining, leave hardware active */
843 if (info->count)
844 goto cleanup;
845
846 info->flags |= ASYNC_CLOSING;
847
848 /* set tty->closing to notify line discipline to
849 * only process XON/XOFF characters. Only the N_TTY
850 * discipline appears to use this (ppp does not).
851 */
852 tty->closing = 1;
853
854 /* wait for transmit data to clear all layers */
855
856 if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE) {
857 if (debug_level >= DEBUG_LEVEL_INFO)
858 printk("%s(%d):%s close() calling tty_wait_until_sent\n",
859 __FILE__,__LINE__, info->device_name );
860 tty_wait_until_sent(tty, info->closing_wait);
861 }
862
863 if (info->flags & ASYNC_INITIALIZED)
864 wait_until_sent(tty, info->timeout);
865
866 if (tty->driver->flush_buffer)
867 tty->driver->flush_buffer(tty);
868
869 tty_ldisc_flush(tty);
870
871 shutdown(info);
872
873 tty->closing = 0;
874 info->tty = NULL;
875
876 if (info->blocked_open) {
877 if (info->close_delay) {
878 msleep_interruptible(jiffies_to_msecs(info->close_delay));
879 }
880 wake_up_interruptible(&info->open_wait);
881 }
882
883 info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
884
885 wake_up_interruptible(&info->close_wait);
886
887 cleanup:
888 if (debug_level >= DEBUG_LEVEL_INFO)
889 printk("%s(%d):%s close() exit, count=%d\n", __FILE__,__LINE__,
890 tty->driver->name, info->count);
891 }
892
893 /* Called by tty_hangup() when a hangup is signaled.
894 * This is the same as closing all open descriptors for the port.
895 */
896 static void hangup(struct tty_struct *tty)
897 {
898 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
899
900 if (debug_level >= DEBUG_LEVEL_INFO)
901 printk("%s(%d):%s hangup()\n",
902 __FILE__,__LINE__, info->device_name );
903
904 if (sanity_check(info, tty->name, "hangup"))
905 return;
906
907 flush_buffer(tty);
908 shutdown(info);
909
910 info->count = 0;
911 info->flags &= ~ASYNC_NORMAL_ACTIVE;
912 info->tty = NULL;
913
914 wake_up_interruptible(&info->open_wait);
915 }
916
917 /* Set new termios settings
918 */
919 static void set_termios(struct tty_struct *tty, struct termios *old_termios)
920 {
921 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
922 unsigned long flags;
923
924 if (debug_level >= DEBUG_LEVEL_INFO)
925 printk("%s(%d):%s set_termios()\n", __FILE__,__LINE__,
926 tty->driver->name );
927
928 /* just return if nothing has changed */
929 if ((tty->termios->c_cflag == old_termios->c_cflag)
930 && (RELEVANT_IFLAG(tty->termios->c_iflag)
931 == RELEVANT_IFLAG(old_termios->c_iflag)))
932 return;
933
934 change_params(info);
935
936 /* Handle transition to B0 status */
937 if (old_termios->c_cflag & CBAUD &&
938 !(tty->termios->c_cflag & CBAUD)) {
939 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
940 spin_lock_irqsave(&info->lock,flags);
941 set_signals(info);
942 spin_unlock_irqrestore(&info->lock,flags);
943 }
944
945 /* Handle transition away from B0 status */
946 if (!(old_termios->c_cflag & CBAUD) &&
947 tty->termios->c_cflag & CBAUD) {
948 info->serial_signals |= SerialSignal_DTR;
949 if (!(tty->termios->c_cflag & CRTSCTS) ||
950 !test_bit(TTY_THROTTLED, &tty->flags)) {
951 info->serial_signals |= SerialSignal_RTS;
952 }
953 spin_lock_irqsave(&info->lock,flags);
954 set_signals(info);
955 spin_unlock_irqrestore(&info->lock,flags);
956 }
957
958 /* Handle turning off CRTSCTS */
959 if (old_termios->c_cflag & CRTSCTS &&
960 !(tty->termios->c_cflag & CRTSCTS)) {
961 tty->hw_stopped = 0;
962 tx_release(tty);
963 }
964 }
965
966 /* Send a block of data
967 *
968 * Arguments:
969 *
970 * tty pointer to tty information structure
971 * buf pointer to buffer containing send data
972 * count size of send data in bytes
973 *
974 * Return Value: number of characters written
975 */
976 static int write(struct tty_struct *tty,
977 const unsigned char *buf, int count)
978 {
979 int c, ret = 0;
980 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
981 unsigned long flags;
982
983 if (debug_level >= DEBUG_LEVEL_INFO)
984 printk("%s(%d):%s write() count=%d\n",
985 __FILE__,__LINE__,info->device_name,count);
986
987 if (sanity_check(info, tty->name, "write"))
988 goto cleanup;
989
990 if (!info->tx_buf)
991 goto cleanup;
992
993 if (info->params.mode == MGSL_MODE_HDLC) {
994 if (count > info->max_frame_size) {
995 ret = -EIO;
996 goto cleanup;
997 }
998 if (info->tx_active)
999 goto cleanup;
1000 if (info->tx_count) {
1001 /* send accumulated data from send_char() calls */
1002 /* as frame and wait before accepting more data. */
1003 tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
1004 goto start;
1005 }
1006 ret = info->tx_count = count;
1007 tx_load_dma_buffer(info, buf, count);
1008 goto start;
1009 }
1010
1011 for (;;) {
1012 c = min_t(int, count,
1013 min(info->max_frame_size - info->tx_count - 1,
1014 info->max_frame_size - info->tx_put));
1015 if (c <= 0)
1016 break;
1017
1018 memcpy(info->tx_buf + info->tx_put, buf, c);
1019
1020 spin_lock_irqsave(&info->lock,flags);
1021 info->tx_put += c;
1022 if (info->tx_put >= info->max_frame_size)
1023 info->tx_put -= info->max_frame_size;
1024 info->tx_count += c;
1025 spin_unlock_irqrestore(&info->lock,flags);
1026
1027 buf += c;
1028 count -= c;
1029 ret += c;
1030 }
1031
1032 if (info->params.mode == MGSL_MODE_HDLC) {
1033 if (count) {
1034 ret = info->tx_count = 0;
1035 goto cleanup;
1036 }
1037 tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
1038 }
1039 start:
1040 if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
1041 spin_lock_irqsave(&info->lock,flags);
1042 if (!info->tx_active)
1043 tx_start(info);
1044 spin_unlock_irqrestore(&info->lock,flags);
1045 }
1046
1047 cleanup:
1048 if (debug_level >= DEBUG_LEVEL_INFO)
1049 printk( "%s(%d):%s write() returning=%d\n",
1050 __FILE__,__LINE__,info->device_name,ret);
1051 return ret;
1052 }
1053
1054 /* Add a character to the transmit buffer.
1055 */
1056 static void put_char(struct tty_struct *tty, unsigned char ch)
1057 {
1058 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1059 unsigned long flags;
1060
1061 if ( debug_level >= DEBUG_LEVEL_INFO ) {
1062 printk( "%s(%d):%s put_char(%d)\n",
1063 __FILE__,__LINE__,info->device_name,ch);
1064 }
1065
1066 if (sanity_check(info, tty->name, "put_char"))
1067 return;
1068
1069 if (!info->tx_buf)
1070 return;
1071
1072 spin_lock_irqsave(&info->lock,flags);
1073
1074 if ( (info->params.mode != MGSL_MODE_HDLC) ||
1075 !info->tx_active ) {
1076
1077 if (info->tx_count < info->max_frame_size - 1) {
1078 info->tx_buf[info->tx_put++] = ch;
1079 if (info->tx_put >= info->max_frame_size)
1080 info->tx_put -= info->max_frame_size;
1081 info->tx_count++;
1082 }
1083 }
1084
1085 spin_unlock_irqrestore(&info->lock,flags);
1086 }
1087
1088 /* Send a high-priority XON/XOFF character
1089 */
1090 static void send_xchar(struct tty_struct *tty, char ch)
1091 {
1092 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1093 unsigned long flags;
1094
1095 if (debug_level >= DEBUG_LEVEL_INFO)
1096 printk("%s(%d):%s send_xchar(%d)\n",
1097 __FILE__,__LINE__, info->device_name, ch );
1098
1099 if (sanity_check(info, tty->name, "send_xchar"))
1100 return;
1101
1102 info->x_char = ch;
1103 if (ch) {
1104 /* Make sure transmit interrupts are on */
1105 spin_lock_irqsave(&info->lock,flags);
1106 if (!info->tx_enabled)
1107 tx_start(info);
1108 spin_unlock_irqrestore(&info->lock,flags);
1109 }
1110 }
1111
1112 /* Wait until the transmitter is empty.
1113 */
1114 static void wait_until_sent(struct tty_struct *tty, int timeout)
1115 {
1116 SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
1117 unsigned long orig_jiffies, char_time;
1118
1119 if (!info )
1120 return;
1121
1122 if (debug_level >= DEBUG_LEVEL_INFO)
1123 printk("%s(%d):%s wait_until_sent() entry\n",
1124 __FILE__,__LINE__, info->device_name );
1125
1126 if (sanity_check(info, tty->name, "wait_until_sent"))
1127 return;
1128
1129 if (!(info->flags & ASYNC_INITIALIZED))
1130 goto exit;
1131
1132 orig_jiffies = jiffies;
1133
1134 /* Set check interval to 1/5 of estimated time to
1135 * send a character, and make it at least 1. The check
1136 * interval should also be less than the timeout.
1137 * Note: use tight timings here to satisfy the NIST-PCTS.
1138 */
1139
1140 if ( info->params.data_rate ) {
1141 char_time = info->timeout/(32 * 5);
1142 if (!char_time)
1143 char_time++;
1144 } else
1145 char_time = 1;
1146
1147 if (timeout)
1148 char_time = min_t(unsigned long, char_time, timeout);
1149
1150 if ( info->params.mode == MGSL_MODE_HDLC ) {
1151 while (info->tx_active) {
1152 msleep_interruptible(jiffies_to_msecs(char_time));
1153 if (signal_pending(current))
1154 break;
1155 if (timeout && time_after(jiffies, orig_jiffies + timeout))
1156 break;
1157 }
1158 } else {
1159 //TODO: determine if there is something similar to USC16C32
1160 // TXSTATUS_ALL_SENT status
1161 while ( info->tx_active && info->tx_enabled) {
1162 msleep_interruptible(jiffies_to_msecs(char_time));
1163 if (signal_pending(current))
1164 break;
1165 if (timeout && time_after(jiffies, orig_jiffies + timeout))
1166 break;
1167 }
1168 }
1169
1170 exit:
1171 if (debug_level >= DEBUG_LEVEL_INFO)
1172 printk("%s(%d):%s wait_until_sent() exit\n",
1173 __FILE__,__LINE__, info->device_name );
1174 }
1175
1176 /* Return the count of free bytes in transmit buffer
1177 */
1178 static int write_room(struct tty_struct *tty)
1179 {
1180 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1181 int ret;
1182
1183 if (sanity_check(info, tty->name, "write_room"))
1184 return 0;
1185
1186 if (info->params.mode == MGSL_MODE_HDLC) {
1187 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
1188 } else {
1189 ret = info->max_frame_size - info->tx_count - 1;
1190 if (ret < 0)
1191 ret = 0;
1192 }
1193
1194 if (debug_level >= DEBUG_LEVEL_INFO)
1195 printk("%s(%d):%s write_room()=%d\n",
1196 __FILE__, __LINE__, info->device_name, ret);
1197
1198 return ret;
1199 }
1200
1201 /* enable transmitter and send remaining buffered characters
1202 */
1203 static void flush_chars(struct tty_struct *tty)
1204 {
1205 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1206 unsigned long flags;
1207
1208 if ( debug_level >= DEBUG_LEVEL_INFO )
1209 printk( "%s(%d):%s flush_chars() entry tx_count=%d\n",
1210 __FILE__,__LINE__,info->device_name,info->tx_count);
1211
1212 if (sanity_check(info, tty->name, "flush_chars"))
1213 return;
1214
1215 if (info->tx_count <= 0 || tty->stopped || tty->hw_stopped ||
1216 !info->tx_buf)
1217 return;
1218
1219 if ( debug_level >= DEBUG_LEVEL_INFO )
1220 printk( "%s(%d):%s flush_chars() entry, starting transmitter\n",
1221 __FILE__,__LINE__,info->device_name );
1222
1223 spin_lock_irqsave(&info->lock,flags);
1224
1225 if (!info->tx_active) {
1226 if ( (info->params.mode == MGSL_MODE_HDLC) &&
1227 info->tx_count ) {
1228 /* operating in synchronous (frame oriented) mode */
1229 /* copy data from circular tx_buf to */
1230 /* transmit DMA buffer. */
1231 tx_load_dma_buffer(info,
1232 info->tx_buf,info->tx_count);
1233 }
1234 tx_start(info);
1235 }
1236
1237 spin_unlock_irqrestore(&info->lock,flags);
1238 }
1239
1240 /* Discard all data in the send buffer
1241 */
1242 static void flush_buffer(struct tty_struct *tty)
1243 {
1244 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1245 unsigned long flags;
1246
1247 if (debug_level >= DEBUG_LEVEL_INFO)
1248 printk("%s(%d):%s flush_buffer() entry\n",
1249 __FILE__,__LINE__, info->device_name );
1250
1251 if (sanity_check(info, tty->name, "flush_buffer"))
1252 return;
1253
1254 spin_lock_irqsave(&info->lock,flags);
1255 info->tx_count = info->tx_put = info->tx_get = 0;
1256 del_timer(&info->tx_timer);
1257 spin_unlock_irqrestore(&info->lock,flags);
1258
1259 wake_up_interruptible(&tty->write_wait);
1260 tty_wakeup(tty);
1261 }
1262
1263 /* throttle (stop) transmitter
1264 */
1265 static void tx_hold(struct tty_struct *tty)
1266 {
1267 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1268 unsigned long flags;
1269
1270 if (sanity_check(info, tty->name, "tx_hold"))
1271 return;
1272
1273 if ( debug_level >= DEBUG_LEVEL_INFO )
1274 printk("%s(%d):%s tx_hold()\n",
1275 __FILE__,__LINE__,info->device_name);
1276
1277 spin_lock_irqsave(&info->lock,flags);
1278 if (info->tx_enabled)
1279 tx_stop(info);
1280 spin_unlock_irqrestore(&info->lock,flags);
1281 }
1282
1283 /* release (start) transmitter
1284 */
1285 static void tx_release(struct tty_struct *tty)
1286 {
1287 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1288 unsigned long flags;
1289
1290 if (sanity_check(info, tty->name, "tx_release"))
1291 return;
1292
1293 if ( debug_level >= DEBUG_LEVEL_INFO )
1294 printk("%s(%d):%s tx_release()\n",
1295 __FILE__,__LINE__,info->device_name);
1296
1297 spin_lock_irqsave(&info->lock,flags);
1298 if (!info->tx_enabled)
1299 tx_start(info);
1300 spin_unlock_irqrestore(&info->lock,flags);
1301 }
1302
1303 /* Service an IOCTL request
1304 *
1305 * Arguments:
1306 *
1307 * tty pointer to tty instance data
1308 * file pointer to associated file object for device
1309 * cmd IOCTL command code
1310 * arg command argument/context
1311 *
1312 * Return Value: 0 if success, otherwise error code
1313 */
1314 static int ioctl(struct tty_struct *tty, struct file *file,
1315 unsigned int cmd, unsigned long arg)
1316 {
1317 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1318 int error;
1319 struct mgsl_icount cnow; /* kernel counter temps */
1320 struct serial_icounter_struct __user *p_cuser; /* user space */
1321 unsigned long flags;
1322 void __user *argp = (void __user *)arg;
1323
1324 if (debug_level >= DEBUG_LEVEL_INFO)
1325 printk("%s(%d):%s ioctl() cmd=%08X\n", __FILE__,__LINE__,
1326 info->device_name, cmd );
1327
1328 if (sanity_check(info, tty->name, "ioctl"))
1329 return -ENODEV;
1330
1331 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1332 (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
1333 if (tty->flags & (1 << TTY_IO_ERROR))
1334 return -EIO;
1335 }
1336
1337 switch (cmd) {
1338 case MGSL_IOCGPARAMS:
1339 return get_params(info, argp);
1340 case MGSL_IOCSPARAMS:
1341 return set_params(info, argp);
1342 case MGSL_IOCGTXIDLE:
1343 return get_txidle(info, argp);
1344 case MGSL_IOCSTXIDLE:
1345 return set_txidle(info, (int)arg);
1346 case MGSL_IOCTXENABLE:
1347 return tx_enable(info, (int)arg);
1348 case MGSL_IOCRXENABLE:
1349 return rx_enable(info, (int)arg);
1350 case MGSL_IOCTXABORT:
1351 return tx_abort(info);
1352 case MGSL_IOCGSTATS:
1353 return get_stats(info, argp);
1354 case MGSL_IOCWAITEVENT:
1355 return wait_mgsl_event(info, argp);
1356 case MGSL_IOCLOOPTXDONE:
1357 return 0; // TODO: Not supported, need to document
1358 /* Wait for modem input (DCD,RI,DSR,CTS) change
1359 * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
1360 */
1361 case TIOCMIWAIT:
1362 return modem_input_wait(info,(int)arg);
1363
1364 /*
1365 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1366 * Return: write counters to the user passed counter struct
1367 * NB: both 1->0 and 0->1 transitions are counted except for
1368 * RI where only 0->1 is counted.
1369 */
1370 case TIOCGICOUNT:
1371 spin_lock_irqsave(&info->lock,flags);
1372 cnow = info->icount;
1373 spin_unlock_irqrestore(&info->lock,flags);
1374 p_cuser = argp;
1375 PUT_USER(error,cnow.cts, &p_cuser->cts);
1376 if (error) return error;
1377 PUT_USER(error,cnow.dsr, &p_cuser->dsr);
1378 if (error) return error;
1379 PUT_USER(error,cnow.rng, &p_cuser->rng);
1380 if (error) return error;
1381 PUT_USER(error,cnow.dcd, &p_cuser->dcd);
1382 if (error) return error;
1383 PUT_USER(error,cnow.rx, &p_cuser->rx);
1384 if (error) return error;
1385 PUT_USER(error,cnow.tx, &p_cuser->tx);
1386 if (error) return error;
1387 PUT_USER(error,cnow.frame, &p_cuser->frame);
1388 if (error) return error;
1389 PUT_USER(error,cnow.overrun, &p_cuser->overrun);
1390 if (error) return error;
1391 PUT_USER(error,cnow.parity, &p_cuser->parity);
1392 if (error) return error;
1393 PUT_USER(error,cnow.brk, &p_cuser->brk);
1394 if (error) return error;
1395 PUT_USER(error,cnow.buf_overrun, &p_cuser->buf_overrun);
1396 if (error) return error;
1397 return 0;
1398 default:
1399 return -ENOIOCTLCMD;
1400 }
1401 return 0;
1402 }
1403
1404 /*
1405 * /proc fs routines....
1406 */
1407
1408 static inline int line_info(char *buf, SLMP_INFO *info)
1409 {
1410 char stat_buf[30];
1411 int ret;
1412 unsigned long flags;
1413
1414 ret = sprintf(buf, "%s: SCABase=%08x Mem=%08X StatusControl=%08x LCR=%08X\n"
1415 "\tIRQ=%d MaxFrameSize=%u\n",
1416 info->device_name,
1417 info->phys_sca_base,
1418 info->phys_memory_base,
1419 info->phys_statctrl_base,
1420 info->phys_lcr_base,
1421 info->irq_level,
1422 info->max_frame_size );
1423
1424 /* output current serial signal states */
1425 spin_lock_irqsave(&info->lock,flags);
1426 get_signals(info);
1427 spin_unlock_irqrestore(&info->lock,flags);
1428
1429 stat_buf[0] = 0;
1430 stat_buf[1] = 0;
1431 if (info->serial_signals & SerialSignal_RTS)
1432 strcat(stat_buf, "|RTS");
1433 if (info->serial_signals & SerialSignal_CTS)
1434 strcat(stat_buf, "|CTS");
1435 if (info->serial_signals & SerialSignal_DTR)
1436 strcat(stat_buf, "|DTR");
1437 if (info->serial_signals & SerialSignal_DSR)
1438 strcat(stat_buf, "|DSR");
1439 if (info->serial_signals & SerialSignal_DCD)
1440 strcat(stat_buf, "|CD");
1441 if (info->serial_signals & SerialSignal_RI)
1442 strcat(stat_buf, "|RI");
1443
1444 if (info->params.mode == MGSL_MODE_HDLC) {
1445 ret += sprintf(buf+ret, "\tHDLC txok:%d rxok:%d",
1446 info->icount.txok, info->icount.rxok);
1447 if (info->icount.txunder)
1448 ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder);
1449 if (info->icount.txabort)
1450 ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort);
1451 if (info->icount.rxshort)
1452 ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort);
1453 if (info->icount.rxlong)
1454 ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong);
1455 if (info->icount.rxover)
1456 ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover);
1457 if (info->icount.rxcrc)
1458 ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxcrc);
1459 } else {
1460 ret += sprintf(buf+ret, "\tASYNC tx:%d rx:%d",
1461 info->icount.tx, info->icount.rx);
1462 if (info->icount.frame)
1463 ret += sprintf(buf+ret, " fe:%d", info->icount.frame);
1464 if (info->icount.parity)
1465 ret += sprintf(buf+ret, " pe:%d", info->icount.parity);
1466 if (info->icount.brk)
1467 ret += sprintf(buf+ret, " brk:%d", info->icount.brk);
1468 if (info->icount.overrun)
1469 ret += sprintf(buf+ret, " oe:%d", info->icount.overrun);
1470 }
1471
1472 /* Append serial signal status to end */
1473 ret += sprintf(buf+ret, " %s\n", stat_buf+1);
1474
1475 ret += sprintf(buf+ret, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1476 info->tx_active,info->bh_requested,info->bh_running,
1477 info->pending_bh);
1478
1479 return ret;
1480 }
1481
1482 /* Called to print information about devices
1483 */
1484 int read_proc(char *page, char **start, off_t off, int count,
1485 int *eof, void *data)
1486 {
1487 int len = 0, l;
1488 off_t begin = 0;
1489 SLMP_INFO *info;
1490
1491 len += sprintf(page, "synclinkmp driver:%s\n", driver_version);
1492
1493 info = synclinkmp_device_list;
1494 while( info ) {
1495 l = line_info(page + len, info);
1496 len += l;
1497 if (len+begin > off+count)
1498 goto done;
1499 if (len+begin < off) {
1500 begin += len;
1501 len = 0;
1502 }
1503 info = info->next_device;
1504 }
1505
1506 *eof = 1;
1507 done:
1508 if (off >= len+begin)
1509 return 0;
1510 *start = page + (off-begin);
1511 return ((count < begin+len-off) ? count : begin+len-off);
1512 }
1513
1514 /* Return the count of bytes in transmit buffer
1515 */
1516 static int chars_in_buffer(struct tty_struct *tty)
1517 {
1518 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1519
1520 if (sanity_check(info, tty->name, "chars_in_buffer"))
1521 return 0;
1522
1523 if (debug_level >= DEBUG_LEVEL_INFO)
1524 printk("%s(%d):%s chars_in_buffer()=%d\n",
1525 __FILE__, __LINE__, info->device_name, info->tx_count);
1526
1527 return info->tx_count;
1528 }
1529
1530 /* Signal remote device to throttle send data (our receive data)
1531 */
1532 static void throttle(struct tty_struct * tty)
1533 {
1534 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1535 unsigned long flags;
1536
1537 if (debug_level >= DEBUG_LEVEL_INFO)
1538 printk("%s(%d):%s throttle() entry\n",
1539 __FILE__,__LINE__, info->device_name );
1540
1541 if (sanity_check(info, tty->name, "throttle"))
1542 return;
1543
1544 if (I_IXOFF(tty))
1545 send_xchar(tty, STOP_CHAR(tty));
1546
1547 if (tty->termios->c_cflag & CRTSCTS) {
1548 spin_lock_irqsave(&info->lock,flags);
1549 info->serial_signals &= ~SerialSignal_RTS;
1550 set_signals(info);
1551 spin_unlock_irqrestore(&info->lock,flags);
1552 }
1553 }
1554
1555 /* Signal remote device to stop throttling send data (our receive data)
1556 */
1557 static void unthrottle(struct tty_struct * tty)
1558 {
1559 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1560 unsigned long flags;
1561
1562 if (debug_level >= DEBUG_LEVEL_INFO)
1563 printk("%s(%d):%s unthrottle() entry\n",
1564 __FILE__,__LINE__, info->device_name );
1565
1566 if (sanity_check(info, tty->name, "unthrottle"))
1567 return;
1568
1569 if (I_IXOFF(tty)) {
1570 if (info->x_char)
1571 info->x_char = 0;
1572 else
1573 send_xchar(tty, START_CHAR(tty));
1574 }
1575
1576 if (tty->termios->c_cflag & CRTSCTS) {
1577 spin_lock_irqsave(&info->lock,flags);
1578 info->serial_signals |= SerialSignal_RTS;
1579 set_signals(info);
1580 spin_unlock_irqrestore(&info->lock,flags);
1581 }
1582 }
1583
1584 /* set or clear transmit break condition
1585 * break_state -1=set break condition, 0=clear
1586 */
1587 static void set_break(struct tty_struct *tty, int break_state)
1588 {
1589 unsigned char RegValue;
1590 SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
1591 unsigned long flags;
1592
1593 if (debug_level >= DEBUG_LEVEL_INFO)
1594 printk("%s(%d):%s set_break(%d)\n",
1595 __FILE__,__LINE__, info->device_name, break_state);
1596
1597 if (sanity_check(info, tty->name, "set_break"))
1598 return;
1599
1600 spin_lock_irqsave(&info->lock,flags);
1601 RegValue = read_reg(info, CTL);
1602 if (break_state == -1)
1603 RegValue |= BIT3;
1604 else
1605 RegValue &= ~BIT3;
1606 write_reg(info, CTL, RegValue);
1607 spin_unlock_irqrestore(&info->lock,flags);
1608 }
1609
1610 #ifdef CONFIG_HDLC
1611
1612 /**
1613 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1614 * set encoding and frame check sequence (FCS) options
1615 *
1616 * dev pointer to network device structure
1617 * encoding serial encoding setting
1618 * parity FCS setting
1619 *
1620 * returns 0 if success, otherwise error code
1621 */
1622 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1623 unsigned short parity)
1624 {
1625 SLMP_INFO *info = dev_to_port(dev);
1626 unsigned char new_encoding;
1627 unsigned short new_crctype;
1628
1629 /* return error if TTY interface open */
1630 if (info->count)
1631 return -EBUSY;
1632
1633 switch (encoding)
1634 {
1635 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
1636 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1637 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1638 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1639 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1640 default: return -EINVAL;
1641 }
1642
1643 switch (parity)
1644 {
1645 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
1646 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1647 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1648 default: return -EINVAL;
1649 }
1650
1651 info->params.encoding = new_encoding;
1652 info->params.crc_type = new_crctype;
1653
1654 /* if network interface up, reprogram hardware */
1655 if (info->netcount)
1656 program_hw(info);
1657
1658 return 0;
1659 }
1660
1661 /**
1662 * called by generic HDLC layer to send frame
1663 *
1664 * skb socket buffer containing HDLC frame
1665 * dev pointer to network device structure
1666 *
1667 * returns 0 if success, otherwise error code
1668 */
1669 static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev)
1670 {
1671 SLMP_INFO *info = dev_to_port(dev);
1672 struct net_device_stats *stats = hdlc_stats(dev);
1673 unsigned long flags;
1674
1675 if (debug_level >= DEBUG_LEVEL_INFO)
1676 printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
1677
1678 /* stop sending until this frame completes */
1679 netif_stop_queue(dev);
1680
1681 /* copy data to device buffers */
1682 info->tx_count = skb->len;
1683 tx_load_dma_buffer(info, skb->data, skb->len);
1684
1685 /* update network statistics */
1686 stats->tx_packets++;
1687 stats->tx_bytes += skb->len;
1688
1689 /* done with socket buffer, so free it */
1690 dev_kfree_skb(skb);
1691
1692 /* save start time for transmit timeout detection */
1693 dev->trans_start = jiffies;
1694
1695 /* start hardware transmitter if necessary */
1696 spin_lock_irqsave(&info->lock,flags);
1697 if (!info->tx_active)
1698 tx_start(info);
1699 spin_unlock_irqrestore(&info->lock,flags);
1700
1701 return 0;
1702 }
1703
1704 /**
1705 * called by network layer when interface enabled
1706 * claim resources and initialize hardware
1707 *
1708 * dev pointer to network device structure
1709 *
1710 * returns 0 if success, otherwise error code
1711 */
1712 static int hdlcdev_open(struct net_device *dev)
1713 {
1714 SLMP_INFO *info = dev_to_port(dev);
1715 int rc;
1716 unsigned long flags;
1717
1718 if (debug_level >= DEBUG_LEVEL_INFO)
1719 printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
1720
1721 /* generic HDLC layer open processing */
1722 if ((rc = hdlc_open(dev)))
1723 return rc;
1724
1725 /* arbitrate between network and tty opens */
1726 spin_lock_irqsave(&info->netlock, flags);
1727 if (info->count != 0 || info->netcount != 0) {
1728 printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
1729 spin_unlock_irqrestore(&info->netlock, flags);
1730 return -EBUSY;
1731 }
1732 info->netcount=1;
1733 spin_unlock_irqrestore(&info->netlock, flags);
1734
1735 /* claim resources and init adapter */
1736 if ((rc = startup(info)) != 0) {
1737 spin_lock_irqsave(&info->netlock, flags);
1738 info->netcount=0;
1739 spin_unlock_irqrestore(&info->netlock, flags);
1740 return rc;
1741 }
1742
1743 /* assert DTR and RTS, apply hardware settings */
1744 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
1745 program_hw(info);
1746
1747 /* enable network layer transmit */
1748 dev->trans_start = jiffies;
1749 netif_start_queue(dev);
1750
1751 /* inform generic HDLC layer of current DCD status */
1752 spin_lock_irqsave(&info->lock, flags);
1753 get_signals(info);
1754 spin_unlock_irqrestore(&info->lock, flags);
1755 if (info->serial_signals & SerialSignal_DCD)
1756 netif_carrier_on(dev);
1757 else
1758 netif_carrier_off(dev);
1759 return 0;
1760 }
1761
1762 /**
1763 * called by network layer when interface is disabled
1764 * shutdown hardware and release resources
1765 *
1766 * dev pointer to network device structure
1767 *
1768 * returns 0 if success, otherwise error code
1769 */
1770 static int hdlcdev_close(struct net_device *dev)
1771 {
1772 SLMP_INFO *info = dev_to_port(dev);
1773 unsigned long flags;
1774
1775 if (debug_level >= DEBUG_LEVEL_INFO)
1776 printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
1777
1778 netif_stop_queue(dev);
1779
1780 /* shutdown adapter and release resources */
1781 shutdown(info);
1782
1783 hdlc_close(dev);
1784
1785 spin_lock_irqsave(&info->netlock, flags);
1786 info->netcount=0;
1787 spin_unlock_irqrestore(&info->netlock, flags);
1788
1789 return 0;
1790 }
1791
1792 /**
1793 * called by network layer to process IOCTL call to network device
1794 *
1795 * dev pointer to network device structure
1796 * ifr pointer to network interface request structure
1797 * cmd IOCTL command code
1798 *
1799 * returns 0 if success, otherwise error code
1800 */
1801 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1802 {
1803 const size_t size = sizeof(sync_serial_settings);
1804 sync_serial_settings new_line;
1805 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1806 SLMP_INFO *info = dev_to_port(dev);
1807 unsigned int flags;
1808
1809 if (debug_level >= DEBUG_LEVEL_INFO)
1810 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
1811
1812 /* return error if TTY interface open */
1813 if (info->count)
1814 return -EBUSY;
1815
1816 if (cmd != SIOCWANDEV)
1817 return hdlc_ioctl(dev, ifr, cmd);
1818
1819 switch(ifr->ifr_settings.type) {
1820 case IF_GET_IFACE: /* return current sync_serial_settings */
1821
1822 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1823 if (ifr->ifr_settings.size < size) {
1824 ifr->ifr_settings.size = size; /* data size wanted */
1825 return -ENOBUFS;
1826 }
1827
1828 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1829 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1830 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1831 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1832
1833 switch (flags){
1834 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1835 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
1836 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
1837 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1838 default: new_line.clock_type = CLOCK_DEFAULT;
1839 }
1840
1841 new_line.clock_rate = info->params.clock_speed;
1842 new_line.loopback = info->params.loopback ? 1:0;
1843
1844 if (copy_to_user(line, &new_line, size))
1845 return -EFAULT;
1846 return 0;
1847
1848 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1849
1850 if(!capable(CAP_NET_ADMIN))
1851 return -EPERM;
1852 if (copy_from_user(&new_line, line, size))
1853 return -EFAULT;
1854
1855 switch (new_line.clock_type)
1856 {
1857 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1858 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1859 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
1860 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
1861 case CLOCK_DEFAULT: flags = info->params.flags &
1862 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1863 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1864 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1865 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
1866 default: return -EINVAL;
1867 }
1868
1869 if (new_line.loopback != 0 && new_line.loopback != 1)
1870 return -EINVAL;
1871
1872 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1873 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1874 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1875 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1876 info->params.flags |= flags;
1877
1878 info->params.loopback = new_line.loopback;
1879
1880 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1881 info->params.clock_speed = new_line.clock_rate;
1882 else
1883 info->params.clock_speed = 0;
1884
1885 /* if network interface up, reprogram hardware */
1886 if (info->netcount)
1887 program_hw(info);
1888 return 0;
1889
1890 default:
1891 return hdlc_ioctl(dev, ifr, cmd);
1892 }
1893 }
1894
1895 /**
1896 * called by network layer when transmit timeout is detected
1897 *
1898 * dev pointer to network device structure
1899 */
1900 static void hdlcdev_tx_timeout(struct net_device *dev)
1901 {
1902 SLMP_INFO *info = dev_to_port(dev);
1903 struct net_device_stats *stats = hdlc_stats(dev);
1904 unsigned long flags;
1905
1906 if (debug_level >= DEBUG_LEVEL_INFO)
1907 printk("hdlcdev_tx_timeout(%s)\n",dev->name);
1908
1909 stats->tx_errors++;
1910 stats->tx_aborted_errors++;
1911
1912 spin_lock_irqsave(&info->lock,flags);
1913 tx_stop(info);
1914 spin_unlock_irqrestore(&info->lock,flags);
1915
1916 netif_wake_queue(dev);
1917 }
1918
1919 /**
1920 * called by device driver when transmit completes
1921 * reenable network layer transmit if stopped
1922 *
1923 * info pointer to device instance information
1924 */
1925 static void hdlcdev_tx_done(SLMP_INFO *info)
1926 {
1927 if (netif_queue_stopped(info->netdev))
1928 netif_wake_queue(info->netdev);
1929 }
1930
1931 /**
1932 * called by device driver when frame received
1933 * pass frame to network layer
1934 *
1935 * info pointer to device instance information
1936 * buf pointer to buffer contianing frame data
1937 * size count of data bytes in buf
1938 */
1939 static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size)
1940 {
1941 struct sk_buff *skb = dev_alloc_skb(size);
1942 struct net_device *dev = info->netdev;
1943 struct net_device_stats *stats = hdlc_stats(dev);
1944
1945 if (debug_level >= DEBUG_LEVEL_INFO)
1946 printk("hdlcdev_rx(%s)\n",dev->name);
1947
1948 if (skb == NULL) {
1949 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n", dev->name);
1950 stats->rx_dropped++;
1951 return;
1952 }
1953
1954 memcpy(skb_put(skb, size),buf,size);
1955
1956 skb->protocol = hdlc_type_trans(skb, info->netdev);
1957
1958 stats->rx_packets++;
1959 stats->rx_bytes += size;
1960
1961 netif_rx(skb);
1962
1963 info->netdev->last_rx = jiffies;
1964 }
1965
1966 /**
1967 * called by device driver when adding device instance
1968 * do generic HDLC initialization
1969 *
1970 * info pointer to device instance information
1971 *
1972 * returns 0 if success, otherwise error code
1973 */
1974 static int hdlcdev_init(SLMP_INFO *info)
1975 {
1976 int rc;
1977 struct net_device *dev;
1978 hdlc_device *hdlc;
1979
1980 /* allocate and initialize network and HDLC layer objects */
1981
1982 if (!(dev = alloc_hdlcdev(info))) {
1983 printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
1984 return -ENOMEM;
1985 }
1986
1987 /* for network layer reporting purposes only */
1988 dev->mem_start = info->phys_sca_base;
1989 dev->mem_end = info->phys_sca_base + SCA_BASE_SIZE - 1;
1990 dev->irq = info->irq_level;
1991
1992 /* network layer callbacks and settings */
1993 dev->do_ioctl = hdlcdev_ioctl;
1994 dev->open = hdlcdev_open;
1995 dev->stop = hdlcdev_close;
1996 dev->tx_timeout = hdlcdev_tx_timeout;
1997 dev->watchdog_timeo = 10*HZ;
1998 dev->tx_queue_len = 50;
1999
2000 /* generic HDLC layer callbacks and settings */
2001 hdlc = dev_to_hdlc(dev);
2002 hdlc->attach = hdlcdev_attach;
2003 hdlc->xmit = hdlcdev_xmit;
2004
2005 /* register objects with HDLC layer */
2006 if ((rc = register_hdlc_device(dev))) {
2007 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
2008 free_netdev(dev);
2009 return rc;
2010 }
2011
2012 info->netdev = dev;
2013 return 0;
2014 }
2015
2016 /**
2017 * called by device driver when removing device instance
2018 * do generic HDLC cleanup
2019 *
2020 * info pointer to device instance information
2021 */
2022 static void hdlcdev_exit(SLMP_INFO *info)
2023 {
2024 unregister_hdlc_device(info->netdev);
2025 free_netdev(info->netdev);
2026 info->netdev = NULL;
2027 }
2028
2029 #endif /* CONFIG_HDLC */
2030
2031
2032 /* Return next bottom half action to perform.
2033 * Return Value: BH action code or 0 if nothing to do.
2034 */
2035 int bh_action(SLMP_INFO *info)
2036 {
2037 unsigned long flags;
2038 int rc = 0;
2039
2040 spin_lock_irqsave(&info->lock,flags);
2041
2042 if (info->pending_bh & BH_RECEIVE) {
2043 info->pending_bh &= ~BH_RECEIVE;
2044 rc = BH_RECEIVE;
2045 } else if (info->pending_bh & BH_TRANSMIT) {
2046 info->pending_bh &= ~BH_TRANSMIT;
2047 rc = BH_TRANSMIT;
2048 } else if (info->pending_bh & BH_STATUS) {
2049 info->pending_bh &= ~BH_STATUS;
2050 rc = BH_STATUS;
2051 }
2052
2053 if (!rc) {
2054 /* Mark BH routine as complete */
2055 info->bh_running = 0;
2056 info->bh_requested = 0;
2057 }
2058
2059 spin_unlock_irqrestore(&info->lock,flags);
2060
2061 return rc;
2062 }
2063
2064 /* Perform bottom half processing of work items queued by ISR.
2065 */
2066 void bh_handler(void* Context)
2067 {
2068 SLMP_INFO *info = (SLMP_INFO*)Context;
2069 int action;
2070
2071 if (!info)
2072 return;
2073
2074 if ( debug_level >= DEBUG_LEVEL_BH )
2075 printk( "%s(%d):%s bh_handler() entry\n",
2076 __FILE__,__LINE__,info->device_name);
2077
2078 info->bh_running = 1;
2079
2080 while((action = bh_action(info)) != 0) {
2081
2082 /* Process work item */
2083 if ( debug_level >= DEBUG_LEVEL_BH )
2084 printk( "%s(%d):%s bh_handler() work item action=%d\n",
2085 __FILE__,__LINE__,info->device_name, action);
2086
2087 switch (action) {
2088
2089 case BH_RECEIVE:
2090 bh_receive(info);
2091 break;
2092 case BH_TRANSMIT:
2093 bh_transmit(info);
2094 break;
2095 case BH_STATUS:
2096 bh_status(info);
2097 break;
2098 default:
2099 /* unknown work item ID */
2100 printk("%s(%d):%s Unknown work item ID=%08X!\n",
2101 __FILE__,__LINE__,info->device_name,action);
2102 break;
2103 }
2104 }
2105
2106 if ( debug_level >= DEBUG_LEVEL_BH )
2107 printk( "%s(%d):%s bh_handler() exit\n",
2108 __FILE__,__LINE__,info->device_name);
2109 }
2110
2111 void bh_receive(SLMP_INFO *info)
2112 {
2113 if ( debug_level >= DEBUG_LEVEL_BH )
2114 printk( "%s(%d):%s bh_receive()\n",
2115 __FILE__,__LINE__,info->device_name);
2116
2117 while( rx_get_frame(info) );
2118 }
2119
2120 void bh_transmit(SLMP_INFO *info)
2121 {
2122 struct tty_struct *tty = info->tty;
2123
2124 if ( debug_level >= DEBUG_LEVEL_BH )
2125 printk( "%s(%d):%s bh_transmit() entry\n",
2126 __FILE__,__LINE__,info->device_name);
2127
2128 if (tty) {
2129 tty_wakeup(tty);
2130 wake_up_interruptible(&tty->write_wait);
2131 }
2132 }
2133
2134 void bh_status(SLMP_INFO *info)
2135 {
2136 if ( debug_level >= DEBUG_LEVEL_BH )
2137 printk( "%s(%d):%s bh_status() entry\n",
2138 __FILE__,__LINE__,info->device_name);
2139
2140 info->ri_chkcount = 0;
2141 info->dsr_chkcount = 0;
2142 info->dcd_chkcount = 0;
2143 info->cts_chkcount = 0;
2144 }
2145
2146 void isr_timer(SLMP_INFO * info)
2147 {
2148 unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
2149
2150 /* IER2<7..4> = timer<3..0> interrupt enables (0=disabled) */
2151 write_reg(info, IER2, 0);
2152
2153 /* TMCS, Timer Control/Status Register
2154 *
2155 * 07 CMF, Compare match flag (read only) 1=match
2156 * 06 ECMI, CMF Interrupt Enable: 0=disabled
2157 * 05 Reserved, must be 0
2158 * 04 TME, Timer Enable
2159 * 03..00 Reserved, must be 0
2160 *
2161 * 0000 0000
2162 */
2163 write_reg(info, (unsigned char)(timer + TMCS), 0);
2164
2165 info->irq_occurred = TRUE;
2166
2167 if ( debug_level >= DEBUG_LEVEL_ISR )
2168 printk("%s(%d):%s isr_timer()\n",
2169 __FILE__,__LINE__,info->device_name);
2170 }
2171
2172 void isr_rxint(SLMP_INFO * info)
2173 {
2174 struct tty_struct *tty = info->tty;
2175 struct mgsl_icount *icount = &info->icount;
2176 unsigned char status = read_reg(info, SR1) & info->ie1_value & (FLGD + IDLD + CDCD + BRKD);
2177 unsigned char status2 = read_reg(info, SR2) & info->ie2_value & OVRN;
2178
2179 /* clear status bits */
2180 if (status)
2181 write_reg(info, SR1, status);
2182
2183 if (status2)
2184 write_reg(info, SR2, status2);
2185
2186 if ( debug_level >= DEBUG_LEVEL_ISR )
2187 printk("%s(%d):%s isr_rxint status=%02X %02x\n",
2188 __FILE__,__LINE__,info->device_name,status,status2);
2189
2190 if (info->params.mode == MGSL_MODE_ASYNC) {
2191 if (status & BRKD) {
2192 icount->brk++;
2193
2194 /* process break detection if tty control
2195 * is not set to ignore it
2196 */
2197 if ( tty ) {
2198 if (!(status & info->ignore_status_mask1)) {
2199 if (info->read_status_mask1 & BRKD) {
2200 tty_insert_flip_char(tty, 0, TTY_BREAK);
2201 if (info->flags & ASYNC_SAK)
2202 do_SAK(tty);
2203 }
2204 }
2205 }
2206 }
2207 }
2208 else {
2209 if (status & (FLGD|IDLD)) {
2210 if (status & FLGD)
2211 info->icount.exithunt++;
2212 else if (status & IDLD)
2213 info->icount.rxidle++;
2214 wake_up_interruptible(&info->event_wait_q);
2215 }
2216 }
2217
2218 if (status & CDCD) {
2219 /* simulate a common modem status change interrupt
2220 * for our handler
2221 */
2222 get_signals( info );
2223 isr_io_pin(info,
2224 MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD));
2225 }
2226 }
2227
2228 /*
2229 * handle async rx data interrupts
2230 */
2231 void isr_rxrdy(SLMP_INFO * info)
2232 {
2233 u16 status;
2234 unsigned char DataByte;
2235 struct tty_struct *tty = info->tty;
2236 struct mgsl_icount *icount = &info->icount;
2237
2238 if ( debug_level >= DEBUG_LEVEL_ISR )
2239 printk("%s(%d):%s isr_rxrdy\n",
2240 __FILE__,__LINE__,info->device_name);
2241
2242 while((status = read_reg(info,CST0)) & BIT0)
2243 {
2244 int flag = 0;
2245 int over = 0;
2246 DataByte = read_reg(info,TRB);
2247
2248 icount->rx++;
2249
2250 if ( status & (PE + FRME + OVRN) ) {
2251 printk("%s(%d):%s rxerr=%04X\n",
2252 __FILE__,__LINE__,info->device_name,status);
2253
2254 /* update error statistics */
2255 if (status & PE)
2256 icount->parity++;
2257 else if (status & FRME)
2258 icount->frame++;
2259 else if (status & OVRN)
2260 icount->overrun++;
2261
2262 /* discard char if tty control flags say so */
2263 if (status & info->ignore_status_mask2)
2264 continue;
2265
2266 status &= info->read_status_mask2;
2267
2268 if ( tty ) {
2269 if (status & PE)
2270 flag = TTY_PARITY;
2271 else if (status & FRME)
2272 flag = TTY_FRAME;
2273 if (status & OVRN) {
2274 /* Overrun is special, since it's
2275 * reported immediately, and doesn't
2276 * affect the current character
2277 */
2278 over = 1;
2279 }
2280 }
2281 } /* end of if (error) */
2282
2283 if ( tty ) {
2284 tty_insert_flip_char(tty, DataByte, flag);
2285 if (over)
2286 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
2287 }
2288 }
2289
2290 if ( debug_level >= DEBUG_LEVEL_ISR ) {
2291 printk("%s(%d):%s rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
2292 __FILE__,__LINE__,info->device_name,
2293 icount->rx,icount->brk,icount->parity,
2294 icount->frame,icount->overrun);
2295 }
2296
2297 if ( tty )
2298 tty_flip_buffer_push(tty);
2299 }
2300
2301 static void isr_txeom(SLMP_INFO * info, unsigned char status)
2302 {
2303 if ( debug_level >= DEBUG_LEVEL_ISR )
2304 printk("%s(%d):%s isr_txeom status=%02x\n",
2305 __FILE__,__LINE__,info->device_name,status);
2306
2307 write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
2308 write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2309 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2310
2311 if (status & UDRN) {
2312 write_reg(info, CMD, TXRESET);
2313 write_reg(info, CMD, TXENABLE);
2314 } else
2315 write_reg(info, CMD, TXBUFCLR);
2316
2317 /* disable and clear tx interrupts */
2318 info->ie0_value &= ~TXRDYE;
2319 info->ie1_value &= ~(IDLE + UDRN);
2320 write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2321 write_reg(info, SR1, (unsigned char)(UDRN + IDLE));
2322
2323 if ( info->tx_active ) {
2324 if (info->params.mode != MGSL_MODE_ASYNC) {
2325 if (status & UDRN)
2326 info->icount.txunder++;
2327 else if (status & IDLE)
2328 info->icount.txok++;
2329 }
2330
2331 info->tx_active = 0;
2332 info->tx_count = info->tx_put = info->tx_get = 0;
2333
2334 del_timer(&info->tx_timer);
2335
2336 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done ) {
2337 info->serial_signals &= ~SerialSignal_RTS;
2338 info->drop_rts_on_tx_done = 0;
2339 set_signals(info);
2340 }
2341
2342 #ifdef CONFIG_HDLC
2343 if (info->netcount)
2344 hdlcdev_tx_done(info);
2345 else
2346 #endif
2347 {
2348 if (info->tty && (info->tty->stopped || info->tty->hw_stopped)) {
2349 tx_stop(info);
2350 return;
2351 }
2352 info->pending_bh |= BH_TRANSMIT;
2353 }
2354 }
2355 }
2356
2357
2358 /*
2359 * handle tx status interrupts
2360 */
2361 void isr_txint(SLMP_INFO * info)
2362 {
2363 unsigned char status = read_reg(info, SR1) & info->ie1_value & (UDRN + IDLE + CCTS);
2364
2365 /* clear status bits */
2366 write_reg(info, SR1, status);
2367
2368 if ( debug_level >= DEBUG_LEVEL_ISR )
2369 printk("%s(%d):%s isr_txint status=%02x\n",
2370 __FILE__,__LINE__,info->device_name,status);
2371
2372 if (status & (UDRN + IDLE))
2373 isr_txeom(info, status);
2374
2375 if (status & CCTS) {
2376 /* simulate a common modem status change interrupt
2377 * for our handler
2378 */
2379 get_signals( info );
2380 isr_io_pin(info,
2381 MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS));
2382
2383 }
2384 }
2385
2386 /*
2387 * handle async tx data interrupts
2388 */
2389 void isr_txrdy(SLMP_INFO * info)
2390 {
2391 if ( debug_level >= DEBUG_LEVEL_ISR )
2392 printk("%s(%d):%s isr_txrdy() tx_count=%d\n",
2393 __FILE__,__LINE__,info->device_name,info->tx_count);
2394
2395 if (info->params.mode != MGSL_MODE_ASYNC) {
2396 /* disable TXRDY IRQ, enable IDLE IRQ */
2397 info->ie0_value &= ~TXRDYE;
2398 info->ie1_value |= IDLE;
2399 write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2400 return;
2401 }
2402
2403 if (info->tty && (info->tty->stopped || info->tty->hw_stopped)) {
2404 tx_stop(info);
2405 return;
2406 }
2407
2408 if ( info->tx_count )
2409 tx_load_fifo( info );
2410 else {
2411 info->tx_active = 0;
2412 info->ie0_value &= ~TXRDYE;
2413 write_reg(info, IE0, info->ie0_value);
2414 }
2415
2416 if (info->tx_count < WAKEUP_CHARS)
2417 info->pending_bh |= BH_TRANSMIT;
2418 }
2419
2420 void isr_rxdmaok(SLMP_INFO * info)
2421 {
2422 /* BIT7 = EOT (end of transfer)
2423 * BIT6 = EOM (end of message/frame)
2424 */
2425 unsigned char status = read_reg(info,RXDMA + DSR) & 0xc0;
2426
2427 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2428 write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2429
2430 if ( debug_level >= DEBUG_LEVEL_ISR )
2431 printk("%s(%d):%s isr_rxdmaok(), status=%02x\n",
2432 __FILE__,__LINE__,info->device_name,status);
2433
2434 info->pending_bh |= BH_RECEIVE;
2435 }
2436
2437 void isr_rxdmaerror(SLMP_INFO * info)
2438 {
2439 /* BIT5 = BOF (buffer overflow)
2440 * BIT4 = COF (counter overflow)
2441 */
2442 unsigned char status = read_reg(info,RXDMA + DSR) & 0x30;
2443
2444 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2445 write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2446
2447 if ( debug_level >= DEBUG_LEVEL_ISR )
2448 printk("%s(%d):%s isr_rxdmaerror(), status=%02x\n",
2449 __FILE__,__LINE__,info->device_name,status);
2450
2451 info->rx_overflow = TRUE;
2452 info->pending_bh |= BH_RECEIVE;
2453 }
2454
2455 void isr_txdmaok(SLMP_INFO * info)
2456 {
2457 unsigned char status_reg1 = read_reg(info, SR1);
2458
2459 write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
2460 write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2461 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2462
2463 if ( debug_level >= DEBUG_LEVEL_ISR )
2464 printk("%s(%d):%s isr_txdmaok(), status=%02x\n",
2465 __FILE__,__LINE__,info->device_name,status_reg1);
2466
2467 /* program TXRDY as FIFO empty flag, enable TXRDY IRQ */
2468 write_reg16(info, TRC0, 0);
2469 info->ie0_value |= TXRDYE;
2470 write_reg(info, IE0, info->ie0_value);
2471 }
2472
2473 void isr_txdmaerror(SLMP_INFO * info)
2474 {
2475 /* BIT5 = BOF (buffer overflow)
2476 * BIT4 = COF (counter overflow)
2477 */
2478 unsigned char status = read_reg(info,TXDMA + DSR) & 0x30;
2479
2480 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2481 write_reg(info, TXDMA + DSR, (unsigned char)(status | 1));
2482
2483 if ( debug_level >= DEBUG_LEVEL_ISR )
2484 printk("%s(%d):%s isr_txdmaerror(), status=%02x\n",
2485 __FILE__,__LINE__,info->device_name,status);
2486 }
2487
2488 /* handle input serial signal changes
2489 */
2490 void isr_io_pin( SLMP_INFO *info, u16 status )
2491 {
2492 struct mgsl_icount *icount;
2493
2494 if ( debug_level >= DEBUG_LEVEL_ISR )
2495 printk("%s(%d):isr_io_pin status=%04X\n",
2496 __FILE__,__LINE__,status);
2497
2498 if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
2499 MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
2500 icount = &info->icount;
2501 /* update input line counters */
2502 if (status & MISCSTATUS_RI_LATCHED) {
2503 icount->rng++;
2504 if ( status & SerialSignal_RI )
2505 info->input_signal_events.ri_up++;
2506 else
2507 info->input_signal_events.ri_down++;
2508 }
2509 if (status & MISCSTATUS_DSR_LATCHED) {
2510 icount->dsr++;
2511 if ( status & SerialSignal_DSR )
2512 info->input_signal_events.dsr_up++;
2513 else
2514 info->input_signal_events.dsr_down++;
2515 }
2516 if (status & MISCSTATUS_DCD_LATCHED) {
2517 if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2518 info->ie1_value &= ~CDCD;
2519 write_reg(info, IE1, info->ie1_value);
2520 }
2521 icount->dcd++;
2522 if (status & SerialSignal_DCD) {
2523 info->input_signal_events.dcd_up++;
2524 } else
2525 info->input_signal_events.dcd_down++;
2526 #ifdef CONFIG_HDLC
2527 if (info->netcount) {
2528 if (status & SerialSignal_DCD)
2529 netif_carrier_on(info->netdev);
2530 else
2531 netif_carrier_off(info->netdev);
2532 }
2533 #endif
2534 }
2535 if (status & MISCSTATUS_CTS_LATCHED)
2536 {
2537 if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2538 info->ie1_value &= ~CCTS;
2539 write_reg(info, IE1, info->ie1_value);
2540 }
2541 icount->cts++;
2542 if ( status & SerialSignal_CTS )
2543 info->input_signal_events.cts_up++;
2544 else
2545 info->input_signal_events.cts_down++;
2546 }
2547 wake_up_interruptible(&info->status_event_wait_q);
2548 wake_up_interruptible(&info->event_wait_q);
2549
2550 if ( (info->flags & ASYNC_CHECK_CD) &&
2551 (status & MISCSTATUS_DCD_LATCHED) ) {
2552 if ( debug_level >= DEBUG_LEVEL_ISR )
2553 printk("%s CD now %s...", info->device_name,
2554 (status & SerialSignal_DCD) ? "on" : "off");
2555 if (status & SerialSignal_DCD)
2556 wake_up_interruptible(&info->open_wait);
2557 else {
2558 if ( debug_level >= DEBUG_LEVEL_ISR )
2559 printk("doing serial hangup...");
2560 if (info->tty)
2561 tty_hangup(info->tty);
2562 }
2563 }
2564
2565 if ( (info->flags & ASYNC_CTS_FLOW) &&
2566 (status & MISCSTATUS_CTS_LATCHED) ) {
2567 if ( info->tty ) {
2568 if (info->tty->hw_stopped) {
2569 if (status & SerialSignal_CTS) {
2570 if ( debug_level >= DEBUG_LEVEL_ISR )
2571 printk("CTS tx start...");
2572 info->tty->hw_stopped = 0;
2573 tx_start(info);
2574 info->pending_bh |= BH_TRANSMIT;
2575 return;
2576 }
2577 } else {
2578 if (!(status & SerialSignal_CTS)) {
2579 if ( debug_level >= DEBUG_LEVEL_ISR )
2580 printk("CTS tx stop...");
2581 info->tty->hw_stopped = 1;
2582 tx_stop(info);
2583 }
2584 }
2585 }
2586 }
2587 }
2588
2589 info->pending_bh |= BH_STATUS;
2590 }
2591
2592 /* Interrupt service routine entry point.
2593 *
2594 * Arguments:
2595 * irq interrupt number that caused interrupt
2596 * dev_id device ID supplied during interrupt registration
2597 * regs interrupted processor context
2598 */
2599 static irqreturn_t synclinkmp_interrupt(int irq, void *dev_id,
2600 struct pt_regs *regs)
2601 {
2602 SLMP_INFO * info;
2603 unsigned char status, status0, status1=0;
2604 unsigned char dmastatus, dmastatus0, dmastatus1=0;
2605 unsigned char timerstatus0, timerstatus1=0;
2606 unsigned char shift;
2607 unsigned int i;
2608 unsigned short tmp;
2609
2610 if ( debug_level >= DEBUG_LEVEL_ISR )
2611 printk("%s(%d): synclinkmp_interrupt(%d)entry.\n",
2612 __FILE__,__LINE__,irq);
2613
2614 info = (SLMP_INFO *)dev_id;
2615 if (!info)
2616 return IRQ_NONE;
2617
2618 spin_lock(&info->lock);
2619
2620 for(;;) {
2621
2622 /* get status for SCA0 (ports 0-1) */
2623 tmp = read_reg16(info, ISR0); /* get ISR0 and ISR1 in one read */
2624 status0 = (unsigned char)tmp;
2625 dmastatus0 = (unsigned char)(tmp>>8);
2626 timerstatus0 = read_reg(info, ISR2);
2627
2628 if ( debug_level >= DEBUG_LEVEL_ISR )
2629 printk("%s(%d):%s status0=%02x, dmastatus0=%02x, timerstatus0=%02x\n",
2630 __FILE__,__LINE__,info->device_name,
2631 status0,dmastatus0,timerstatus0);
2632
2633 if (info->port_count == 4) {
2634 /* get status for SCA1 (ports 2-3) */
2635 tmp = read_reg16(info->port_array[2], ISR0);
2636 status1 = (unsigned char)tmp;
2637 dmastatus1 = (unsigned char)(tmp>>8);
2638 timerstatus1 = read_reg(info->port_array[2], ISR2);
2639
2640 if ( debug_level >= DEBUG_LEVEL_ISR )
2641 printk("%s(%d):%s status1=%02x, dmastatus1=%02x, timerstatus1=%02x\n",
2642 __FILE__,__LINE__,info->device_name,
2643 status1,dmastatus1,timerstatus1);
2644 }
2645
2646 if (!status0 && !dmastatus0 && !timerstatus0 &&
2647 !status1 && !dmastatus1 && !timerstatus1)
2648 break;
2649
2650 for(i=0; i < info->port_count ; i++) {
2651 if (info->port_array[i] == NULL)
2652 continue;
2653 if (i < 2) {
2654 status = status0;
2655 dmastatus = dmastatus0;
2656 } else {
2657 status = status1;
2658 dmastatus = dmastatus1;
2659 }
2660
2661 shift = i & 1 ? 4 :0;
2662
2663 if (status & BIT0 << shift)
2664 isr_rxrdy(info->port_array[i]);
2665 if (status & BIT1 << shift)
2666 isr_txrdy(info->port_array[i]);
2667 if (status & BIT2 << shift)
2668 isr_rxint(info->port_array[i]);
2669 if (status & BIT3 << shift)
2670 isr_txint(info->port_array[i]);
2671
2672 if (dmastatus & BIT0 << shift)
2673 isr_rxdmaerror(info->port_array[i]);
2674 if (dmastatus & BIT1 << shift)
2675 isr_rxdmaok(info->port_array[i]);
2676 if (dmastatus & BIT2 << shift)
2677 isr_txdmaerror(info->port_array[i]);
2678 if (dmastatus & BIT3 << shift)
2679 isr_txdmaok(info->port_array[i]);
2680 }
2681
2682 if (timerstatus0 & (BIT5 | BIT4))
2683 isr_timer(info->port_array[0]);
2684 if (timerstatus0 & (BIT7 | BIT6))
2685 isr_timer(info->port_array[1]);
2686 if (timerstatus1 & (BIT5 | BIT4))
2687 isr_timer(info->port_array[2]);
2688 if (timerstatus1 & (BIT7 | BIT6))
2689 isr_timer(info->port_array[3]);
2690 }
2691
2692 for(i=0; i < info->port_count ; i++) {
2693 SLMP_INFO * port = info->port_array[i];
2694
2695 /* Request bottom half processing if there's something
2696 * for it to do and the bh is not already running.
2697 *
2698 * Note: startup adapter diags require interrupts.
2699 * do not request bottom half processing if the
2700 * device is not open in a normal mode.
2701 */
2702 if ( port && (port->count || port->netcount) &&
2703 port->pending_bh && !port->bh_running &&
2704 !port->bh_requested ) {
2705 if ( debug_level >= DEBUG_LEVEL_ISR )
2706 printk("%s(%d):%s queueing bh task.\n",
2707 __FILE__,__LINE__,port->device_name);
2708 schedule_work(&port->task);
2709 port->bh_requested = 1;
2710 }
2711 }
2712
2713 spin_unlock(&info->lock);
2714
2715 if ( debug_level >= DEBUG_LEVEL_ISR )
2716 printk("%s(%d):synclinkmp_interrupt(%d)exit.\n",
2717 __FILE__,__LINE__,irq);
2718 return IRQ_HANDLED;
2719 }
2720
2721 /* Initialize and start device.
2722 */
2723 static int startup(SLMP_INFO * info)
2724 {
2725 if ( debug_level >= DEBUG_LEVEL_INFO )
2726 printk("%s(%d):%s tx_releaseup()\n",__FILE__,__LINE__,info->device_name);
2727
2728 if (info->flags & ASYNC_INITIALIZED)
2729 return 0;
2730
2731 if (!info->tx_buf) {
2732 info->tx_buf = (unsigned char *)kmalloc(info->max_frame_size, GFP_KERNEL);
2733 if (!info->tx_buf) {
2734 printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
2735 __FILE__,__LINE__,info->device_name);
2736 return -ENOMEM;
2737 }
2738 }
2739
2740 info->pending_bh = 0;
2741
2742 memset(&info->icount, 0, sizeof(info->icount));
2743
2744 /* program hardware for current parameters */
2745 reset_port(info);
2746
2747 change_params(info);
2748
2749 info->status_timer.expires = jiffies + msecs_to_jiffies(10);
2750 add_timer(&info->status_timer);
2751
2752 if (info->tty)
2753 clear_bit(TTY_IO_ERROR, &info->tty->flags);
2754
2755 info->flags |= ASYNC_INITIALIZED;
2756
2757 return 0;
2758 }
2759
2760 /* Called by close() and hangup() to shutdown hardware
2761 */
2762 static void shutdown(SLMP_INFO * info)
2763 {
2764 unsigned long flags;
2765
2766 if (!(info->flags & ASYNC_INITIALIZED))
2767 return;
2768
2769 if (debug_level >= DEBUG_LEVEL_INFO)
2770 printk("%s(%d):%s synclinkmp_shutdown()\n",
2771 __FILE__,__LINE__, info->device_name );
2772
2773 /* clear status wait queue because status changes */
2774 /* can't happen after shutting down the hardware */
2775 wake_up_interruptible(&info->status_event_wait_q);
2776 wake_up_interruptible(&info->event_wait_q);
2777
2778 del_timer(&info->tx_timer);
2779 del_timer(&info->status_timer);
2780
2781 kfree(info->tx_buf);
2782 info->tx_buf = NULL;
2783
2784 spin_lock_irqsave(&info->lock,flags);
2785
2786 reset_port(info);
2787
2788 if (!info->tty || info->tty->termios->c_cflag & HUPCL) {
2789 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2790 set_signals(info);
2791 }
2792
2793 spin_unlock_irqrestore(&info->lock,flags);
2794
2795 if (info->tty)
2796 set_bit(TTY_IO_ERROR, &info->tty->flags);
2797
2798 info->flags &= ~ASYNC_INITIALIZED;
2799 }
2800
2801 static void program_hw(SLMP_INFO *info)
2802 {
2803 unsigned long flags;
2804
2805 spin_lock_irqsave(&info->lock,flags);
2806
2807 rx_stop(info);
2808 tx_stop(info);
2809
2810 info->tx_count = info->tx_put = info->tx_get = 0;
2811
2812 if (info->params.mode == MGSL_MODE_HDLC || info->netcount)
2813 hdlc_mode(info);
2814 else
2815 async_mode(info);
2816
2817 set_signals(info);
2818
2819 info->dcd_chkcount = 0;
2820 info->cts_chkcount = 0;
2821 info->ri_chkcount = 0;
2822 info->dsr_chkcount = 0;
2823
2824 info->ie1_value |= (CDCD|CCTS);
2825 write_reg(info, IE1, info->ie1_value);
2826
2827 get_signals(info);
2828
2829 if (info->netcount || (info->tty && info->tty->termios->c_cflag & CREAD) )
2830 rx_start(info);
2831
2832 spin_unlock_irqrestore(&info->lock,flags);
2833 }
2834
2835 /* Reconfigure adapter based on new parameters
2836 */
2837 static void change_params(SLMP_INFO *info)
2838 {
2839 unsigned cflag;
2840 int bits_per_char;
2841
2842 if (!info->tty || !info->tty->termios)
2843 return;
2844
2845 if (debug_level >= DEBUG_LEVEL_INFO)
2846 printk("%s(%d):%s change_params()\n",
2847 __FILE__,__LINE__, info->device_name );
2848
2849 cflag = info->tty->termios->c_cflag;
2850
2851 /* if B0 rate (hangup) specified then negate DTR and RTS */
2852 /* otherwise assert DTR and RTS */
2853 if (cflag & CBAUD)
2854 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
2855 else
2856 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2857
2858 /* byte size and parity */
2859
2860 switch (cflag & CSIZE) {
2861 case CS5: info->params.data_bits = 5; break;
2862 case CS6: info->params.data_bits = 6; break;
2863 case CS7: info->params.data_bits = 7; break;
2864 case CS8: info->params.data_bits = 8; break;
2865 /* Never happens, but GCC is too dumb to figure it out */
2866 default: info->params.data_bits = 7; break;
2867 }
2868
2869 if (cflag & CSTOPB)
2870 info->params.stop_bits = 2;
2871 else
2872 info->params.stop_bits = 1;
2873
2874 info->params.parity = ASYNC_PARITY_NONE;
2875 if (cflag & PARENB) {
2876 if (cflag & PARODD)
2877 info->params.parity = ASYNC_PARITY_ODD;
2878 else
2879 info->params.parity = ASYNC_PARITY_EVEN;
2880 #ifdef CMSPAR
2881 if (cflag & CMSPAR)
2882 info->params.parity = ASYNC_PARITY_SPACE;
2883 #endif
2884 }
2885
2886 /* calculate number of jiffies to transmit a full
2887 * FIFO (32 bytes) at specified data rate
2888 */
2889 bits_per_char = info->params.data_bits +
2890 info->params.stop_bits + 1;
2891
2892 /* if port data rate is set to 460800 or less then
2893 * allow tty settings to override, otherwise keep the
2894 * current data rate.
2895 */
2896 if (info->params.data_rate <= 460800) {
2897 info->params.data_rate = tty_get_baud_rate(info->tty);
2898 }
2899
2900 if ( info->params.data_rate ) {
2901 info->timeout = (32*HZ*bits_per_char) /
2902 info->params.data_rate;
2903 }
2904 info->timeout += HZ/50; /* Add .02 seconds of slop */
2905
2906 if (cflag & CRTSCTS)
2907 info->flags |= ASYNC_CTS_FLOW;
2908 else
2909 info->flags &= ~ASYNC_CTS_FLOW;
2910
2911 if (cflag & CLOCAL)
2912 info->flags &= ~ASYNC_CHECK_CD;
2913 else
2914 info->flags |= ASYNC_CHECK_CD;
2915
2916 /* process tty input control flags */
2917
2918 info->read_status_mask2 = OVRN;
2919 if (I_INPCK(info->tty))
2920 info->read_status_mask2 |= PE | FRME;
2921 if (I_BRKINT(info->tty) || I_PARMRK(info->tty))
2922 info->read_status_mask1 |= BRKD;
2923 if (I_IGNPAR(info->tty))
2924 info->ignore_status_mask2 |= PE | FRME;
2925 if (I_IGNBRK(info->tty)) {
2926 info->ignore_status_mask1 |= BRKD;
2927 /* If ignoring parity and break indicators, ignore
2928 * overruns too. (For real raw support).
2929 */
2930 if (I_IGNPAR(info->tty))
2931 info->ignore_status_mask2 |= OVRN;
2932 }
2933
2934 program_hw(info);
2935 }
2936
2937 static int get_stats(SLMP_INFO * info, struct mgsl_icount __user *user_icount)
2938 {
2939 int err;
2940
2941 if (debug_level >= DEBUG_LEVEL_INFO)
2942 printk("%s(%d):%s get_params()\n",
2943 __FILE__,__LINE__, info->device_name);
2944
2945 if (!user_icount) {
2946 memset(&info->icount, 0, sizeof(info->icount));
2947 } else {
2948 COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
2949 if (err)
2950 return -EFAULT;
2951 }
2952
2953 return 0;
2954 }
2955
2956 static int get_params(SLMP_INFO * info, MGSL_PARAMS __user *user_params)
2957 {
2958 int err;
2959 if (debug_level >= DEBUG_LEVEL_INFO)
2960 printk("%s(%d):%s get_params()\n",
2961 __FILE__,__LINE__, info->device_name);
2962
2963 COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
2964 if (err) {
2965 if ( debug_level >= DEBUG_LEVEL_INFO )
2966 printk( "%s(%d):%s get_params() user buffer copy failed\n",
2967 __FILE__,__LINE__,info->device_name);
2968 return -EFAULT;
2969 }
2970
2971 return 0;
2972 }
2973
2974 static int set_params(SLMP_INFO * info, MGSL_PARAMS __user *new_params)
2975 {
2976 unsigned long flags;
2977 MGSL_PARAMS tmp_params;
2978 int err;
2979
2980 if (debug_level >= DEBUG_LEVEL_INFO)
2981 printk("%s(%d):%s set_params\n",
2982 __FILE__,__LINE__,info->device_name );
2983 COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
2984 if (err) {
2985 if ( debug_level >= DEBUG_LEVEL_INFO )
2986 printk( "%s(%d):%s set_params() user buffer copy failed\n",
2987 __FILE__,__LINE__,info->device_name);
2988 return -EFAULT;
2989 }
2990
2991 spin_lock_irqsave(&info->lock,flags);
2992 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
2993 spin_unlock_irqrestore(&info->lock,flags);
2994
2995 change_params(info);
2996
2997 return 0;
2998 }
2999
3000 static int get_txidle(SLMP_INFO * info, int __user *idle_mode)
3001 {
3002 int err;
3003
3004 if (debug_level >= DEBUG_LEVEL_INFO)
3005 printk("%s(%d):%s get_txidle()=%d\n",
3006 __FILE__,__LINE__, info->device_name, info->idle_mode);
3007
3008 COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
3009 if (err) {
3010 if ( debug_level >= DEBUG_LEVEL_INFO )
3011 printk( "%s(%d):%s get_txidle() user buffer copy failed\n",
3012 __FILE__,__LINE__,info->device_name);
3013 return -EFAULT;
3014 }
3015
3016 return 0;
3017 }
3018
3019 static int set_txidle(SLMP_INFO * info, int idle_mode)
3020 {
3021 unsigned long flags;
3022
3023 if (debug_level >= DEBUG_LEVEL_INFO)
3024 printk("%s(%d):%s set_txidle(%d)\n",
3025 __FILE__,__LINE__,info->device_name, idle_mode );
3026
3027 spin_lock_irqsave(&info->lock,flags);
3028 info->idle_mode = idle_mode;
3029 tx_set_idle( info );
3030 spin_unlock_irqrestore(&info->lock,flags);
3031 return 0;
3032 }
3033
3034 static int tx_enable(SLMP_INFO * info, int enable)
3035 {
3036 unsigned long flags;
3037
3038 if (debug_level >= DEBUG_LEVEL_INFO)
3039 printk("%s(%d):%s tx_enable(%d)\n",
3040 __FILE__,__LINE__,info->device_name, enable);
3041
3042 spin_lock_irqsave(&info->lock,flags);
3043 if ( enable ) {
3044 if ( !info->tx_enabled ) {
3045 tx_start(info);
3046 }
3047 } else {
3048 if ( info->tx_enabled )
3049 tx_stop(info);
3050 }
3051 spin_unlock_irqrestore(&info->lock,flags);
3052 return 0;
3053 }
3054
3055 /* abort send HDLC frame
3056 */
3057 static int tx_abort(SLMP_INFO * info)
3058 {
3059 unsigned long flags;
3060
3061 if (debug_level >= DEBUG_LEVEL_INFO)
3062 printk("%s(%d):%s tx_abort()\n",
3063 __FILE__,__LINE__,info->device_name);
3064
3065 spin_lock_irqsave(&info->lock,flags);
3066 if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC ) {
3067 info->ie1_value &= ~UDRN;
3068 info->ie1_value |= IDLE;
3069 write_reg(info, IE1, info->ie1_value); /* disable tx status interrupts */
3070 write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); /* clear pending */
3071
3072 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
3073 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
3074
3075 write_reg(info, CMD, TXABORT);
3076 }
3077 spin_unlock_irqrestore(&info->lock,flags);
3078 return 0;
3079 }
3080
3081 static int rx_enable(SLMP_INFO * info, int enable)
3082 {
3083 unsigned long flags;
3084
3085 if (debug_level >= DEBUG_LEVEL_INFO)
3086 printk("%s(%d):%s rx_enable(%d)\n",
3087 __FILE__,__LINE__,info->device_name,enable);
3088
3089 spin_lock_irqsave(&info->lock,flags);
3090 if ( enable ) {
3091 if ( !info->rx_enabled )
3092 rx_start(info);
3093 } else {
3094 if ( info->rx_enabled )
3095 rx_stop(info);
3096 }
3097 spin_unlock_irqrestore(&info->lock,flags);
3098 return 0;
3099 }
3100
3101 /* wait for specified event to occur
3102 */
3103 static int wait_mgsl_event(SLMP_INFO * info, int __user *mask_ptr)
3104 {
3105 unsigned long flags;
3106 int s;
3107 int rc=0;
3108 struct mgsl_icount cprev, cnow;
3109 int events;
3110 int mask;
3111 struct _input_signal_events oldsigs, newsigs;
3112 DECLARE_WAITQUEUE(wait, current);
3113
3114 COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
3115 if (rc) {
3116 return -EFAULT;
3117 }
3118
3119 if (debug_level >= DEBUG_LEVEL_INFO)
3120 printk("%s(%d):%s wait_mgsl_event(%d)\n",
3121 __FILE__,__LINE__,info->device_name,mask);
3122
3123 spin_lock_irqsave(&info->lock,flags);
3124
3125 /* return immediately if state matches requested events */
3126 get_signals(info);
3127 s = info->serial_signals;
3128
3129 events = mask &
3130 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
3131 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
3132 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
3133 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
3134 if (events) {
3135 spin_unlock_irqrestore(&info->lock,flags);
3136 goto exit;
3137 }
3138
3139 /* save current irq counts */
3140 cprev = info->icount;
3141 oldsigs = info->input_signal_events;
3142
3143 /* enable hunt and idle irqs if needed */
3144 if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
3145 unsigned char oldval = info->ie1_value;
3146 unsigned char newval = oldval +
3147 (mask & MgslEvent_ExitHuntMode ? FLGD:0) +
3148 (mask & MgslEvent_IdleReceived ? IDLD:0);
3149 if ( oldval != newval ) {
3150 info->ie1_value = newval;
3151 write_reg(info, IE1, info->ie1_value);
3152 }
3153 }
3154
3155 set_current_state(TASK_INTERRUPTIBLE);
3156 add_wait_queue(&info->event_wait_q, &wait);
3157
3158 spin_unlock_irqrestore(&info->lock,flags);
3159
3160 for(;;) {
3161 schedule();
3162 if (signal_pending(current)) {
3163 rc = -ERESTARTSYS;
3164 break;
3165 }
3166
3167 /* get current irq counts */
3168 spin_lock_irqsave(&info->lock,flags);
3169 cnow = info->icount;
3170 newsigs = info->input_signal_events;
3171 set_current_state(TASK_INTERRUPTIBLE);
3172 spin_unlock_irqrestore(&info->lock,flags);
3173
3174 /* if no change, wait aborted for some reason */
3175 if (newsigs.dsr_up == oldsigs.dsr_up &&
3176 newsigs.dsr_down == oldsigs.dsr_down &&
3177 newsigs.dcd_up == oldsigs.dcd_up &&
3178 newsigs.dcd_down == oldsigs.dcd_down &&
3179 newsigs.cts_up == oldsigs.cts_up &&
3180 newsigs.cts_down == oldsigs.cts_down &&
3181 newsigs.ri_up == oldsigs.ri_up &&
3182 newsigs.ri_down == oldsigs.ri_down &&
3183 cnow.exithunt == cprev.exithunt &&
3184 cnow.rxidle == cprev.rxidle) {
3185 rc = -EIO;
3186 break;
3187 }
3188
3189 events = mask &
3190 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
3191 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
3192 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
3193 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
3194 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
3195 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
3196 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
3197 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
3198 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
3199 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
3200 if (events)
3201 break;
3202
3203 cprev = cnow;
3204 oldsigs = newsigs;
3205 }
3206
3207 remove_wait_queue(&info->event_wait_q, &wait);
3208 set_current_state(TASK_RUNNING);
3209
3210
3211 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
3212 spin_lock_irqsave(&info->lock,flags);
3213 if (!waitqueue_active(&info->event_wait_q)) {
3214 /* disable enable exit hunt mode/idle rcvd IRQs */
3215 info->ie1_value &= ~(FLGD|IDLD);
3216 write_reg(info, IE1, info->ie1_value);
3217 }
3218 spin_unlock_irqrestore(&info->lock,flags);
3219 }
3220 exit:
3221 if ( rc == 0 )
3222 PUT_USER(rc, events, mask_ptr);
3223
3224 return rc;
3225 }
3226
3227 static int modem_input_wait(SLMP_INFO *info,int arg)
3228 {
3229 unsigned long flags;
3230 int rc;
3231 struct mgsl_icount cprev, cnow;
3232 DECLARE_WAITQUEUE(wait, current);
3233
3234 /* save current irq counts */
3235 spin_lock_irqsave(&info->lock,flags);
3236 cprev = info->icount;
3237 add_wait_queue(&info->status_event_wait_q, &wait);
3238 set_current_state(TASK_INTERRUPTIBLE);
3239 spin_unlock_irqrestore(&info->lock,flags);
3240
3241 for(;;) {
3242 schedule();
3243 if (signal_pending(current)) {
3244 rc = -ERESTARTSYS;
3245 break;
3246 }
3247
3248 /* get new irq counts */
3249 spin_lock_irqsave(&info->lock,flags);
3250 cnow = info->icount;
3251 set_current_state(TASK_INTERRUPTIBLE);
3252 spin_unlock_irqrestore(&info->lock,flags);
3253
3254 /* if no change, wait aborted for some reason */
3255 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3256 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3257 rc = -EIO;
3258 break;
3259 }
3260
3261 /* check for change in caller specified modem input */
3262 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3263 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3264 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
3265 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3266 rc = 0;
3267 break;
3268 }
3269
3270 cprev = cnow;
3271 }
3272 remove_wait_queue(&info->status_event_wait_q, &wait);
3273 set_current_state(TASK_RUNNING);
3274 return rc;
3275 }
3276
3277 /* return the state of the serial control and status signals
3278 */
3279 static int tiocmget(struct tty_struct *tty, struct file *file)
3280 {
3281 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
3282 unsigned int result;
3283 unsigned long flags;
3284
3285 spin_lock_irqsave(&info->lock,flags);
3286 get_signals(info);
3287 spin_unlock_irqrestore(&info->lock,flags);
3288
3289 result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3290 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3291 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3292 ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG:0) +
3293 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3294 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3295
3296 if (debug_level >= DEBUG_LEVEL_INFO)
3297 printk("%s(%d):%s tiocmget() value=%08X\n",
3298 __FILE__,__LINE__, info->device_name, result );
3299 return result;
3300 }
3301
3302 /* set modem control signals (DTR/RTS)
3303 */
3304 static int tiocmset(struct tty_struct *tty, struct file *file,
3305 unsigned int set, unsigned int clear)
3306 {
3307 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
3308 unsigned long flags;
3309
3310 if (debug_level >= DEBUG_LEVEL_INFO)
3311 printk("%s(%d):%s tiocmset(%x,%x)\n",
3312 __FILE__,__LINE__,info->device_name, set, clear);
3313
3314 if (set & TIOCM_RTS)
3315 info->serial_signals |= SerialSignal_RTS;
3316 if (set & TIOCM_DTR)
3317 info->serial_signals |= SerialSignal_DTR;
3318 if (clear & TIOCM_RTS)
3319 info->serial_signals &= ~SerialSignal_RTS;
3320 if (clear & TIOCM_DTR)
3321 info->serial_signals &= ~SerialSignal_DTR;
3322
3323 spin_lock_irqsave(&info->lock,flags);
3324 set_signals(info);
3325 spin_unlock_irqrestore(&info->lock,flags);
3326
3327 return 0;
3328 }
3329
3330
3331
3332 /* Block the current process until the specified port is ready to open.
3333 */
3334 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3335 SLMP_INFO *info)
3336 {
3337 DECLARE_WAITQUEUE(wait, current);
3338 int retval;
3339 int do_clocal = 0, extra_count = 0;
3340 unsigned long flags;
3341
3342 if (debug_level >= DEBUG_LEVEL_INFO)
3343 printk("%s(%d):%s block_til_ready()\n",
3344 __FILE__,__LINE__, tty->driver->name );
3345
3346 if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3347 /* nonblock mode is set or port is not enabled */
3348 /* just verify that callout device is not active */
3349 info->flags |= ASYNC_NORMAL_ACTIVE;
3350 return 0;
3351 }
3352
3353 if (tty->termios->c_cflag & CLOCAL)
3354 do_clocal = 1;
3355
3356 /* Wait for carrier detect and the line to become
3357 * free (i.e., not in use by the callout). While we are in
3358 * this loop, info->count is dropped by one, so that
3359 * close() knows when to free things. We restore it upon
3360 * exit, either normal or abnormal.
3361 */
3362
3363 retval = 0;
3364 add_wait_queue(&info->open_wait, &wait);
3365
3366 if (debug_level >= DEBUG_LEVEL_INFO)
3367 printk("%s(%d):%s block_til_ready() before block, count=%d\n",
3368 __FILE__,__LINE__, tty->driver->name, info->count );
3369
3370 spin_lock_irqsave(&info->lock, flags);
3371 if (!tty_hung_up_p(filp)) {
3372 extra_count = 1;
3373 info->count--;
3374 }
3375 spin_unlock_irqrestore(&info->lock, flags);
3376 info->blocked_open++;
3377
3378 while (1) {
3379 if ((tty->termios->c_cflag & CBAUD)) {
3380 spin_lock_irqsave(&info->lock,flags);
3381 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
3382 set_signals(info);
3383 spin_unlock_irqrestore(&info->lock,flags);
3384 }
3385
3386 set_current_state(TASK_INTERRUPTIBLE);
3387
3388 if (tty_hung_up_p(filp) || !(info->flags & ASYNC_INITIALIZED)){
3389 retval = (info->flags & ASYNC_HUP_NOTIFY) ?
3390 -EAGAIN : -ERESTARTSYS;
3391 break;
3392 }
3393
3394 spin_lock_irqsave(&info->lock,flags);
3395 get_signals(info);
3396 spin_unlock_irqrestore(&info->lock,flags);
3397
3398 if (!(info->flags & ASYNC_CLOSING) &&
3399 (do_clocal || (info->serial_signals & SerialSignal_DCD)) ) {
3400 break;
3401 }
3402
3403 if (signal_pending(current)) {
3404 retval = -ERESTARTSYS;
3405 break;
3406 }
3407
3408 if (debug_level >= DEBUG_LEVEL_INFO)
3409 printk("%s(%d):%s block_til_ready() count=%d\n",
3410 __FILE__,__LINE__, tty->driver->name, info->count );
3411
3412 schedule();
3413 }
3414
3415 set_current_state(TASK_RUNNING);
3416 remove_wait_queue(&info->open_wait, &wait);
3417
3418 if (extra_count)
3419 info->count++;
3420 info->blocked_open--;
3421
3422 if (debug_level >= DEBUG_LEVEL_INFO)
3423 printk("%s(%d):%s block_til_ready() after, count=%d\n",
3424 __FILE__,__LINE__, tty->driver->name, info->count );
3425
3426 if (!retval)
3427 info->flags |= ASYNC_NORMAL_ACTIVE;
3428
3429 return retval;
3430 }
3431
3432 int alloc_dma_bufs(SLMP_INFO *info)
3433 {
3434 unsigned short BuffersPerFrame;
3435 unsigned short BufferCount;
3436
3437 // Force allocation to start at 64K boundary for each port.
3438 // This is necessary because *all* buffer descriptors for a port
3439 // *must* be in the same 64K block. All descriptors on a port
3440 // share a common 'base' address (upper 8 bits of 24 bits) programmed
3441 // into the CBP register.
3442 info->port_array[0]->last_mem_alloc = (SCA_MEM_SIZE/4) * info->port_num;
3443
3444 /* Calculate the number of DMA buffers necessary to hold the */
3445 /* largest allowable frame size. Note: If the max frame size is */
3446 /* not an even multiple of the DMA buffer size then we need to */
3447 /* round the buffer count per frame up one. */
3448
3449 BuffersPerFrame = (unsigned short)(info->max_frame_size/SCABUFSIZE);
3450 if ( info->max_frame_size % SCABUFSIZE )
3451 BuffersPerFrame++;
3452
3453 /* calculate total number of data buffers (SCABUFSIZE) possible
3454 * in one ports memory (SCA_MEM_SIZE/4) after allocating memory
3455 * for the descriptor list (BUFFERLISTSIZE).
3456 */
3457 BufferCount = (SCA_MEM_SIZE/4 - BUFFERLISTSIZE)/SCABUFSIZE;
3458
3459 /* limit number of buffers to maximum amount of descriptors */
3460 if (BufferCount > BUFFERLISTSIZE/sizeof(SCADESC))
3461 BufferCount = BUFFERLISTSIZE/sizeof(SCADESC);
3462
3463 /* use enough buffers to transmit one max size frame */
3464 info->tx_buf_count = BuffersPerFrame + 1;
3465
3466 /* never use more than half the available buffers for transmit */
3467 if (info->tx_buf_count > (BufferCount/2))
3468 info->tx_buf_count = BufferCount/2;
3469
3470 if (info->tx_buf_count > SCAMAXDESC)
3471 info->tx_buf_count = SCAMAXDESC;
3472
3473 /* use remaining buffers for receive */
3474 info->rx_buf_count = BufferCount - info->tx_buf_count;
3475
3476 if (info->rx_buf_count > SCAMAXDESC)
3477 info->rx_buf_count = SCAMAXDESC;
3478
3479 if ( debug_level >= DEBUG_LEVEL_INFO )
3480 printk("%s(%d):%s Allocating %d TX and %d RX DMA buffers.\n",
3481 __FILE__,__LINE__, info->device_name,
3482 info->tx_buf_count,info->rx_buf_count);
3483
3484 if ( alloc_buf_list( info ) < 0 ||
3485 alloc_frame_bufs(info,
3486 info->rx_buf_list,
3487 info->rx_buf_list_ex,
3488 info->rx_buf_count) < 0 ||
3489 alloc_frame_bufs(info,
3490 info->tx_buf_list,
3491 info->tx_buf_list_ex,
3492 info->tx_buf_count) < 0 ||
3493 alloc_tmp_rx_buf(info) < 0 ) {
3494 printk("%s(%d):%s Can't allocate DMA buffer memory\n",
3495 __FILE__,__LINE__, info->device_name);
3496 return -ENOMEM;
3497 }
3498
3499 rx_reset_buffers( info );
3500
3501 return 0;
3502 }
3503
3504 /* Allocate DMA buffers for the transmit and receive descriptor lists.
3505 */
3506 int alloc_buf_list(SLMP_INFO *info)
3507 {
3508 unsigned int i;
3509
3510 /* build list in adapter shared memory */
3511 info->buffer_list = info->memory_base + info->port_array[0]->last_mem_alloc;
3512 info->buffer_list_phys = info->port_array[0]->last_mem_alloc;
3513 info->port_array[0]->last_mem_alloc += BUFFERLISTSIZE;
3514
3515 memset(info->buffer_list, 0, BUFFERLISTSIZE);
3516
3517 /* Save virtual address pointers to the receive and */
3518 /* transmit buffer lists. (Receive 1st). These pointers will */
3519 /* be used by the processor to access the lists. */
3520 info->rx_buf_list = (SCADESC *)info->buffer_list;
3521
3522 info->tx_buf_list = (SCADESC *)info->buffer_list;
3523 info->tx_buf_list += info->rx_buf_count;
3524
3525 /* Build links for circular buffer entry lists (tx and rx)
3526 *
3527 * Note: links are physical addresses read by the SCA device
3528 * to determine the next buffer entry to use.
3529 */
3530
3531 for ( i = 0; i < info->rx_buf_count; i++ ) {
3532 /* calculate and store physical address of this buffer entry */
3533 info->rx_buf_list_ex[i].phys_entry =
3534 info->buffer_list_phys + (i * sizeof(SCABUFSIZE));
3535
3536 /* calculate and store physical address of */
3537 /* next entry in cirular list of entries */
3538 info->rx_buf_list[i].next = info->buffer_list_phys;
3539 if ( i < info->rx_buf_count - 1 )
3540 info->rx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3541
3542 info->rx_buf_list[i].length = SCABUFSIZE;
3543 }
3544
3545 for ( i = 0; i < info->tx_buf_count; i++ ) {
3546 /* calculate and store physical address of this buffer entry */
3547 info->tx_buf_list_ex[i].phys_entry = info->buffer_list_phys +
3548 ((info->rx_buf_count + i) * sizeof(SCADESC));
3549
3550 /* calculate and store physical address of */
3551 /* next entry in cirular list of entries */
3552
3553 info->tx_buf_list[i].next = info->buffer_list_phys +
3554 info->rx_buf_count * sizeof(SCADESC);
3555
3556 if ( i < info->tx_buf_count - 1 )
3557 info->tx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3558 }
3559
3560 return 0;
3561 }
3562
3563 /* Allocate the frame DMA buffers used by the specified buffer list.
3564 */
3565 int alloc_frame_bufs(SLMP_INFO *info, SCADESC *buf_list,SCADESC_EX *buf_list_ex,int count)
3566 {
3567 int i;
3568 unsigned long phys_addr;
3569
3570 for ( i = 0; i < count; i++ ) {
3571 buf_list_ex[i].virt_addr = info->memory_base + info->port_array[0]->last_mem_alloc;
3572 phys_addr = info->port_array[0]->last_mem_alloc;
3573 info->port_array[0]->last_mem_alloc += SCABUFSIZE;
3574
3575 buf_list[i].buf_ptr = (unsigned short)phys_addr;
3576 buf_list[i].buf_base = (unsigned char)(phys_addr >> 16);
3577 }
3578
3579 return 0;
3580 }
3581
3582 void free_dma_bufs(SLMP_INFO *info)
3583 {
3584 info->buffer_list = NULL;
3585 info->rx_buf_list = NULL;
3586 info->tx_buf_list = NULL;
3587 }
3588
3589 /* allocate buffer large enough to hold max_frame_size.
3590 * This buffer is used to pass an assembled frame to the line discipline.
3591 */
3592 int alloc_tmp_rx_buf(SLMP_INFO *info)
3593 {
3594 info->tmp_rx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
3595 if (info->tmp_rx_buf == NULL)
3596 return -ENOMEM;
3597 return 0;
3598 }
3599
3600 void free_tmp_rx_buf(SLMP_INFO *info)
3601 {
3602 kfree(info->tmp_rx_buf);
3603 info->tmp_rx_buf = NULL;
3604 }
3605
3606 int claim_resources(SLMP_INFO *info)
3607 {
3608 if (request_mem_region(info->phys_memory_base,SCA_MEM_SIZE,"synclinkmp") == NULL) {
3609 printk( "%s(%d):%s mem addr conflict, Addr=%08X\n",
3610 __FILE__,__LINE__,info->device_name, info->phys_memory_base);
3611 info->init_error = DiagStatus_AddressConflict;
3612 goto errout;
3613 }
3614 else
3615 info->shared_mem_requested = 1;
3616
3617 if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclinkmp") == NULL) {
3618 printk( "%s(%d):%s lcr mem addr conflict, Addr=%08X\n",
3619 __FILE__,__LINE__,info->device_name, info->phys_lcr_base);
3620 info->init_error = DiagStatus_AddressConflict;
3621 goto errout;
3622 }
3623 else
3624 info->lcr_mem_requested = 1;
3625
3626 if (request_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE,"synclinkmp") == NULL) {
3627 printk( "%s(%d):%s sca mem addr conflict, Addr=%08X\n",
3628 __FILE__,__LINE__,info->device_name, info->phys_sca_base);
3629 info->init_error = DiagStatus_AddressConflict;
3630 goto errout;
3631 }
3632 else
3633 info->sca_base_requested = 1;
3634
3635 if (request_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE,"synclinkmp") == NULL) {
3636 printk( "%s(%d):%s stat/ctrl mem addr conflict, Addr=%08X\n",
3637 __FILE__,__LINE__,info->device_name, info->phys_statctrl_base);
3638 info->init_error = DiagStatus_AddressConflict;
3639 goto errout;
3640 }
3641 else
3642 info->sca_statctrl_requested = 1;
3643
3644 info->memory_base = ioremap(info->phys_memory_base,SCA_MEM_SIZE);
3645 if (!info->memory_base) {
3646 printk( "%s(%d):%s Cant map shared memory, MemAddr=%08X\n",
3647 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3648 info->init_error = DiagStatus_CantAssignPciResources;
3649 goto errout;
3650 }
3651
3652 info->lcr_base = ioremap(info->phys_lcr_base,PAGE_SIZE);
3653 if (!info->lcr_base) {
3654 printk( "%s(%d):%s Cant map LCR memory, MemAddr=%08X\n",
3655 __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
3656 info->init_error = DiagStatus_CantAssignPciResources;
3657 goto errout;
3658 }
3659 info->lcr_base += info->lcr_offset;
3660
3661 info->sca_base = ioremap(info->phys_sca_base,PAGE_SIZE);
3662 if (!info->sca_base) {
3663 printk( "%s(%d):%s Cant map SCA memory, MemAddr=%08X\n",
3664 __FILE__,__LINE__,info->device_name, info->phys_sca_base );
3665 info->init_error = DiagStatus_CantAssignPciResources;
3666 goto errout;
3667 }
3668 info->sca_base += info->sca_offset;
3669
3670 info->statctrl_base = ioremap(info->phys_statctrl_base,PAGE_SIZE);
3671 if (!info->statctrl_base) {
3672 printk( "%s(%d):%s Cant map SCA Status/Control memory, MemAddr=%08X\n",
3673 __FILE__,__LINE__,info->device_name, info->phys_statctrl_base );
3674 info->init_error = DiagStatus_CantAssignPciResources;
3675 goto errout;
3676 }
3677 info->statctrl_base += info->statctrl_offset;
3678
3679 if ( !memory_test(info) ) {
3680 printk( "%s(%d):Shared Memory Test failed for device %s MemAddr=%08X\n",
3681 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3682 info->init_error = DiagStatus_MemoryError;
3683 goto errout;
3684 }
3685
3686 return 0;
3687
3688 errout:
3689 release_resources( info );
3690 return -ENODEV;
3691 }
3692
3693 void release_resources(SLMP_INFO *info)
3694 {
3695 if ( debug_level >= DEBUG_LEVEL_INFO )
3696 printk( "%s(%d):%s release_resources() entry\n",
3697 __FILE__,__LINE__,info->device_name );
3698
3699 if ( info->irq_requested ) {
3700 free_irq(info->irq_level, info);
3701 info->irq_requested = 0;
3702 }
3703
3704 if ( info->shared_mem_requested ) {
3705 release_mem_region(info->phys_memory_base,SCA_MEM_SIZE);
3706 info->shared_mem_requested = 0;
3707 }
3708 if ( info->lcr_mem_requested ) {
3709 release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
3710 info->lcr_mem_requested = 0;
3711 }
3712 if ( info->sca_base_requested ) {
3713 release_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE);
3714 info->sca_base_requested = 0;
3715 }
3716 if ( info->sca_statctrl_requested ) {
3717 release_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE);
3718 info->sca_statctrl_requested = 0;
3719 }
3720
3721 if (info->memory_base){
3722 iounmap(info->memory_base);
3723 info->memory_base = NULL;
3724 }
3725
3726 if (info->sca_base) {
3727 iounmap(info->sca_base - info->sca_offset);
3728 info->sca_base=NULL;
3729 }
3730
3731 if (info->statctrl_base) {
3732 iounmap(info->statctrl_base - info->statctrl_offset);
3733 info->statctrl_base=NULL;
3734 }
3735
3736 if (info->lcr_base){
3737 iounmap(info->lcr_base - info->lcr_offset);
3738 info->lcr_base = NULL;
3739 }
3740
3741 if ( debug_level >= DEBUG_LEVEL_INFO )
3742 printk( "%s(%d):%s release_resources() exit\n",
3743 __FILE__,__LINE__,info->device_name );
3744 }
3745
3746 /* Add the specified device instance data structure to the
3747 * global linked list of devices and increment the device count.
3748 */
3749 void add_device(SLMP_INFO *info)
3750 {
3751 info->next_device = NULL;
3752 info->line = synclinkmp_device_count;
3753 sprintf(info->device_name,"ttySLM%dp%d",info->adapter_num,info->port_num);
3754
3755 if (info->line < MAX_DEVICES) {
3756 if (maxframe[info->line])
3757 info->max_frame_size = maxframe[info->line];
3758 info->dosyncppp = dosyncppp[info->line];
3759 }
3760
3761 synclinkmp_device_count++;
3762
3763 if ( !synclinkmp_device_list )
3764 synclinkmp_device_list = info;
3765 else {
3766 SLMP_INFO *current_dev = synclinkmp_device_list;
3767 while( current_dev->next_device )
3768 current_dev = current_dev->next_device;
3769 current_dev->next_device = info;
3770 }
3771
3772 if ( info->max_frame_size < 4096 )
3773 info->max_frame_size = 4096;
3774 else if ( info->max_frame_size > 65535 )
3775 info->max_frame_size = 65535;
3776
3777 printk( "SyncLink MultiPort %s: "
3778 "Mem=(%08x %08X %08x %08X) IRQ=%d MaxFrameSize=%u\n",
3779 info->device_name,
3780 info->phys_sca_base,
3781 info->phys_memory_base,
3782 info->phys_statctrl_base,
3783 info->phys_lcr_base,
3784 info->irq_level,
3785 info->max_frame_size );
3786
3787 #ifdef CONFIG_HDLC
3788 hdlcdev_init(info);
3789 #endif
3790 }
3791
3792 /* Allocate and initialize a device instance structure
3793 *
3794 * Return Value: pointer to SLMP_INFO if success, otherwise NULL
3795 */
3796 static SLMP_INFO *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3797 {
3798 SLMP_INFO *info;
3799
3800 info = (SLMP_INFO *)kmalloc(sizeof(SLMP_INFO),
3801 GFP_KERNEL);
3802
3803 if (!info) {
3804 printk("%s(%d) Error can't allocate device instance data for adapter %d, port %d\n",
3805 __FILE__,__LINE__, adapter_num, port_num);
3806 } else {
3807 memset(info, 0, sizeof(SLMP_INFO));
3808 info->magic = MGSL_MAGIC;
3809 INIT_WORK(&info->task, bh_handler, info);
3810 info->max_frame_size = 4096;
3811 info->close_delay = 5*HZ/10;
3812 info->closing_wait = 30*HZ;
3813 init_waitqueue_head(&info->open_wait);
3814 init_waitqueue_head(&info->close_wait);
3815 init_waitqueue_head(&info->status_event_wait_q);
3816 init_waitqueue_head(&info->event_wait_q);
3817 spin_lock_init(&info->netlock);
3818 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3819 info->idle_mode = HDLC_TXIDLE_FLAGS;
3820 info->adapter_num = adapter_num;
3821 info->port_num = port_num;
3822
3823 /* Copy configuration info to device instance data */
3824 info->irq_level = pdev->irq;
3825 info->phys_lcr_base = pci_resource_start(pdev,0);
3826 info->phys_sca_base = pci_resource_start(pdev,2);
3827 info->phys_memory_base = pci_resource_start(pdev,3);
3828 info->phys_statctrl_base = pci_resource_start(pdev,4);
3829
3830 /* Because veremap only works on page boundaries we must map
3831 * a larger area than is actually implemented for the LCR
3832 * memory range. We map a full page starting at the page boundary.
3833 */
3834 info->lcr_offset = info->phys_lcr_base & (PAGE_SIZE-1);
3835 info->phys_lcr_base &= ~(PAGE_SIZE-1);
3836
3837 info->sca_offset = info->phys_sca_base & (PAGE_SIZE-1);
3838 info->phys_sca_base &= ~(PAGE_SIZE-1);
3839
3840 info->statctrl_offset = info->phys_statctrl_base & (PAGE_SIZE-1);
3841 info->phys_statctrl_base &= ~(PAGE_SIZE-1);
3842
3843 info->bus_type = MGSL_BUS_TYPE_PCI;
3844 info->irq_flags = IRQF_SHARED;
3845
3846 init_timer(&info->tx_timer);
3847 info->tx_timer.data = (unsigned long)info;
3848 info->tx_timer.function = tx_timeout;
3849
3850 init_timer(&info->status_timer);
3851 info->status_timer.data = (unsigned long)info;
3852 info->status_timer.function = status_timeout;
3853
3854 /* Store the PCI9050 misc control register value because a flaw
3855 * in the PCI9050 prevents LCR registers from being read if
3856 * BIOS assigns an LCR base address with bit 7 set.
3857 *
3858 * Only the misc control register is accessed for which only
3859 * write access is needed, so set an initial value and change
3860 * bits to the device instance data as we write the value
3861 * to the actual misc control register.
3862 */
3863 info->misc_ctrl_value = 0x087e4546;
3864
3865 /* initial port state is unknown - if startup errors
3866 * occur, init_error will be set to indicate the
3867 * problem. Once the port is fully initialized,
3868 * this value will be set to 0 to indicate the
3869 * port is available.
3870 */
3871 info->init_error = -1;
3872 }
3873
3874 return info;
3875 }
3876
3877 void device_init(int adapter_num, struct pci_dev *pdev)
3878 {
3879 SLMP_INFO *port_array[SCA_MAX_PORTS];
3880 int port;
3881
3882 /* allocate device instances for up to SCA_MAX_PORTS devices */
3883 for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3884 port_array[port] = alloc_dev(adapter_num,port,pdev);
3885 if( port_array[port] == NULL ) {
3886 for ( --port; port >= 0; --port )
3887 kfree(port_array[port]);
3888 return;
3889 }
3890 }
3891
3892 /* give copy of port_array to all ports and add to device list */
3893 for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3894 memcpy(port_array[port]->port_array,port_array,sizeof(port_array));
3895 add_device( port_array[port] );
3896 spin_lock_init(&port_array[port]->lock);
3897 }
3898
3899 /* Allocate and claim adapter resources */
3900 if ( !claim_resources(port_array[0]) ) {
3901
3902 alloc_dma_bufs(port_array[0]);
3903
3904 /* copy resource information from first port to others */
3905 for ( port = 1; port < SCA_MAX_PORTS; ++port ) {
3906 port_array[port]->lock = port_array[0]->lock;
3907 port_array[port]->irq_level = port_array[0]->irq_level;
3908 port_array[port]->memory_base = port_array[0]->memory_base;
3909 port_array[port]->sca_base = port_array[0]->sca_base;
3910 port_array[port]->statctrl_base = port_array[0]->statctrl_base;
3911 port_array[port]->lcr_base = port_array[0]->lcr_base;
3912 alloc_dma_bufs(port_array[port]);
3913 }
3914
3915 if ( request_irq(port_array[0]->irq_level,
3916 synclinkmp_interrupt,
3917 port_array[0]->irq_flags,
3918 port_array[0]->device_name,
3919 port_array[0]) < 0 ) {
3920 printk( "%s(%d):%s Cant request interrupt, IRQ=%d\n",
3921 __FILE__,__LINE__,
3922 port_array[0]->device_name,
3923 port_array[0]->irq_level );
3924 }
3925 else {
3926 port_array[0]->irq_requested = 1;
3927 adapter_test(port_array[0]);
3928 }
3929 }
3930 }
3931
3932 static struct tty_operations ops = {
3933 .open = open,
3934 .close = close,
3935 .write = write,
3936 .put_char = put_char,
3937 .flush_chars = flush_chars,
3938 .write_room = write_room,
3939 .chars_in_buffer = chars_in_buffer,
3940 .flush_buffer = flush_buffer,
3941 .ioctl = ioctl,
3942 .throttle = throttle,
3943 .unthrottle = unthrottle,
3944 .send_xchar = send_xchar,
3945 .break_ctl = set_break,
3946 .wait_until_sent = wait_until_sent,
3947 .read_proc = read_proc,
3948 .set_termios = set_termios,
3949 .stop = tx_hold,
3950 .start = tx_release,
3951 .hangup = hangup,
3952 .tiocmget = tiocmget,
3953 .tiocmset = tiocmset,
3954 };
3955
3956 static void synclinkmp_cleanup(void)
3957 {
3958 int rc;
3959 SLMP_INFO *info;
3960 SLMP_INFO *tmp;
3961
3962 printk("Unloading %s %s\n", driver_name, driver_version);
3963
3964 if (serial_driver) {
3965 if ((rc = tty_unregister_driver(serial_driver)))
3966 printk("%s(%d) failed to unregister tty driver err=%d\n",
3967 __FILE__,__LINE__,rc);
3968 put_tty_driver(serial_driver);
3969 }
3970
3971 /* reset devices */
3972 info = synclinkmp_device_list;
3973 while(info) {
3974 reset_port(info);
3975 info = info->next_device;
3976 }
3977
3978 /* release devices */
3979 info = synclinkmp_device_list;
3980 while(info) {
3981 #ifdef CONFIG_HDLC
3982 hdlcdev_exit(info);
3983 #endif
3984 free_dma_bufs(info);
3985 free_tmp_rx_buf(info);
3986 if ( info->port_num == 0 ) {
3987 if (info->sca_base)
3988 write_reg(info, LPR, 1); /* set low power mode */
3989 release_resources(info);
3990 }
3991 tmp = info;
3992 info = info->next_device;
3993 kfree(tmp);
3994 }
3995
3996 pci_unregister_driver(&synclinkmp_pci_driver);
3997 }
3998
3999 /* Driver initialization entry point.
4000 */
4001
4002 static int __init synclinkmp_init(void)
4003 {
4004 int rc;
4005
4006 if (break_on_load) {
4007 synclinkmp_get_text_ptr();
4008 BREAKPOINT();
4009 }
4010
4011 printk("%s %s\n", driver_name, driver_version);
4012
4013 if ((rc = pci_register_driver(&synclinkmp_pci_driver)) < 0) {
4014 printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
4015 return rc;
4016 }
4017
4018 serial_driver = alloc_tty_driver(128);
4019 if (!serial_driver) {
4020 rc = -ENOMEM;
4021 goto error;
4022 }
4023
4024 /* Initialize the tty_driver structure */
4025
4026 serial_driver->owner = THIS_MODULE;
4027 serial_driver->driver_name = "synclinkmp";
4028 serial_driver->name = "ttySLM";
4029 serial_driver->major = ttymajor;
4030 serial_driver->minor_start = 64;
4031 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
4032 serial_driver->subtype = SERIAL_TYPE_NORMAL;
4033 serial_driver->init_termios = tty_std_termios;
4034 serial_driver->init_termios.c_cflag =
4035 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
4036 serial_driver->flags = TTY_DRIVER_REAL_RAW;
4037 tty_set_operations(serial_driver, &ops);
4038 if ((rc = tty_register_driver(serial_driver)) < 0) {
4039 printk("%s(%d):Couldn't register serial driver\n",
4040 __FILE__,__LINE__);
4041 put_tty_driver(serial_driver);
4042 serial_driver = NULL;
4043 goto error;
4044 }
4045
4046 printk("%s %s, tty major#%d\n",
4047 driver_name, driver_version,
4048 serial_driver->major);
4049
4050 return 0;
4051
4052 error:
4053 synclinkmp_cleanup();
4054 return rc;
4055 }
4056
4057 static void __exit synclinkmp_exit(void)
4058 {
4059 synclinkmp_cleanup();
4060 }
4061
4062 module_init(synclinkmp_init);
4063 module_exit(synclinkmp_exit);
4064
4065 /* Set the port for internal loopback mode.
4066 * The TxCLK and RxCLK signals are generated from the BRG and
4067 * the TxD is looped back to the RxD internally.
4068 */
4069 void enable_loopback(SLMP_INFO *info, int enable)
4070 {
4071 if (enable) {
4072 /* MD2 (Mode Register 2)
4073 * 01..00 CNCT<1..0> Channel Connection 11=Local Loopback
4074 */
4075 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) | (BIT1 + BIT0)));
4076
4077 /* degate external TxC clock source */
4078 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4079 write_control_reg(info);
4080
4081 /* RXS/TXS (Rx/Tx clock source)
4082 * 07 Reserved, must be 0
4083 * 06..04 Clock Source, 100=BRG
4084 * 03..00 Clock Divisor, 0000=1
4085 */
4086 write_reg(info, RXS, 0x40);
4087 write_reg(info, TXS, 0x40);
4088
4089 } else {
4090 /* MD2 (Mode Register 2)
4091 * 01..00 CNCT<1..0> Channel connection, 0=normal
4092 */
4093 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) & ~(BIT1 + BIT0)));
4094
4095 /* RXS/TXS (Rx/Tx clock source)
4096 * 07 Reserved, must be 0
4097 * 06..04 Clock Source, 000=RxC/TxC Pin
4098 * 03..00 Clock Divisor, 0000=1
4099 */
4100 write_reg(info, RXS, 0x00);
4101 write_reg(info, TXS, 0x00);
4102 }
4103
4104 /* set LinkSpeed if available, otherwise default to 2Mbps */
4105 if (info->params.clock_speed)
4106 set_rate(info, info->params.clock_speed);
4107 else
4108 set_rate(info, 3686400);
4109 }
4110
4111 /* Set the baud rate register to the desired speed
4112 *
4113 * data_rate data rate of clock in bits per second
4114 * A data rate of 0 disables the AUX clock.
4115 */
4116 void set_rate( SLMP_INFO *info, u32 data_rate )
4117 {
4118 u32 TMCValue;
4119 unsigned char BRValue;
4120 u32 Divisor=0;
4121
4122 /* fBRG = fCLK/(TMC * 2^BR)
4123 */
4124 if (data_rate != 0) {
4125 Divisor = 14745600/data_rate;
4126 if (!Divisor)
4127 Divisor = 1;
4128
4129 TMCValue = Divisor;
4130
4131 BRValue = 0;
4132 if (TMCValue != 1 && TMCValue != 2) {
4133 /* BRValue of 0 provides 50/50 duty cycle *only* when
4134 * TMCValue is 1 or 2. BRValue of 1 to 9 always provides
4135 * 50/50 duty cycle.
4136 */
4137 BRValue = 1;
4138 TMCValue >>= 1;
4139 }
4140
4141 /* while TMCValue is too big for TMC register, divide
4142 * by 2 and increment BR exponent.
4143 */
4144 for(; TMCValue > 256 && BRValue < 10; BRValue++)
4145 TMCValue >>= 1;
4146
4147 write_reg(info, TXS,
4148 (unsigned char)((read_reg(info, TXS) & 0xf0) | BRValue));
4149 write_reg(info, RXS,
4150 (unsigned char)((read_reg(info, RXS) & 0xf0) | BRValue));
4151 write_reg(info, TMC, (unsigned char)TMCValue);
4152 }
4153 else {
4154 write_reg(info, TXS,0);
4155 write_reg(info, RXS,0);
4156 write_reg(info, TMC, 0);
4157 }
4158 }
4159
4160 /* Disable receiver
4161 */
4162 void rx_stop(SLMP_INFO *info)
4163 {
4164 if (debug_level >= DEBUG_LEVEL_ISR)
4165 printk("%s(%d):%s rx_stop()\n",
4166 __FILE__,__LINE__, info->device_name );
4167
4168 write_reg(info, CMD, RXRESET);
4169
4170 info->ie0_value &= ~RXRDYE;
4171 write_reg(info, IE0, info->ie0_value); /* disable Rx data interrupts */
4172
4173 write_reg(info, RXDMA + DSR, 0); /* disable Rx DMA */
4174 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4175 write_reg(info, RXDMA + DIR, 0); /* disable Rx DMA interrupts */
4176
4177 info->rx_enabled = 0;
4178 info->rx_overflow = 0;
4179 }
4180
4181 /* enable the receiver
4182 */
4183 void rx_start(SLMP_INFO *info)
4184 {
4185 int i;
4186
4187 if (debug_level >= DEBUG_LEVEL_ISR)
4188 printk("%s(%d):%s rx_start()\n",
4189 __FILE__,__LINE__, info->device_name );
4190
4191 write_reg(info, CMD, RXRESET);
4192
4193 if ( info->params.mode == MGSL_MODE_HDLC ) {
4194 /* HDLC, disabe IRQ on rxdata */
4195 info->ie0_value &= ~RXRDYE;
4196 write_reg(info, IE0, info->ie0_value);
4197
4198 /* Reset all Rx DMA buffers and program rx dma */
4199 write_reg(info, RXDMA + DSR, 0); /* disable Rx DMA */
4200 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4201
4202 for (i = 0; i < info->rx_buf_count; i++) {
4203 info->rx_buf_list[i].status = 0xff;
4204
4205 // throttle to 4 shared memory writes at a time to prevent
4206 // hogging local bus (keep latency time for DMA requests low).
4207 if (!(i % 4))
4208 read_status_reg(info);
4209 }
4210 info->current_rx_buf = 0;
4211
4212 /* set current/1st descriptor address */
4213 write_reg16(info, RXDMA + CDA,
4214 info->rx_buf_list_ex[0].phys_entry);
4215
4216 /* set new last rx descriptor address */
4217 write_reg16(info, RXDMA + EDA,
4218 info->rx_buf_list_ex[info->rx_buf_count - 1].phys_entry);
4219
4220 /* set buffer length (shared by all rx dma data buffers) */
4221 write_reg16(info, RXDMA + BFL, SCABUFSIZE);
4222
4223 write_reg(info, RXDMA + DIR, 0x60); /* enable Rx DMA interrupts (EOM/BOF) */
4224 write_reg(info, RXDMA + DSR, 0xf2); /* clear Rx DMA IRQs, enable Rx DMA */
4225 } else {
4226 /* async, enable IRQ on rxdata */
4227 info->ie0_value |= RXRDYE;
4228 write_reg(info, IE0, info->ie0_value);
4229 }
4230
4231 write_reg(info, CMD, RXENABLE);
4232
4233 info->rx_overflow = FALSE;
4234 info->rx_enabled = 1;
4235 }
4236
4237 /* Enable the transmitter and send a transmit frame if
4238 * one is loaded in the DMA buffers.
4239 */
4240 void tx_start(SLMP_INFO *info)
4241 {
4242 if (debug_level >= DEBUG_LEVEL_ISR)
4243 printk("%s(%d):%s tx_start() tx_count=%d\n",
4244 __FILE__,__LINE__, info->device_name,info->tx_count );
4245
4246 if (!info->tx_enabled ) {
4247 write_reg(info, CMD, TXRESET);
4248 write_reg(info, CMD, TXENABLE);
4249 info->tx_enabled = TRUE;
4250 }
4251
4252 if ( info->tx_count ) {
4253
4254 /* If auto RTS enabled and RTS is inactive, then assert */
4255 /* RTS and set a flag indicating that the driver should */
4256 /* negate RTS when the transmission completes. */
4257
4258 info->drop_rts_on_tx_done = 0;
4259
4260 if (info->params.mode != MGSL_MODE_ASYNC) {
4261
4262 if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
4263 get_signals( info );
4264 if ( !(info->serial_signals & SerialSignal_RTS) ) {
4265 info->serial_signals |= SerialSignal_RTS;
4266 set_signals( info );
4267 info->drop_rts_on_tx_done = 1;
4268 }
4269 }
4270
4271 write_reg16(info, TRC0,
4272 (unsigned short)(((tx_negate_fifo_level-1)<<8) + tx_active_fifo_level));
4273
4274 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
4275 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4276
4277 /* set TX CDA (current descriptor address) */
4278 write_reg16(info, TXDMA + CDA,
4279 info->tx_buf_list_ex[0].phys_entry);
4280
4281 /* set TX EDA (last descriptor address) */
4282 write_reg16(info, TXDMA + EDA,
4283 info->tx_buf_list_ex[info->last_tx_buf].phys_entry);
4284
4285 /* enable underrun IRQ */
4286 info->ie1_value &= ~IDLE;
4287 info->ie1_value |= UDRN;
4288 write_reg(info, IE1, info->ie1_value);
4289 write_reg(info, SR1, (unsigned char)(IDLE + UDRN));
4290
4291 write_reg(info, TXDMA + DIR, 0x40); /* enable Tx DMA interrupts (EOM) */
4292 write_reg(info, TXDMA + DSR, 0xf2); /* clear Tx DMA IRQs, enable Tx DMA */
4293
4294 info->tx_timer.expires = jiffies + msecs_to_jiffies(5000);
4295 add_timer(&info->tx_timer);
4296 }
4297 else {
4298 tx_load_fifo(info);
4299 /* async, enable IRQ on txdata */
4300 info->ie0_value |= TXRDYE;
4301 write_reg(info, IE0, info->ie0_value);
4302 }
4303
4304 info->tx_active = 1;
4305 }
4306 }
4307
4308 /* stop the transmitter and DMA
4309 */
4310 void tx_stop( SLMP_INFO *info )
4311 {
4312 if (debug_level >= DEBUG_LEVEL_ISR)
4313 printk("%s(%d):%s tx_stop()\n",
4314 __FILE__,__LINE__, info->device_name );
4315
4316 del_timer(&info->tx_timer);
4317
4318 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
4319 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4320
4321 write_reg(info, CMD, TXRESET);
4322
4323 info->ie1_value &= ~(UDRN + IDLE);
4324 write_reg(info, IE1, info->ie1_value); /* disable tx status interrupts */
4325 write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); /* clear pending */
4326
4327 info->ie0_value &= ~TXRDYE;
4328 write_reg(info, IE0, info->ie0_value); /* disable tx data interrupts */
4329
4330 info->tx_enabled = 0;
4331 info->tx_active = 0;
4332 }
4333
4334 /* Fill the transmit FIFO until the FIFO is full or
4335 * there is no more data to load.
4336 */
4337 void tx_load_fifo(SLMP_INFO *info)
4338 {
4339 u8 TwoBytes[2];
4340
4341 /* do nothing is now tx data available and no XON/XOFF pending */
4342
4343 if ( !info->tx_count && !info->x_char )
4344 return;
4345
4346 /* load the Transmit FIFO until FIFOs full or all data sent */
4347
4348 while( info->tx_count && (read_reg(info,SR0) & BIT1) ) {
4349
4350 /* there is more space in the transmit FIFO and */
4351 /* there is more data in transmit buffer */
4352
4353 if ( (info->tx_count > 1) && !info->x_char ) {
4354 /* write 16-bits */
4355 TwoBytes[0] = info->tx_buf[info->tx_get++];
4356 if (info->tx_get >= info->max_frame_size)
4357 info->tx_get -= info->max_frame_size;
4358 TwoBytes[1] = info->tx_buf[info->tx_get++];
4359 if (info->tx_get >= info->max_frame_size)
4360 info->tx_get -= info->max_frame_size;
4361
4362 write_reg16(info, TRB, *((u16 *)TwoBytes));
4363
4364 info->tx_count -= 2;
4365 info->icount.tx += 2;
4366 } else {
4367 /* only 1 byte left to transmit or 1 FIFO slot left */
4368
4369 if (info->x_char) {
4370 /* transmit pending high priority char */
4371 write_reg(info, TRB, info->x_char);
4372 info->x_char = 0;
4373 } else {
4374 write_reg(info, TRB, info->tx_buf[info->tx_get++]);
4375 if (info->tx_get >= info->max_frame_size)
4376 info->tx_get -= info->max_frame_size;
4377 info->tx_count--;
4378 }
4379 info->icount.tx++;
4380 }
4381 }
4382 }
4383
4384 /* Reset a port to a known state
4385 */
4386 void reset_port(SLMP_INFO *info)
4387 {
4388 if (info->sca_base) {
4389
4390 tx_stop(info);
4391 rx_stop(info);
4392
4393 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
4394 set_signals(info);
4395
4396 /* disable all port interrupts */
4397 info->ie0_value = 0;
4398 info->ie1_value = 0;
4399 info->ie2_value = 0;
4400 write_reg(info, IE0, info->ie0_value);
4401 write_reg(info, IE1, info->ie1_value);
4402 write_reg(info, IE2, info->ie2_value);
4403
4404 write_reg(info, CMD, CHRESET);
4405 }
4406 }
4407
4408 /* Reset all the ports to a known state.
4409 */
4410 void reset_adapter(SLMP_INFO *info)
4411 {
4412 int i;
4413
4414 for ( i=0; i < SCA_MAX_PORTS; ++i) {
4415 if (info->port_array[i])
4416 reset_port(info->port_array[i]);
4417 }
4418 }
4419
4420 /* Program port for asynchronous communications.
4421 */
4422 void async_mode(SLMP_INFO *info)
4423 {
4424
4425 unsigned char RegValue;
4426
4427 tx_stop(info);
4428 rx_stop(info);
4429
4430 /* MD0, Mode Register 0
4431 *
4432 * 07..05 PRCTL<2..0>, Protocol Mode, 000=async
4433 * 04 AUTO, Auto-enable (RTS/CTS/DCD)
4434 * 03 Reserved, must be 0
4435 * 02 CRCCC, CRC Calculation, 0=disabled
4436 * 01..00 STOP<1..0> Stop bits (00=1,10=2)
4437 *
4438 * 0000 0000
4439 */
4440 RegValue = 0x00;
4441 if (info->params.stop_bits != 1)
4442 RegValue |= BIT1;
4443 write_reg(info, MD0, RegValue);
4444
4445 /* MD1, Mode Register 1
4446 *
4447 * 07..06 BRATE<1..0>, bit rate, 00=1/1 01=1/16 10=1/32 11=1/64
4448 * 05..04 TXCHR<1..0>, tx char size, 00=8 bits,01=7,10=6,11=5
4449 * 03..02 RXCHR<1..0>, rx char size
4450 * 01..00 PMPM<1..0>, Parity mode, 00=none 10=even 11=odd
4451 *
4452 * 0100 0000
4453 */
4454 RegValue = 0x40;
4455 switch (info->params.data_bits) {
4456 case 7: RegValue |= BIT4 + BIT2; break;
4457 case 6: RegValue |= BIT5 + BIT3; break;
4458 case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break;
4459 }
4460 if (info->params.parity != ASYNC_PARITY_NONE) {
4461 RegValue |= BIT1;
4462 if (info->params.parity == ASYNC_PARITY_ODD)
4463 RegValue |= BIT0;
4464 }
4465 write_reg(info, MD1, RegValue);
4466
4467 /* MD2, Mode Register 2
4468 *
4469 * 07..02 Reserved, must be 0
4470 * 01..00 CNCT<1..0> Channel connection, 00=normal 11=local loopback
4471 *
4472 * 0000 0000
4473 */
4474 RegValue = 0x00;
4475 if (info->params.loopback)
4476 RegValue |= (BIT1 + BIT0);
4477 write_reg(info, MD2, RegValue);
4478
4479 /* RXS, Receive clock source
4480 *
4481 * 07 Reserved, must be 0
4482 * 06..04 RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4483 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4484 */
4485 RegValue=BIT6;
4486 write_reg(info, RXS, RegValue);
4487
4488 /* TXS, Transmit clock source
4489 *
4490 * 07 Reserved, must be 0
4491 * 06..04 RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4492 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4493 */
4494 RegValue=BIT6;
4495 write_reg(info, TXS, RegValue);
4496
4497 /* Control Register
4498 *
4499 * 6,4,2,0 CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4500 */
4501 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4502 write_control_reg(info);
4503
4504 tx_set_idle(info);
4505
4506 /* RRC Receive Ready Control 0
4507 *
4508 * 07..05 Reserved, must be 0
4509 * 04..00 RRC<4..0> Rx FIFO trigger active 0x00 = 1 byte
4510 */
4511 write_reg(info, RRC, 0x00);
4512
4513 /* TRC0 Transmit Ready Control 0
4514 *
4515 * 07..05 Reserved, must be 0
4516 * 04..00 TRC<4..0> Tx FIFO trigger active 0x10 = 16 bytes
4517 */
4518 write_reg(info, TRC0, 0x10);
4519
4520 /* TRC1 Transmit Ready Control 1
4521 *
4522 * 07..05 Reserved, must be 0
4523 * 04..00 TRC<4..0> Tx FIFO trigger inactive 0x1e = 31 bytes (full-1)
4524 */
4525 write_reg(info, TRC1, 0x1e);
4526
4527 /* CTL, MSCI control register
4528 *
4529 * 07..06 Reserved, set to 0
4530 * 05 UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4531 * 04 IDLC, idle control, 0=mark 1=idle register
4532 * 03 BRK, break, 0=off 1 =on (async)
4533 * 02 SYNCLD, sync char load enable (BSC) 1=enabled
4534 * 01 GOP, go active on poll (LOOP mode) 1=enabled
4535 * 00 RTS, RTS output control, 0=active 1=inactive
4536 *
4537 * 0001 0001
4538 */
4539 RegValue = 0x10;
4540 if (!(info->serial_signals & SerialSignal_RTS))
4541 RegValue |= 0x01;
4542 write_reg(info, CTL, RegValue);
4543
4544 /* enable status interrupts */
4545 info->ie0_value |= TXINTE + RXINTE;
4546 write_reg(info, IE0, info->ie0_value);
4547
4548 /* enable break detect interrupt */
4549 info->ie1_value = BRKD;
4550 write_reg(info, IE1, info->ie1_value);
4551
4552 /* enable rx overrun interrupt */
4553 info->ie2_value = OVRN;
4554 write_reg(info, IE2, info->ie2_value);
4555
4556 set_rate( info, info->params.data_rate * 16 );
4557 }
4558
4559 /* Program the SCA for HDLC communications.
4560 */
4561 void hdlc_mode(SLMP_INFO *info)
4562 {
4563 unsigned char RegValue;
4564 u32 DpllDivisor;
4565
4566 // Can't use DPLL because SCA outputs recovered clock on RxC when
4567 // DPLL mode selected. This causes output contention with RxC receiver.
4568 // Use of DPLL would require external hardware to disable RxC receiver
4569 // when DPLL mode selected.
4570 info->params.flags &= ~(HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL);
4571
4572 /* disable DMA interrupts */
4573 write_reg(info, TXDMA + DIR, 0);
4574 write_reg(info, RXDMA + DIR, 0);
4575
4576 /* MD0, Mode Register 0
4577 *
4578 * 07..05 PRCTL<2..0>, Protocol Mode, 100=HDLC
4579 * 04 AUTO, Auto-enable (RTS/CTS/DCD)
4580 * 03 Reserved, must be 0
4581 * 02 CRCCC, CRC Calculation, 1=enabled
4582 * 01 CRC1, CRC selection, 0=CRC-16,1=CRC-CCITT-16
4583 * 00 CRC0, CRC initial value, 1 = all 1s
4584 *
4585 * 1000 0001
4586 */
4587 RegValue = 0x81;
4588 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4589 RegValue |= BIT4;
4590 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4591 RegValue |= BIT4;
4592 if (info->params.crc_type == HDLC_CRC_16_CCITT)
4593 RegValue |= BIT2 + BIT1;
4594 write_reg(info, MD0, RegValue);
4595
4596 /* MD1, Mode Register 1
4597 *
4598 * 07..06 ADDRS<1..0>, Address detect, 00=no addr check
4599 * 05..04 TXCHR<1..0>, tx char size, 00=8 bits
4600 * 03..02 RXCHR<1..0>, rx char size, 00=8 bits
4601 * 01..00 PMPM<1..0>, Parity mode, 00=no parity
4602 *
4603 * 0000 0000
4604 */
4605 RegValue = 0x00;
4606 write_reg(info, MD1, RegValue);
4607
4608 /* MD2, Mode Register 2
4609 *
4610 * 07 NRZFM, 0=NRZ, 1=FM
4611 * 06..05 CODE<1..0> Encoding, 00=NRZ
4612 * 04..03 DRATE<1..0> DPLL Divisor, 00=8
4613 * 02 Reserved, must be 0
4614 * 01..00 CNCT<1..0> Channel connection, 0=normal
4615 *
4616 * 0000 0000
4617 */
4618 RegValue = 0x00;
4619 switch(info->params.encoding) {
4620 case HDLC_ENCODING_NRZI: RegValue |= BIT5; break;
4621 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT7 + BIT5; break; /* aka FM1 */
4622 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT7 + BIT6; break; /* aka FM0 */
4623 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT7; break; /* aka Manchester */
4624 #if 0
4625 case HDLC_ENCODING_NRZB: /* not supported */
4626 case HDLC_ENCODING_NRZI_MARK: /* not supported */
4627 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: /* not supported */
4628 #endif
4629 }
4630 if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
4631 DpllDivisor = 16;
4632 RegValue |= BIT3;
4633 } else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
4634 DpllDivisor = 8;
4635 } else {
4636 DpllDivisor = 32;
4637 RegValue |= BIT4;
4638 }
4639 write_reg(info, MD2, RegValue);
4640
4641
4642 /* RXS, Receive clock source
4643 *
4644 * 07 Reserved, must be 0
4645 * 06..04 RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4646 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4647 */
4648 RegValue=0;
4649 if (info->params.flags & HDLC_FLAG_RXC_BRG)
4650 RegValue |= BIT6;
4651 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4652 RegValue |= BIT6 + BIT5;
4653 write_reg(info, RXS, RegValue);
4654
4655 /* TXS, Transmit clock source
4656 *
4657 * 07 Reserved, must be 0
4658 * 06..04 RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4659 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4660 */
4661 RegValue=0;
4662 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4663 RegValue |= BIT6;
4664 if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4665 RegValue |= BIT6 + BIT5;
4666 write_reg(info, TXS, RegValue);
4667
4668 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4669 set_rate(info, info->params.clock_speed * DpllDivisor);
4670 else
4671 set_rate(info, info->params.clock_speed);
4672
4673 /* GPDATA (General Purpose I/O Data Register)
4674 *
4675 * 6,4,2,0 CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4676 */
4677 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4678 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4679 else
4680 info->port_array[0]->ctrlreg_value &= ~(BIT0 << (info->port_num * 2));
4681 write_control_reg(info);
4682
4683 /* RRC Receive Ready Control 0
4684 *
4685 * 07..05 Reserved, must be 0
4686 * 04..00 RRC<4..0> Rx FIFO trigger active
4687 */
4688 write_reg(info, RRC, rx_active_fifo_level);
4689
4690 /* TRC0 Transmit Ready Control 0
4691 *
4692 * 07..05 Reserved, must be 0
4693 * 04..00 TRC<4..0> Tx FIFO trigger active
4694 */
4695 write_reg(info, TRC0, tx_active_fifo_level);
4696
4697 /* TRC1 Transmit Ready Control 1
4698 *
4699 * 07..05 Reserved, must be 0
4700 * 04..00 TRC<4..0> Tx FIFO trigger inactive 0x1f = 32 bytes (full)
4701 */
4702 write_reg(info, TRC1, (unsigned char)(tx_negate_fifo_level - 1));
4703
4704 /* DMR, DMA Mode Register
4705 *
4706 * 07..05 Reserved, must be 0
4707 * 04 TMOD, Transfer Mode: 1=chained-block
4708 * 03 Reserved, must be 0
4709 * 02 NF, Number of Frames: 1=multi-frame
4710 * 01 CNTE, Frame End IRQ Counter enable: 0=disabled
4711 * 00 Reserved, must be 0
4712 *
4713 * 0001 0100
4714 */
4715 write_reg(info, TXDMA + DMR, 0x14);
4716 write_reg(info, RXDMA + DMR, 0x14);
4717
4718 /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4719 write_reg(info, RXDMA + CPB,
4720 (unsigned char)(info->buffer_list_phys >> 16));
4721
4722 /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4723 write_reg(info, TXDMA + CPB,
4724 (unsigned char)(info->buffer_list_phys >> 16));
4725
4726 /* enable status interrupts. other code enables/disables
4727 * the individual sources for these two interrupt classes.
4728 */
4729 info->ie0_value |= TXINTE + RXINTE;
4730 write_reg(info, IE0, info->ie0_value);
4731
4732 /* CTL, MSCI control register
4733 *
4734 * 07..06 Reserved, set to 0
4735 * 05 UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4736 * 04 IDLC, idle control, 0=mark 1=idle register
4737 * 03 BRK, break, 0=off 1 =on (async)
4738 * 02 SYNCLD, sync char load enable (BSC) 1=enabled
4739 * 01 GOP, go active on poll (LOOP mode) 1=enabled
4740 * 00 RTS, RTS output control, 0=active 1=inactive
4741 *
4742 * 0001 0001
4743 */
4744 RegValue = 0x10;
4745 if (!(info->serial_signals & SerialSignal_RTS))
4746 RegValue |= 0x01;
4747 write_reg(info, CTL, RegValue);
4748
4749 /* preamble not supported ! */
4750
4751 tx_set_idle(info);
4752 tx_stop(info);
4753 rx_stop(info);
4754
4755 set_rate(info, info->params.clock_speed);
4756
4757 if (info->params.loopback)
4758 enable_loopback(info,1);
4759 }
4760
4761 /* Set the transmit HDLC idle mode
4762 */
4763 void tx_set_idle(SLMP_INFO *info)
4764 {
4765 unsigned char RegValue = 0xff;
4766
4767 /* Map API idle mode to SCA register bits */
4768 switch(info->idle_mode) {
4769 case HDLC_TXIDLE_FLAGS: RegValue = 0x7e; break;
4770 case HDLC_TXIDLE_ALT_ZEROS_ONES: RegValue = 0xaa; break;
4771 case HDLC_TXIDLE_ZEROS: RegValue = 0x00; break;
4772 case HDLC_TXIDLE_ONES: RegValue = 0xff; break;
4773 case HDLC_TXIDLE_ALT_MARK_SPACE: RegValue = 0xaa; break;
4774 case HDLC_TXIDLE_SPACE: RegValue = 0x00; break;
4775 case HDLC_TXIDLE_MARK: RegValue = 0xff; break;
4776 }
4777
4778 write_reg(info, IDL, RegValue);
4779 }
4780
4781 /* Query the adapter for the state of the V24 status (input) signals.
4782 */
4783 void get_signals(SLMP_INFO *info)
4784 {
4785 u16 status = read_reg(info, SR3);
4786 u16 gpstatus = read_status_reg(info);
4787 u16 testbit;
4788
4789 /* clear all serial signals except DTR and RTS */
4790 info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS;
4791
4792 /* set serial signal bits to reflect MISR */
4793
4794 if (!(status & BIT3))
4795 info->serial_signals |= SerialSignal_CTS;
4796
4797 if ( !(status & BIT2))
4798 info->serial_signals |= SerialSignal_DCD;
4799
4800 testbit = BIT1 << (info->port_num * 2); // Port 0..3 RI is GPDATA<1,3,5,7>
4801 if (!(gpstatus & testbit))
4802 info->serial_signals |= SerialSignal_RI;
4803
4804 testbit = BIT0 << (info->port_num * 2); // Port 0..3 DSR is GPDATA<0,2,4,6>
4805 if (!(gpstatus & testbit))
4806 info->serial_signals |= SerialSignal_DSR;
4807 }
4808
4809 /* Set the state of DTR and RTS based on contents of
4810 * serial_signals member of device context.
4811 */
4812 void set_signals(SLMP_INFO *info)
4813 {
4814 unsigned char RegValue;
4815 u16 EnableBit;
4816
4817 RegValue = read_reg(info, CTL);
4818 if (info->serial_signals & SerialSignal_RTS)
4819 RegValue &= ~BIT0;
4820 else
4821 RegValue |= BIT0;
4822 write_reg(info, CTL, RegValue);
4823
4824 // Port 0..3 DTR is ctrl reg <1,3,5,7>
4825 EnableBit = BIT1 << (info->port_num*2);
4826 if (info->serial_signals & SerialSignal_DTR)
4827 info->port_array[0]->ctrlreg_value &= ~EnableBit;
4828 else
4829 info->port_array[0]->ctrlreg_value |= EnableBit;
4830 write_control_reg(info);
4831 }
4832
4833 /*******************/
4834 /* DMA Buffer Code */
4835 /*******************/
4836
4837 /* Set the count for all receive buffers to SCABUFSIZE
4838 * and set the current buffer to the first buffer. This effectively
4839 * makes all buffers free and discards any data in buffers.
4840 */
4841 void rx_reset_buffers(SLMP_INFO *info)
4842 {
4843 rx_free_frame_buffers(info, 0, info->rx_buf_count - 1);
4844 }
4845
4846 /* Free the buffers used by a received frame
4847 *
4848 * info pointer to device instance data
4849 * first index of 1st receive buffer of frame
4850 * last index of last receive buffer of frame
4851 */
4852 void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last)
4853 {
4854 int done = 0;
4855
4856 while(!done) {
4857 /* reset current buffer for reuse */
4858 info->rx_buf_list[first].status = 0xff;
4859
4860 if (first == last) {
4861 done = 1;
4862 /* set new last rx descriptor address */
4863 write_reg16(info, RXDMA + EDA, info->rx_buf_list_ex[first].phys_entry);
4864 }
4865
4866 first++;
4867 if (first == info->rx_buf_count)
4868 first = 0;
4869 }
4870
4871 /* set current buffer to next buffer after last buffer of frame */
4872 info->current_rx_buf = first;
4873 }
4874
4875 /* Return a received frame from the receive DMA buffers.
4876 * Only frames received without errors are returned.
4877 *
4878 * Return Value: 1 if frame returned, otherwise 0
4879 */
4880 int rx_get_frame(SLMP_INFO *info)
4881 {
4882 unsigned int StartIndex, EndIndex; /* index of 1st and last buffers of Rx frame */
4883 unsigned short status;
4884 unsigned int framesize = 0;
4885 int ReturnCode = 0;
4886 unsigned long flags;
4887 struct tty_struct *tty = info->tty;
4888 unsigned char addr_field = 0xff;
4889 SCADESC *desc;
4890 SCADESC_EX *desc_ex;
4891
4892 CheckAgain:
4893 /* assume no frame returned, set zero length */
4894 framesize = 0;
4895 addr_field = 0xff;
4896
4897 /*
4898 * current_rx_buf points to the 1st buffer of the next available
4899 * receive frame. To find the last buffer of the frame look for
4900 * a non-zero status field in the buffer entries. (The status
4901 * field is set by the 16C32 after completing a receive frame.
4902 */
4903 StartIndex = EndIndex = info->current_rx_buf;
4904
4905 for ( ;; ) {
4906 desc = &info->rx_buf_list[EndIndex];
4907 desc_ex = &info->rx_buf_list_ex[EndIndex];
4908
4909 if (desc->status == 0xff)
4910 goto Cleanup; /* current desc still in use, no frames available */
4911
4912 if (framesize == 0 && info->params.addr_filter != 0xff)
4913 addr_field = desc_ex->virt_addr[0];
4914
4915 framesize += desc->length;
4916
4917 /* Status != 0 means last buffer of frame */
4918 if (desc->status)
4919 break;
4920
4921 EndIndex++;
4922 if (EndIndex == info->rx_buf_count)
4923 EndIndex = 0;
4924
4925 if (EndIndex == info->current_rx_buf) {
4926 /* all buffers have been 'used' but none mark */
4927 /* the end of a frame. Reset buffers and receiver. */
4928 if ( info->rx_enabled ){
4929 spin_lock_irqsave(&info->lock,flags);
4930 rx_start(info);
4931 spin_unlock_irqrestore(&info->lock,flags);
4932 }
4933 goto Cleanup;
4934 }
4935
4936 }
4937
4938 /* check status of receive frame */
4939
4940 /* frame status is byte stored after frame data
4941 *
4942 * 7 EOM (end of msg), 1 = last buffer of frame
4943 * 6 Short Frame, 1 = short frame
4944 * 5 Abort, 1 = frame aborted
4945 * 4 Residue, 1 = last byte is partial
4946 * 3 Overrun, 1 = overrun occurred during frame reception
4947 * 2 CRC, 1 = CRC error detected
4948 *
4949 */
4950 status = desc->status;
4951
4952 /* ignore CRC bit if not using CRC (bit is undefined) */
4953 /* Note:CRC is not save to data buffer */
4954 if (info->params.crc_type == HDLC_CRC_NONE)
4955 status &= ~BIT2;
4956
4957 if (framesize == 0 ||
4958 (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4959 /* discard 0 byte frames, this seems to occur sometime
4960 * when remote is idling flags.
4961 */
4962 rx_free_frame_buffers(info, StartIndex, EndIndex);
4963 goto CheckAgain;
4964 }
4965
4966 if (framesize < 2)
4967 status |= BIT6;
4968
4969 if (status & (BIT6+BIT5+BIT3+BIT2)) {
4970 /* received frame has errors,
4971 * update counts and mark frame size as 0
4972 */
4973 if (status & BIT6)
4974 info->icount.rxshort++;
4975 else if (status & BIT5)
4976 info->icount.rxabort++;
4977 else if (status & BIT3)
4978 info->icount.rxover++;
4979 else
4980 info->icount.rxcrc++;
4981
4982 framesize = 0;
4983 #ifdef CONFIG_HDLC
4984 {
4985 struct net_device_stats *stats = hdlc_stats(info->netdev);
4986 stats->rx_errors++;
4987 stats->rx_frame_errors++;
4988 }
4989 #endif
4990 }
4991
4992 if ( debug_level >= DEBUG_LEVEL_BH )
4993 printk("%s(%d):%s rx_get_frame() status=%04X size=%d\n",
4994 __FILE__,__LINE__,info->device_name,status,framesize);
4995
4996 if ( debug_level >= DEBUG_LEVEL_DATA )
4997 trace_block(info,info->rx_buf_list_ex[StartIndex].virt_addr,
4998 min_t(int, framesize,SCABUFSIZE),0);
4999
5000 if (framesize) {
5001 if (framesize > info->max_frame_size)
5002 info->icount.rxlong++;
5003 else {
5004 /* copy dma buffer(s) to contiguous intermediate buffer */
5005 int copy_count = framesize;
5006 int index = StartIndex;
5007 unsigned char *ptmp = info->tmp_rx_buf;
5008 info->tmp_rx_buf_count = framesize;
5009
5010 info->icount.rxok++;
5011
5012 while(copy_count) {
5013 int partial_count = min(copy_count,SCABUFSIZE);
5014 memcpy( ptmp,
5015 info->rx_buf_list_ex[index].virt_addr,
5016 partial_count );
5017 ptmp += partial_count;
5018 copy_count -= partial_count;
5019
5020 if ( ++index == info->rx_buf_count )
5021 index = 0;
5022 }
5023
5024 #ifdef CONFIG_HDLC
5025 if (info->netcount)
5026 hdlcdev_rx(info,info->tmp_rx_buf,framesize);
5027 else
5028 #endif
5029 ldisc_receive_buf(tty,info->tmp_rx_buf,
5030 info->flag_buf, framesize);
5031 }
5032 }
5033 /* Free the buffers used by this frame. */
5034 rx_free_frame_buffers( info, StartIndex, EndIndex );
5035
5036 ReturnCode = 1;
5037
5038 Cleanup:
5039 if ( info->rx_enabled && info->rx_overflow ) {
5040 /* Receiver is enabled, but needs to restarted due to
5041 * rx buffer overflow. If buffers are empty, restart receiver.
5042 */
5043 if (info->rx_buf_list[EndIndex].status == 0xff) {
5044 spin_lock_irqsave(&info->lock,flags);
5045 rx_start(info);
5046 spin_unlock_irqrestore(&info->lock,flags);
5047 }
5048 }
5049
5050 return ReturnCode;
5051 }
5052
5053 /* load the transmit DMA buffer with data
5054 */
5055 void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count)
5056 {
5057 unsigned short copy_count;
5058 unsigned int i = 0;
5059 SCADESC *desc;
5060 SCADESC_EX *desc_ex;
5061
5062 if ( debug_level >= DEBUG_LEVEL_DATA )
5063 trace_block(info,buf, min_t(int, count,SCABUFSIZE), 1);
5064
5065 /* Copy source buffer to one or more DMA buffers, starting with
5066 * the first transmit dma buffer.
5067 */
5068 for(i=0;;)
5069 {
5070 copy_count = min_t(unsigned short,count,SCABUFSIZE);
5071
5072 desc = &info->tx_buf_list[i];
5073 desc_ex = &info->tx_buf_list_ex[i];
5074
5075 load_pci_memory(info, desc_ex->virt_addr,buf,copy_count);
5076
5077 desc->length = copy_count;
5078 desc->status = 0;
5079
5080 buf += copy_count;
5081 count -= copy_count;
5082
5083 if (!count)
5084 break;
5085
5086 i++;
5087 if (i >= info->tx_buf_count)
5088 i = 0;
5089 }
5090
5091 info->tx_buf_list[i].status = 0x81; /* set EOM and EOT status */
5092 info->last_tx_buf = ++i;
5093 }
5094
5095 int register_test(SLMP_INFO *info)
5096 {
5097 static unsigned char testval[] = {0x00, 0xff, 0xaa, 0x55, 0x69, 0x96};
5098 static unsigned int count = ARRAY_SIZE(testval);
5099 unsigned int i;
5100 int rc = TRUE;
5101 unsigned long flags;
5102
5103 spin_lock_irqsave(&info->lock,flags);
5104 reset_port(info);
5105
5106 /* assume failure */
5107 info->init_error = DiagStatus_AddressFailure;
5108
5109 /* Write bit patterns to various registers but do it out of */
5110 /* sync, then read back and verify values. */
5111
5112 for (i = 0 ; i < count ; i++) {
5113 write_reg(info, TMC, testval[i]);
5114 write_reg(info, IDL, testval[(i+1)%count]);
5115 write_reg(info, SA0, testval[(i+2)%count]);
5116 write_reg(info, SA1, testval[(i+3)%count]);
5117
5118 if ( (read_reg(info, TMC) != testval[i]) ||
5119 (read_reg(info, IDL) != testval[(i+1)%count]) ||
5120 (read_reg(info, SA0) != testval[(i+2)%count]) ||
5121 (read_reg(info, SA1) != testval[(i+3)%count]) )
5122 {
5123 rc = FALSE;
5124 break;
5125 }
5126 }
5127
5128 reset_port(info);
5129 spin_unlock_irqrestore(&info->lock,flags);
5130
5131 return rc;
5132 }
5133
5134 int irq_test(SLMP_INFO *info)
5135 {
5136 unsigned long timeout;
5137 unsigned long flags;
5138
5139 unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
5140
5141 spin_lock_irqsave(&info->lock,flags);
5142 reset_port(info);
5143
5144 /* assume failure */
5145 info->init_error = DiagStatus_IrqFailure;
5146 info->irq_occurred = FALSE;
5147
5148 /* setup timer0 on SCA0 to interrupt */
5149
5150 /* IER2<7..4> = timer<3..0> interrupt enables (1=enabled) */
5151 write_reg(info, IER2, (unsigned char)((info->port_num & 1) ? BIT6 : BIT4));
5152
5153 write_reg(info, (unsigned char)(timer + TEPR), 0); /* timer expand prescale */
5154 write_reg16(info, (unsigned char)(timer + TCONR), 1); /* timer constant */
5155
5156
5157 /* TMCS, Timer Control/Status Register
5158 *
5159 * 07 CMF, Compare match flag (read only) 1=match
5160 * 06 ECMI, CMF Interrupt Enable: 1=enabled
5161 * 05 Reserved, must be 0
5162 * 04 TME, Timer Enable
5163 * 03..00 Reserved, must be 0
5164 *
5165 * 0101 0000
5166 */
5167 write_reg(info, (unsigned char)(timer + TMCS), 0x50);
5168
5169 spin_unlock_irqrestore(&info->lock,flags);
5170
5171 timeout=100;
5172 while( timeout-- && !info->irq_occurred ) {
5173 msleep_interruptible(10);
5174 }
5175
5176 spin_lock_irqsave(&info->lock,flags);
5177 reset_port(info);
5178 spin_unlock_irqrestore(&info->lock,flags);
5179
5180 return info->irq_occurred;
5181 }
5182
5183 /* initialize individual SCA device (2 ports)
5184 */
5185 static int sca_init(SLMP_INFO *info)
5186 {
5187 /* set wait controller to single mem partition (low), no wait states */
5188 write_reg(info, PABR0, 0); /* wait controller addr boundary 0 */
5189 write_reg(info, PABR1, 0); /* wait controller addr boundary 1 */
5190 write_reg(info, WCRL, 0); /* wait controller low range */
5191 write_reg(info, WCRM, 0); /* wait controller mid range */
5192 write_reg(info, WCRH, 0); /* wait controller high range */
5193
5194 /* DPCR, DMA Priority Control
5195 *
5196 * 07..05 Not used, must be 0
5197 * 04 BRC, bus release condition: 0=all transfers complete
5198 * 03 CCC, channel change condition: 0=every cycle
5199 * 02..00 PR<2..0>, priority 100=round robin
5200 *
5201 * 00000100 = 0x04
5202 */
5203 write_reg(info, DPCR, dma_priority);
5204
5205 /* DMA Master Enable, BIT7: 1=enable all channels */
5206 write_reg(info, DMER, 0x80);
5207
5208 /* enable all interrupt classes */
5209 write_reg(info, IER0, 0xff); /* TxRDY,RxRDY,TxINT,RxINT (ports 0-1) */
5210 write_reg(info, IER1, 0xff); /* DMIB,DMIA (channels 0-3) */
5211 write_reg(info, IER2, 0xf0); /* TIRQ (timers 0-3) */
5212
5213 /* ITCR, interrupt control register
5214 * 07 IPC, interrupt priority, 0=MSCI->DMA
5215 * 06..05 IAK<1..0>, Acknowledge cycle, 00=non-ack cycle
5216 * 04 VOS, Vector Output, 0=unmodified vector
5217 * 03..00 Reserved, must be 0
5218 */
5219 write_reg(info, ITCR, 0);
5220
5221 return TRUE;
5222 }
5223
5224 /* initialize adapter hardware
5225 */
5226 int init_adapter(SLMP_INFO *info)
5227 {
5228 int i;
5229
5230 /* Set BIT30 of Local Control Reg 0x50 to reset SCA */
5231 volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5232 u32 readval;
5233
5234 info->misc_ctrl_value |= BIT30;
5235 *MiscCtrl = info->misc_ctrl_value;
5236
5237 /*
5238 * Force at least 170ns delay before clearing
5239 * reset bit. Each read from LCR takes at least
5240 * 30ns so 10 times for 300ns to be safe.
5241 */
5242 for(i=0;i<10;i++)
5243 readval = *MiscCtrl;
5244
5245 info->misc_ctrl_value &= ~BIT30;
5246 *MiscCtrl = info->misc_ctrl_value;
5247
5248 /* init control reg (all DTRs off, all clksel=input) */
5249 info->ctrlreg_value = 0xaa;
5250 write_control_reg(info);
5251
5252 {
5253 volatile u32 *LCR1BRDR = (u32 *)(info->lcr_base + 0x2c);
5254 lcr1_brdr_value &= ~(BIT5 + BIT4 + BIT3);
5255
5256 switch(read_ahead_count)
5257 {
5258 case 16:
5259 lcr1_brdr_value |= BIT5 + BIT4 + BIT3;
5260 break;
5261 case 8:
5262 lcr1_brdr_value |= BIT5 + BIT4;
5263 break;
5264 case 4:
5265 lcr1_brdr_value |= BIT5 + BIT3;
5266 break;
5267 case 0:
5268 lcr1_brdr_value |= BIT5;
5269 break;
5270 }
5271
5272 *LCR1BRDR = lcr1_brdr_value;
5273 *MiscCtrl = misc_ctrl_value;
5274 }
5275
5276 sca_init(info->port_array[0]);
5277 sca_init(info->port_array[2]);
5278
5279 return TRUE;
5280 }
5281
5282 /* Loopback an HDLC frame to test the hardware
5283 * interrupt and DMA functions.
5284 */
5285 int loopback_test(SLMP_INFO *info)
5286 {
5287 #define TESTFRAMESIZE 20
5288
5289 unsigned long timeout;
5290 u16 count = TESTFRAMESIZE;
5291 unsigned char buf[TESTFRAMESIZE];
5292 int rc = FALSE;
5293 unsigned long flags;
5294
5295 struct tty_struct *oldtty = info->tty;
5296 u32 speed = info->params.clock_speed;
5297
5298 info->params.clock_speed = 3686400;
5299 info->tty = NULL;
5300
5301 /* assume failure */
5302 info->init_error = DiagStatus_DmaFailure;
5303
5304 /* build and send transmit frame */
5305 for (count = 0; count < TESTFRAMESIZE;++count)
5306 buf[count] = (unsigned char)count;
5307
5308 memset(info->tmp_rx_buf,0,TESTFRAMESIZE);
5309
5310 /* program hardware for HDLC and enabled receiver */
5311 spin_lock_irqsave(&info->lock,flags);
5312 hdlc_mode(info);
5313 enable_loopback(info,1);
5314 rx_start(info);
5315 info->tx_count = count;
5316 tx_load_dma_buffer(info,buf,count);
5317 tx_start(info);
5318 spin_unlock_irqrestore(&info->lock,flags);
5319
5320 /* wait for receive complete */
5321 /* Set a timeout for waiting for interrupt. */
5322 for ( timeout = 100; timeout; --timeout ) {
5323 msleep_interruptible(10);
5324
5325 if (rx_get_frame(info)) {
5326 rc = TRUE;
5327 break;
5328 }
5329 }
5330
5331 /* verify received frame length and contents */
5332 if (rc == TRUE &&
5333 ( info->tmp_rx_buf_count != count ||
5334 memcmp(buf, info->tmp_rx_buf,count))) {
5335 rc = FALSE;
5336 }
5337
5338 spin_lock_irqsave(&info->lock,flags);
5339 reset_adapter(info);
5340 spin_unlock_irqrestore(&info->lock,flags);
5341
5342 info->params.clock_speed = speed;
5343 info->tty = oldtty;
5344
5345 return rc;
5346 }
5347
5348 /* Perform diagnostics on hardware
5349 */
5350 int adapter_test( SLMP_INFO *info )
5351 {
5352 unsigned long flags;
5353 if ( debug_level >= DEBUG_LEVEL_INFO )
5354 printk( "%s(%d):Testing device %s\n",
5355 __FILE__,__LINE__,info->device_name );
5356
5357 spin_lock_irqsave(&info->lock,flags);
5358 init_adapter(info);
5359 spin_unlock_irqrestore(&info->lock,flags);
5360
5361 info->port_array[0]->port_count = 0;
5362
5363 if ( register_test(info->port_array[0]) &&
5364 register_test(info->port_array[1])) {
5365
5366 info->port_array[0]->port_count = 2;
5367
5368 if ( register_test(info->port_array[2]) &&
5369 register_test(info->port_array[3]) )
5370 info->port_array[0]->port_count += 2;
5371 }
5372 else {
5373 printk( "%s(%d):Register test failure for device %s Addr=%08lX\n",
5374 __FILE__,__LINE__,info->device_name, (unsigned long)(info->phys_sca_base));
5375 return -ENODEV;
5376 }
5377
5378 if ( !irq_test(info->port_array[0]) ||
5379 !irq_test(info->port_array[1]) ||
5380 (info->port_count == 4 && !irq_test(info->port_array[2])) ||
5381 (info->port_count == 4 && !irq_test(info->port_array[3]))) {
5382 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
5383 __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
5384 return -ENODEV;
5385 }
5386
5387 if (!loopback_test(info->port_array[0]) ||
5388 !loopback_test(info->port_array[1]) ||
5389 (info->port_count == 4 && !loopback_test(info->port_array[2])) ||
5390 (info->port_count == 4 && !loopback_test(info->port_array[3]))) {
5391 printk( "%s(%d):DMA test failure for device %s\n",
5392 __FILE__,__LINE__,info->device_name);
5393 return -ENODEV;
5394 }
5395
5396 if ( debug_level >= DEBUG_LEVEL_INFO )
5397 printk( "%s(%d):device %s passed diagnostics\n",
5398 __FILE__,__LINE__,info->device_name );
5399
5400 info->port_array[0]->init_error = 0;
5401 info->port_array[1]->init_error = 0;
5402 if ( info->port_count > 2 ) {
5403 info->port_array[2]->init_error = 0;
5404 info->port_array[3]->init_error = 0;
5405 }
5406
5407 return 0;
5408 }
5409
5410 /* Test the shared memory on a PCI adapter.
5411 */
5412 int memory_test(SLMP_INFO *info)
5413 {
5414 static unsigned long testval[] = { 0x0, 0x55555555, 0xaaaaaaaa,
5415 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
5416 unsigned long count = ARRAY_SIZE(testval);
5417 unsigned long i;
5418 unsigned long limit = SCA_MEM_SIZE/sizeof(unsigned long);
5419 unsigned long * addr = (unsigned long *)info->memory_base;
5420
5421 /* Test data lines with test pattern at one location. */
5422
5423 for ( i = 0 ; i < count ; i++ ) {
5424 *addr = testval[i];
5425 if ( *addr != testval[i] )
5426 return FALSE;
5427 }
5428
5429 /* Test address lines with incrementing pattern over */
5430 /* entire address range. */
5431
5432 for ( i = 0 ; i < limit ; i++ ) {
5433 *addr = i * 4;
5434 addr++;
5435 }
5436
5437 addr = (unsigned long *)info->memory_base;
5438
5439 for ( i = 0 ; i < limit ; i++ ) {
5440 if ( *addr != i * 4 )
5441 return FALSE;
5442 addr++;
5443 }
5444
5445 memset( info->memory_base, 0, SCA_MEM_SIZE );
5446 return TRUE;
5447 }
5448
5449 /* Load data into PCI adapter shared memory.
5450 *
5451 * The PCI9050 releases control of the local bus
5452 * after completing the current read or write operation.
5453 *
5454 * While the PCI9050 write FIFO not empty, the
5455 * PCI9050 treats all of the writes as a single transaction
5456 * and does not release the bus. This causes DMA latency problems
5457 * at high speeds when copying large data blocks to the shared memory.
5458 *
5459 * This function breaks a write into multiple transations by
5460 * interleaving a read which flushes the write FIFO and 'completes'
5461 * the write transation. This allows any pending DMA request to gain control
5462 * of the local bus in a timely fasion.
5463 */
5464 void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count)
5465 {
5466 /* A load interval of 16 allows for 4 32-bit writes at */
5467 /* 136ns each for a maximum latency of 542ns on the local bus.*/
5468
5469 unsigned short interval = count / sca_pci_load_interval;
5470 unsigned short i;
5471
5472 for ( i = 0 ; i < interval ; i++ )
5473 {
5474 memcpy(dest, src, sca_pci_load_interval);
5475 read_status_reg(info);
5476 dest += sca_pci_load_interval;
5477 src += sca_pci_load_interval;
5478 }
5479
5480 memcpy(dest, src, count % sca_pci_load_interval);
5481 }
5482
5483 void trace_block(SLMP_INFO *info,const char* data, int count, int xmit)
5484 {
5485 int i;
5486 int linecount;
5487 if (xmit)
5488 printk("%s tx data:\n",info->device_name);
5489 else
5490 printk("%s rx data:\n",info->device_name);
5491
5492 while(count) {
5493 if (count > 16)
5494 linecount = 16;
5495 else
5496 linecount = count;
5497
5498 for(i=0;i<linecount;i++)
5499 printk("%02X ",(unsigned char)data[i]);
5500 for(;i<17;i++)
5501 printk(" ");
5502 for(i=0;i<linecount;i++) {
5503 if (data[i]>=040 && data[i]<=0176)
5504 printk("%c",data[i]);
5505 else
5506 printk(".");
5507 }
5508 printk("\n");
5509
5510 data += linecount;
5511 count -= linecount;
5512 }
5513 } /* end of trace_block() */
5514
5515 /* called when HDLC frame times out
5516 * update stats and do tx completion processing
5517 */
5518 void tx_timeout(unsigned long context)
5519 {
5520 SLMP_INFO *info = (SLMP_INFO*)context;
5521 unsigned long flags;
5522
5523 if ( debug_level >= DEBUG_LEVEL_INFO )
5524 printk( "%s(%d):%s tx_timeout()\n",
5525 __FILE__,__LINE__,info->device_name);
5526 if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5527 info->icount.txtimeout++;
5528 }
5529 spin_lock_irqsave(&info->lock,flags);
5530 info->tx_active = 0;
5531 info->tx_count = info->tx_put = info->tx_get = 0;
5532
5533 spin_unlock_irqrestore(&info->lock,flags);
5534
5535 #ifdef CONFIG_HDLC
5536 if (info->netcount)
5537 hdlcdev_tx_done(info);
5538 else
5539 #endif
5540 bh_transmit(info);
5541 }
5542
5543 /* called to periodically check the DSR/RI modem signal input status
5544 */
5545 void status_timeout(unsigned long context)
5546 {
5547 u16 status = 0;
5548 SLMP_INFO *info = (SLMP_INFO*)context;
5549 unsigned long flags;
5550 unsigned char delta;
5551
5552
5553 spin_lock_irqsave(&info->lock,flags);
5554 get_signals(info);
5555 spin_unlock_irqrestore(&info->lock,flags);
5556
5557 /* check for DSR/RI state change */
5558
5559 delta = info->old_signals ^ info->serial_signals;
5560 info->old_signals = info->serial_signals;
5561
5562 if (delta & SerialSignal_DSR)
5563 status |= MISCSTATUS_DSR_LATCHED|(info->serial_signals&SerialSignal_DSR);
5564
5565 if (delta & SerialSignal_RI)
5566 status |= MISCSTATUS_RI_LATCHED|(info->serial_signals&SerialSignal_RI);
5567
5568 if (delta & SerialSignal_DCD)
5569 status |= MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD);
5570
5571 if (delta & SerialSignal_CTS)
5572 status |= MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS);
5573
5574 if (status)
5575 isr_io_pin(info,status);
5576
5577 info->status_timer.data = (unsigned long)info;
5578 info->status_timer.function = status_timeout;
5579 info->status_timer.expires = jiffies + msecs_to_jiffies(10);
5580 add_timer(&info->status_timer);
5581 }
5582
5583
5584 /* Register Access Routines -
5585 * All registers are memory mapped
5586 */
5587 #define CALC_REGADDR() \
5588 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \
5589 if (info->port_num > 1) \
5590 RegAddr += 256; /* port 0-1 SCA0, 2-3 SCA1 */ \
5591 if ( info->port_num & 1) { \
5592 if (Addr > 0x7f) \
5593 RegAddr += 0x40; /* DMA access */ \
5594 else if (Addr > 0x1f && Addr < 0x60) \
5595 RegAddr += 0x20; /* MSCI access */ \
5596 }
5597
5598
5599 unsigned char read_reg(SLMP_INFO * info, unsigned char Addr)
5600 {
5601 CALC_REGADDR();
5602 return *RegAddr;
5603 }
5604 void write_reg(SLMP_INFO * info, unsigned char Addr, unsigned char Value)
5605 {
5606 CALC_REGADDR();
5607 *RegAddr = Value;
5608 }
5609
5610 u16 read_reg16(SLMP_INFO * info, unsigned char Addr)
5611 {
5612 CALC_REGADDR();
5613 return *((u16 *)RegAddr);
5614 }
5615
5616 void write_reg16(SLMP_INFO * info, unsigned char Addr, u16 Value)
5617 {
5618 CALC_REGADDR();
5619 *((u16 *)RegAddr) = Value;
5620 }
5621
5622 unsigned char read_status_reg(SLMP_INFO * info)
5623 {
5624 unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5625 return *RegAddr;
5626 }
5627
5628 void write_control_reg(SLMP_INFO * info)
5629 {
5630 unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5631 *RegAddr = info->port_array[0]->ctrlreg_value;
5632 }
5633
5634
5635 static int __devinit synclinkmp_init_one (struct pci_dev *dev,
5636 const struct pci_device_id *ent)
5637 {
5638 if (pci_enable_device(dev)) {
5639 printk("error enabling pci device %p\n", dev);
5640 return -EIO;
5641 }
5642 device_init( ++synclinkmp_adapter_count, dev );
5643 return 0;
5644 }
5645
5646 static void __devexit synclinkmp_remove_one (struct pci_dev *dev)
5647 {
5648 }
Software Suspend 2 for 2.6.18.y (mirror)