3 * 3780i.c -- helper routines for the 3780i DSP
6 * Written By: Mike Sullivan IBM Corporation
8 * Copyright (C) 1999 IBM Corporation
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
21 * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
22 * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
23 * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
24 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
25 * solely responsible for determining the appropriateness of using and
26 * distributing the Program and assumes all risks associated with its
27 * exercise of rights under this Agreement, including but not limited to
28 * the risks and costs of program errors, damage to or loss of data,
29 * programs or equipment, and unavailability or interruption of operations.
31 * DISCLAIMER OF LIABILITY
32 * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
33 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
34 * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
35 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
36 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
37 * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
38 * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
40 * You should have received a copy of the GNU General Public License
41 * along with this program; if not, write to the Free Software
42 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
45 * 10/23/2000 - Alpha Release
46 * First release to the public
49 #include <linux/kernel.h>
50 #include <linux/unistd.h>
51 #include <linux/delay.h>
52 #include <linux/ioport.h>
53 #include <linux/init.h>
54 #include <linux/bitops.h>
55 #include <linux/sched.h> /* cond_resched() */
58 #include <asm/uaccess.h>
59 #include <asm/system.h>
65 static DEFINE_SPINLOCK(dsp_lock
);
66 static unsigned long flags
;
69 static void PaceMsaAccess(unsigned short usDspBaseIO
)
76 unsigned short dsp3780I_ReadMsaCfg(unsigned short usDspBaseIO
,
77 unsigned long ulMsaAddr
)
82 "3780i::dsp3780I_ReadMsaCfg entry usDspBaseIO %x ulMsaAddr %lx\n",
83 usDspBaseIO
, ulMsaAddr
);
85 spin_lock_irqsave(&dsp_lock
, flags
);
86 OutWordDsp(DSP_MsaAddrLow
, (unsigned short) ulMsaAddr
);
87 OutWordDsp(DSP_MsaAddrHigh
, (unsigned short) (ulMsaAddr
>> 16));
88 val
= InWordDsp(DSP_MsaDataDSISHigh
);
89 spin_unlock_irqrestore(&dsp_lock
, flags
);
91 PRINTK_2(TRACE_3780I
, "3780i::dsp3780I_ReadMsaCfg exit val %x\n", val
);
96 void dsp3780I_WriteMsaCfg(unsigned short usDspBaseIO
,
97 unsigned long ulMsaAddr
, unsigned short usValue
)
100 PRINTK_4(TRACE_3780I
,
101 "3780i::dsp3780i_WriteMsaCfg entry usDspBaseIO %x ulMsaAddr %lx usValue %x\n",
102 usDspBaseIO
, ulMsaAddr
, usValue
);
104 spin_lock_irqsave(&dsp_lock
, flags
);
105 OutWordDsp(DSP_MsaAddrLow
, (unsigned short) ulMsaAddr
);
106 OutWordDsp(DSP_MsaAddrHigh
, (unsigned short) (ulMsaAddr
>> 16));
107 OutWordDsp(DSP_MsaDataDSISHigh
, usValue
);
108 spin_unlock_irqrestore(&dsp_lock
, flags
);
111 static void dsp3780I_WriteGenCfg(unsigned short usDspBaseIO
, unsigned uIndex
,
112 unsigned char ucValue
)
114 DSP_ISA_SLAVE_CONTROL rSlaveControl
;
115 DSP_ISA_SLAVE_CONTROL rSlaveControl_Save
;
118 PRINTK_4(TRACE_3780I
,
119 "3780i::dsp3780i_WriteGenCfg entry usDspBaseIO %x uIndex %x ucValue %x\n",
120 usDspBaseIO
, uIndex
, ucValue
);
122 MKBYTE(rSlaveControl
) = InByteDsp(DSP_IsaSlaveControl
);
124 PRINTK_2(TRACE_3780I
,
125 "3780i::dsp3780i_WriteGenCfg rSlaveControl %x\n",
126 MKBYTE(rSlaveControl
));
128 rSlaveControl_Save
= rSlaveControl
;
129 rSlaveControl
.ConfigMode
= TRUE
;
131 PRINTK_2(TRACE_3780I
,
132 "3780i::dsp3780i_WriteGenCfg entry rSlaveControl+ConfigMode %x\n",
133 MKBYTE(rSlaveControl
));
135 OutByteDsp(DSP_IsaSlaveControl
, MKBYTE(rSlaveControl
));
136 OutByteDsp(DSP_ConfigAddress
, (unsigned char) uIndex
);
137 OutByteDsp(DSP_ConfigData
, ucValue
);
138 OutByteDsp(DSP_IsaSlaveControl
, MKBYTE(rSlaveControl_Save
));
140 PRINTK_1(TRACE_3780I
, "3780i::dsp3780i_WriteGenCfg exit\n");
146 unsigned char dsp3780I_ReadGenCfg(unsigned short usDspBaseIO
,
149 DSP_ISA_SLAVE_CONTROL rSlaveControl
;
150 DSP_ISA_SLAVE_CONTROL rSlaveControl_Save
;
151 unsigned char ucValue
;
154 PRINTK_3(TRACE_3780I
,
155 "3780i::dsp3780i_ReadGenCfg entry usDspBaseIO %x uIndex %x\n",
156 usDspBaseIO
, uIndex
);
158 MKBYTE(rSlaveControl
) = InByteDsp(DSP_IsaSlaveControl
);
159 rSlaveControl_Save
= rSlaveControl
;
160 rSlaveControl
.ConfigMode
= TRUE
;
161 OutByteDsp(DSP_IsaSlaveControl
, MKBYTE(rSlaveControl
));
162 OutByteDsp(DSP_ConfigAddress
, (unsigned char) uIndex
);
163 ucValue
= InByteDsp(DSP_ConfigData
);
164 OutByteDsp(DSP_IsaSlaveControl
, MKBYTE(rSlaveControl_Save
));
166 PRINTK_2(TRACE_3780I
,
167 "3780i::dsp3780i_ReadGenCfg exit ucValue %x\n", ucValue
);
174 int dsp3780I_EnableDSP(DSP_3780I_CONFIG_SETTINGS
* pSettings
,
175 unsigned short *pIrqMap
,
176 unsigned short *pDmaMap
)
178 unsigned short usDspBaseIO
= pSettings
->usDspBaseIO
;
180 DSP_UART_CFG_1 rUartCfg1
;
181 DSP_UART_CFG_2 rUartCfg2
;
182 DSP_HBRIDGE_CFG_1 rHBridgeCfg1
;
183 DSP_HBRIDGE_CFG_2 rHBridgeCfg2
;
184 DSP_BUSMASTER_CFG_1 rBusmasterCfg1
;
185 DSP_BUSMASTER_CFG_2 rBusmasterCfg2
;
186 DSP_ISA_PROT_CFG rIsaProtCfg
;
187 DSP_POWER_MGMT_CFG rPowerMgmtCfg
;
188 DSP_HBUS_TIMER_CFG rHBusTimerCfg
;
189 DSP_LBUS_TIMEOUT_DISABLE rLBusTimeoutDisable
;
190 DSP_CHIP_RESET rChipReset
;
191 DSP_CLOCK_CONTROL_1 rClockControl1
;
192 DSP_CLOCK_CONTROL_2 rClockControl2
;
193 DSP_ISA_SLAVE_CONTROL rSlaveControl
;
194 DSP_HBRIDGE_CONTROL rHBridgeControl
;
195 unsigned short ChipID
= 0;
199 PRINTK_2(TRACE_3780I
,
200 "3780i::dsp3780I_EnableDSP entry pSettings->bDSPEnabled %x\n",
201 pSettings
->bDSPEnabled
);
204 if (!pSettings
->bDSPEnabled
) {
205 PRINTK_ERROR( KERN_ERR
"3780i::dsp3780I_EnableDSP: Error: DSP not enabled. Aborting.\n" );
210 PRINTK_2(TRACE_3780I
,
211 "3780i::dsp3780i_EnableDSP entry pSettings->bModemEnabled %x\n",
212 pSettings
->bModemEnabled
);
214 if (pSettings
->bModemEnabled
) {
215 rUartCfg1
.Reserved
= rUartCfg2
.Reserved
= 0;
216 rUartCfg1
.IrqActiveLow
= pSettings
->bUartIrqActiveLow
;
217 rUartCfg1
.IrqPulse
= pSettings
->bUartIrqPulse
;
219 (unsigned char) pIrqMap
[pSettings
->usUartIrq
];
220 switch (pSettings
->usUartBaseIO
) {
222 rUartCfg1
.BaseIO
= 0;
225 rUartCfg1
.BaseIO
= 1;
228 rUartCfg1
.BaseIO
= 2;
231 rUartCfg1
.BaseIO
= 3;
234 rUartCfg2
.Enable
= TRUE
;
237 rHBridgeCfg1
.Reserved
= rHBridgeCfg2
.Reserved
= 0;
238 rHBridgeCfg1
.IrqActiveLow
= pSettings
->bDspIrqActiveLow
;
239 rHBridgeCfg1
.IrqPulse
= pSettings
->bDspIrqPulse
;
240 rHBridgeCfg1
.Irq
= (unsigned char) pIrqMap
[pSettings
->usDspIrq
];
241 rHBridgeCfg1
.AccessMode
= 1;
242 rHBridgeCfg2
.Enable
= TRUE
;
245 rBusmasterCfg2
.Reserved
= 0;
246 rBusmasterCfg1
.Dma
= (unsigned char) pDmaMap
[pSettings
->usDspDma
];
247 rBusmasterCfg1
.NumTransfers
=
248 (unsigned char) pSettings
->usNumTransfers
;
249 rBusmasterCfg1
.ReRequest
= (unsigned char) pSettings
->usReRequest
;
250 rBusmasterCfg1
.MEMCS16
= pSettings
->bEnableMEMCS16
;
251 rBusmasterCfg2
.IsaMemCmdWidth
=
252 (unsigned char) pSettings
->usIsaMemCmdWidth
;
255 rIsaProtCfg
.Reserved
= 0;
256 rIsaProtCfg
.GateIOCHRDY
= pSettings
->bGateIOCHRDY
;
258 rPowerMgmtCfg
.Reserved
= 0;
259 rPowerMgmtCfg
.Enable
= pSettings
->bEnablePwrMgmt
;
261 rHBusTimerCfg
.LoadValue
=
262 (unsigned char) pSettings
->usHBusTimerLoadValue
;
264 rLBusTimeoutDisable
.Reserved
= 0;
265 rLBusTimeoutDisable
.DisableTimeout
=
266 pSettings
->bDisableLBusTimeout
;
268 MKWORD(rChipReset
) = ~pSettings
->usChipletEnable
;
270 rClockControl1
.Reserved1
= rClockControl1
.Reserved2
= 0;
271 rClockControl1
.N_Divisor
= pSettings
->usN_Divisor
;
272 rClockControl1
.M_Multiplier
= pSettings
->usM_Multiplier
;
274 rClockControl2
.Reserved
= 0;
275 rClockControl2
.PllBypass
= pSettings
->bPllBypass
;
277 /* Issue a soft reset to the chip */
278 /* Note: Since we may be coming in with 3780i clocks suspended, we must keep
279 * soft-reset active for 10ms.
281 rSlaveControl
.ClockControl
= 0;
282 rSlaveControl
.SoftReset
= TRUE
;
283 rSlaveControl
.ConfigMode
= FALSE
;
284 rSlaveControl
.Reserved
= 0;
286 PRINTK_4(TRACE_3780I
,
287 "3780i::dsp3780i_EnableDSP usDspBaseIO %x index %x taddr %x\n",
288 usDspBaseIO
, DSP_IsaSlaveControl
,
289 usDspBaseIO
+ DSP_IsaSlaveControl
);
291 PRINTK_2(TRACE_3780I
,
292 "3780i::dsp3780i_EnableDSP rSlaveContrl %x\n",
293 MKWORD(rSlaveControl
));
295 spin_lock_irqsave(&dsp_lock
, flags
);
296 OutWordDsp(DSP_IsaSlaveControl
, MKWORD(rSlaveControl
));
297 MKWORD(tval
) = InWordDsp(DSP_IsaSlaveControl
);
299 PRINTK_2(TRACE_3780I
,
300 "3780i::dsp3780i_EnableDSP rSlaveControl 2 %x\n", tval
);
303 for (i
= 0; i
< 11; i
++)
306 rSlaveControl
.SoftReset
= FALSE
;
307 OutWordDsp(DSP_IsaSlaveControl
, MKWORD(rSlaveControl
));
309 MKWORD(tval
) = InWordDsp(DSP_IsaSlaveControl
);
311 PRINTK_2(TRACE_3780I
,
312 "3780i::dsp3780i_EnableDSP rSlaveControl 3 %x\n", tval
);
315 /* Program our general configuration registers */
316 WriteGenCfg(DSP_HBridgeCfg1Index
, MKBYTE(rHBridgeCfg1
));
317 WriteGenCfg(DSP_HBridgeCfg2Index
, MKBYTE(rHBridgeCfg2
));
318 WriteGenCfg(DSP_BusMasterCfg1Index
, MKBYTE(rBusmasterCfg1
));
319 WriteGenCfg(DSP_BusMasterCfg2Index
, MKBYTE(rBusmasterCfg2
));
320 WriteGenCfg(DSP_IsaProtCfgIndex
, MKBYTE(rIsaProtCfg
));
321 WriteGenCfg(DSP_PowerMgCfgIndex
, MKBYTE(rPowerMgmtCfg
));
322 WriteGenCfg(DSP_HBusTimerCfgIndex
, MKBYTE(rHBusTimerCfg
));
324 if (pSettings
->bModemEnabled
) {
325 WriteGenCfg(DSP_UartCfg1Index
, MKBYTE(rUartCfg1
));
326 WriteGenCfg(DSP_UartCfg2Index
, MKBYTE(rUartCfg2
));
330 rHBridgeControl
.EnableDspInt
= FALSE
;
331 rHBridgeControl
.MemAutoInc
= TRUE
;
332 rHBridgeControl
.IoAutoInc
= FALSE
;
333 rHBridgeControl
.DiagnosticMode
= FALSE
;
335 PRINTK_3(TRACE_3780I
,
336 "3780i::dsp3780i_EnableDSP DSP_HBridgeControl %x rHBridgeControl %x\n",
337 DSP_HBridgeControl
, MKWORD(rHBridgeControl
));
339 OutWordDsp(DSP_HBridgeControl
, MKWORD(rHBridgeControl
));
340 spin_unlock_irqrestore(&dsp_lock
, flags
);
341 WriteMsaCfg(DSP_LBusTimeoutDisable
, MKWORD(rLBusTimeoutDisable
));
342 WriteMsaCfg(DSP_ClockControl_1
, MKWORD(rClockControl1
));
343 WriteMsaCfg(DSP_ClockControl_2
, MKWORD(rClockControl2
));
344 WriteMsaCfg(DSP_ChipReset
, MKWORD(rChipReset
));
346 ChipID
= ReadMsaCfg(DSP_ChipID
);
348 PRINTK_2(TRACE_3780I
,
349 "3780i::dsp3780I_EnableDSP exiting bRC=TRUE, ChipID %x\n",
355 int dsp3780I_DisableDSP(DSP_3780I_CONFIG_SETTINGS
* pSettings
)
357 unsigned short usDspBaseIO
= pSettings
->usDspBaseIO
;
358 DSP_ISA_SLAVE_CONTROL rSlaveControl
;
361 PRINTK_1(TRACE_3780I
, "3780i::dsp3780i_DisableDSP entry\n");
363 rSlaveControl
.ClockControl
= 0;
364 rSlaveControl
.SoftReset
= TRUE
;
365 rSlaveControl
.ConfigMode
= FALSE
;
366 rSlaveControl
.Reserved
= 0;
367 spin_lock_irqsave(&dsp_lock
, flags
);
368 OutWordDsp(DSP_IsaSlaveControl
, MKWORD(rSlaveControl
));
372 rSlaveControl
.ClockControl
= 1;
373 OutWordDsp(DSP_IsaSlaveControl
, MKWORD(rSlaveControl
));
374 spin_unlock_irqrestore(&dsp_lock
, flags
);
379 PRINTK_1(TRACE_3780I
, "3780i::dsp3780i_DisableDSP exit\n");
384 int dsp3780I_Reset(DSP_3780I_CONFIG_SETTINGS
* pSettings
)
386 unsigned short usDspBaseIO
= pSettings
->usDspBaseIO
;
387 DSP_BOOT_DOMAIN rBootDomain
;
388 DSP_HBRIDGE_CONTROL rHBridgeControl
;
391 PRINTK_1(TRACE_3780I
, "3780i::dsp3780i_Reset entry\n");
393 spin_lock_irqsave(&dsp_lock
, flags
);
394 /* Mask DSP to PC interrupt */
395 MKWORD(rHBridgeControl
) = InWordDsp(DSP_HBridgeControl
);
397 PRINTK_2(TRACE_3780I
, "3780i::dsp3780i_Reset rHBridgeControl %x\n",
398 MKWORD(rHBridgeControl
));
400 rHBridgeControl
.EnableDspInt
= FALSE
;
401 OutWordDsp(DSP_HBridgeControl
, MKWORD(rHBridgeControl
));
402 spin_unlock_irqrestore(&dsp_lock
, flags
);
404 /* Reset the core via the boot domain register */
405 rBootDomain
.ResetCore
= TRUE
;
406 rBootDomain
.Halt
= TRUE
;
407 rBootDomain
.NMI
= TRUE
;
408 rBootDomain
.Reserved
= 0;
410 PRINTK_2(TRACE_3780I
, "3780i::dsp3780i_Reset rBootDomain %x\n",
411 MKWORD(rBootDomain
));
413 WriteMsaCfg(DSP_MspBootDomain
, MKWORD(rBootDomain
));
415 /* Reset all the chiplets and then reactivate them */
416 WriteMsaCfg(DSP_ChipReset
, 0xFFFF);
418 WriteMsaCfg(DSP_ChipReset
,
419 (unsigned short) (~pSettings
->usChipletEnable
));
422 PRINTK_1(TRACE_3780I
, "3780i::dsp3780i_Reset exit bRC=0\n");
428 int dsp3780I_Run(DSP_3780I_CONFIG_SETTINGS
* pSettings
)
430 unsigned short usDspBaseIO
= pSettings
->usDspBaseIO
;
431 DSP_BOOT_DOMAIN rBootDomain
;
432 DSP_HBRIDGE_CONTROL rHBridgeControl
;
435 PRINTK_1(TRACE_3780I
, "3780i::dsp3780i_Run entry\n");
438 /* Transition the core to a running state */
439 rBootDomain
.ResetCore
= TRUE
;
440 rBootDomain
.Halt
= FALSE
;
441 rBootDomain
.NMI
= TRUE
;
442 rBootDomain
.Reserved
= 0;
443 WriteMsaCfg(DSP_MspBootDomain
, MKWORD(rBootDomain
));
447 rBootDomain
.ResetCore
= FALSE
;
448 WriteMsaCfg(DSP_MspBootDomain
, MKWORD(rBootDomain
));
451 rBootDomain
.NMI
= FALSE
;
452 WriteMsaCfg(DSP_MspBootDomain
, MKWORD(rBootDomain
));
455 /* Enable DSP to PC interrupt */
456 spin_lock_irqsave(&dsp_lock
, flags
);
457 MKWORD(rHBridgeControl
) = InWordDsp(DSP_HBridgeControl
);
458 rHBridgeControl
.EnableDspInt
= TRUE
;
460 PRINTK_2(TRACE_3780I
, "3780i::dsp3780i_Run rHBridgeControl %x\n",
461 MKWORD(rHBridgeControl
));
463 OutWordDsp(DSP_HBridgeControl
, MKWORD(rHBridgeControl
));
464 spin_unlock_irqrestore(&dsp_lock
, flags
);
467 PRINTK_1(TRACE_3780I
, "3780i::dsp3780i_Run exit bRC=TRUE\n");
473 int dsp3780I_ReadDStore(unsigned short usDspBaseIO
, void __user
*pvBuffer
,
474 unsigned uCount
, unsigned long ulDSPAddr
)
476 unsigned short __user
*pusBuffer
= pvBuffer
;
480 PRINTK_5(TRACE_3780I
,
481 "3780i::dsp3780I_ReadDStore entry usDspBaseIO %x, pusBuffer %p, uCount %x, ulDSPAddr %lx\n",
482 usDspBaseIO
, pusBuffer
, uCount
, ulDSPAddr
);
485 /* Set the initial MSA address. No adjustments need to be made to data store addresses */
486 spin_lock_irqsave(&dsp_lock
, flags
);
487 OutWordDsp(DSP_MsaAddrLow
, (unsigned short) ulDSPAddr
);
488 OutWordDsp(DSP_MsaAddrHigh
, (unsigned short) (ulDSPAddr
>> 16));
489 spin_unlock_irqrestore(&dsp_lock
, flags
);
491 /* Transfer the memory block */
492 while (uCount
-- != 0) {
493 spin_lock_irqsave(&dsp_lock
, flags
);
494 val
= InWordDsp(DSP_MsaDataDSISHigh
);
495 spin_unlock_irqrestore(&dsp_lock
, flags
);
496 if(put_user(val
, pusBuffer
++))
499 PRINTK_3(TRACE_3780I
,
500 "3780I::dsp3780I_ReadDStore uCount %x val %x\n",
503 PaceMsaAccess(usDspBaseIO
);
507 PRINTK_1(TRACE_3780I
,
508 "3780I::dsp3780I_ReadDStore exit bRC=TRUE\n");
513 int dsp3780I_ReadAndClearDStore(unsigned short usDspBaseIO
,
514 void __user
*pvBuffer
, unsigned uCount
,
515 unsigned long ulDSPAddr
)
517 unsigned short __user
*pusBuffer
= pvBuffer
;
521 PRINTK_5(TRACE_3780I
,
522 "3780i::dsp3780I_ReadAndDStore entry usDspBaseIO %x, pusBuffer %p, uCount %x, ulDSPAddr %lx\n",
523 usDspBaseIO
, pusBuffer
, uCount
, ulDSPAddr
);
526 /* Set the initial MSA address. No adjustments need to be made to data store addresses */
527 spin_lock_irqsave(&dsp_lock
, flags
);
528 OutWordDsp(DSP_MsaAddrLow
, (unsigned short) ulDSPAddr
);
529 OutWordDsp(DSP_MsaAddrHigh
, (unsigned short) (ulDSPAddr
>> 16));
530 spin_unlock_irqrestore(&dsp_lock
, flags
);
532 /* Transfer the memory block */
533 while (uCount
-- != 0) {
534 spin_lock_irqsave(&dsp_lock
, flags
);
535 val
= InWordDsp(DSP_ReadAndClear
);
536 spin_unlock_irqrestore(&dsp_lock
, flags
);
537 if(put_user(val
, pusBuffer
++))
540 PRINTK_3(TRACE_3780I
,
541 "3780I::dsp3780I_ReadAndCleanDStore uCount %x val %x\n",
544 PaceMsaAccess(usDspBaseIO
);
548 PRINTK_1(TRACE_3780I
,
549 "3780I::dsp3780I_ReadAndClearDStore exit bRC=TRUE\n");
555 int dsp3780I_WriteDStore(unsigned short usDspBaseIO
, void __user
*pvBuffer
,
556 unsigned uCount
, unsigned long ulDSPAddr
)
558 unsigned short __user
*pusBuffer
= pvBuffer
;
561 PRINTK_5(TRACE_3780I
,
562 "3780i::dsp3780D_WriteDStore entry usDspBaseIO %x, pusBuffer %p, uCount %x, ulDSPAddr %lx\n",
563 usDspBaseIO
, pusBuffer
, uCount
, ulDSPAddr
);
566 /* Set the initial MSA address. No adjustments need to be made to data store addresses */
567 spin_lock_irqsave(&dsp_lock
, flags
);
568 OutWordDsp(DSP_MsaAddrLow
, (unsigned short) ulDSPAddr
);
569 OutWordDsp(DSP_MsaAddrHigh
, (unsigned short) (ulDSPAddr
>> 16));
570 spin_unlock_irqrestore(&dsp_lock
, flags
);
572 /* Transfer the memory block */
573 while (uCount
-- != 0) {
575 if(get_user(val
, pusBuffer
++))
577 spin_lock_irqsave(&dsp_lock
, flags
);
578 OutWordDsp(DSP_MsaDataDSISHigh
, val
);
579 spin_unlock_irqrestore(&dsp_lock
, flags
);
581 PRINTK_3(TRACE_3780I
,
582 "3780I::dsp3780I_WriteDStore uCount %x val %x\n",
585 PaceMsaAccess(usDspBaseIO
);
589 PRINTK_1(TRACE_3780I
,
590 "3780I::dsp3780D_WriteDStore exit bRC=TRUE\n");
596 int dsp3780I_ReadIStore(unsigned short usDspBaseIO
, void __user
*pvBuffer
,
597 unsigned uCount
, unsigned long ulDSPAddr
)
599 unsigned short __user
*pusBuffer
= pvBuffer
;
601 PRINTK_5(TRACE_3780I
,
602 "3780i::dsp3780I_ReadIStore entry usDspBaseIO %x, pusBuffer %p, uCount %x, ulDSPAddr %lx\n",
603 usDspBaseIO
, pusBuffer
, uCount
, ulDSPAddr
);
606 * Set the initial MSA address. To convert from an instruction store
607 * address to an MSA address
608 * shift the address two bits to the left and set bit 22
610 ulDSPAddr
= (ulDSPAddr
<< 2) | (1 << 22);
611 spin_lock_irqsave(&dsp_lock
, flags
);
612 OutWordDsp(DSP_MsaAddrLow
, (unsigned short) ulDSPAddr
);
613 OutWordDsp(DSP_MsaAddrHigh
, (unsigned short) (ulDSPAddr
>> 16));
614 spin_unlock_irqrestore(&dsp_lock
, flags
);
616 /* Transfer the memory block */
617 while (uCount
-- != 0) {
618 unsigned short val_lo
, val_hi
;
619 spin_lock_irqsave(&dsp_lock
, flags
);
620 val_lo
= InWordDsp(DSP_MsaDataISLow
);
621 val_hi
= InWordDsp(DSP_MsaDataDSISHigh
);
622 spin_unlock_irqrestore(&dsp_lock
, flags
);
623 if(put_user(val_lo
, pusBuffer
++))
625 if(put_user(val_hi
, pusBuffer
++))
628 PRINTK_4(TRACE_3780I
,
629 "3780I::dsp3780I_ReadIStore uCount %x val_lo %x val_hi %x\n",
630 uCount
, val_lo
, val_hi
);
632 PaceMsaAccess(usDspBaseIO
);
636 PRINTK_1(TRACE_3780I
,
637 "3780I::dsp3780I_ReadIStore exit bRC=TRUE\n");
643 int dsp3780I_WriteIStore(unsigned short usDspBaseIO
, void __user
*pvBuffer
,
644 unsigned uCount
, unsigned long ulDSPAddr
)
646 unsigned short __user
*pusBuffer
= pvBuffer
;
648 PRINTK_5(TRACE_3780I
,
649 "3780i::dsp3780I_WriteIStore entry usDspBaseIO %x, pusBuffer %p, uCount %x, ulDSPAddr %lx\n",
650 usDspBaseIO
, pusBuffer
, uCount
, ulDSPAddr
);
654 * Set the initial MSA address. To convert from an instruction store
655 * address to an MSA address
656 * shift the address two bits to the left and set bit 22
658 ulDSPAddr
= (ulDSPAddr
<< 2) | (1 << 22);
659 spin_lock_irqsave(&dsp_lock
, flags
);
660 OutWordDsp(DSP_MsaAddrLow
, (unsigned short) ulDSPAddr
);
661 OutWordDsp(DSP_MsaAddrHigh
, (unsigned short) (ulDSPAddr
>> 16));
662 spin_unlock_irqrestore(&dsp_lock
, flags
);
664 /* Transfer the memory block */
665 while (uCount
-- != 0) {
666 unsigned short val_lo
, val_hi
;
667 if(get_user(val_lo
, pusBuffer
++))
669 if(get_user(val_hi
, pusBuffer
++))
671 spin_lock_irqsave(&dsp_lock
, flags
);
672 OutWordDsp(DSP_MsaDataISLow
, val_lo
);
673 OutWordDsp(DSP_MsaDataDSISHigh
, val_hi
);
674 spin_unlock_irqrestore(&dsp_lock
, flags
);
676 PRINTK_4(TRACE_3780I
,
677 "3780I::dsp3780I_WriteIStore uCount %x val_lo %x val_hi %x\n",
678 uCount
, val_lo
, val_hi
);
680 PaceMsaAccess(usDspBaseIO
);
684 PRINTK_1(TRACE_3780I
,
685 "3780I::dsp3780I_WriteIStore exit bRC=TRUE\n");
691 int dsp3780I_GetIPCSource(unsigned short usDspBaseIO
,
692 unsigned short *pusIPCSource
)
694 DSP_HBRIDGE_CONTROL rHBridgeControl
;
698 PRINTK_3(TRACE_3780I
,
699 "3780i::dsp3780I_GetIPCSource entry usDspBaseIO %x pusIPCSource %p\n",
700 usDspBaseIO
, pusIPCSource
);
703 * Disable DSP to PC interrupts, read the interrupt register,
704 * clear the pending IPC bits, and reenable DSP to PC interrupts
706 spin_lock_irqsave(&dsp_lock
, flags
);
707 MKWORD(rHBridgeControl
) = InWordDsp(DSP_HBridgeControl
);
708 rHBridgeControl
.EnableDspInt
= FALSE
;
709 OutWordDsp(DSP_HBridgeControl
, MKWORD(rHBridgeControl
));
711 *pusIPCSource
= InWordDsp(DSP_Interrupt
);
712 temp
= (unsigned short) ~(*pusIPCSource
);
714 PRINTK_3(TRACE_3780I
,
715 "3780i::dsp3780I_GetIPCSource, usIPCSource %x ~ %x\n",
716 *pusIPCSource
, temp
);
718 OutWordDsp(DSP_Interrupt
, (unsigned short) ~(*pusIPCSource
));
720 rHBridgeControl
.EnableDspInt
= TRUE
;
721 OutWordDsp(DSP_HBridgeControl
, MKWORD(rHBridgeControl
));
722 spin_unlock_irqrestore(&dsp_lock
, flags
);
725 PRINTK_2(TRACE_3780I
,
726 "3780i::dsp3780I_GetIPCSource exit usIPCSource %x\n",