2 * ahci.c - AHCI SATA support
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/sched.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/device.h>
45 #include <scsi/scsi_host.h>
46 #include <scsi/scsi_cmnd.h>
47 #include <linux/libata.h>
50 #define DRV_NAME "ahci"
51 #define DRV_VERSION "1.2"
56 AHCI_MAX_SG
= 168, /* hardware max is 64K */
57 AHCI_DMA_BOUNDARY
= 0xffffffff,
58 AHCI_USE_CLUSTERING
= 0,
59 AHCI_CMD_SLOT_SZ
= 32 * 32,
61 AHCI_CMD_TBL_HDR
= 0x80,
62 AHCI_CMD_TBL_CDB
= 0x40,
63 AHCI_CMD_TBL_SZ
= AHCI_CMD_TBL_HDR
+ (AHCI_MAX_SG
* 16),
64 AHCI_PORT_PRIV_DMA_SZ
= AHCI_CMD_SLOT_SZ
+ AHCI_CMD_TBL_SZ
+
66 AHCI_IRQ_ON_SG
= (1 << 31),
67 AHCI_CMD_ATAPI
= (1 << 5),
68 AHCI_CMD_WRITE
= (1 << 6),
70 RX_FIS_D2H_REG
= 0x40, /* offset of D2H Register FIS data */
74 /* global controller registers */
75 HOST_CAP
= 0x00, /* host capabilities */
76 HOST_CTL
= 0x04, /* global host control */
77 HOST_IRQ_STAT
= 0x08, /* interrupt status */
78 HOST_PORTS_IMPL
= 0x0c, /* bitmap of implemented ports */
79 HOST_VERSION
= 0x10, /* AHCI spec. version compliancy */
82 HOST_RESET
= (1 << 0), /* reset controller; self-clear */
83 HOST_IRQ_EN
= (1 << 1), /* global IRQ enable */
84 HOST_AHCI_EN
= (1 << 31), /* AHCI enabled */
87 HOST_CAP_64
= (1 << 31), /* PCI DAC (64-bit DMA) support */
89 /* registers for each SATA port */
90 PORT_LST_ADDR
= 0x00, /* command list DMA addr */
91 PORT_LST_ADDR_HI
= 0x04, /* command list DMA addr hi */
92 PORT_FIS_ADDR
= 0x08, /* FIS rx buf addr */
93 PORT_FIS_ADDR_HI
= 0x0c, /* FIS rx buf addr hi */
94 PORT_IRQ_STAT
= 0x10, /* interrupt status */
95 PORT_IRQ_MASK
= 0x14, /* interrupt enable/disable mask */
96 PORT_CMD
= 0x18, /* port command */
97 PORT_TFDATA
= 0x20, /* taskfile data */
98 PORT_SIG
= 0x24, /* device TF signature */
99 PORT_CMD_ISSUE
= 0x38, /* command issue */
100 PORT_SCR
= 0x28, /* SATA phy register block */
101 PORT_SCR_STAT
= 0x28, /* SATA phy register: SStatus */
102 PORT_SCR_CTL
= 0x2c, /* SATA phy register: SControl */
103 PORT_SCR_ERR
= 0x30, /* SATA phy register: SError */
104 PORT_SCR_ACT
= 0x34, /* SATA phy register: SActive */
106 /* PORT_IRQ_{STAT,MASK} bits */
107 PORT_IRQ_COLD_PRES
= (1 << 31), /* cold presence detect */
108 PORT_IRQ_TF_ERR
= (1 << 30), /* task file error */
109 PORT_IRQ_HBUS_ERR
= (1 << 29), /* host bus fatal error */
110 PORT_IRQ_HBUS_DATA_ERR
= (1 << 28), /* host bus data error */
111 PORT_IRQ_IF_ERR
= (1 << 27), /* interface fatal error */
112 PORT_IRQ_IF_NONFATAL
= (1 << 26), /* interface non-fatal error */
113 PORT_IRQ_OVERFLOW
= (1 << 24), /* xfer exhausted available S/G */
114 PORT_IRQ_BAD_PMP
= (1 << 23), /* incorrect port multiplier */
116 PORT_IRQ_PHYRDY
= (1 << 22), /* PhyRdy changed */
117 PORT_IRQ_DEV_ILCK
= (1 << 7), /* device interlock */
118 PORT_IRQ_CONNECT
= (1 << 6), /* port connect change status */
119 PORT_IRQ_SG_DONE
= (1 << 5), /* descriptor processed */
120 PORT_IRQ_UNK_FIS
= (1 << 4), /* unknown FIS rx'd */
121 PORT_IRQ_SDB_FIS
= (1 << 3), /* Set Device Bits FIS rx'd */
122 PORT_IRQ_DMAS_FIS
= (1 << 2), /* DMA Setup FIS rx'd */
123 PORT_IRQ_PIOS_FIS
= (1 << 1), /* PIO Setup FIS rx'd */
124 PORT_IRQ_D2H_REG_FIS
= (1 << 0), /* D2H Register FIS rx'd */
126 PORT_IRQ_FATAL
= PORT_IRQ_TF_ERR
|
128 PORT_IRQ_HBUS_DATA_ERR
|
130 DEF_PORT_IRQ
= PORT_IRQ_FATAL
| PORT_IRQ_PHYRDY
|
131 PORT_IRQ_CONNECT
| PORT_IRQ_SG_DONE
|
132 PORT_IRQ_UNK_FIS
| PORT_IRQ_SDB_FIS
|
133 PORT_IRQ_DMAS_FIS
| PORT_IRQ_PIOS_FIS
|
134 PORT_IRQ_D2H_REG_FIS
,
137 PORT_CMD_ATAPI
= (1 << 24), /* Device is ATAPI */
138 PORT_CMD_LIST_ON
= (1 << 15), /* cmd list DMA engine running */
139 PORT_CMD_FIS_ON
= (1 << 14), /* FIS DMA engine running */
140 PORT_CMD_FIS_RX
= (1 << 4), /* Enable FIS receive DMA engine */
141 PORT_CMD_POWER_ON
= (1 << 2), /* Power up device */
142 PORT_CMD_SPIN_UP
= (1 << 1), /* Spin up device */
143 PORT_CMD_START
= (1 << 0), /* Enable port DMA engine */
145 PORT_CMD_ICC_ACTIVE
= (0x1 << 28), /* Put i/f in active state */
146 PORT_CMD_ICC_PARTIAL
= (0x2 << 28), /* Put i/f in partial state */
147 PORT_CMD_ICC_SLUMBER
= (0x6 << 28), /* Put i/f in slumber state */
149 /* hpriv->flags bits */
150 AHCI_FLAG_MSI
= (1 << 0),
153 struct ahci_cmd_hdr
{
168 struct ahci_host_priv
{
170 u32 cap
; /* cache of HOST_CAP register */
171 u32 port_map
; /* cache of HOST_PORTS_IMPL reg */
174 struct ahci_port_priv
{
175 struct ahci_cmd_hdr
*cmd_slot
;
176 dma_addr_t cmd_slot_dma
;
178 dma_addr_t cmd_tbl_dma
;
179 struct ahci_sg
*cmd_tbl_sg
;
181 dma_addr_t rx_fis_dma
;
184 static u32
ahci_scr_read (struct ata_port
*ap
, unsigned int sc_reg
);
185 static void ahci_scr_write (struct ata_port
*ap
, unsigned int sc_reg
, u32 val
);
186 static int ahci_init_one (struct pci_dev
*pdev
, const struct pci_device_id
*ent
);
187 static unsigned int ahci_qc_issue(struct ata_queued_cmd
*qc
);
188 static irqreturn_t
ahci_interrupt (int irq
, void *dev_instance
, struct pt_regs
*regs
);
189 static void ahci_phy_reset(struct ata_port
*ap
);
190 static void ahci_irq_clear(struct ata_port
*ap
);
191 static void ahci_eng_timeout(struct ata_port
*ap
);
192 static int ahci_port_start(struct ata_port
*ap
);
193 static void ahci_port_stop(struct ata_port
*ap
);
194 static void ahci_tf_read(struct ata_port
*ap
, struct ata_taskfile
*tf
);
195 static void ahci_qc_prep(struct ata_queued_cmd
*qc
);
196 static u8
ahci_check_status(struct ata_port
*ap
);
197 static inline int ahci_host_intr(struct ata_port
*ap
, struct ata_queued_cmd
*qc
);
198 static void ahci_remove_one (struct pci_dev
*pdev
);
200 static struct scsi_host_template ahci_sht
= {
201 .module
= THIS_MODULE
,
203 .ioctl
= ata_scsi_ioctl
,
204 .queuecommand
= ata_scsi_queuecmd
,
205 .eh_strategy_handler
= ata_scsi_error
,
206 .can_queue
= ATA_DEF_QUEUE
,
207 .this_id
= ATA_SHT_THIS_ID
,
208 .sg_tablesize
= AHCI_MAX_SG
,
209 .max_sectors
= ATA_MAX_SECTORS
,
210 .cmd_per_lun
= ATA_SHT_CMD_PER_LUN
,
211 .emulated
= ATA_SHT_EMULATED
,
212 .use_clustering
= AHCI_USE_CLUSTERING
,
213 .proc_name
= DRV_NAME
,
214 .dma_boundary
= AHCI_DMA_BOUNDARY
,
215 .slave_configure
= ata_scsi_slave_config
,
216 .bios_param
= ata_std_bios_param
,
219 static const struct ata_port_operations ahci_ops
= {
220 .port_disable
= ata_port_disable
,
222 .check_status
= ahci_check_status
,
223 .check_altstatus
= ahci_check_status
,
224 .dev_select
= ata_noop_dev_select
,
226 .tf_read
= ahci_tf_read
,
228 .phy_reset
= ahci_phy_reset
,
230 .qc_prep
= ahci_qc_prep
,
231 .qc_issue
= ahci_qc_issue
,
233 .eng_timeout
= ahci_eng_timeout
,
235 .irq_handler
= ahci_interrupt
,
236 .irq_clear
= ahci_irq_clear
,
238 .scr_read
= ahci_scr_read
,
239 .scr_write
= ahci_scr_write
,
241 .port_start
= ahci_port_start
,
242 .port_stop
= ahci_port_stop
,
245 static const struct ata_port_info ahci_port_info
[] = {
249 .host_flags
= ATA_FLAG_SATA
| ATA_FLAG_NO_LEGACY
|
250 ATA_FLAG_SATA_RESET
| ATA_FLAG_MMIO
|
252 .pio_mask
= 0x1f, /* pio0-4 */
253 .udma_mask
= 0x7f, /* udma0-6 ; FIXME */
254 .port_ops
= &ahci_ops
,
258 static const struct pci_device_id ahci_pci_tbl
[] = {
259 { PCI_VENDOR_ID_INTEL
, 0x2652, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
260 board_ahci
}, /* ICH6 */
261 { PCI_VENDOR_ID_INTEL
, 0x2653, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
262 board_ahci
}, /* ICH6M */
263 { PCI_VENDOR_ID_INTEL
, 0x27c1, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
264 board_ahci
}, /* ICH7 */
265 { PCI_VENDOR_ID_INTEL
, 0x27c5, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
266 board_ahci
}, /* ICH7M */
267 { PCI_VENDOR_ID_INTEL
, 0x27c3, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
268 board_ahci
}, /* ICH7R */
269 { PCI_VENDOR_ID_AL
, 0x5288, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
270 board_ahci
}, /* ULi M5288 */
271 { PCI_VENDOR_ID_INTEL
, 0x2681, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
272 board_ahci
}, /* ESB2 */
273 { PCI_VENDOR_ID_INTEL
, 0x2682, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
274 board_ahci
}, /* ESB2 */
275 { PCI_VENDOR_ID_INTEL
, 0x2683, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
276 board_ahci
}, /* ESB2 */
277 { PCI_VENDOR_ID_INTEL
, 0x27c6, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
278 board_ahci
}, /* ICH7-M DH */
279 { PCI_VENDOR_ID_INTEL
, 0x2821, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
280 board_ahci
}, /* ICH8 */
281 { PCI_VENDOR_ID_INTEL
, 0x2822, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
282 board_ahci
}, /* ICH8 */
283 { PCI_VENDOR_ID_INTEL
, 0x2824, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
284 board_ahci
}, /* ICH8 */
285 { PCI_VENDOR_ID_INTEL
, 0x2829, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
286 board_ahci
}, /* ICH8M */
287 { PCI_VENDOR_ID_INTEL
, 0x282a, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
288 board_ahci
}, /* ICH8M */
289 { } /* terminate list */
293 static struct pci_driver ahci_pci_driver
= {
295 .id_table
= ahci_pci_tbl
,
296 .probe
= ahci_init_one
,
297 .remove
= ahci_remove_one
,
301 static inline unsigned long ahci_port_base_ul (unsigned long base
, unsigned int port
)
303 return base
+ 0x100 + (port
* 0x80);
306 static inline void __iomem
*ahci_port_base (void __iomem
*base
, unsigned int port
)
308 return (void __iomem
*) ahci_port_base_ul((unsigned long)base
, port
);
311 static int ahci_port_start(struct ata_port
*ap
)
313 struct device
*dev
= ap
->host_set
->dev
;
314 struct ahci_host_priv
*hpriv
= ap
->host_set
->private_data
;
315 struct ahci_port_priv
*pp
;
316 void __iomem
*mmio
= ap
->host_set
->mmio_base
;
317 void __iomem
*port_mmio
= ahci_port_base(mmio
, ap
->port_no
);
322 pp
= kmalloc(sizeof(*pp
), GFP_KERNEL
);
325 memset(pp
, 0, sizeof(*pp
));
327 rc
= ata_pad_alloc(ap
, dev
);
333 mem
= dma_alloc_coherent(dev
, AHCI_PORT_PRIV_DMA_SZ
, &mem_dma
, GFP_KERNEL
);
335 ata_pad_free(ap
, dev
);
339 memset(mem
, 0, AHCI_PORT_PRIV_DMA_SZ
);
342 * First item in chunk of DMA memory: 32-slot command table,
343 * 32 bytes each in size
346 pp
->cmd_slot_dma
= mem_dma
;
348 mem
+= AHCI_CMD_SLOT_SZ
;
349 mem_dma
+= AHCI_CMD_SLOT_SZ
;
352 * Second item: Received-FIS area
355 pp
->rx_fis_dma
= mem_dma
;
357 mem
+= AHCI_RX_FIS_SZ
;
358 mem_dma
+= AHCI_RX_FIS_SZ
;
361 * Third item: data area for storing a single command
362 * and its scatter-gather table
365 pp
->cmd_tbl_dma
= mem_dma
;
367 pp
->cmd_tbl_sg
= mem
+ AHCI_CMD_TBL_HDR
;
369 ap
->private_data
= pp
;
371 if (hpriv
->cap
& HOST_CAP_64
)
372 writel((pp
->cmd_slot_dma
>> 16) >> 16, port_mmio
+ PORT_LST_ADDR_HI
);
373 writel(pp
->cmd_slot_dma
& 0xffffffff, port_mmio
+ PORT_LST_ADDR
);
374 readl(port_mmio
+ PORT_LST_ADDR
); /* flush */
376 if (hpriv
->cap
& HOST_CAP_64
)
377 writel((pp
->rx_fis_dma
>> 16) >> 16, port_mmio
+ PORT_FIS_ADDR_HI
);
378 writel(pp
->rx_fis_dma
& 0xffffffff, port_mmio
+ PORT_FIS_ADDR
);
379 readl(port_mmio
+ PORT_FIS_ADDR
); /* flush */
381 writel(PORT_CMD_ICC_ACTIVE
| PORT_CMD_FIS_RX
|
382 PORT_CMD_POWER_ON
| PORT_CMD_SPIN_UP
|
383 PORT_CMD_START
, port_mmio
+ PORT_CMD
);
384 readl(port_mmio
+ PORT_CMD
); /* flush */
390 static void ahci_port_stop(struct ata_port
*ap
)
392 struct device
*dev
= ap
->host_set
->dev
;
393 struct ahci_port_priv
*pp
= ap
->private_data
;
394 void __iomem
*mmio
= ap
->host_set
->mmio_base
;
395 void __iomem
*port_mmio
= ahci_port_base(mmio
, ap
->port_no
);
398 tmp
= readl(port_mmio
+ PORT_CMD
);
399 tmp
&= ~(PORT_CMD_START
| PORT_CMD_FIS_RX
);
400 writel(tmp
, port_mmio
+ PORT_CMD
);
401 readl(port_mmio
+ PORT_CMD
); /* flush */
403 /* spec says 500 msecs for each PORT_CMD_{START,FIS_RX} bit, so
404 * this is slightly incorrect.
408 ap
->private_data
= NULL
;
409 dma_free_coherent(dev
, AHCI_PORT_PRIV_DMA_SZ
,
410 pp
->cmd_slot
, pp
->cmd_slot_dma
);
411 ata_pad_free(ap
, dev
);
415 static u32
ahci_scr_read (struct ata_port
*ap
, unsigned int sc_reg_in
)
420 case SCR_STATUS
: sc_reg
= 0; break;
421 case SCR_CONTROL
: sc_reg
= 1; break;
422 case SCR_ERROR
: sc_reg
= 2; break;
423 case SCR_ACTIVE
: sc_reg
= 3; break;
428 return readl((void __iomem
*) ap
->ioaddr
.scr_addr
+ (sc_reg
* 4));
432 static void ahci_scr_write (struct ata_port
*ap
, unsigned int sc_reg_in
,
438 case SCR_STATUS
: sc_reg
= 0; break;
439 case SCR_CONTROL
: sc_reg
= 1; break;
440 case SCR_ERROR
: sc_reg
= 2; break;
441 case SCR_ACTIVE
: sc_reg
= 3; break;
446 writel(val
, (void __iomem
*) ap
->ioaddr
.scr_addr
+ (sc_reg
* 4));
449 static int ahci_stop_engine(struct ata_port
*ap
)
451 void __iomem
*mmio
= ap
->host_set
->mmio_base
;
452 void __iomem
*port_mmio
= ahci_port_base(mmio
, ap
->port_no
);
456 tmp
= readl(port_mmio
+ PORT_CMD
);
457 tmp
&= ~PORT_CMD_START
;
458 writel(tmp
, port_mmio
+ PORT_CMD
);
460 /* wait for engine to stop. TODO: this could be
461 * as long as 500 msec
465 tmp
= readl(port_mmio
+ PORT_CMD
);
466 if ((tmp
& PORT_CMD_LIST_ON
) == 0)
474 static void ahci_start_engine(struct ata_port
*ap
)
476 void __iomem
*mmio
= ap
->host_set
->mmio_base
;
477 void __iomem
*port_mmio
= ahci_port_base(mmio
, ap
->port_no
);
480 tmp
= readl(port_mmio
+ PORT_CMD
);
481 tmp
|= PORT_CMD_START
;
482 writel(tmp
, port_mmio
+ PORT_CMD
);
483 readl(port_mmio
+ PORT_CMD
); /* flush */
486 static unsigned int ahci_dev_classify(struct ata_port
*ap
)
488 void __iomem
*port_mmio
= (void __iomem
*) ap
->ioaddr
.cmd_addr
;
489 struct ata_taskfile tf
;
492 tmp
= readl(port_mmio
+ PORT_SIG
);
493 tf
.lbah
= (tmp
>> 24) & 0xff;
494 tf
.lbam
= (tmp
>> 16) & 0xff;
495 tf
.lbal
= (tmp
>> 8) & 0xff;
496 tf
.nsect
= (tmp
) & 0xff;
498 return ata_dev_classify(&tf
);
501 static void ahci_phy_reset(struct ata_port
*ap
)
503 void __iomem
*port_mmio
= (void __iomem
*) ap
->ioaddr
.cmd_addr
;
504 struct ata_device
*dev
= &ap
->device
[0];
507 __sata_phy_reset(ap
);
509 if (ap
->flags
& ATA_FLAG_PORT_DISABLED
)
512 dev
->class = ahci_dev_classify(ap
);
513 if (!ata_dev_present(dev
)) {
514 ata_port_disable(ap
);
518 /* Make sure port's ATAPI bit is set appropriately */
519 new_tmp
= tmp
= readl(port_mmio
+ PORT_CMD
);
520 if (dev
->class == ATA_DEV_ATAPI
)
521 new_tmp
|= PORT_CMD_ATAPI
;
523 new_tmp
&= ~PORT_CMD_ATAPI
;
524 if (new_tmp
!= tmp
) {
525 writel(new_tmp
, port_mmio
+ PORT_CMD
);
526 readl(port_mmio
+ PORT_CMD
); /* flush */
530 static u8
ahci_check_status(struct ata_port
*ap
)
532 void __iomem
*mmio
= (void __iomem
*) ap
->ioaddr
.cmd_addr
;
534 return readl(mmio
+ PORT_TFDATA
) & 0xFF;
537 static void ahci_tf_read(struct ata_port
*ap
, struct ata_taskfile
*tf
)
539 struct ahci_port_priv
*pp
= ap
->private_data
;
540 u8
*d2h_fis
= pp
->rx_fis
+ RX_FIS_D2H_REG
;
542 ata_tf_from_fis(d2h_fis
, tf
);
545 static unsigned int ahci_fill_sg(struct ata_queued_cmd
*qc
)
547 struct ahci_port_priv
*pp
= qc
->ap
->private_data
;
548 struct scatterlist
*sg
;
549 struct ahci_sg
*ahci_sg
;
550 unsigned int n_sg
= 0;
555 * Next, the S/G list.
557 ahci_sg
= pp
->cmd_tbl_sg
;
558 ata_for_each_sg(sg
, qc
) {
559 dma_addr_t addr
= sg_dma_address(sg
);
560 u32 sg_len
= sg_dma_len(sg
);
562 ahci_sg
->addr
= cpu_to_le32(addr
& 0xffffffff);
563 ahci_sg
->addr_hi
= cpu_to_le32((addr
>> 16) >> 16);
564 ahci_sg
->flags_size
= cpu_to_le32(sg_len
- 1);
573 static void ahci_qc_prep(struct ata_queued_cmd
*qc
)
575 struct ata_port
*ap
= qc
->ap
;
576 struct ahci_port_priv
*pp
= ap
->private_data
;
578 const u32 cmd_fis_len
= 5; /* five dwords */
582 * Fill in command slot information (currently only one slot,
583 * slot 0, is currently since we don't do queueing)
587 if (qc
->tf
.flags
& ATA_TFLAG_WRITE
)
588 opts
|= AHCI_CMD_WRITE
;
589 if (is_atapi_taskfile(&qc
->tf
))
590 opts
|= AHCI_CMD_ATAPI
;
592 pp
->cmd_slot
[0].opts
= cpu_to_le32(opts
);
593 pp
->cmd_slot
[0].status
= 0;
594 pp
->cmd_slot
[0].tbl_addr
= cpu_to_le32(pp
->cmd_tbl_dma
& 0xffffffff);
595 pp
->cmd_slot
[0].tbl_addr_hi
= cpu_to_le32((pp
->cmd_tbl_dma
>> 16) >> 16);
598 * Fill in command table information. First, the header,
599 * a SATA Register - Host to Device command FIS.
601 ata_tf_to_fis(&qc
->tf
, pp
->cmd_tbl
, 0);
602 if (opts
& AHCI_CMD_ATAPI
) {
603 memset(pp
->cmd_tbl
+ AHCI_CMD_TBL_CDB
, 0, 32);
604 memcpy(pp
->cmd_tbl
+ AHCI_CMD_TBL_CDB
, qc
->cdb
, ap
->cdb_len
);
607 if (!(qc
->flags
& ATA_QCFLAG_DMAMAP
))
610 n_elem
= ahci_fill_sg(qc
);
612 pp
->cmd_slot
[0].opts
|= cpu_to_le32(n_elem
<< 16);
615 static void ahci_restart_port(struct ata_port
*ap
, u32 irq_stat
)
617 void __iomem
*mmio
= ap
->host_set
->mmio_base
;
618 void __iomem
*port_mmio
= ahci_port_base(mmio
, ap
->port_no
);
621 if ((ap
->device
[0].class != ATA_DEV_ATAPI
) ||
622 ((irq_stat
& PORT_IRQ_TF_ERR
) == 0))
623 printk(KERN_WARNING
"ata%u: port reset, "
624 "p_is %x is %x pis %x cmd %x tf %x ss %x se %x\n",
627 readl(mmio
+ HOST_IRQ_STAT
),
628 readl(port_mmio
+ PORT_IRQ_STAT
),
629 readl(port_mmio
+ PORT_CMD
),
630 readl(port_mmio
+ PORT_TFDATA
),
631 readl(port_mmio
+ PORT_SCR_STAT
),
632 readl(port_mmio
+ PORT_SCR_ERR
));
635 ahci_stop_engine(ap
);
637 /* clear SATA phy error, if any */
638 tmp
= readl(port_mmio
+ PORT_SCR_ERR
);
639 writel(tmp
, port_mmio
+ PORT_SCR_ERR
);
641 /* if DRQ/BSY is set, device needs to be reset.
642 * if so, issue COMRESET
644 tmp
= readl(port_mmio
+ PORT_TFDATA
);
645 if (tmp
& (ATA_BUSY
| ATA_DRQ
)) {
646 writel(0x301, port_mmio
+ PORT_SCR_CTL
);
647 readl(port_mmio
+ PORT_SCR_CTL
); /* flush */
649 writel(0x300, port_mmio
+ PORT_SCR_CTL
);
650 readl(port_mmio
+ PORT_SCR_CTL
); /* flush */
654 ahci_start_engine(ap
);
657 static void ahci_eng_timeout(struct ata_port
*ap
)
659 struct ata_host_set
*host_set
= ap
->host_set
;
660 void __iomem
*mmio
= host_set
->mmio_base
;
661 void __iomem
*port_mmio
= ahci_port_base(mmio
, ap
->port_no
);
662 struct ata_queued_cmd
*qc
;
665 printk(KERN_WARNING
"ata%u: handling error/timeout\n", ap
->id
);
667 spin_lock_irqsave(&host_set
->lock
, flags
);
669 qc
= ata_qc_from_tag(ap
, ap
->active_tag
);
671 printk(KERN_ERR
"ata%u: BUG: timeout without command\n",
674 ahci_restart_port(ap
, readl(port_mmio
+ PORT_IRQ_STAT
));
676 /* hack alert! We cannot use the supplied completion
677 * function from inside the ->eh_strategy_handler() thread.
678 * libata is the only user of ->eh_strategy_handler() in
679 * any kernel, so the default scsi_done() assumes it is
680 * not being called from the SCSI EH.
682 qc
->scsidone
= scsi_finish_command
;
683 qc
->err_mask
|= AC_ERR_TIMEOUT
;
687 spin_unlock_irqrestore(&host_set
->lock
, flags
);
690 static inline int ahci_host_intr(struct ata_port
*ap
, struct ata_queued_cmd
*qc
)
692 void __iomem
*mmio
= ap
->host_set
->mmio_base
;
693 void __iomem
*port_mmio
= ahci_port_base(mmio
, ap
->port_no
);
694 u32 status
, serr
, ci
;
696 serr
= readl(port_mmio
+ PORT_SCR_ERR
);
697 writel(serr
, port_mmio
+ PORT_SCR_ERR
);
699 status
= readl(port_mmio
+ PORT_IRQ_STAT
);
700 writel(status
, port_mmio
+ PORT_IRQ_STAT
);
702 ci
= readl(port_mmio
+ PORT_CMD_ISSUE
);
703 if (likely((ci
& 0x1) == 0)) {
705 assert(qc
->err_mask
== 0);
711 if (status
& PORT_IRQ_FATAL
) {
712 unsigned int err_mask
;
713 if (status
& PORT_IRQ_TF_ERR
)
714 err_mask
= AC_ERR_DEV
;
715 else if (status
& PORT_IRQ_IF_ERR
)
716 err_mask
= AC_ERR_ATA_BUS
;
718 err_mask
= AC_ERR_HOST_BUS
;
720 /* command processing has stopped due to error; restart */
721 ahci_restart_port(ap
, status
);
724 qc
->err_mask
|= err_mask
;
732 static void ahci_irq_clear(struct ata_port
*ap
)
737 static irqreturn_t
ahci_interrupt (int irq
, void *dev_instance
, struct pt_regs
*regs
)
739 struct ata_host_set
*host_set
= dev_instance
;
740 struct ahci_host_priv
*hpriv
;
741 unsigned int i
, handled
= 0;
743 u32 irq_stat
, irq_ack
= 0;
747 hpriv
= host_set
->private_data
;
748 mmio
= host_set
->mmio_base
;
750 /* sigh. 0xffffffff is a valid return from h/w */
751 irq_stat
= readl(mmio
+ HOST_IRQ_STAT
);
752 irq_stat
&= hpriv
->port_map
;
756 spin_lock(&host_set
->lock
);
758 for (i
= 0; i
< host_set
->n_ports
; i
++) {
761 if (!(irq_stat
& (1 << i
)))
764 ap
= host_set
->ports
[i
];
766 struct ata_queued_cmd
*qc
;
767 qc
= ata_qc_from_tag(ap
, ap
->active_tag
);
768 if (!ahci_host_intr(ap
, qc
))
769 if (ata_ratelimit()) {
770 struct pci_dev
*pdev
=
771 to_pci_dev(ap
->host_set
->dev
);
772 dev_printk(KERN_WARNING
, &pdev
->dev
,
773 "unhandled interrupt on port %u\n",
777 VPRINTK("port %u\n", i
);
779 VPRINTK("port %u (no irq)\n", i
);
780 if (ata_ratelimit()) {
781 struct pci_dev
*pdev
=
782 to_pci_dev(ap
->host_set
->dev
);
783 dev_printk(KERN_WARNING
, &pdev
->dev
,
784 "interrupt on disabled port %u\n", i
);
792 writel(irq_ack
, mmio
+ HOST_IRQ_STAT
);
796 spin_unlock(&host_set
->lock
);
800 return IRQ_RETVAL(handled
);
803 static unsigned int ahci_qc_issue(struct ata_queued_cmd
*qc
)
805 struct ata_port
*ap
= qc
->ap
;
806 void __iomem
*port_mmio
= (void __iomem
*) ap
->ioaddr
.cmd_addr
;
808 writel(1, port_mmio
+ PORT_CMD_ISSUE
);
809 readl(port_mmio
+ PORT_CMD_ISSUE
); /* flush */
814 static void ahci_setup_port(struct ata_ioports
*port
, unsigned long base
,
815 unsigned int port_idx
)
817 VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base
, port_idx
);
818 base
= ahci_port_base_ul(base
, port_idx
);
819 VPRINTK("base now==0x%lx\n", base
);
821 port
->cmd_addr
= base
;
822 port
->scr_addr
= base
+ PORT_SCR
;
827 static int ahci_host_init(struct ata_probe_ent
*probe_ent
)
829 struct ahci_host_priv
*hpriv
= probe_ent
->private_data
;
830 struct pci_dev
*pdev
= to_pci_dev(probe_ent
->dev
);
831 void __iomem
*mmio
= probe_ent
->mmio_base
;
834 unsigned int i
, j
, using_dac
;
836 void __iomem
*port_mmio
;
838 cap_save
= readl(mmio
+ HOST_CAP
);
839 cap_save
&= ( (1<<28) | (1<<17) );
840 cap_save
|= (1 << 27);
842 /* global controller reset */
843 tmp
= readl(mmio
+ HOST_CTL
);
844 if ((tmp
& HOST_RESET
) == 0) {
845 writel(tmp
| HOST_RESET
, mmio
+ HOST_CTL
);
846 readl(mmio
+ HOST_CTL
); /* flush */
849 /* reset must complete within 1 second, or
850 * the hardware should be considered fried.
854 tmp
= readl(mmio
+ HOST_CTL
);
855 if (tmp
& HOST_RESET
) {
856 dev_printk(KERN_ERR
, &pdev
->dev
,
857 "controller reset failed (0x%x)\n", tmp
);
861 writel(HOST_AHCI_EN
, mmio
+ HOST_CTL
);
862 (void) readl(mmio
+ HOST_CTL
); /* flush */
863 writel(cap_save
, mmio
+ HOST_CAP
);
864 writel(0xf, mmio
+ HOST_PORTS_IMPL
);
865 (void) readl(mmio
+ HOST_PORTS_IMPL
); /* flush */
867 pci_read_config_word(pdev
, 0x92, &tmp16
);
869 pci_write_config_word(pdev
, 0x92, tmp16
);
871 hpriv
->cap
= readl(mmio
+ HOST_CAP
);
872 hpriv
->port_map
= readl(mmio
+ HOST_PORTS_IMPL
);
873 probe_ent
->n_ports
= (hpriv
->cap
& 0x1f) + 1;
875 VPRINTK("cap 0x%x port_map 0x%x n_ports %d\n",
876 hpriv
->cap
, hpriv
->port_map
, probe_ent
->n_ports
);
878 using_dac
= hpriv
->cap
& HOST_CAP_64
;
880 !pci_set_dma_mask(pdev
, DMA_64BIT_MASK
)) {
881 rc
= pci_set_consistent_dma_mask(pdev
, DMA_64BIT_MASK
);
883 rc
= pci_set_consistent_dma_mask(pdev
, DMA_32BIT_MASK
);
885 dev_printk(KERN_ERR
, &pdev
->dev
,
886 "64-bit DMA enable failed\n");
891 rc
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
893 dev_printk(KERN_ERR
, &pdev
->dev
,
894 "32-bit DMA enable failed\n");
897 rc
= pci_set_consistent_dma_mask(pdev
, DMA_32BIT_MASK
);
899 dev_printk(KERN_ERR
, &pdev
->dev
,
900 "32-bit consistent DMA enable failed\n");
905 for (i
= 0; i
< probe_ent
->n_ports
; i
++) {
906 #if 0 /* BIOSen initialize this incorrectly */
907 if (!(hpriv
->port_map
& (1 << i
)))
911 port_mmio
= ahci_port_base(mmio
, i
);
912 VPRINTK("mmio %p port_mmio %p\n", mmio
, port_mmio
);
914 ahci_setup_port(&probe_ent
->port
[i
],
915 (unsigned long) mmio
, i
);
917 /* make sure port is not active */
918 tmp
= readl(port_mmio
+ PORT_CMD
);
919 VPRINTK("PORT_CMD 0x%x\n", tmp
);
920 if (tmp
& (PORT_CMD_LIST_ON
| PORT_CMD_FIS_ON
|
921 PORT_CMD_FIS_RX
| PORT_CMD_START
)) {
922 tmp
&= ~(PORT_CMD_LIST_ON
| PORT_CMD_FIS_ON
|
923 PORT_CMD_FIS_RX
| PORT_CMD_START
);
924 writel(tmp
, port_mmio
+ PORT_CMD
);
925 readl(port_mmio
+ PORT_CMD
); /* flush */
927 /* spec says 500 msecs for each bit, so
928 * this is slightly incorrect.
933 writel(PORT_CMD_SPIN_UP
, port_mmio
+ PORT_CMD
);
938 tmp
= readl(port_mmio
+ PORT_SCR_STAT
);
939 if ((tmp
& 0xf) == 0x3)
944 tmp
= readl(port_mmio
+ PORT_SCR_ERR
);
945 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp
);
946 writel(tmp
, port_mmio
+ PORT_SCR_ERR
);
948 /* ack any pending irq events for this port */
949 tmp
= readl(port_mmio
+ PORT_IRQ_STAT
);
950 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp
);
952 writel(tmp
, port_mmio
+ PORT_IRQ_STAT
);
954 writel(1 << i
, mmio
+ HOST_IRQ_STAT
);
956 /* set irq mask (enables interrupts) */
957 writel(DEF_PORT_IRQ
, port_mmio
+ PORT_IRQ_MASK
);
960 tmp
= readl(mmio
+ HOST_CTL
);
961 VPRINTK("HOST_CTL 0x%x\n", tmp
);
962 writel(tmp
| HOST_IRQ_EN
, mmio
+ HOST_CTL
);
963 tmp
= readl(mmio
+ HOST_CTL
);
964 VPRINTK("HOST_CTL 0x%x\n", tmp
);
966 pci_set_master(pdev
);
971 static void ahci_print_info(struct ata_probe_ent
*probe_ent
)
973 struct ahci_host_priv
*hpriv
= probe_ent
->private_data
;
974 struct pci_dev
*pdev
= to_pci_dev(probe_ent
->dev
);
975 void __iomem
*mmio
= probe_ent
->mmio_base
;
976 u32 vers
, cap
, impl
, speed
;
981 vers
= readl(mmio
+ HOST_VERSION
);
983 impl
= hpriv
->port_map
;
985 speed
= (cap
>> 20) & 0xf;
993 pci_read_config_word(pdev
, 0x0a, &cc
);
996 else if (cc
== 0x0106)
998 else if (cc
== 0x0104)
1003 dev_printk(KERN_INFO
, &pdev
->dev
,
1004 "AHCI %02x%02x.%02x%02x "
1005 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
1008 (vers
>> 24) & 0xff,
1009 (vers
>> 16) & 0xff,
1013 ((cap
>> 8) & 0x1f) + 1,
1019 dev_printk(KERN_INFO
, &pdev
->dev
,
1025 cap
& (1 << 31) ? "64bit " : "",
1026 cap
& (1 << 30) ? "ncq " : "",
1027 cap
& (1 << 28) ? "ilck " : "",
1028 cap
& (1 << 27) ? "stag " : "",
1029 cap
& (1 << 26) ? "pm " : "",
1030 cap
& (1 << 25) ? "led " : "",
1032 cap
& (1 << 24) ? "clo " : "",
1033 cap
& (1 << 19) ? "nz " : "",
1034 cap
& (1 << 18) ? "only " : "",
1035 cap
& (1 << 17) ? "pmp " : "",
1036 cap
& (1 << 15) ? "pio " : "",
1037 cap
& (1 << 14) ? "slum " : "",
1038 cap
& (1 << 13) ? "part " : ""
1042 static int ahci_init_one (struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
1044 static int printed_version
;
1045 struct ata_probe_ent
*probe_ent
= NULL
;
1046 struct ahci_host_priv
*hpriv
;
1048 void __iomem
*mmio_base
;
1049 unsigned int board_idx
= (unsigned int) ent
->driver_data
;
1050 int have_msi
, pci_dev_busy
= 0;
1055 if (!printed_version
++)
1056 dev_printk(KERN_DEBUG
, &pdev
->dev
, "version " DRV_VERSION
"\n");
1058 rc
= pci_enable_device(pdev
);
1062 rc
= pci_request_regions(pdev
, DRV_NAME
);
1068 if (pci_enable_msi(pdev
) == 0)
1075 probe_ent
= kmalloc(sizeof(*probe_ent
), GFP_KERNEL
);
1076 if (probe_ent
== NULL
) {
1081 memset(probe_ent
, 0, sizeof(*probe_ent
));
1082 probe_ent
->dev
= pci_dev_to_dev(pdev
);
1083 INIT_LIST_HEAD(&probe_ent
->node
);
1085 mmio_base
= pci_iomap(pdev
, AHCI_PCI_BAR
, 0);
1086 if (mmio_base
== NULL
) {
1088 goto err_out_free_ent
;
1090 base
= (unsigned long) mmio_base
;
1092 hpriv
= kmalloc(sizeof(*hpriv
), GFP_KERNEL
);
1095 goto err_out_iounmap
;
1097 memset(hpriv
, 0, sizeof(*hpriv
));
1099 probe_ent
->sht
= ahci_port_info
[board_idx
].sht
;
1100 probe_ent
->host_flags
= ahci_port_info
[board_idx
].host_flags
;
1101 probe_ent
->pio_mask
= ahci_port_info
[board_idx
].pio_mask
;
1102 probe_ent
->udma_mask
= ahci_port_info
[board_idx
].udma_mask
;
1103 probe_ent
->port_ops
= ahci_port_info
[board_idx
].port_ops
;
1105 probe_ent
->irq
= pdev
->irq
;
1106 probe_ent
->irq_flags
= SA_SHIRQ
;
1107 probe_ent
->mmio_base
= mmio_base
;
1108 probe_ent
->private_data
= hpriv
;
1111 hpriv
->flags
|= AHCI_FLAG_MSI
;
1113 /* initialize adapter */
1114 rc
= ahci_host_init(probe_ent
);
1118 ahci_print_info(probe_ent
);
1120 /* FIXME: check ata_device_add return value */
1121 ata_device_add(probe_ent
);
1129 pci_iounmap(pdev
, mmio_base
);
1134 pci_disable_msi(pdev
);
1137 pci_release_regions(pdev
);
1140 pci_disable_device(pdev
);
1144 static void ahci_remove_one (struct pci_dev
*pdev
)
1146 struct device
*dev
= pci_dev_to_dev(pdev
);
1147 struct ata_host_set
*host_set
= dev_get_drvdata(dev
);
1148 struct ahci_host_priv
*hpriv
= host_set
->private_data
;
1149 struct ata_port
*ap
;
1153 for (i
= 0; i
< host_set
->n_ports
; i
++) {
1154 ap
= host_set
->ports
[i
];
1156 scsi_remove_host(ap
->host
);
1159 have_msi
= hpriv
->flags
& AHCI_FLAG_MSI
;
1160 free_irq(host_set
->irq
, host_set
);
1162 for (i
= 0; i
< host_set
->n_ports
; i
++) {
1163 ap
= host_set
->ports
[i
];
1165 ata_scsi_release(ap
->host
);
1166 scsi_host_put(ap
->host
);
1170 pci_iounmap(pdev
, host_set
->mmio_base
);
1174 pci_disable_msi(pdev
);
1177 pci_release_regions(pdev
);
1178 pci_disable_device(pdev
);
1179 dev_set_drvdata(dev
, NULL
);
1182 static int __init
ahci_init(void)
1184 return pci_module_init(&ahci_pci_driver
);
1187 static void __exit
ahci_exit(void)
1189 pci_unregister_driver(&ahci_pci_driver
);
1193 MODULE_AUTHOR("Jeff Garzik");
1194 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1195 MODULE_LICENSE("GPL");
1196 MODULE_DEVICE_TABLE(pci
, ahci_pci_tbl
);
1197 MODULE_VERSION(DRV_VERSION
);
1199 module_init(ahci_init
);
1200 module_exit(ahci_exit
);