arch/mips/cobalt/irq.c

   1 /*
   2  * IRQ vector handles
   3  *
   4  * This file is subject to the terms and conditions of the GNU General Public
   5  * License.  See the file "COPYING" in the main directory of this archive
   6  * for more details.
   7  *
   8  * Copyright (C) 1995, 1996, 1997, 2003 by Ralf Baechle
   9  */
  10 #include <linux/kernel.h>
  11 #include <linux/init.h>
  12 #include <linux/irq.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/pci.h>
  15
  16 #include <asm/i8259.h>
  17 #include <asm/irq_cpu.h>
  18 #include <asm/gt64120.h>
  19 #include <asm/ptrace.h>
  20
  21 #include <asm/mach-cobalt/cobalt.h>
  22
  23 /*
  24  * We have two types of interrupts that we handle, ones that come in through
  25  * the CPU interrupt lines, and ones that come in on the via chip. The CPU
  26  * mappings are:
  27  *
  28  *    16   - Software interrupt 0 (unused)      IE_SW0
  29  *    17   - Software interrupt 1 (unused)      IE_SW1
  30  *    18   - Galileo chip (timer)               IE_IRQ0
  31  *    19   - Tulip 0 + NCR SCSI                 IE_IRQ1
  32  *    20   - Tulip 1                            IE_IRQ2
  33  *    21   - 16550 UART                         IE_IRQ3
  34  *    22   - VIA southbridge PIC                IE_IRQ4
  35  *    23   - unused                             IE_IRQ5
  36  *
  37  * The VIA chip is a master/slave 8259 setup and has the following interrupts:
  38  *
  39  *     8  - RTC
  40  *     9  - PCI
  41  *    14  - IDE0
  42  *    15  - IDE1
  43  */
  44
  45 static inline void galileo_irq(struct pt_regs *regs)
  46 {
  47         unsigned int mask, pending, devfn;
  48
  49         mask = GALILEO_INL(GT_INTRMASK_OFS);
  50         pending = GALILEO_INL(GT_INTRCAUSE_OFS) & mask;
  51
  52         if (pending & GALILEO_INTR_T0EXP) {
  53
  54                 GALILEO_OUTL(~GALILEO_INTR_T0EXP, GT_INTRCAUSE_OFS);
  55                 do_IRQ(COBALT_GALILEO_IRQ, regs);
  56
  57         } else if (pending & GALILEO_INTR_RETRY_CTR) {
  58
  59                 devfn = GALILEO_INL(GT_PCI0_CFGADDR_OFS) >> 8;
  60                 GALILEO_OUTL(~GALILEO_INTR_RETRY_CTR, GT_INTRCAUSE_OFS);
  61                 printk(KERN_WARNING "Galileo: PCI retry count exceeded (%02x.%u)\n",
  62                         PCI_SLOT(devfn), PCI_FUNC(devfn));
  63
  64         } else {
  65
  66                 GALILEO_OUTL(mask & ~pending, GT_INTRMASK_OFS);
  67                 printk(KERN_WARNING "Galileo: masking unexpected interrupt %08x\n", pending);
  68         }
  69 }
  70
  71 static inline void via_pic_irq(struct pt_regs *regs)
  72 {
  73         int irq;
  74
  75         irq = i8259_irq();
  76         if (irq >= 0)
  77                 do_IRQ(irq, regs);
  78 }
  79
  80 asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
  81 {
  82         unsigned pending;
  83
  84         pending = read_c0_status() & read_c0_cause();
  85
  86         if (pending & CAUSEF_IP2)                       /* COBALT_GALILEO_IRQ (18) */
  87
  88                 galileo_irq(regs);
  89
  90         else if (pending & CAUSEF_IP6)                  /* COBALT_VIA_IRQ (22) */
  91
  92                 via_pic_irq(regs);
  93
  94         else if (pending & CAUSEF_IP3)                  /* COBALT_ETH0_IRQ (19) */
  95
  96                 do_IRQ(COBALT_CPU_IRQ + 3, regs);
  97
  98         else if (pending & CAUSEF_IP4)                  /* COBALT_ETH1_IRQ (20) */
  99
 100                 do_IRQ(COBALT_CPU_IRQ + 4, regs);
 101
 102         else if (pending & CAUSEF_IP5)                  /* COBALT_SERIAL_IRQ (21) */
 103
 104                 do_IRQ(COBALT_CPU_IRQ + 5, regs);
 105
 106         else if (pending & CAUSEF_IP7)                  /* IRQ 23 */
 107
 108                 do_IRQ(COBALT_CPU_IRQ + 7, regs);
 109 }
 110
 111 static struct irqaction irq_via = {
 112         no_action, 0, { { 0, } }, "cascade", NULL, NULL
 113 };
 114
 115 void __init arch_init_irq(void)
 116 {
 117         /*
 118          * Mask all Galileo interrupts. The Galileo
 119          * handler is set in cobalt_timer_setup()
 120          */
 121         GALILEO_OUTL(0, GT_INTRMASK_OFS);
 122
 123         init_i8259_irqs();                              /*  0 ... 15 */
 124         mips_cpu_irq_init(COBALT_CPU_IRQ);              /* 16 ... 23 */
 125
 126         /*
 127          * Mask all cpu interrupts
 128          *  (except IE4, we already masked those at VIA level)
 129          */
 130         change_c0_status(ST0_IM, IE_IRQ4);
 131
 132         setup_irq(COBALT_VIA_IRQ, &irq_via);
 133 }