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[PATCH] bcm43xx: >1G and 64bit DMA support
[linux-2.6/suspend2-2.6.18.git] / drivers / net / wireless / bcm43xx / bcm43xx_dma.h
blob258a2f9bd7a63c67810e352f4f007fd9a456271e
1 #ifndef BCM43xx_DMA_H_
2 #define BCM43xx_DMA_H_
3
4 #include <linux/list.h>
5 #include <linux/spinlock.h>
6 #include <linux/workqueue.h>
7 #include <linux/linkage.h>
8 #include <asm/atomic.h>
9
10
11 /* DMA-Interrupt reasons. */
12 #define BCM43xx_DMAIRQ_FATALMASK ((1 << 10) | (1 << 11) | (1 << 12) \
13 | (1 << 14) | (1 << 15))
14 #define BCM43xx_DMAIRQ_NONFATALMASK (1 << 13)
15 #define BCM43xx_DMAIRQ_RX_DONE (1 << 16)
16
17
18 /*** 32-bit DMA Engine. ***/
19
20 /* 32-bit DMA controller registers. */
21 #define BCM43xx_DMA32_TXCTL 0x00
22 #define BCM43xx_DMA32_TXENABLE 0x00000001
23 #define BCM43xx_DMA32_TXSUSPEND 0x00000002
24 #define BCM43xx_DMA32_TXLOOPBACK 0x00000004
25 #define BCM43xx_DMA32_TXFLUSH 0x00000010
26 #define BCM43xx_DMA32_TXADDREXT_MASK 0x00030000
27 #define BCM43xx_DMA32_TXADDREXT_SHIFT 16
28 #define BCM43xx_DMA32_TXRING 0x04
29 #define BCM43xx_DMA32_TXINDEX 0x08
30 #define BCM43xx_DMA32_TXSTATUS 0x0C
31 #define BCM43xx_DMA32_TXDPTR 0x00000FFF
32 #define BCM43xx_DMA32_TXSTATE 0x0000F000
33 #define BCM43xx_DMA32_TXSTAT_DISABLED 0x00000000
34 #define BCM43xx_DMA32_TXSTAT_ACTIVE 0x00001000
35 #define BCM43xx_DMA32_TXSTAT_IDLEWAIT 0x00002000
36 #define BCM43xx_DMA32_TXSTAT_STOPPED 0x00003000
37 #define BCM43xx_DMA32_TXSTAT_SUSP 0x00004000
38 #define BCM43xx_DMA32_TXERROR 0x000F0000
39 #define BCM43xx_DMA32_TXERR_NOERR 0x00000000
40 #define BCM43xx_DMA32_TXERR_PROT 0x00010000
41 #define BCM43xx_DMA32_TXERR_UNDERRUN 0x00020000
42 #define BCM43xx_DMA32_TXERR_BUFREAD 0x00030000
43 #define BCM43xx_DMA32_TXERR_DESCREAD 0x00040000
44 #define BCM43xx_DMA32_TXACTIVE 0xFFF00000
45 #define BCM43xx_DMA32_RXCTL 0x10
46 #define BCM43xx_DMA32_RXENABLE 0x00000001
47 #define BCM43xx_DMA32_RXFROFF_MASK 0x000000FE
48 #define BCM43xx_DMA32_RXFROFF_SHIFT 1
49 #define BCM43xx_DMA32_RXDIRECTFIFO 0x00000100
50 #define BCM43xx_DMA32_RXADDREXT_MASK 0x00030000
51 #define BCM43xx_DMA32_RXADDREXT_SHIFT 16
52 #define BCM43xx_DMA32_RXRING 0x14
53 #define BCM43xx_DMA32_RXINDEX 0x18
54 #define BCM43xx_DMA32_RXSTATUS 0x1C
55 #define BCM43xx_DMA32_RXDPTR 0x00000FFF
56 #define BCM43xx_DMA32_RXSTATE 0x0000F000
57 #define BCM43xx_DMA32_RXSTAT_DISABLED 0x00000000
58 #define BCM43xx_DMA32_RXSTAT_ACTIVE 0x00001000
59 #define BCM43xx_DMA32_RXSTAT_IDLEWAIT 0x00002000
60 #define BCM43xx_DMA32_RXSTAT_STOPPED 0x00003000
61 #define BCM43xx_DMA32_RXERROR 0x000F0000
62 #define BCM43xx_DMA32_RXERR_NOERR 0x00000000
63 #define BCM43xx_DMA32_RXERR_PROT 0x00010000
64 #define BCM43xx_DMA32_RXERR_OVERFLOW 0x00020000
65 #define BCM43xx_DMA32_RXERR_BUFWRITE 0x00030000
66 #define BCM43xx_DMA32_RXERR_DESCREAD 0x00040000
67 #define BCM43xx_DMA32_RXACTIVE 0xFFF00000
68
69 /* 32-bit DMA descriptor. */
70 struct bcm43xx_dmadesc32 {
71 __le32 control;
72 __le32 address;
73 } __attribute__((__packed__));
74 #define BCM43xx_DMA32_DCTL_BYTECNT 0x00001FFF
75 #define BCM43xx_DMA32_DCTL_ADDREXT_MASK 0x00030000
76 #define BCM43xx_DMA32_DCTL_ADDREXT_SHIFT 16
77 #define BCM43xx_DMA32_DCTL_DTABLEEND 0x10000000
78 #define BCM43xx_DMA32_DCTL_IRQ 0x20000000
79 #define BCM43xx_DMA32_DCTL_FRAMEEND 0x40000000
80 #define BCM43xx_DMA32_DCTL_FRAMESTART 0x80000000
81
82 /* Address field Routing value. */
83 #define BCM43xx_DMA32_ROUTING 0xC0000000
84 #define BCM43xx_DMA32_ROUTING_SHIFT 30
85 #define BCM43xx_DMA32_NOTRANS 0x00000000
86 #define BCM43xx_DMA32_CLIENTTRANS 0x40000000
87
88
89
90 /*** 64-bit DMA Engine. ***/
91
92 /* 64-bit DMA controller registers. */
93 #define BCM43xx_DMA64_TXCTL 0x00
94 #define BCM43xx_DMA64_TXENABLE 0x00000001
95 #define BCM43xx_DMA64_TXSUSPEND 0x00000002
96 #define BCM43xx_DMA64_TXLOOPBACK 0x00000004
97 #define BCM43xx_DMA64_TXFLUSH 0x00000010
98 #define BCM43xx_DMA64_TXADDREXT_MASK 0x00030000
99 #define BCM43xx_DMA64_TXADDREXT_SHIFT 16
100 #define BCM43xx_DMA64_TXINDEX 0x04
101 #define BCM43xx_DMA64_TXRINGLO 0x08
102 #define BCM43xx_DMA64_TXRINGHI 0x0C
103 #define BCM43xx_DMA64_TXSTATUS 0x10
104 #define BCM43xx_DMA64_TXSTATDPTR 0x00001FFF
105 #define BCM43xx_DMA64_TXSTAT 0xF0000000
106 #define BCM43xx_DMA64_TXSTAT_DISABLED 0x00000000
107 #define BCM43xx_DMA64_TXSTAT_ACTIVE 0x10000000
108 #define BCM43xx_DMA64_TXSTAT_IDLEWAIT 0x20000000
109 #define BCM43xx_DMA64_TXSTAT_STOPPED 0x30000000
110 #define BCM43xx_DMA64_TXSTAT_SUSP 0x40000000
111 #define BCM43xx_DMA64_TXERROR 0x14
112 #define BCM43xx_DMA64_TXERRDPTR 0x0001FFFF
113 #define BCM43xx_DMA64_TXERR 0xF0000000
114 #define BCM43xx_DMA64_TXERR_NOERR 0x00000000
115 #define BCM43xx_DMA64_TXERR_PROT 0x10000000
116 #define BCM43xx_DMA64_TXERR_UNDERRUN 0x20000000
117 #define BCM43xx_DMA64_TXERR_TRANSFER 0x30000000
118 #define BCM43xx_DMA64_TXERR_DESCREAD 0x40000000
119 #define BCM43xx_DMA64_TXERR_CORE 0x50000000
120 #define BCM43xx_DMA64_RXCTL 0x20
121 #define BCM43xx_DMA64_RXENABLE 0x00000001
122 #define BCM43xx_DMA64_RXFROFF_MASK 0x000000FE
123 #define BCM43xx_DMA64_RXFROFF_SHIFT 1
124 #define BCM43xx_DMA64_RXDIRECTFIFO 0x00000100
125 #define BCM43xx_DMA64_RXADDREXT_MASK 0x00030000
126 #define BCM43xx_DMA64_RXADDREXT_SHIFT 16
127 #define BCM43xx_DMA64_RXINDEX 0x24
128 #define BCM43xx_DMA64_RXRINGLO 0x28
129 #define BCM43xx_DMA64_RXRINGHI 0x2C
130 #define BCM43xx_DMA64_RXSTATUS 0x30
131 #define BCM43xx_DMA64_RXSTATDPTR 0x00001FFF
132 #define BCM43xx_DMA64_RXSTAT 0xF0000000
133 #define BCM43xx_DMA64_RXSTAT_DISABLED 0x00000000
134 #define BCM43xx_DMA64_RXSTAT_ACTIVE 0x10000000
135 #define BCM43xx_DMA64_RXSTAT_IDLEWAIT 0x20000000
136 #define BCM43xx_DMA64_RXSTAT_STOPPED 0x30000000
137 #define BCM43xx_DMA64_RXSTAT_SUSP 0x40000000
138 #define BCM43xx_DMA64_RXERROR 0x34
139 #define BCM43xx_DMA64_RXERRDPTR 0x0001FFFF
140 #define BCM43xx_DMA64_RXERR 0xF0000000
141 #define BCM43xx_DMA64_RXERR_NOERR 0x00000000
142 #define BCM43xx_DMA64_RXERR_PROT 0x10000000
143 #define BCM43xx_DMA64_RXERR_UNDERRUN 0x20000000
144 #define BCM43xx_DMA64_RXERR_TRANSFER 0x30000000
145 #define BCM43xx_DMA64_RXERR_DESCREAD 0x40000000
146 #define BCM43xx_DMA64_RXERR_CORE 0x50000000
147
148 /* 64-bit DMA descriptor. */
149 struct bcm43xx_dmadesc64 {
150 __le32 control0;
151 __le32 control1;
152 __le32 address_low;
153 __le32 address_high;
154 } __attribute__((__packed__));
155 #define BCM43xx_DMA64_DCTL0_DTABLEEND 0x10000000
156 #define BCM43xx_DMA64_DCTL0_IRQ 0x20000000
157 #define BCM43xx_DMA64_DCTL0_FRAMEEND 0x40000000
158 #define BCM43xx_DMA64_DCTL0_FRAMESTART 0x80000000
159 #define BCM43xx_DMA64_DCTL1_BYTECNT 0x00001FFF
160 #define BCM43xx_DMA64_DCTL1_ADDREXT_MASK 0x00030000
161 #define BCM43xx_DMA64_DCTL1_ADDREXT_SHIFT 16
162
163 /* Address field Routing value. */
164 #define BCM43xx_DMA64_ROUTING 0xC0000000
165 #define BCM43xx_DMA64_ROUTING_SHIFT 30
166 #define BCM43xx_DMA64_NOTRANS 0x00000000
167 #define BCM43xx_DMA64_CLIENTTRANS 0x80000000
168
169
170
171 struct bcm43xx_dmadesc_generic {
172 union {
173 struct bcm43xx_dmadesc32 dma32;
174 struct bcm43xx_dmadesc64 dma64;
175 } __attribute__((__packed__));
176 } __attribute__((__packed__));
177
178
179 /* Misc DMA constants */
180 #define BCM43xx_DMA_RINGMEMSIZE PAGE_SIZE
181 #define BCM43xx_DMA0_RX_FRAMEOFFSET 30
182 #define BCM43xx_DMA3_RX_FRAMEOFFSET 0
183
184
185 /* DMA engine tuning knobs */
186 #define BCM43xx_TXRING_SLOTS 512
187 #define BCM43xx_RXRING_SLOTS 64
188 #define BCM43xx_DMA0_RX_BUFFERSIZE (2304 + 100)
189 #define BCM43xx_DMA3_RX_BUFFERSIZE 16
190 /* Suspend the tx queue, if less than this percent slots are free. */
191 #define BCM43xx_TXSUSPEND_PERCENT 20
192 /* Resume the tx queue, if more than this percent slots are free. */
193 #define BCM43xx_TXRESUME_PERCENT 50
194
195
196
197 #ifdef CONFIG_BCM43XX_DMA
198
199
200 struct sk_buff;
201 struct bcm43xx_private;
202 struct bcm43xx_xmitstatus;
203
204
205 struct bcm43xx_dmadesc_meta {
206 /* The kernel DMA-able buffer. */
207 struct sk_buff *skb;
208 /* DMA base bus-address of the descriptor buffer. */
209 dma_addr_t dmaaddr;
210 };
211
212 struct bcm43xx_dmaring {
213 /* Kernel virtual base address of the ring memory. */
214 void *descbase;
215 /* Meta data about all descriptors. */
216 struct bcm43xx_dmadesc_meta *meta;
217 /* DMA Routing value. */
218 u32 routing;
219 /* (Unadjusted) DMA base bus-address of the ring memory. */
220 dma_addr_t dmabase;
221 /* Number of descriptor slots in the ring. */
222 int nr_slots;
223 /* Number of used descriptor slots. */
224 int used_slots;
225 /* Currently used slot in the ring. */
226 int current_slot;
227 /* Marks to suspend/resume the queue. */
228 int suspend_mark;
229 int resume_mark;
230 /* Frameoffset in octets. */
231 u32 frameoffset;
232 /* Descriptor buffer size. */
233 u16 rx_buffersize;
234 /* The MMIO base register of the DMA controller. */
235 u16 mmio_base;
236 /* DMA controller index number (0-5). */
237 int index;
238 u8 tx:1, /* TRUE, if this is a TX ring. */
239 dma64:1, /* TRUE, if 64-bit DMA is enabled (FALSE if 32bit). */
240 suspended:1; /* TRUE, if transfers are suspended on this ring. */
241 struct bcm43xx_private *bcm;
242 #ifdef CONFIG_BCM43XX_DEBUG
243 /* Maximum number of used slots. */
244 int max_used_slots;
245 #endif /* CONFIG_BCM43XX_DEBUG*/
246 };
247
248
249 static inline
250 int bcm43xx_dma_desc2idx(struct bcm43xx_dmaring *ring,
251 struct bcm43xx_dmadesc_generic *desc)
252 {
253 if (ring->dma64) {
254 struct bcm43xx_dmadesc64 *dd64 = ring->descbase;
255 return (int)(&(desc->dma64) - dd64);
256 } else {
257 struct bcm43xx_dmadesc32 *dd32 = ring->descbase;
258 return (int)(&(desc->dma32) - dd32);
259 }
260 }
261
262 static inline
263 struct bcm43xx_dmadesc_generic * bcm43xx_dma_idx2desc(struct bcm43xx_dmaring *ring,
264 int slot,
265 struct bcm43xx_dmadesc_meta **meta)
266 {
267 *meta = &(ring->meta[slot]);
268 if (ring->dma64) {
269 struct bcm43xx_dmadesc64 *dd64 = ring->descbase;
270 return (struct bcm43xx_dmadesc_generic *)(&(dd64[slot]));
271 } else {
272 struct bcm43xx_dmadesc32 *dd32 = ring->descbase;
273 return (struct bcm43xx_dmadesc_generic *)(&(dd32[slot]));
274 }
275 }
276
277 static inline
278 u32 bcm43xx_dma_read(struct bcm43xx_dmaring *ring,
279 u16 offset)
280 {
281 return bcm43xx_read32(ring->bcm, ring->mmio_base + offset);
282 }
283
284 static inline
285 void bcm43xx_dma_write(struct bcm43xx_dmaring *ring,
286 u16 offset, u32 value)
287 {
288 bcm43xx_write32(ring->bcm, ring->mmio_base + offset, value);
289 }
290
291
292 int bcm43xx_dma_init(struct bcm43xx_private *bcm);
293 void bcm43xx_dma_free(struct bcm43xx_private *bcm);
294
295 int bcm43xx_dmacontroller_rx_reset(struct bcm43xx_private *bcm,
296 u16 dmacontroller_mmio_base,
297 int dma64);
298 int bcm43xx_dmacontroller_tx_reset(struct bcm43xx_private *bcm,
299 u16 dmacontroller_mmio_base,
300 int dma64);
301
302 u16 bcm43xx_dmacontroller_base(int dma64bit, int dmacontroller_idx);
303
304 void bcm43xx_dma_tx_suspend(struct bcm43xx_dmaring *ring);
305 void bcm43xx_dma_tx_resume(struct bcm43xx_dmaring *ring);
306
307 void bcm43xx_dma_handle_xmitstatus(struct bcm43xx_private *bcm,
308 struct bcm43xx_xmitstatus *status);
309
310 int bcm43xx_dma_tx(struct bcm43xx_private *bcm,
311 struct ieee80211_txb *txb);
312 void bcm43xx_dma_rx(struct bcm43xx_dmaring *ring);
313
314 #else /* CONFIG_BCM43XX_DMA */
315
316
317 static inline
318 int bcm43xx_dma_init(struct bcm43xx_private *bcm)
319 {
320 return 0;
321 }
322 static inline
323 void bcm43xx_dma_free(struct bcm43xx_private *bcm)
324 {
325 }
326 static inline
327 int bcm43xx_dmacontroller_rx_reset(struct bcm43xx_private *bcm,
328 u16 dmacontroller_mmio_base,
329 int dma64)
330 {
331 return 0;
332 }
333 static inline
334 int bcm43xx_dmacontroller_tx_reset(struct bcm43xx_private *bcm,
335 u16 dmacontroller_mmio_base,
336 int dma64)
337 {
338 return 0;
339 }
340 static inline
341 int bcm43xx_dma_tx(struct bcm43xx_private *bcm,
342 struct ieee80211_txb *txb)
343 {
344 return 0;
345 }
346 static inline
347 void bcm43xx_dma_handle_xmitstatus(struct bcm43xx_private *bcm,
348 struct bcm43xx_xmitstatus *status)
349 {
350 }
351 static inline
352 void bcm43xx_dma_rx(struct bcm43xx_dmaring *ring)
353 {
354 }
355 static inline
356 void bcm43xx_dma_tx_suspend(struct bcm43xx_dmaring *ring)
357 {
358 }
359 static inline
360 void bcm43xx_dma_tx_resume(struct bcm43xx_dmaring *ring)
361 {
362 }
363
364 #endif /* CONFIG_BCM43XX_DMA */
365 #endif /* BCM43xx_DMA_H_ */
Software Suspend 2 for 2.6.18.y (mirror)