include/asm-sh/io.h

   1 #ifndef __ASM_SH_IO_H
   2 #define __ASM_SH_IO_H
   3
   4 /*
   5  * Convention:
   6  *    read{b,w,l}/write{b,w,l} are for PCI,
   7  *    while in{b,w,l}/out{b,w,l} are for ISA
   8  * These may (will) be platform specific function.
   9  * In addition we have 'pausing' versions: in{b,w,l}_p/out{b,w,l}_p
  10  * and 'string' versions: ins{b,w,l}/outs{b,w,l}
  11  * For read{b,w,l} and write{b,w,l} there are also __raw versions, which
  12  * do not have a memory barrier after them.
  13  *
  14  * In addition, we have
  15  *   ctrl_in{b,w,l}/ctrl_out{b,w,l} for SuperH specific I/O.
  16  *   which are processor specific.
  17  */
  18
  19 /*
  20  * We follow the Alpha convention here:
  21  *  __inb expands to an inline function call (which calls via the mv)
  22  *  _inb  is a real function call (note ___raw fns are _ version of __raw)
  23  *  inb   by default expands to _inb, but the machine specific code may
  24  *        define it to __inb if it chooses.
  25  */
  26 #include <linux/config.h>
  27 #include <asm/cache.h>
  28 #include <asm/system.h>
  29 #include <asm/addrspace.h>
  30 #include <asm/machvec.h>
  31 #include <asm/pgtable.h>
  32 #include <asm-generic/iomap.h>
  33
  34 #ifdef __KERNEL__
  35
  36 /*
  37  * Depending on which platform we are running on, we need different
  38  * I/O functions.
  39  */
  40 #define __IO_PREFIX     generic
  41 #include <asm/io_generic.h>
  42
  43 #define maybebadio(port) \
  44   printk(KERN_ERR "bad PC-like io %s:%u for port 0x%lx at 0x%08x\n", \
  45          __FUNCTION__, __LINE__, (port), (u32)__builtin_return_address(0))
  46
  47 /*
  48  * Since boards are able to define their own set of I/O routines through
  49  * their respective machine vector, we always wrap through the mv.
  50  *
  51  * Also, in the event that a board hasn't provided its own definition for
  52  * a given routine, it will be wrapped to generic code at run-time.
  53  */
  54
  55 #define __inb(p)        sh_mv.mv_inb((p))
  56 #define __inw(p)        sh_mv.mv_inw((p))
  57 #define __inl(p)        sh_mv.mv_inl((p))
  58 #define __outb(x,p)     sh_mv.mv_outb((x),(p))
  59 #define __outw(x,p)     sh_mv.mv_outw((x),(p))
  60 #define __outl(x,p)     sh_mv.mv_outl((x),(p))
  61
  62 #define __inb_p(p)      sh_mv.mv_inb_p((p))
  63 #define __inw_p(p)      sh_mv.mv_inw_p((p))
  64 #define __inl_p(p)      sh_mv.mv_inl_p((p))
  65 #define __outb_p(x,p)   sh_mv.mv_outb_p((x),(p))
  66 #define __outw_p(x,p)   sh_mv.mv_outw_p((x),(p))
  67 #define __outl_p(x,p)   sh_mv.mv_outl_p((x),(p))
  68
  69 #define __insb(p,b,c)   sh_mv.mv_insb((p), (b), (c))
  70 #define __insw(p,b,c)   sh_mv.mv_insw((p), (b), (c))
  71 #define __insl(p,b,c)   sh_mv.mv_insl((p), (b), (c))
  72 #define __outsb(p,b,c)  sh_mv.mv_outsb((p), (b), (c))
  73 #define __outsw(p,b,c)  sh_mv.mv_outsw((p), (b), (c))
  74 #define __outsl(p,b,c)  sh_mv.mv_outsl((p), (b), (c))
  75
  76 #define __readb(a)      sh_mv.mv_readb((a))
  77 #define __readw(a)      sh_mv.mv_readw((a))
  78 #define __readl(a)      sh_mv.mv_readl((a))
  79 #define __writeb(v,a)   sh_mv.mv_writeb((v),(a))
  80 #define __writew(v,a)   sh_mv.mv_writew((v),(a))
  81 #define __writel(v,a)   sh_mv.mv_writel((v),(a))
  82
  83 #define inb             __inb
  84 #define inw             __inw
  85 #define inl             __inl
  86 #define outb            __outb
  87 #define outw            __outw
  88 #define outl            __outl
  89
  90 #define inb_p           __inb_p
  91 #define inw_p           __inw_p
  92 #define inl_p           __inl_p
  93 #define outb_p          __outb_p
  94 #define outw_p          __outw_p
  95 #define outl_p          __outl_p
  96
  97 #define insb            __insb
  98 #define insw            __insw
  99 #define insl            __insl
 100 #define outsb           __outsb
 101 #define outsw           __outsw
 102 #define outsl           __outsl
 103
 104 #define __raw_readb(a)          __readb((void __iomem *)(a))
 105 #define __raw_readw(a)          __readw((void __iomem *)(a))
 106 #define __raw_readl(a)          __readl((void __iomem *)(a))
 107 #define __raw_writeb(v, a)      __writeb(v, (void __iomem *)(a))
 108 #define __raw_writew(v, a)      __writew(v, (void __iomem *)(a))
 109 #define __raw_writel(v, a)      __writel(v, (void __iomem *)(a))
 110
 111 /*
 112  * The platform header files may define some of these macros to use
 113  * the inlined versions where appropriate.  These macros may also be
 114  * redefined by userlevel programs.
 115  */
 116 #ifdef __readb
 117 # define readb(a)       ({ unsigned long r_ = __raw_readb(a); mb(); r_; })
 118 #endif
 119 #ifdef __raw_readw
 120 # define readw(a)       ({ unsigned long r_ = __raw_readw(a); mb(); r_; })
 121 #endif
 122 #ifdef __raw_readl
 123 # define readl(a)       ({ unsigned long r_ = __raw_readl(a); mb(); r_; })
 124 #endif
 125
 126 #ifdef __raw_writeb
 127 # define writeb(v,a)    ({ __raw_writeb((v),(a)); mb(); })
 128 #endif
 129 #ifdef __raw_writew
 130 # define writew(v,a)    ({ __raw_writew((v),(a)); mb(); })
 131 #endif
 132 #ifdef __raw_writel
 133 # define writel(v,a)    ({ __raw_writel((v),(a)); mb(); })
 134 #endif
 135
 136 #define readb_relaxed(a) readb(a)
 137 #define readw_relaxed(a) readw(a)
 138 #define readl_relaxed(a) readl(a)
 139
 140 /* Simple MMIO */
 141 #define ioread8(a)              readb(a)
 142 #define ioread16(a)             readw(a)
 143 #define ioread16be(a)           be16_to_cpu(__raw_readw((a)))
 144 #define ioread32(a)             readl(a)
 145 #define ioread32be(a)           be32_to_cpu(__raw_readl((a)))
 146
 147 #define iowrite8(v,a)           writeb((v),(a))
 148 #define iowrite16(v,a)          writew((v),(a))
 149 #define iowrite16be(v,a)        __raw_writew(cpu_to_be16((v)),(a))
 150 #define iowrite32(v,a)          writel((v),(a))
 151 #define iowrite32be(v,a)        __raw_writel(cpu_to_be32((v)),(a))
 152
 153 #define ioread8_rep(a,d,c)      insb((a),(d),(c))
 154 #define ioread16_rep(a,d,c)     insw((a),(d),(c))
 155 #define ioread32_rep(a,d,c)     insl((a),(d),(c))
 156
 157 #define iowrite8_rep(a,s,c)     outsb((a),(s),(c))
 158 #define iowrite16_rep(a,s,c)    outsw((a),(s),(c))
 159 #define iowrite32_rep(a,s,c)    outsl((a),(s),(c))
 160
 161 #define mmiowb()        wmb()   /* synco on SH-4A, otherwise a nop */
 162
 163 /*
 164  * This function provides a method for the generic case where a board-specific
 165  * ioport_map simply needs to return the port + some arbitrary port base.
 166  *
 167  * We use this at board setup time to implicitly set the port base, and
 168  * as a result, we can use the generic ioport_map.
 169  */
 170 static inline void __set_io_port_base(unsigned long pbase)
 171 {
 172         extern unsigned long generic_io_base;
 173
 174         generic_io_base = pbase;
 175 }
 176
 177 /* We really want to try and get these to memcpy etc */
 178 extern void memcpy_fromio(void *, volatile void __iomem *, unsigned long);
 179 extern void memcpy_toio(volatile void __iomem *, const void *, unsigned long);
 180 extern void memset_io(volatile void __iomem *, int, unsigned long);
 181
 182 /* SuperH on-chip I/O functions */
 183 static inline unsigned char ctrl_inb(unsigned long addr)
 184 {
 185         return *(volatile unsigned char*)addr;
 186 }
 187
 188 static inline unsigned short ctrl_inw(unsigned long addr)
 189 {
 190         return *(volatile unsigned short*)addr;
 191 }
 192
 193 static inline unsigned int ctrl_inl(unsigned long addr)
 194 {
 195         return *(volatile unsigned long*)addr;
 196 }
 197
 198 static inline void ctrl_outb(unsigned char b, unsigned long addr)
 199 {
 200         *(volatile unsigned char*)addr = b;
 201 }
 202
 203 static inline void ctrl_outw(unsigned short b, unsigned long addr)
 204 {
 205         *(volatile unsigned short*)addr = b;
 206 }
 207
 208 static inline void ctrl_outl(unsigned int b, unsigned long addr)
 209 {
 210         *(volatile unsigned long*)addr = b;
 211 }
 212
 213 #define IO_SPACE_LIMIT 0xffffffff
 214
 215 /*
 216  * Change virtual addresses to physical addresses and vv.
 217  * These are trivial on the 1:1 Linux/SuperH mapping
 218  */
 219 static inline unsigned long virt_to_phys(volatile void *address)
 220 {
 221         return PHYSADDR(address);
 222 }
 223
 224 static inline void *phys_to_virt(unsigned long address)
 225 {
 226         return (void *)P1SEGADDR(address);
 227 }
 228
 229 #define virt_to_bus virt_to_phys
 230 #define bus_to_virt phys_to_virt
 231 #define page_to_bus page_to_phys
 232
 233 /*
 234  * readX/writeX() are used to access memory mapped devices. On some
 235  * architectures the memory mapped IO stuff needs to be accessed
 236  * differently. On the x86 architecture, we just read/write the
 237  * memory location directly.
 238  *
 239  * On SH, we traditionally have the whole physical address space mapped
 240  * at all times (as MIPS does), so "ioremap()" and "iounmap()" do not
 241  * need to do anything but place the address in the proper segment. This
 242  * is true for P1 and P2 addresses, as well as some P3 ones. However,
 243  * most of the P3 addresses and newer cores using extended addressing
 244  * need to map through page tables, so the ioremap() implementation
 245  * becomes a bit more complicated. See arch/sh/mm/ioremap.c for
 246  * additional notes on this.
 247  *
 248  * We cheat a bit and always return uncachable areas until we've fixed
 249  * the drivers to handle caching properly.
 250  */
 251 #ifdef CONFIG_MMU
 252 void __iomem *__ioremap(unsigned long offset, unsigned long size,
 253                         unsigned long flags);
 254 void __iounmap(void __iomem *addr);
 255 #else
 256 #define __ioremap(offset, size, flags)  ((void __iomem *)(offset))
 257 #define __iounmap(addr)                 do { } while (0)
 258 #endif /* CONFIG_MMU */
 259
 260 static inline void __iomem *
 261 __ioremap_mode(unsigned long offset, unsigned long size, unsigned long flags)
 262 {
 263         unsigned long last_addr = offset + size - 1;
 264
 265         /*
 266          * For P1 and P2 space this is trivial, as everything is already
 267          * mapped. Uncached access for P1 addresses are done through P2.
 268          * In the P3 case or for addresses outside of the 29-bit space,
 269          * mapping must be done by the PMB or by using page tables.
 270          */
 271         if (likely(PXSEG(offset) < P3SEG && PXSEG(last_addr) < P3SEG)) {
 272                 if (unlikely(flags & _PAGE_CACHABLE))
 273                         return (void __iomem *)P1SEGADDR(offset);
 274
 275                 return (void __iomem *)P2SEGADDR(offset);
 276         }
 277
 278         return __ioremap(offset, size, flags);
 279 }
 280
 281 #define ioremap(offset, size)                           \
 282         __ioremap_mode((offset), (size), 0)
 283 #define ioremap_nocache(offset, size)                   \
 284         __ioremap_mode((offset), (size), 0)
 285 #define ioremap_cache(offset, size)                     \
 286         __ioremap_mode((offset), (size), _PAGE_CACHABLE)
 287 #define p3_ioremap(offset, size, flags)                 \
 288         __ioremap((offset), (size), (flags))
 289 #define iounmap(addr)                                   \
 290         __iounmap((addr))
 291
 292 static inline int check_signature(char __iomem *io_addr,
 293                         const unsigned char *signature, int length)
 294 {
 295         int retval = 0;
 296         do {
 297                 if (readb(io_addr) != *signature)
 298                         goto out;
 299                 io_addr++;
 300                 signature++;
 301                 length--;
 302         } while (length);
 303         retval = 1;
 304 out:
 305         return retval;
 306 }
 307
 308 /*
 309  * The caches on some architectures aren't dma-coherent and have need to
 310  * handle this in software.  There are three types of operations that
 311  * can be applied to dma buffers.
 312  *
 313  *  - dma_cache_wback_inv(start, size) makes caches and RAM coherent by
 314  *    writing the content of the caches back to memory, if necessary.
 315  *    The function also invalidates the affected part of the caches as
 316  *    necessary before DMA transfers from outside to memory.
 317  *  - dma_cache_inv(start, size) invalidates the affected parts of the
 318  *    caches.  Dirty lines of the caches may be written back or simply
 319  *    be discarded.  This operation is necessary before dma operations
 320  *    to the memory.
 321  *  - dma_cache_wback(start, size) writes back any dirty lines but does
 322  *    not invalidate the cache.  This can be used before DMA reads from
 323  *    memory,
 324  */
 325
 326 #define dma_cache_wback_inv(_start,_size) \
 327     __flush_purge_region(_start,_size)
 328 #define dma_cache_inv(_start,_size) \
 329     __flush_invalidate_region(_start,_size)
 330 #define dma_cache_wback(_start,_size) \
 331     __flush_wback_region(_start,_size)
 332
 333 /*
 334  * Convert a physical pointer to a virtual kernel pointer for /dev/mem
 335  * access
 336  */
 337 #define xlate_dev_mem_ptr(p)    __va(p)
 338
 339 /*
 340  * Convert a virtual cached pointer to an uncached pointer
 341  */
 342 #define xlate_dev_kmem_ptr(p)   p
 343
 344 #endif /* __KERNEL__ */
 345
 346 #endif /* __ASM_SH_IO_H */