| blob | 04b66a9328ef8fbeeb51d7eed141b1cc0f1353ff |
1 /*
2 * linux/arch/arm/kernel/head.S
3 *
4 * Copyright (C) 1994-2002 Russell King
5 * Copyright (c) 2003 ARM Limited
6 * All Rights Reserved
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Kernel startup code for all 32-bit CPUs
13 */
14 #include <linux/config.h>
15 #include <linux/linkage.h>
16 #include <linux/init.h>
18 #include <asm/assembler.h>
19 #include <asm/domain.h>
20 #include <asm/procinfo.h>
21 #include <asm/ptrace.h>
22 #include <asm/asm-offsets.h>
23 #include <asm/memory.h>
24 #include <asm/thread_info.h>
25 #include <asm/system.h>
27 #define PROCINFO_MMUFLAGS 8
28 #define PROCINFO_INITFUNC 12
30 #define MACHINFO_TYPE 0
31 #define MACHINFO_PHYSIO 4
32 #define MACHINFO_PGOFFIO 8
33 #define MACHINFO_NAME 12
35 #define KERNEL_RAM_ADDR (PAGE_OFFSET + TEXT_OFFSET)
37 /*
38 * swapper_pg_dir is the virtual address of the initial page table.
39 * We place the page tables 16K below KERNEL_RAM_ADDR. Therefore, we must
40 * make sure that KERNEL_RAM_ADDR is correctly set. Currently, we expect
41 * the least significant 16 bits to be 0x8000, but we could probably
42 * relax this restriction to KERNEL_RAM_ADDR >= PAGE_OFFSET + 0x4000.
43 */
44 #if (KERNEL_RAM_ADDR & 0xffff) != 0x8000
45 #error KERNEL_RAM_ADDR must start at 0xXXXX8000
46 #endif
48 .globl swapper_pg_dir
49 .equ swapper_pg_dir, KERNEL_RAM_ADDR - 0x4000
51 .macro pgtbl, rd
52 ldr \rd, =(__virt_to_phys(KERNEL_RAM_ADDR - 0x4000))
53 .endm
55 #ifdef CONFIG_XIP_KERNEL
56 #define TEXTADDR XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR)
57 #else
58 #define TEXTADDR KERNEL_RAM_ADDR
59 #endif
61 /*
62 * Kernel startup entry point.
63 * ---------------------------
64 *
65 * This is normally called from the decompressor code. The requirements
66 * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0,
67 * r1 = machine nr.
68 *
69 * This code is mostly position independent, so if you link the kernel at
70 * 0xc0008000, you call this at __pa(0xc0008000).
71 *
72 * See linux/arch/arm/tools/mach-types for the complete list of machine
73 * numbers for r1.
74 *
75 * We're trying to keep crap to a minimum; DO NOT add any machine specific
76 * crap here - that's what the boot loader (or in extreme, well justified
77 * circumstances, zImage) is for.
78 */
79 __INIT
80 .type stext, %function
81 ENTRY(stext)
82 msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | MODE_SVC @ ensure svc mode
83 @ and irqs disabled
84 mrc p15, 0, r9, c0, c0 @ get processor id
85 bl __lookup_processor_type @ r5=procinfo r9=cpuid
86 movs r10, r5 @ invalid processor (r5=0)?
87 beq __error_p @ yes, error 'p'
88 bl __lookup_machine_type @ r5=machinfo
89 movs r8, r5 @ invalid machine (r5=0)?
90 beq __error_a @ yes, error 'a'
91 bl __create_page_tables
93 /*
94 * The following calls CPU specific code in a position independent
95 * manner. See arch/arm/mm/proc-*.S for details. r10 = base of
96 * xxx_proc_info structure selected by __lookup_machine_type
97 * above. On return, the CPU will be ready for the MMU to be
98 * turned on, and r0 will hold the CPU control register value.
99 */
100 ldr r13, __switch_data @ address to jump to after
101 @ mmu has been enabled
102 adr lr, __enable_mmu @ return (PIC) address
103 add pc, r10, #PROCINFO_INITFUNC
105 #if defined(CONFIG_SMP)
106 .type secondary_startup, #function
107 ENTRY(secondary_startup)
108 /*
109 * Common entry point for secondary CPUs.
110 *
111 * Ensure that we're in SVC mode, and IRQs are disabled. Lookup
112 * the processor type - there is no need to check the machine type
113 * as it has already been validated by the primary processor.
114 */
115 msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | MODE_SVC
116 mrc p15, 0, r9, c0, c0 @ get processor id
117 bl __lookup_processor_type
118 movs r10, r5 @ invalid processor?
119 moveq r0, #'p' @ yes, error 'p'
120 beq __error
122 /*
123 * Use the page tables supplied from __cpu_up.
124 */
125 adr r4, __secondary_data
126 ldmia r4, {r5, r6, r13} @ address to jump to after
127 sub r4, r4, r5 @ mmu has been enabled
128 ldr r4, [r6, r4] @ get secondary_data.pgdir
129 adr lr, __enable_mmu @ return address
130 add pc, r10, #12 @ initialise processor
131 @ (return control reg)
133 /*
134 * r6 = &secondary_data
135 */
136 ENTRY(__secondary_switched)
137 ldr sp, [r6, #4] @ get secondary_data.stack
138 mov fp, #0
139 b secondary_start_kernel
141 .type __secondary_data, %object
142 __secondary_data:
143 .long .
144 .long secondary_data
145 .long __secondary_switched
146 #endif /* defined(CONFIG_SMP) */
150 /*
151 * Setup common bits before finally enabling the MMU. Essentially
152 * this is just loading the page table pointer and domain access
153 * registers.
154 */
155 .type __enable_mmu, %function
156 __enable_mmu:
157 #ifdef CONFIG_ALIGNMENT_TRAP
158 orr r0, r0, #CR_A
159 #else
160 bic r0, r0, #CR_A
161 #endif
162 #ifdef CONFIG_CPU_DCACHE_DISABLE
163 bic r0, r0, #CR_C
164 #endif
165 #ifdef CONFIG_CPU_BPREDICT_DISABLE
166 bic r0, r0, #CR_Z
167 #endif
168 #ifdef CONFIG_CPU_ICACHE_DISABLE
169 bic r0, r0, #CR_I
170 #endif
171 mov r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \
172 domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \
173 domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \
174 domain_val(DOMAIN_IO, DOMAIN_CLIENT))
175 mcr p15, 0, r5, c3, c0, 0 @ load domain access register
176 mcr p15, 0, r4, c2, c0, 0 @ load page table pointer
177 b __turn_mmu_on
179 /*
180 * Enable the MMU. This completely changes the structure of the visible
181 * memory space. You will not be able to trace execution through this.
182 * If you have an enquiry about this, *please* check the linux-arm-kernel
183 * mailing list archives BEFORE sending another post to the list.
184 *
185 * r0 = cp#15 control register
186 * r13 = *virtual* address to jump to upon completion
187 *
188 * other registers depend on the function called upon completion
189 */
190 .align 5
191 .type __turn_mmu_on, %function
192 __turn_mmu_on:
193 mov r0, r0
194 mcr p15, 0, r0, c1, c0, 0 @ write control reg
195 mrc p15, 0, r3, c0, c0, 0 @ read id reg
196 mov r3, r3
197 mov r3, r3
198 mov pc, r13
202 /*
203 * Setup the initial page tables. We only setup the barest
204 * amount which are required to get the kernel running, which
205 * generally means mapping in the kernel code.
206 *
207 * r8 = machinfo
208 * r9 = cpuid
209 * r10 = procinfo
210 *
211 * Returns:
212 * r0, r3, r6, r7 corrupted
213 * r4 = physical page table address
214 */
215 .type __create_page_tables, %function
216 __create_page_tables:
217 pgtbl r4 @ page table address
219 /*
220 * Clear the 16K level 1 swapper page table
221 */
222 mov r0, r4
223 mov r3, #0
224 add r6, r0, #0x4000
225 1: str r3, [r0], #4
226 str r3, [r0], #4
227 str r3, [r0], #4
228 str r3, [r0], #4
229 teq r0, r6
230 bne 1b
232 ldr r7, [r10, #PROCINFO_MMUFLAGS] @ mmuflags
234 /*
235 * Create identity mapping for first MB of kernel to
236 * cater for the MMU enable. This identity mapping
237 * will be removed by paging_init(). We use our current program
238 * counter to determine corresponding section base address.
239 */
240 mov r6, pc, lsr #20 @ start of kernel section
241 orr r3, r7, r6, lsl #20 @ flags + kernel base
242 str r3, [r4, r6, lsl #2] @ identity mapping
244 /*
245 * Now setup the pagetables for our kernel direct
246 * mapped region. We round TEXTADDR down to the
247 * nearest megabyte boundary. It is assumed that
248 * the kernel fits within 4 contigous 1MB sections.
249 */
250 add r0, r4, #(TEXTADDR & 0xff000000) >> 18 @ start of kernel
251 str r3, [r0, #(TEXTADDR & 0x00f00000) >> 18]!
252 add r3, r3, #1 << 20
253 str r3, [r0, #4]! @ KERNEL + 1MB
254 add r3, r3, #1 << 20
255 str r3, [r0, #4]! @ KERNEL + 2MB
256 add r3, r3, #1 << 20
257 str r3, [r0, #4] @ KERNEL + 3MB
259 /*
260 * Then map first 1MB of ram in case it contains our boot params.
261 */
262 add r0, r4, #PAGE_OFFSET >> 18
263 orr r6, r7, #PHYS_OFFSET
264 str r6, [r0]
266 #ifdef CONFIG_XIP_KERNEL
267 /*
268 * Map some ram to cover our .data and .bss areas.
269 * Mapping 3MB should be plenty.
270 */
271 sub r3, r4, #PHYS_OFFSET
272 mov r3, r3, lsr #20
273 add r0, r0, r3, lsl #2
274 add r6, r6, r3, lsl #20
275 str r6, [r0], #4
276 add r6, r6, #(1 << 20)
277 str r6, [r0], #4
278 add r6, r6, #(1 << 20)
279 str r6, [r0]
280 #endif
282 #ifdef CONFIG_DEBUG_LL
283 bic r7, r7, #0x0c @ turn off cacheable
284 @ and bufferable bits
285 /*
286 * Map in IO space for serial debugging.
287 * This allows debug messages to be output
288 * via a serial console before paging_init.
289 */
290 ldr r3, [r8, #MACHINFO_PGOFFIO]
291 add r0, r4, r3
292 rsb r3, r3, #0x4000 @ PTRS_PER_PGD*sizeof(long)
293 cmp r3, #0x0800 @ limit to 512MB
294 movhi r3, #0x0800
295 add r6, r0, r3
296 ldr r3, [r8, #MACHINFO_PHYSIO]
297 orr r3, r3, r7
298 1: str r3, [r0], #4
299 add r3, r3, #1 << 20
300 teq r0, r6
301 bne 1b
302 #if defined(CONFIG_ARCH_NETWINDER) || defined(CONFIG_ARCH_CATS)
303 /*
304 * If we're using the NetWinder or CATS, we also need to map
305 * in the 16550-type serial port for the debug messages
306 */
307 add r0, r4, #0xff000000 >> 18
308 orr r3, r7, #0x7c000000
309 str r3, [r0]
310 #endif
311 #ifdef CONFIG_ARCH_RPC
312 /*
313 * Map in screen at 0x02000000 & SCREEN2_BASE
314 * Similar reasons here - for debug. This is
315 * only for Acorn RiscPC architectures.
316 */
317 add r0, r4, #0x02000000 >> 18
318 orr r3, r7, #0x02000000
319 str r3, [r0]
320 add r0, r4, #0xd8000000 >> 18
321 str r3, [r0]
322 #endif
323 #endif
324 mov pc, lr
325 .ltorg
327 #include "head-common.S"