2 * $Id: pci.c,v 1.91 1999/01/21 13:34:01 davem Exp $
4 * PCI Bus Services, see include/linux/pci.h for further explanation.
6 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
9 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
12 #include <linux/kernel.h>
13 #include <linux/delay.h>
14 #include <linux/init.h>
15 #include <linux/pci.h>
16 #include <linux/module.h>
17 #include <linux/spinlock.h>
18 #include <asm/dma.h> /* isa_dma_bridge_buggy */
23 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
24 * @bus: pointer to PCI bus structure to search
26 * Given a PCI bus, returns the highest PCI bus number present in the set
27 * including the given PCI bus and its list of child PCI buses.
29 unsigned char __devinit
30 pci_bus_max_busnr(struct pci_bus
* bus
)
32 struct list_head
*tmp
;
36 list_for_each(tmp
, &bus
->children
) {
37 n
= pci_bus_max_busnr(pci_bus_b(tmp
));
45 * pci_max_busnr - returns maximum PCI bus number
47 * Returns the highest PCI bus number present in the system global list of
50 unsigned char __devinit
53 struct pci_bus
*bus
= NULL
;
57 while ((bus
= pci_find_next_bus(bus
)) != NULL
) {
58 n
= pci_bus_max_busnr(bus
);
65 static int __pci_bus_find_cap(struct pci_bus
*bus
, unsigned int devfn
, u8 hdr_type
, int cap
)
71 pci_bus_read_config_word(bus
, devfn
, PCI_STATUS
, &status
);
72 if (!(status
& PCI_STATUS_CAP_LIST
))
76 case PCI_HEADER_TYPE_NORMAL
:
77 case PCI_HEADER_TYPE_BRIDGE
:
78 pci_bus_read_config_byte(bus
, devfn
, PCI_CAPABILITY_LIST
, &pos
);
80 case PCI_HEADER_TYPE_CARDBUS
:
81 pci_bus_read_config_byte(bus
, devfn
, PCI_CB_CAPABILITY_LIST
, &pos
);
86 while (ttl
-- && pos
>= 0x40) {
88 pci_bus_read_config_byte(bus
, devfn
, pos
+ PCI_CAP_LIST_ID
, &id
);
93 pci_bus_read_config_byte(bus
, devfn
, pos
+ PCI_CAP_LIST_NEXT
, &pos
);
99 * pci_find_capability - query for devices' capabilities
100 * @dev: PCI device to query
101 * @cap: capability code
103 * Tell if a device supports a given PCI capability.
104 * Returns the address of the requested capability structure within the
105 * device's PCI configuration space or 0 in case the device does not
106 * support it. Possible values for @cap:
108 * %PCI_CAP_ID_PM Power Management
109 * %PCI_CAP_ID_AGP Accelerated Graphics Port
110 * %PCI_CAP_ID_VPD Vital Product Data
111 * %PCI_CAP_ID_SLOTID Slot Identification
112 * %PCI_CAP_ID_MSI Message Signalled Interrupts
113 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
114 * %PCI_CAP_ID_PCIX PCI-X
115 * %PCI_CAP_ID_EXP PCI Express
117 int pci_find_capability(struct pci_dev
*dev
, int cap
)
119 return __pci_bus_find_cap(dev
->bus
, dev
->devfn
, dev
->hdr_type
, cap
);
123 * pci_bus_find_capability - query for devices' capabilities
124 * @bus: the PCI bus to query
125 * @devfn: PCI device to query
126 * @cap: capability code
128 * Like pci_find_capability() but works for pci devices that do not have a
129 * pci_dev structure set up yet.
131 * Returns the address of the requested capability structure within the
132 * device's PCI configuration space or 0 in case the device does not
135 int pci_bus_find_capability(struct pci_bus
*bus
, unsigned int devfn
, int cap
)
139 pci_bus_read_config_byte(bus
, devfn
, PCI_HEADER_TYPE
, &hdr_type
);
141 return __pci_bus_find_cap(bus
, devfn
, hdr_type
& 0x7f, cap
);
145 * pci_find_ext_capability - Find an extended capability
146 * @dev: PCI device to query
147 * @cap: capability code
149 * Returns the address of the requested extended capability structure
150 * within the device's PCI configuration space or 0 if the device does
151 * not support it. Possible values for @cap:
153 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
154 * %PCI_EXT_CAP_ID_VC Virtual Channel
155 * %PCI_EXT_CAP_ID_DSN Device Serial Number
156 * %PCI_EXT_CAP_ID_PWR Power Budgeting
158 int pci_find_ext_capability(struct pci_dev
*dev
, int cap
)
161 int ttl
= 480; /* 3840 bytes, minimum 8 bytes per capability */
164 if (dev
->cfg_size
<= 256)
167 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
171 * If we have no capabilities, this is indicated by cap ID,
172 * cap version and next pointer all being 0.
178 if (PCI_EXT_CAP_ID(header
) == cap
)
181 pos
= PCI_EXT_CAP_NEXT(header
);
185 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
193 * pci_find_parent_resource - return resource region of parent bus of given region
194 * @dev: PCI device structure contains resources to be searched
195 * @res: child resource record for which parent is sought
197 * For given resource region of given device, return the resource
198 * region of parent bus the given region is contained in or where
199 * it should be allocated from.
202 pci_find_parent_resource(const struct pci_dev
*dev
, struct resource
*res
)
204 const struct pci_bus
*bus
= dev
->bus
;
206 struct resource
*best
= NULL
;
208 for(i
= 0; i
< PCI_BUS_NUM_RESOURCES
; i
++) {
209 struct resource
*r
= bus
->resource
[i
];
212 if (res
->start
&& !(res
->start
>= r
->start
&& res
->end
<= r
->end
))
213 continue; /* Not contained */
214 if ((res
->flags
^ r
->flags
) & (IORESOURCE_IO
| IORESOURCE_MEM
))
215 continue; /* Wrong type */
216 if (!((res
->flags
^ r
->flags
) & IORESOURCE_PREFETCH
))
217 return r
; /* Exact match */
218 if ((res
->flags
& IORESOURCE_PREFETCH
) && !(r
->flags
& IORESOURCE_PREFETCH
))
219 best
= r
; /* Approximating prefetchable by non-prefetchable */
225 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
226 * @dev: PCI device to have its BARs restored
228 * Restore the BAR values for a given device, so as to make it
229 * accessible by its driver.
232 pci_restore_bars(struct pci_dev
*dev
)
236 switch (dev
->hdr_type
) {
237 case PCI_HEADER_TYPE_NORMAL
:
240 case PCI_HEADER_TYPE_BRIDGE
:
243 case PCI_HEADER_TYPE_CARDBUS
:
247 /* Should never get here, but just in case... */
251 for (i
= 0; i
< numres
; i
++)
252 pci_update_resource(dev
, &dev
->resource
[i
], i
);
256 * pci_set_power_state - Set the power state of a PCI device
257 * @dev: PCI device to be suspended
258 * @state: PCI power state (D0, D1, D2, D3hot, D3cold) we're entering
260 * Transition a device to a new power state, using the Power Management
261 * Capabilities in the device's config space.
264 * -EINVAL if trying to enter a lower state than we're already in.
265 * 0 if we're already in the requested state.
266 * -EIO if device does not support PCI PM.
267 * 0 if we can successfully change the power state.
269 int (*platform_pci_set_power_state
)(struct pci_dev
*dev
, pci_power_t t
);
271 pci_set_power_state(struct pci_dev
*dev
, pci_power_t state
)
273 int pm
, need_restore
= 0;
276 /* bound the state we're entering */
277 if (state
> PCI_D3hot
)
280 /* Validate current state:
281 * Can enter D0 from any state, but if we can only go deeper
282 * to sleep if we're already in a low power state
284 if (state
!= PCI_D0
&& dev
->current_state
> state
)
286 else if (dev
->current_state
== state
)
287 return 0; /* we're already there */
289 /* find PCI PM capability in list */
290 pm
= pci_find_capability(dev
, PCI_CAP_ID_PM
);
292 /* abort if the device doesn't support PM capabilities */
296 pci_read_config_word(dev
,pm
+ PCI_PM_PMC
,&pmc
);
297 if ((pmc
& PCI_PM_CAP_VER_MASK
) > 3) {
299 "PCI: %s has unsupported PM cap regs version (%u)\n",
300 pci_name(dev
), pmc
& PCI_PM_CAP_VER_MASK
);
304 /* check if this device supports the desired state */
305 if (state
== PCI_D1
&& !(pmc
& PCI_PM_CAP_D1
))
307 else if (state
== PCI_D2
&& !(pmc
& PCI_PM_CAP_D2
))
310 pci_read_config_word(dev
, pm
+ PCI_PM_CTRL
, &pmcsr
);
312 /* If we're (effectively) in D3, force entire word to 0.
313 * This doesn't affect PME_Status, disables PME_En, and
314 * sets PowerState to 0.
316 switch (dev
->current_state
) {
317 case PCI_UNKNOWN
: /* Boot-up */
318 if ((pmcsr
& PCI_PM_CTRL_STATE_MASK
) == PCI_D3hot
319 && !(pmcsr
& PCI_PM_CTRL_NO_SOFT_RESET
))
321 /* Fall-through: force to D0 */
324 case PCI_POWER_ERROR
:
328 pmcsr
&= ~PCI_PM_CTRL_STATE_MASK
;
333 /* enter specified state */
334 pci_write_config_word(dev
, pm
+ PCI_PM_CTRL
, pmcsr
);
336 /* Mandatory power management transition delays */
337 /* see PCI PM 1.1 5.6.1 table 18 */
338 if (state
== PCI_D3hot
|| dev
->current_state
== PCI_D3hot
)
340 else if (state
== PCI_D2
|| dev
->current_state
== PCI_D2
)
344 * Give firmware a chance to be called, such as ACPI _PRx, _PSx
345 * Firmware method after natice method ?
347 if (platform_pci_set_power_state
)
348 platform_pci_set_power_state(dev
, state
);
350 dev
->current_state
= state
;
352 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
353 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
354 * from D3hot to D0 _may_ perform an internal reset, thereby
355 * going to "D0 Uninitialized" rather than "D0 Initialized".
356 * For example, at least some versions of the 3c905B and the
357 * 3c556B exhibit this behaviour.
359 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
360 * devices in a D3hot state at boot. Consequently, we need to
361 * restore at least the BARs so that the device will be
362 * accessible to its driver.
365 pci_restore_bars(dev
);
370 int (*platform_pci_choose_state
)(struct pci_dev
*dev
, pm_message_t state
);
373 * pci_choose_state - Choose the power state of a PCI device
374 * @dev: PCI device to be suspended
375 * @state: target sleep state for the whole system. This is the value
376 * that is passed to suspend() function.
378 * Returns PCI power state suitable for given device and given system
382 pci_power_t
pci_choose_state(struct pci_dev
*dev
, pm_message_t state
)
386 if (!pci_find_capability(dev
, PCI_CAP_ID_PM
))
389 if (platform_pci_choose_state
) {
390 ret
= platform_pci_choose_state(dev
, state
);
395 switch (state
.event
) {
398 case PM_EVENT_FREEZE
:
399 case PM_EVENT_SUSPEND
:
402 printk("They asked me for state %d\n", state
.event
);
408 EXPORT_SYMBOL(pci_choose_state
);
411 * pci_save_state - save the PCI configuration space of a device before suspending
412 * @dev: - PCI device that we're dealing with
415 pci_save_state(struct pci_dev
*dev
)
418 /* XXX: 100% dword access ok here? */
419 for (i
= 0; i
< 16; i
++)
420 pci_read_config_dword(dev
, i
* 4,&dev
->saved_config_space
[i
]);
425 * pci_restore_state - Restore the saved state of a PCI device
426 * @dev: - PCI device that we're dealing with
429 pci_restore_state(struct pci_dev
*dev
)
433 for (i
= 0; i
< 16; i
++)
434 pci_write_config_dword(dev
,i
* 4, dev
->saved_config_space
[i
]);
439 * pci_enable_device_bars - Initialize some of a device for use
440 * @dev: PCI device to be initialized
441 * @bars: bitmask of BAR's that must be configured
443 * Initialize device before it's used by a driver. Ask low-level code
444 * to enable selected I/O and memory resources. Wake up the device if it
445 * was suspended. Beware, this function can fail.
449 pci_enable_device_bars(struct pci_dev
*dev
, int bars
)
453 err
= pci_set_power_state(dev
, PCI_D0
);
454 if (err
< 0 && err
!= -EIO
)
456 err
= pcibios_enable_device(dev
, bars
);
463 * pci_enable_device - Initialize device before it's used by a driver.
464 * @dev: PCI device to be initialized
466 * Initialize device before it's used by a driver. Ask low-level code
467 * to enable I/O and memory. Wake up the device if it was suspended.
468 * Beware, this function can fail.
471 pci_enable_device(struct pci_dev
*dev
)
475 if ((err
= pci_enable_device_bars(dev
, (1 << PCI_NUM_RESOURCES
) - 1)))
477 pci_fixup_device(pci_fixup_enable
, dev
);
483 * pcibios_disable_device - disable arch specific PCI resources for device dev
484 * @dev: the PCI device to disable
486 * Disables architecture specific PCI resources for the device. This
487 * is the default implementation. Architecture implementations can
490 void __attribute__ ((weak
)) pcibios_disable_device (struct pci_dev
*dev
) {}
493 * pci_disable_device - Disable PCI device after use
494 * @dev: PCI device to be disabled
496 * Signal to the system that the PCI device is not in use by the system
497 * anymore. This only involves disabling PCI bus-mastering, if active.
500 pci_disable_device(struct pci_dev
*dev
)
504 pci_read_config_word(dev
, PCI_COMMAND
, &pci_command
);
505 if (pci_command
& PCI_COMMAND_MASTER
) {
506 pci_command
&= ~PCI_COMMAND_MASTER
;
507 pci_write_config_word(dev
, PCI_COMMAND
, pci_command
);
509 dev
->is_busmaster
= 0;
511 pcibios_disable_device(dev
);
516 * pci_enable_wake - enable device to generate PME# when suspended
517 * @dev: - PCI device to operate on
518 * @state: - Current state of device.
519 * @enable: - Flag to enable or disable generation
521 * Set the bits in the device's PM Capabilities to generate PME# when
522 * the system is suspended.
524 * -EIO is returned if device doesn't have PM Capabilities.
525 * -EINVAL is returned if device supports it, but can't generate wake events.
526 * 0 if operation is successful.
529 int pci_enable_wake(struct pci_dev
*dev
, pci_power_t state
, int enable
)
534 /* find PCI PM capability in list */
535 pm
= pci_find_capability(dev
, PCI_CAP_ID_PM
);
537 /* If device doesn't support PM Capabilities, but request is to disable
538 * wake events, it's a nop; otherwise fail */
540 return enable
? -EIO
: 0;
542 /* Check device's ability to generate PME# */
543 pci_read_config_word(dev
,pm
+PCI_PM_PMC
,&value
);
545 value
&= PCI_PM_CAP_PME_MASK
;
546 value
>>= ffs(PCI_PM_CAP_PME_MASK
) - 1; /* First bit of mask */
548 /* Check if it can generate PME# from requested state. */
549 if (!value
|| !(value
& (1 << state
)))
550 return enable
? -EINVAL
: 0;
552 pci_read_config_word(dev
, pm
+ PCI_PM_CTRL
, &value
);
554 /* Clear PME_Status by writing 1 to it and enable PME# */
555 value
|= PCI_PM_CTRL_PME_STATUS
| PCI_PM_CTRL_PME_ENABLE
;
558 value
&= ~PCI_PM_CTRL_PME_ENABLE
;
560 pci_write_config_word(dev
, pm
+ PCI_PM_CTRL
, value
);
566 pci_get_interrupt_pin(struct pci_dev
*dev
, struct pci_dev
**bridge
)
570 pci_read_config_byte(dev
, PCI_INTERRUPT_PIN
, &pin
);
574 while (dev
->bus
->self
) {
575 pin
= (pin
+ PCI_SLOT(dev
->devfn
)) % 4;
576 dev
= dev
->bus
->self
;
583 * pci_release_region - Release a PCI bar
584 * @pdev: PCI device whose resources were previously reserved by pci_request_region
585 * @bar: BAR to release
587 * Releases the PCI I/O and memory resources previously reserved by a
588 * successful call to pci_request_region. Call this function only
589 * after all use of the PCI regions has ceased.
591 void pci_release_region(struct pci_dev
*pdev
, int bar
)
593 if (pci_resource_len(pdev
, bar
) == 0)
595 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
)
596 release_region(pci_resource_start(pdev
, bar
),
597 pci_resource_len(pdev
, bar
));
598 else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
)
599 release_mem_region(pci_resource_start(pdev
, bar
),
600 pci_resource_len(pdev
, bar
));
604 * pci_request_region - Reserved PCI I/O and memory resource
605 * @pdev: PCI device whose resources are to be reserved
606 * @bar: BAR to be reserved
607 * @res_name: Name to be associated with resource.
609 * Mark the PCI region associated with PCI device @pdev BR @bar as
610 * being reserved by owner @res_name. Do not access any
611 * address inside the PCI regions unless this call returns
614 * Returns 0 on success, or %EBUSY on error. A warning
615 * message is also printed on failure.
617 int pci_request_region(struct pci_dev
*pdev
, int bar
, char *res_name
)
619 if (pci_resource_len(pdev
, bar
) == 0)
622 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
) {
623 if (!request_region(pci_resource_start(pdev
, bar
),
624 pci_resource_len(pdev
, bar
), res_name
))
627 else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
) {
628 if (!request_mem_region(pci_resource_start(pdev
, bar
),
629 pci_resource_len(pdev
, bar
), res_name
))
636 printk (KERN_WARNING
"PCI: Unable to reserve %s region #%d:%lx@%lx for device %s\n",
637 pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
? "I/O" : "mem",
638 bar
+ 1, /* PCI BAR # */
639 pci_resource_len(pdev
, bar
), pci_resource_start(pdev
, bar
),
646 * pci_release_regions - Release reserved PCI I/O and memory resources
647 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
649 * Releases all PCI I/O and memory resources previously reserved by a
650 * successful call to pci_request_regions. Call this function only
651 * after all use of the PCI regions has ceased.
654 void pci_release_regions(struct pci_dev
*pdev
)
658 for (i
= 0; i
< 6; i
++)
659 pci_release_region(pdev
, i
);
663 * pci_request_regions - Reserved PCI I/O and memory resources
664 * @pdev: PCI device whose resources are to be reserved
665 * @res_name: Name to be associated with resource.
667 * Mark all PCI regions associated with PCI device @pdev as
668 * being reserved by owner @res_name. Do not access any
669 * address inside the PCI regions unless this call returns
672 * Returns 0 on success, or %EBUSY on error. A warning
673 * message is also printed on failure.
675 int pci_request_regions(struct pci_dev
*pdev
, char *res_name
)
679 for (i
= 0; i
< 6; i
++)
680 if(pci_request_region(pdev
, i
, res_name
))
686 pci_release_region(pdev
, i
);
692 * pci_set_master - enables bus-mastering for device dev
693 * @dev: the PCI device to enable
695 * Enables bus-mastering on the device and calls pcibios_set_master()
696 * to do the needed arch specific settings.
699 pci_set_master(struct pci_dev
*dev
)
703 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
704 if (! (cmd
& PCI_COMMAND_MASTER
)) {
705 pr_debug("PCI: Enabling bus mastering for device %s\n", pci_name(dev
));
706 cmd
|= PCI_COMMAND_MASTER
;
707 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
709 dev
->is_busmaster
= 1;
710 pcibios_set_master(dev
);
713 #ifndef HAVE_ARCH_PCI_MWI
714 /* This can be overridden by arch code. */
715 u8 pci_cache_line_size
= L1_CACHE_BYTES
>> 2;
718 * pci_generic_prep_mwi - helper function for pci_set_mwi
719 * @dev: the PCI device for which MWI is enabled
721 * Helper function for generic implementation of pcibios_prep_mwi
722 * function. Originally copied from drivers/net/acenic.c.
723 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
725 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
728 pci_generic_prep_mwi(struct pci_dev
*dev
)
732 if (!pci_cache_line_size
)
733 return -EINVAL
; /* The system doesn't support MWI. */
735 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
736 equal to or multiple of the right value. */
737 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
738 if (cacheline_size
>= pci_cache_line_size
&&
739 (cacheline_size
% pci_cache_line_size
) == 0)
742 /* Write the correct value. */
743 pci_write_config_byte(dev
, PCI_CACHE_LINE_SIZE
, pci_cache_line_size
);
745 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
746 if (cacheline_size
== pci_cache_line_size
)
749 printk(KERN_DEBUG
"PCI: cache line size of %d is not supported "
750 "by device %s\n", pci_cache_line_size
<< 2, pci_name(dev
));
754 #endif /* !HAVE_ARCH_PCI_MWI */
757 * pci_set_mwi - enables memory-write-invalidate PCI transaction
758 * @dev: the PCI device for which MWI is enabled
760 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND,
761 * and then calls @pcibios_set_mwi to do the needed arch specific
762 * operations or a generic mwi-prep function.
764 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
767 pci_set_mwi(struct pci_dev
*dev
)
772 #ifdef HAVE_ARCH_PCI_MWI
773 rc
= pcibios_prep_mwi(dev
);
775 rc
= pci_generic_prep_mwi(dev
);
781 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
782 if (! (cmd
& PCI_COMMAND_INVALIDATE
)) {
783 pr_debug("PCI: Enabling Mem-Wr-Inval for device %s\n", pci_name(dev
));
784 cmd
|= PCI_COMMAND_INVALIDATE
;
785 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
792 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
793 * @dev: the PCI device to disable
795 * Disables PCI Memory-Write-Invalidate transaction on the device
798 pci_clear_mwi(struct pci_dev
*dev
)
802 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
803 if (cmd
& PCI_COMMAND_INVALIDATE
) {
804 cmd
&= ~PCI_COMMAND_INVALIDATE
;
805 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
810 * pci_intx - enables/disables PCI INTx for device dev
811 * @dev: the PCI device to operate on
814 * Enables/disables PCI INTx for device dev
817 pci_intx(struct pci_dev
*pdev
, int enable
)
819 u16 pci_command
, new;
821 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_command
);
824 new = pci_command
& ~PCI_COMMAND_INTX_DISABLE
;
826 new = pci_command
| PCI_COMMAND_INTX_DISABLE
;
829 if (new != pci_command
) {
830 pci_write_config_word(pdev
, PCI_COMMAND
, new);
834 #ifndef HAVE_ARCH_PCI_SET_DMA_MASK
836 * These can be overridden by arch-specific implementations
839 pci_set_dma_mask(struct pci_dev
*dev
, u64 mask
)
841 if (!pci_dma_supported(dev
, mask
))
844 dev
->dma_mask
= mask
;
850 pci_set_consistent_dma_mask(struct pci_dev
*dev
, u64 mask
)
852 if (!pci_dma_supported(dev
, mask
))
855 dev
->dev
.coherent_dma_mask
= mask
;
861 static int __devinit
pci_init(void)
863 struct pci_dev
*dev
= NULL
;
865 while ((dev
= pci_get_device(PCI_ANY_ID
, PCI_ANY_ID
, dev
)) != NULL
) {
866 pci_fixup_device(pci_fixup_final
, dev
);
871 static int __devinit
pci_setup(char *str
)
874 char *k
= strchr(str
, ',');
877 if (*str
&& (str
= pcibios_setup(str
)) && *str
) {
878 /* PCI layer options should be handled here */
879 printk(KERN_ERR
"PCI: Unknown option `%s'\n", str
);
886 device_initcall(pci_init
);
888 __setup("pci=", pci_setup
);
890 #if defined(CONFIG_ISA) || defined(CONFIG_EISA)
891 /* FIXME: Some boxes have multiple ISA bridges! */
892 struct pci_dev
*isa_bridge
;
893 EXPORT_SYMBOL(isa_bridge
);
896 EXPORT_SYMBOL_GPL(pci_restore_bars
);
897 EXPORT_SYMBOL(pci_enable_device_bars
);
898 EXPORT_SYMBOL(pci_enable_device
);
899 EXPORT_SYMBOL(pci_disable_device
);
900 EXPORT_SYMBOL(pci_max_busnr
);
901 EXPORT_SYMBOL(pci_bus_max_busnr
);
902 EXPORT_SYMBOL(pci_find_capability
);
903 EXPORT_SYMBOL(pci_bus_find_capability
);
904 EXPORT_SYMBOL(pci_release_regions
);
905 EXPORT_SYMBOL(pci_request_regions
);
906 EXPORT_SYMBOL(pci_release_region
);
907 EXPORT_SYMBOL(pci_request_region
);
908 EXPORT_SYMBOL(pci_set_master
);
909 EXPORT_SYMBOL(pci_set_mwi
);
910 EXPORT_SYMBOL(pci_clear_mwi
);
911 EXPORT_SYMBOL_GPL(pci_intx
);
912 EXPORT_SYMBOL(pci_set_dma_mask
);
913 EXPORT_SYMBOL(pci_set_consistent_dma_mask
);
914 EXPORT_SYMBOL(pci_assign_resource
);
915 EXPORT_SYMBOL(pci_find_parent_resource
);
917 EXPORT_SYMBOL(pci_set_power_state
);
918 EXPORT_SYMBOL(pci_save_state
);
919 EXPORT_SYMBOL(pci_restore_state
);
920 EXPORT_SYMBOL(pci_enable_wake
);
924 EXPORT_SYMBOL(isa_dma_bridge_buggy
);
925 EXPORT_SYMBOL(pci_pci_problems
);