?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
[PATCH] 64bit Resource: convert a few remaining drivers to use resource_size_t where...
[linux-2.6/suspend2-2.6.18.git] / drivers / net / 8139cp.c
blobd26dd6a7062dcd2e72cb05a973fe1e78962fb7b4
1 /* 8139cp.c: A Linux PCI Ethernet driver for the RealTek 8139C+ chips. */
2 /*
3 Copyright 2001-2004 Jeff Garzik <jgarzik@pobox.com>
4
5 Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com) [tg3.c]
6 Copyright (C) 2000, 2001 David S. Miller (davem@redhat.com) [sungem.c]
7 Copyright 2001 Manfred Spraul [natsemi.c]
8 Copyright 1999-2001 by Donald Becker. [natsemi.c]
9 Written 1997-2001 by Donald Becker. [8139too.c]
10 Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. [acenic.c]
11
12 This software may be used and distributed according to the terms of
13 the GNU General Public License (GPL), incorporated herein by reference.
14 Drivers based on or derived from this code fall under the GPL and must
15 retain the authorship, copyright and license notice. This file is not
16 a complete program and may only be used when the entire operating
17 system is licensed under the GPL.
18
19 See the file COPYING in this distribution for more information.
20
21 Contributors:
22
23 Wake-on-LAN support - Felipe Damasio <felipewd@terra.com.br>
24 PCI suspend/resume - Felipe Damasio <felipewd@terra.com.br>
25 LinkChg interrupt - Felipe Damasio <felipewd@terra.com.br>
26
27 TODO:
28 * Test Tx checksumming thoroughly
29 * Implement dev->tx_timeout
30
31 Low priority TODO:
32 * Complete reset on PciErr
33 * Consider Rx interrupt mitigation using TimerIntr
34 * Investigate using skb->priority with h/w VLAN priority
35 * Investigate using High Priority Tx Queue with skb->priority
36 * Adjust Rx FIFO threshold and Max Rx DMA burst on Rx FIFO error
37 * Adjust Tx FIFO threshold and Max Tx DMA burst on Tx FIFO error
38 * Implement Tx software interrupt mitigation via
39 Tx descriptor bit
40 * The real minimum of CP_MIN_MTU is 4 bytes. However,
41 for this to be supported, one must(?) turn on packet padding.
42 * Support external MII transceivers (patch available)
43
44 NOTES:
45 * TX checksumming is considered experimental. It is off by
46 default, use ethtool to turn it on.
47
48 */
49
50 #define DRV_NAME "8139cp"
51 #define DRV_VERSION "1.2"
52 #define DRV_RELDATE "Mar 22, 2004"
53
54
55 #include <linux/config.h>
56 #include <linux/module.h>
57 #include <linux/moduleparam.h>
58 #include <linux/kernel.h>
59 #include <linux/compiler.h>
60 #include <linux/netdevice.h>
61 #include <linux/etherdevice.h>
62 #include <linux/init.h>
63 #include <linux/pci.h>
64 #include <linux/dma-mapping.h>
65 #include <linux/delay.h>
66 #include <linux/ethtool.h>
67 #include <linux/mii.h>
68 #include <linux/if_vlan.h>
69 #include <linux/crc32.h>
70 #include <linux/in.h>
71 #include <linux/ip.h>
72 #include <linux/tcp.h>
73 #include <linux/udp.h>
74 #include <linux/cache.h>
75 #include <asm/io.h>
76 #include <asm/irq.h>
77 #include <asm/uaccess.h>
78
79 /* VLAN tagging feature enable/disable */
80 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
81 #define CP_VLAN_TAG_USED 1
82 #define CP_VLAN_TX_TAG(tx_desc,vlan_tag_value) \
83 do { (tx_desc)->opts2 = (vlan_tag_value); } while (0)
84 #else
85 #define CP_VLAN_TAG_USED 0
86 #define CP_VLAN_TX_TAG(tx_desc,vlan_tag_value) \
87 do { (tx_desc)->opts2 = 0; } while (0)
88 #endif
89
90 /* These identify the driver base version and may not be removed. */
91 static char version[] =
92 KERN_INFO DRV_NAME ": 10/100 PCI Ethernet driver v" DRV_VERSION " (" DRV_RELDATE ")\n";
93
94 MODULE_AUTHOR("Jeff Garzik <jgarzik@pobox.com>");
95 MODULE_DESCRIPTION("RealTek RTL-8139C+ series 10/100 PCI Ethernet driver");
96 MODULE_VERSION(DRV_VERSION);
97 MODULE_LICENSE("GPL");
98
99 static int debug = -1;
100 module_param(debug, int, 0);
101 MODULE_PARM_DESC (debug, "8139cp: bitmapped message enable number");
102
103 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
104 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
105 static int multicast_filter_limit = 32;
106 module_param(multicast_filter_limit, int, 0);
107 MODULE_PARM_DESC (multicast_filter_limit, "8139cp: maximum number of filtered multicast addresses");
108
109 #define PFX DRV_NAME ": "
110
111 #ifndef TRUE
112 #define FALSE 0
113 #define TRUE (!FALSE)
114 #endif
115
116 #define CP_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
117 NETIF_MSG_PROBE | \
118 NETIF_MSG_LINK)
119 #define CP_NUM_STATS 14 /* struct cp_dma_stats, plus one */
120 #define CP_STATS_SIZE 64 /* size in bytes of DMA stats block */
121 #define CP_REGS_SIZE (0xff + 1)
122 #define CP_REGS_VER 1 /* version 1 */
123 #define CP_RX_RING_SIZE 64
124 #define CP_TX_RING_SIZE 64
125 #define CP_RING_BYTES \
126 ((sizeof(struct cp_desc) * CP_RX_RING_SIZE) + \
127 (sizeof(struct cp_desc) * CP_TX_RING_SIZE) + \
128 CP_STATS_SIZE)
129 #define NEXT_TX(N) (((N) + 1) & (CP_TX_RING_SIZE - 1))
130 #define NEXT_RX(N) (((N) + 1) & (CP_RX_RING_SIZE - 1))
131 #define TX_BUFFS_AVAIL(CP) \
132 (((CP)->tx_tail <= (CP)->tx_head) ? \
133 (CP)->tx_tail + (CP_TX_RING_SIZE - 1) - (CP)->tx_head : \
134 (CP)->tx_tail - (CP)->tx_head - 1)
135
136 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
137 #define RX_OFFSET 2
138 #define CP_INTERNAL_PHY 32
139
140 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
141 #define RX_FIFO_THRESH 5 /* Rx buffer level before first PCI xfer. */
142 #define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 */
143 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
144 #define TX_EARLY_THRESH 256 /* Early Tx threshold, in bytes */
145
146 /* Time in jiffies before concluding the transmitter is hung. */
147 #define TX_TIMEOUT (6*HZ)
148
149 /* hardware minimum and maximum for a single frame's data payload */
150 #define CP_MIN_MTU 60 /* TODO: allow lower, but pad */
151 #define CP_MAX_MTU 4096
152
153 enum {
154 /* NIC register offsets */
155 MAC0 = 0x00, /* Ethernet hardware address. */
156 MAR0 = 0x08, /* Multicast filter. */
157 StatsAddr = 0x10, /* 64-bit start addr of 64-byte DMA stats blk */
158 TxRingAddr = 0x20, /* 64-bit start addr of Tx ring */
159 HiTxRingAddr = 0x28, /* 64-bit start addr of high priority Tx ring */
160 Cmd = 0x37, /* Command register */
161 IntrMask = 0x3C, /* Interrupt mask */
162 IntrStatus = 0x3E, /* Interrupt status */
163 TxConfig = 0x40, /* Tx configuration */
164 ChipVersion = 0x43, /* 8-bit chip version, inside TxConfig */
165 RxConfig = 0x44, /* Rx configuration */
166 RxMissed = 0x4C, /* 24 bits valid, write clears */
167 Cfg9346 = 0x50, /* EEPROM select/control; Cfg reg [un]lock */
168 Config1 = 0x52, /* Config1 */
169 Config3 = 0x59, /* Config3 */
170 Config4 = 0x5A, /* Config4 */
171 MultiIntr = 0x5C, /* Multiple interrupt select */
172 BasicModeCtrl = 0x62, /* MII BMCR */
173 BasicModeStatus = 0x64, /* MII BMSR */
174 NWayAdvert = 0x66, /* MII ADVERTISE */
175 NWayLPAR = 0x68, /* MII LPA */
176 NWayExpansion = 0x6A, /* MII Expansion */
177 Config5 = 0xD8, /* Config5 */
178 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */
179 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */
180 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */
181 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */
182 RxRingAddr = 0xE4, /* 64-bit start addr of Rx ring */
183 TxThresh = 0xEC, /* Early Tx threshold */
184 OldRxBufAddr = 0x30, /* DMA address of Rx ring buffer (C mode) */
185 OldTSD0 = 0x10, /* DMA address of first Tx desc (C mode) */
186
187 /* Tx and Rx status descriptors */
188 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
189 RingEnd = (1 << 30), /* End of descriptor ring */
190 FirstFrag = (1 << 29), /* First segment of a packet */
191 LastFrag = (1 << 28), /* Final segment of a packet */
192 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
193 MSSShift = 16, /* MSS value position */
194 MSSMask = 0xfff, /* MSS value: 11 bits */
195 TxError = (1 << 23), /* Tx error summary */
196 RxError = (1 << 20), /* Rx error summary */
197 IPCS = (1 << 18), /* Calculate IP checksum */
198 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
199 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
200 TxVlanTag = (1 << 17), /* Add VLAN tag */
201 RxVlanTagged = (1 << 16), /* Rx VLAN tag available */
202 IPFail = (1 << 15), /* IP checksum failed */
203 UDPFail = (1 << 14), /* UDP/IP checksum failed */
204 TCPFail = (1 << 13), /* TCP/IP checksum failed */
205 NormalTxPoll = (1 << 6), /* One or more normal Tx packets to send */
206 PID1 = (1 << 17), /* 2 protocol id bits: 0==non-IP, */
207 PID0 = (1 << 16), /* 1==UDP/IP, 2==TCP/IP, 3==IP */
208 RxProtoTCP = 1,
209 RxProtoUDP = 2,
210 RxProtoIP = 3,
211 TxFIFOUnder = (1 << 25), /* Tx FIFO underrun */
212 TxOWC = (1 << 22), /* Tx Out-of-window collision */
213 TxLinkFail = (1 << 21), /* Link failed during Tx of packet */
214 TxMaxCol = (1 << 20), /* Tx aborted due to excessive collisions */
215 TxColCntShift = 16, /* Shift, to get 4-bit Tx collision cnt */
216 TxColCntMask = 0x01 | 0x02 | 0x04 | 0x08, /* 4-bit collision count */
217 RxErrFrame = (1 << 27), /* Rx frame alignment error */
218 RxMcast = (1 << 26), /* Rx multicast packet rcv'd */
219 RxErrCRC = (1 << 18), /* Rx CRC error */
220 RxErrRunt = (1 << 19), /* Rx error, packet < 64 bytes */
221 RxErrLong = (1 << 21), /* Rx error, packet > 4096 bytes */
222 RxErrFIFO = (1 << 22), /* Rx error, FIFO overflowed, pkt bad */
223
224 /* StatsAddr register */
225 DumpStats = (1 << 3), /* Begin stats dump */
226
227 /* RxConfig register */
228 RxCfgFIFOShift = 13, /* Shift, to get Rx FIFO thresh value */
229 RxCfgDMAShift = 8, /* Shift, to get Rx Max DMA value */
230 AcceptErr = 0x20, /* Accept packets with CRC errors */
231 AcceptRunt = 0x10, /* Accept runt (<64 bytes) packets */
232 AcceptBroadcast = 0x08, /* Accept broadcast packets */
233 AcceptMulticast = 0x04, /* Accept multicast packets */
234 AcceptMyPhys = 0x02, /* Accept pkts with our MAC as dest */
235 AcceptAllPhys = 0x01, /* Accept all pkts w/ physical dest */
236
237 /* IntrMask / IntrStatus registers */
238 PciErr = (1 << 15), /* System error on the PCI bus */
239 TimerIntr = (1 << 14), /* Asserted when TCTR reaches TimerInt value */
240 LenChg = (1 << 13), /* Cable length change */
241 SWInt = (1 << 8), /* Software-requested interrupt */
242 TxEmpty = (1 << 7), /* No Tx descriptors available */
243 RxFIFOOvr = (1 << 6), /* Rx FIFO Overflow */
244 LinkChg = (1 << 5), /* Packet underrun, or link change */
245 RxEmpty = (1 << 4), /* No Rx descriptors available */
246 TxErr = (1 << 3), /* Tx error */
247 TxOK = (1 << 2), /* Tx packet sent */
248 RxErr = (1 << 1), /* Rx error */
249 RxOK = (1 << 0), /* Rx packet received */
250 IntrResvd = (1 << 10), /* reserved, according to RealTek engineers,
251 but hardware likes to raise it */
252
253 IntrAll = PciErr | TimerIntr | LenChg | SWInt | TxEmpty |
254 RxFIFOOvr | LinkChg | RxEmpty | TxErr | TxOK |
255 RxErr | RxOK | IntrResvd,
256
257 /* C mode command register */
258 CmdReset = (1 << 4), /* Enable to reset; self-clearing */
259 RxOn = (1 << 3), /* Rx mode enable */
260 TxOn = (1 << 2), /* Tx mode enable */
261
262 /* C+ mode command register */
263 RxVlanOn = (1 << 6), /* Rx VLAN de-tagging enable */
264 RxChkSum = (1 << 5), /* Rx checksum offload enable */
265 PCIDAC = (1 << 4), /* PCI Dual Address Cycle (64-bit PCI) */
266 PCIMulRW = (1 << 3), /* Enable PCI read/write multiple */
267 CpRxOn = (1 << 1), /* Rx mode enable */
268 CpTxOn = (1 << 0), /* Tx mode enable */
269
270 /* Cfg9436 EEPROM control register */
271 Cfg9346_Lock = 0x00, /* Lock ConfigX/MII register access */
272 Cfg9346_Unlock = 0xC0, /* Unlock ConfigX/MII register access */
273
274 /* TxConfig register */
275 IFG = (1 << 25) | (1 << 24), /* standard IEEE interframe gap */
276 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
277
278 /* Early Tx Threshold register */
279 TxThreshMask = 0x3f, /* Mask bits 5-0 */
280 TxThreshMax = 2048, /* Max early Tx threshold */
281
282 /* Config1 register */
283 DriverLoaded = (1 << 5), /* Software marker, driver is loaded */
284 LWACT = (1 << 4), /* LWAKE active mode */
285 PMEnable = (1 << 0), /* Enable various PM features of chip */
286
287 /* Config3 register */
288 PARMEnable = (1 << 6), /* Enable auto-loading of PHY parms */
289 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
290 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
291
292 /* Config4 register */
293 LWPTN = (1 << 1), /* LWAKE Pattern */
294 LWPME = (1 << 4), /* LANWAKE vs PMEB */
295
296 /* Config5 register */
297 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
298 MWF = (1 << 5), /* Accept Multicast wakeup frame */
299 UWF = (1 << 4), /* Accept Unicast wakeup frame */
300 LANWake = (1 << 1), /* Enable LANWake signal */
301 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
302
303 cp_norx_intr_mask = PciErr | LinkChg | TxOK | TxErr | TxEmpty,
304 cp_rx_intr_mask = RxOK | RxErr | RxEmpty | RxFIFOOvr,
305 cp_intr_mask = cp_rx_intr_mask | cp_norx_intr_mask,
306 };
307
308 static const unsigned int cp_rx_config =
309 (RX_FIFO_THRESH << RxCfgFIFOShift) |
310 (RX_DMA_BURST << RxCfgDMAShift);
311
312 struct cp_desc {
313 u32 opts1;
314 u32 opts2;
315 u64 addr;
316 };
317
318 struct ring_info {
319 struct sk_buff *skb;
320 dma_addr_t mapping;
321 u32 len;
322 };
323
324 struct cp_dma_stats {
325 u64 tx_ok;
326 u64 rx_ok;
327 u64 tx_err;
328 u32 rx_err;
329 u16 rx_fifo;
330 u16 frame_align;
331 u32 tx_ok_1col;
332 u32 tx_ok_mcol;
333 u64 rx_ok_phys;
334 u64 rx_ok_bcast;
335 u32 rx_ok_mcast;
336 u16 tx_abort;
337 u16 tx_underrun;
338 } __attribute__((packed));
339
340 struct cp_extra_stats {
341 unsigned long rx_frags;
342 };
343
344 struct cp_private {
345 void __iomem *regs;
346 struct net_device *dev;
347 spinlock_t lock;
348 u32 msg_enable;
349
350 struct pci_dev *pdev;
351 u32 rx_config;
352 u16 cpcmd;
353
354 struct net_device_stats net_stats;
355 struct cp_extra_stats cp_stats;
356
357 unsigned rx_tail ____cacheline_aligned;
358 struct cp_desc *rx_ring;
359 struct ring_info rx_skb[CP_RX_RING_SIZE];
360 unsigned rx_buf_sz;
361
362 unsigned tx_head ____cacheline_aligned;
363 unsigned tx_tail;
364
365 struct cp_desc *tx_ring;
366 struct ring_info tx_skb[CP_TX_RING_SIZE];
367 dma_addr_t ring_dma;
368
369 #if CP_VLAN_TAG_USED
370 struct vlan_group *vlgrp;
371 #endif
372
373 unsigned int wol_enabled : 1; /* Is Wake-on-LAN enabled? */
374
375 struct mii_if_info mii_if;
376 };
377
378 #define cpr8(reg) readb(cp->regs + (reg))
379 #define cpr16(reg) readw(cp->regs + (reg))
380 #define cpr32(reg) readl(cp->regs + (reg))
381 #define cpw8(reg,val) writeb((val), cp->regs + (reg))
382 #define cpw16(reg,val) writew((val), cp->regs + (reg))
383 #define cpw32(reg,val) writel((val), cp->regs + (reg))
384 #define cpw8_f(reg,val) do { \
385 writeb((val), cp->regs + (reg)); \
386 readb(cp->regs + (reg)); \
387 } while (0)
388 #define cpw16_f(reg,val) do { \
389 writew((val), cp->regs + (reg)); \
390 readw(cp->regs + (reg)); \
391 } while (0)
392 #define cpw32_f(reg,val) do { \
393 writel((val), cp->regs + (reg)); \
394 readl(cp->regs + (reg)); \
395 } while (0)
396
397
398 static void __cp_set_rx_mode (struct net_device *dev);
399 static void cp_tx (struct cp_private *cp);
400 static void cp_clean_rings (struct cp_private *cp);
401 #ifdef CONFIG_NET_POLL_CONTROLLER
402 static void cp_poll_controller(struct net_device *dev);
403 #endif
404 static int cp_get_eeprom_len(struct net_device *dev);
405 static int cp_get_eeprom(struct net_device *dev,
406 struct ethtool_eeprom *eeprom, u8 *data);
407 static int cp_set_eeprom(struct net_device *dev,
408 struct ethtool_eeprom *eeprom, u8 *data);
409
410 static struct pci_device_id cp_pci_tbl[] = {
411 { PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139,
412 PCI_ANY_ID, PCI_ANY_ID, 0, 0, },
413 { PCI_VENDOR_ID_TTTECH, PCI_DEVICE_ID_TTTECH_MC322,
414 PCI_ANY_ID, PCI_ANY_ID, 0, 0, },
415 { },
416 };
417 MODULE_DEVICE_TABLE(pci, cp_pci_tbl);
418
419 static struct {
420 const char str[ETH_GSTRING_LEN];
421 } ethtool_stats_keys[] = {
422 { "tx_ok" },
423 { "rx_ok" },
424 { "tx_err" },
425 { "rx_err" },
426 { "rx_fifo" },
427 { "frame_align" },
428 { "tx_ok_1col" },
429 { "tx_ok_mcol" },
430 { "rx_ok_phys" },
431 { "rx_ok_bcast" },
432 { "rx_ok_mcast" },
433 { "tx_abort" },
434 { "tx_underrun" },
435 { "rx_frags" },
436 };
437
438
439 #if CP_VLAN_TAG_USED
440 static void cp_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
441 {
442 struct cp_private *cp = netdev_priv(dev);
443 unsigned long flags;
444
445 spin_lock_irqsave(&cp->lock, flags);
446 cp->vlgrp = grp;
447 cp->cpcmd |= RxVlanOn;
448 cpw16(CpCmd, cp->cpcmd);
449 spin_unlock_irqrestore(&cp->lock, flags);
450 }
451
452 static void cp_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
453 {
454 struct cp_private *cp = netdev_priv(dev);
455 unsigned long flags;
456
457 spin_lock_irqsave(&cp->lock, flags);
458 cp->cpcmd &= ~RxVlanOn;
459 cpw16(CpCmd, cp->cpcmd);
460 if (cp->vlgrp)
461 cp->vlgrp->vlan_devices[vid] = NULL;
462 spin_unlock_irqrestore(&cp->lock, flags);
463 }
464 #endif /* CP_VLAN_TAG_USED */
465
466 static inline void cp_set_rxbufsize (struct cp_private *cp)
467 {
468 unsigned int mtu = cp->dev->mtu;
469
470 if (mtu > ETH_DATA_LEN)
471 /* MTU + ethernet header + FCS + optional VLAN tag */
472 cp->rx_buf_sz = mtu + ETH_HLEN + 8;
473 else
474 cp->rx_buf_sz = PKT_BUF_SZ;
475 }
476
477 static inline void cp_rx_skb (struct cp_private *cp, struct sk_buff *skb,
478 struct cp_desc *desc)
479 {
480 skb->protocol = eth_type_trans (skb, cp->dev);
481
482 cp->net_stats.rx_packets++;
483 cp->net_stats.rx_bytes += skb->len;
484 cp->dev->last_rx = jiffies;
485
486 #if CP_VLAN_TAG_USED
487 if (cp->vlgrp && (desc->opts2 & RxVlanTagged)) {
488 vlan_hwaccel_receive_skb(skb, cp->vlgrp,
489 be16_to_cpu(desc->opts2 & 0xffff));
490 } else
491 #endif
492 netif_receive_skb(skb);
493 }
494
495 static void cp_rx_err_acct (struct cp_private *cp, unsigned rx_tail,
496 u32 status, u32 len)
497 {
498 if (netif_msg_rx_err (cp))
499 printk (KERN_DEBUG
500 "%s: rx err, slot %d status 0x%x len %d\n",
501 cp->dev->name, rx_tail, status, len);
502 cp->net_stats.rx_errors++;
503 if (status & RxErrFrame)
504 cp->net_stats.rx_frame_errors++;
505 if (status & RxErrCRC)
506 cp->net_stats.rx_crc_errors++;
507 if ((status & RxErrRunt) || (status & RxErrLong))
508 cp->net_stats.rx_length_errors++;
509 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag))
510 cp->net_stats.rx_length_errors++;
511 if (status & RxErrFIFO)
512 cp->net_stats.rx_fifo_errors++;
513 }
514
515 static inline unsigned int cp_rx_csum_ok (u32 status)
516 {
517 unsigned int protocol = (status >> 16) & 0x3;
518
519 if (likely((protocol == RxProtoTCP) && (!(status & TCPFail))))
520 return 1;
521 else if ((protocol == RxProtoUDP) && (!(status & UDPFail)))
522 return 1;
523 else if ((protocol == RxProtoIP) && (!(status & IPFail)))
524 return 1;
525 return 0;
526 }
527
528 static int cp_rx_poll (struct net_device *dev, int *budget)
529 {
530 struct cp_private *cp = netdev_priv(dev);
531 unsigned rx_tail = cp->rx_tail;
532 unsigned rx_work = dev->quota;
533 unsigned rx;
534
535 rx_status_loop:
536 rx = 0;
537 cpw16(IntrStatus, cp_rx_intr_mask);
538
539 while (1) {
540 u32 status, len;
541 dma_addr_t mapping;
542 struct sk_buff *skb, *new_skb;
543 struct cp_desc *desc;
544 unsigned buflen;
545
546 skb = cp->rx_skb[rx_tail].skb;
547 BUG_ON(!skb);
548
549 desc = &cp->rx_ring[rx_tail];
550 status = le32_to_cpu(desc->opts1);
551 if (status & DescOwn)
552 break;
553
554 len = (status & 0x1fff) - 4;
555 mapping = cp->rx_skb[rx_tail].mapping;
556
557 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag)) {
558 /* we don't support incoming fragmented frames.
559 * instead, we attempt to ensure that the
560 * pre-allocated RX skbs are properly sized such
561 * that RX fragments are never encountered
562 */
563 cp_rx_err_acct(cp, rx_tail, status, len);
564 cp->net_stats.rx_dropped++;
565 cp->cp_stats.rx_frags++;
566 goto rx_next;
567 }
568
569 if (status & (RxError | RxErrFIFO)) {
570 cp_rx_err_acct(cp, rx_tail, status, len);
571 goto rx_next;
572 }
573
574 if (netif_msg_rx_status(cp))
575 printk(KERN_DEBUG "%s: rx slot %d status 0x%x len %d\n",
576 cp->dev->name, rx_tail, status, len);
577
578 buflen = cp->rx_buf_sz + RX_OFFSET;
579 new_skb = dev_alloc_skb (buflen);
580 if (!new_skb) {
581 cp->net_stats.rx_dropped++;
582 goto rx_next;
583 }
584
585 skb_reserve(new_skb, RX_OFFSET);
586 new_skb->dev = cp->dev;
587
588 pci_unmap_single(cp->pdev, mapping,
589 buflen, PCI_DMA_FROMDEVICE);
590
591 /* Handle checksum offloading for incoming packets. */
592 if (cp_rx_csum_ok(status))
593 skb->ip_summed = CHECKSUM_UNNECESSARY;
594 else
595 skb->ip_summed = CHECKSUM_NONE;
596
597 skb_put(skb, len);
598
599 mapping =
600 cp->rx_skb[rx_tail].mapping =
601 pci_map_single(cp->pdev, new_skb->data,
602 buflen, PCI_DMA_FROMDEVICE);
603 cp->rx_skb[rx_tail].skb = new_skb;
604
605 cp_rx_skb(cp, skb, desc);
606 rx++;
607
608 rx_next:
609 cp->rx_ring[rx_tail].opts2 = 0;
610 cp->rx_ring[rx_tail].addr = cpu_to_le64(mapping);
611 if (rx_tail == (CP_RX_RING_SIZE - 1))
612 desc->opts1 = cpu_to_le32(DescOwn | RingEnd |
613 cp->rx_buf_sz);
614 else
615 desc->opts1 = cpu_to_le32(DescOwn | cp->rx_buf_sz);
616 rx_tail = NEXT_RX(rx_tail);
617
618 if (!rx_work--)
619 break;
620 }
621
622 cp->rx_tail = rx_tail;
623
624 dev->quota -= rx;
625 *budget -= rx;
626
627 /* if we did not reach work limit, then we're done with
628 * this round of polling
629 */
630 if (rx_work) {
631 if (cpr16(IntrStatus) & cp_rx_intr_mask)
632 goto rx_status_loop;
633
634 local_irq_disable();
635 cpw16_f(IntrMask, cp_intr_mask);
636 __netif_rx_complete(dev);
637 local_irq_enable();
638
639 return 0; /* done */
640 }
641
642 return 1; /* not done */
643 }
644
645 static irqreturn_t
646 cp_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
647 {
648 struct net_device *dev = dev_instance;
649 struct cp_private *cp;
650 u16 status;
651
652 if (unlikely(dev == NULL))
653 return IRQ_NONE;
654 cp = netdev_priv(dev);
655
656 status = cpr16(IntrStatus);
657 if (!status || (status == 0xFFFF))
658 return IRQ_NONE;
659
660 if (netif_msg_intr(cp))
661 printk(KERN_DEBUG "%s: intr, status %04x cmd %02x cpcmd %04x\n",
662 dev->name, status, cpr8(Cmd), cpr16(CpCmd));
663
664 cpw16(IntrStatus, status & ~cp_rx_intr_mask);
665
666 spin_lock(&cp->lock);
667
668 /* close possible race's with dev_close */
669 if (unlikely(!netif_running(dev))) {
670 cpw16(IntrMask, 0);
671 spin_unlock(&cp->lock);
672 return IRQ_HANDLED;
673 }
674
675 if (status & (RxOK | RxErr | RxEmpty | RxFIFOOvr))
676 if (netif_rx_schedule_prep(dev)) {
677 cpw16_f(IntrMask, cp_norx_intr_mask);
678 __netif_rx_schedule(dev);
679 }
680
681 if (status & (TxOK | TxErr | TxEmpty | SWInt))
682 cp_tx(cp);
683 if (status & LinkChg)
684 mii_check_media(&cp->mii_if, netif_msg_link(cp), FALSE);
685
686 spin_unlock(&cp->lock);
687
688 if (status & PciErr) {
689 u16 pci_status;
690
691 pci_read_config_word(cp->pdev, PCI_STATUS, &pci_status);
692 pci_write_config_word(cp->pdev, PCI_STATUS, pci_status);
693 printk(KERN_ERR "%s: PCI bus error, status=%04x, PCI status=%04x\n",
694 dev->name, status, pci_status);
695
696 /* TODO: reset hardware */
697 }
698
699 return IRQ_HANDLED;
700 }
701
702 #ifdef CONFIG_NET_POLL_CONTROLLER
703 /*
704 * Polling receive - used by netconsole and other diagnostic tools
705 * to allow network i/o with interrupts disabled.
706 */
707 static void cp_poll_controller(struct net_device *dev)
708 {
709 disable_irq(dev->irq);
710 cp_interrupt(dev->irq, dev, NULL);
711 enable_irq(dev->irq);
712 }
713 #endif
714
715 static void cp_tx (struct cp_private *cp)
716 {
717 unsigned tx_head = cp->tx_head;
718 unsigned tx_tail = cp->tx_tail;
719
720 while (tx_tail != tx_head) {
721 struct sk_buff *skb;
722 u32 status;
723
724 rmb();
725 status = le32_to_cpu(cp->tx_ring[tx_tail].opts1);
726 if (status & DescOwn)
727 break;
728
729 skb = cp->tx_skb[tx_tail].skb;
730 BUG_ON(!skb);
731
732 pci_unmap_single(cp->pdev, cp->tx_skb[tx_tail].mapping,
733 cp->tx_skb[tx_tail].len, PCI_DMA_TODEVICE);
734
735 if (status & LastFrag) {
736 if (status & (TxError | TxFIFOUnder)) {
737 if (netif_msg_tx_err(cp))
738 printk(KERN_DEBUG "%s: tx err, status 0x%x\n",
739 cp->dev->name, status);
740 cp->net_stats.tx_errors++;
741 if (status & TxOWC)
742 cp->net_stats.tx_window_errors++;
743 if (status & TxMaxCol)
744 cp->net_stats.tx_aborted_errors++;
745 if (status & TxLinkFail)
746 cp->net_stats.tx_carrier_errors++;
747 if (status & TxFIFOUnder)
748 cp->net_stats.tx_fifo_errors++;
749 } else {
750 cp->net_stats.collisions +=
751 ((status >> TxColCntShift) & TxColCntMask);
752 cp->net_stats.tx_packets++;
753 cp->net_stats.tx_bytes += skb->len;
754 if (netif_msg_tx_done(cp))
755 printk(KERN_DEBUG "%s: tx done, slot %d\n", cp->dev->name, tx_tail);
756 }
757 dev_kfree_skb_irq(skb);
758 }
759
760 cp->tx_skb[tx_tail].skb = NULL;
761
762 tx_tail = NEXT_TX(tx_tail);
763 }
764
765 cp->tx_tail = tx_tail;
766
767 if (TX_BUFFS_AVAIL(cp) > (MAX_SKB_FRAGS + 1))
768 netif_wake_queue(cp->dev);
769 }
770
771 static int cp_start_xmit (struct sk_buff *skb, struct net_device *dev)
772 {
773 struct cp_private *cp = netdev_priv(dev);
774 unsigned entry;
775 u32 eor, flags;
776 #if CP_VLAN_TAG_USED
777 u32 vlan_tag = 0;
778 #endif
779 int mss = 0;
780
781 spin_lock_irq(&cp->lock);
782
783 /* This is a hard error, log it. */
784 if (TX_BUFFS_AVAIL(cp) <= (skb_shinfo(skb)->nr_frags + 1)) {
785 netif_stop_queue(dev);
786 spin_unlock_irq(&cp->lock);
787 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
788 dev->name);
789 return 1;
790 }
791
792 #if CP_VLAN_TAG_USED
793 if (cp->vlgrp && vlan_tx_tag_present(skb))
794 vlan_tag = TxVlanTag | cpu_to_be16(vlan_tx_tag_get(skb));
795 #endif
796
797 entry = cp->tx_head;
798 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
799 if (dev->features & NETIF_F_TSO)
800 mss = skb_shinfo(skb)->gso_size;
801
802 if (skb_shinfo(skb)->nr_frags == 0) {
803 struct cp_desc *txd = &cp->tx_ring[entry];
804 u32 len;
805 dma_addr_t mapping;
806
807 len = skb->len;
808 mapping = pci_map_single(cp->pdev, skb->data, len, PCI_DMA_TODEVICE);
809 CP_VLAN_TX_TAG(txd, vlan_tag);
810 txd->addr = cpu_to_le64(mapping);
811 wmb();
812
813 flags = eor | len | DescOwn | FirstFrag | LastFrag;
814
815 if (mss)
816 flags |= LargeSend | ((mss & MSSMask) << MSSShift);
817 else if (skb->ip_summed == CHECKSUM_HW) {
818 const struct iphdr *ip = skb->nh.iph;
819 if (ip->protocol == IPPROTO_TCP)
820 flags |= IPCS | TCPCS;
821 else if (ip->protocol == IPPROTO_UDP)
822 flags |= IPCS | UDPCS;
823 else
824 WARN_ON(1); /* we need a WARN() */
825 }
826
827 txd->opts1 = cpu_to_le32(flags);
828 wmb();
829
830 cp->tx_skb[entry].skb = skb;
831 cp->tx_skb[entry].mapping = mapping;
832 cp->tx_skb[entry].len = len;
833 entry = NEXT_TX(entry);
834 } else {
835 struct cp_desc *txd;
836 u32 first_len, first_eor;
837 dma_addr_t first_mapping;
838 int frag, first_entry = entry;
839 const struct iphdr *ip = skb->nh.iph;
840
841 /* We must give this initial chunk to the device last.
842 * Otherwise we could race with the device.
843 */
844 first_eor = eor;
845 first_len = skb_headlen(skb);
846 first_mapping = pci_map_single(cp->pdev, skb->data,
847 first_len, PCI_DMA_TODEVICE);
848 cp->tx_skb[entry].skb = skb;
849 cp->tx_skb[entry].mapping = first_mapping;
850 cp->tx_skb[entry].len = first_len;
851 entry = NEXT_TX(entry);
852
853 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
854 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
855 u32 len;
856 u32 ctrl;
857 dma_addr_t mapping;
858
859 len = this_frag->size;
860 mapping = pci_map_single(cp->pdev,
861 ((void *) page_address(this_frag->page) +
862 this_frag->page_offset),
863 len, PCI_DMA_TODEVICE);
864 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
865
866 ctrl = eor | len | DescOwn;
867
868 if (mss)
869 ctrl |= LargeSend |
870 ((mss & MSSMask) << MSSShift);
871 else if (skb->ip_summed == CHECKSUM_HW) {
872 if (ip->protocol == IPPROTO_TCP)
873 ctrl |= IPCS | TCPCS;
874 else if (ip->protocol == IPPROTO_UDP)
875 ctrl |= IPCS | UDPCS;
876 else
877 BUG();
878 }
879
880 if (frag == skb_shinfo(skb)->nr_frags - 1)
881 ctrl |= LastFrag;
882
883 txd = &cp->tx_ring[entry];
884 CP_VLAN_TX_TAG(txd, vlan_tag);
885 txd->addr = cpu_to_le64(mapping);
886 wmb();
887
888 txd->opts1 = cpu_to_le32(ctrl);
889 wmb();
890
891 cp->tx_skb[entry].skb = skb;
892 cp->tx_skb[entry].mapping = mapping;
893 cp->tx_skb[entry].len = len;
894 entry = NEXT_TX(entry);
895 }
896
897 txd = &cp->tx_ring[first_entry];
898 CP_VLAN_TX_TAG(txd, vlan_tag);
899 txd->addr = cpu_to_le64(first_mapping);
900 wmb();
901
902 if (skb->ip_summed == CHECKSUM_HW) {
903 if (ip->protocol == IPPROTO_TCP)
904 txd->opts1 = cpu_to_le32(first_eor | first_len |
905 FirstFrag | DescOwn |
906 IPCS | TCPCS);
907 else if (ip->protocol == IPPROTO_UDP)
908 txd->opts1 = cpu_to_le32(first_eor | first_len |
909 FirstFrag | DescOwn |
910 IPCS | UDPCS);
911 else
912 BUG();
913 } else
914 txd->opts1 = cpu_to_le32(first_eor | first_len |
915 FirstFrag | DescOwn);
916 wmb();
917 }
918 cp->tx_head = entry;
919 if (netif_msg_tx_queued(cp))
920 printk(KERN_DEBUG "%s: tx queued, slot %d, skblen %d\n",
921 dev->name, entry, skb->len);
922 if (TX_BUFFS_AVAIL(cp) <= (MAX_SKB_FRAGS + 1))
923 netif_stop_queue(dev);
924
925 spin_unlock_irq(&cp->lock);
926
927 cpw8(TxPoll, NormalTxPoll);
928 dev->trans_start = jiffies;
929
930 return 0;
931 }
932
933 /* Set or clear the multicast filter for this adaptor.
934 This routine is not state sensitive and need not be SMP locked. */
935
936 static void __cp_set_rx_mode (struct net_device *dev)
937 {
938 struct cp_private *cp = netdev_priv(dev);
939 u32 mc_filter[2]; /* Multicast hash filter */
940 int i, rx_mode;
941 u32 tmp;
942
943 /* Note: do not reorder, GCC is clever about common statements. */
944 if (dev->flags & IFF_PROMISC) {
945 /* Unconditionally log net taps. */
946 printk (KERN_NOTICE "%s: Promiscuous mode enabled.\n",
947 dev->name);
948 rx_mode =
949 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
950 AcceptAllPhys;
951 mc_filter[1] = mc_filter[0] = 0xffffffff;
952 } else if ((dev->mc_count > multicast_filter_limit)
953 || (dev->flags & IFF_ALLMULTI)) {
954 /* Too many to filter perfectly -- accept all multicasts. */
955 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
956 mc_filter[1] = mc_filter[0] = 0xffffffff;
957 } else {
958 struct dev_mc_list *mclist;
959 rx_mode = AcceptBroadcast | AcceptMyPhys;
960 mc_filter[1] = mc_filter[0] = 0;
961 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
962 i++, mclist = mclist->next) {
963 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
964
965 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
966 rx_mode |= AcceptMulticast;
967 }
968 }
969
970 /* We can safely update without stopping the chip. */
971 tmp = cp_rx_config | rx_mode;
972 if (cp->rx_config != tmp) {
973 cpw32_f (RxConfig, tmp);
974 cp->rx_config = tmp;
975 }
976 cpw32_f (MAR0 + 0, mc_filter[0]);
977 cpw32_f (MAR0 + 4, mc_filter[1]);
978 }
979
980 static void cp_set_rx_mode (struct net_device *dev)
981 {
982 unsigned long flags;
983 struct cp_private *cp = netdev_priv(dev);
984
985 spin_lock_irqsave (&cp->lock, flags);
986 __cp_set_rx_mode(dev);
987 spin_unlock_irqrestore (&cp->lock, flags);
988 }
989
990 static void __cp_get_stats(struct cp_private *cp)
991 {
992 /* only lower 24 bits valid; write any value to clear */
993 cp->net_stats.rx_missed_errors += (cpr32 (RxMissed) & 0xffffff);
994 cpw32 (RxMissed, 0);
995 }
996
997 static struct net_device_stats *cp_get_stats(struct net_device *dev)
998 {
999 struct cp_private *cp = netdev_priv(dev);
1000 unsigned long flags;
1001
1002 /* The chip only need report frame silently dropped. */
1003 spin_lock_irqsave(&cp->lock, flags);
1004 if (netif_running(dev) && netif_device_present(dev))
1005 __cp_get_stats(cp);
1006 spin_unlock_irqrestore(&cp->lock, flags);
1007
1008 return &cp->net_stats;
1009 }
1010
1011 static void cp_stop_hw (struct cp_private *cp)
1012 {
1013 cpw16(IntrStatus, ~(cpr16(IntrStatus)));
1014 cpw16_f(IntrMask, 0);
1015 cpw8(Cmd, 0);
1016 cpw16_f(CpCmd, 0);
1017 cpw16_f(IntrStatus, ~(cpr16(IntrStatus)));
1018
1019 cp->rx_tail = 0;
1020 cp->tx_head = cp->tx_tail = 0;
1021 }
1022
1023 static void cp_reset_hw (struct cp_private *cp)
1024 {
1025 unsigned work = 1000;
1026
1027 cpw8(Cmd, CmdReset);
1028
1029 while (work--) {
1030 if (!(cpr8(Cmd) & CmdReset))
1031 return;
1032
1033 schedule_timeout_uninterruptible(10);
1034 }
1035
1036 printk(KERN_ERR "%s: hardware reset timeout\n", cp->dev->name);
1037 }
1038
1039 static inline void cp_start_hw (struct cp_private *cp)
1040 {
1041 cpw16(CpCmd, cp->cpcmd);
1042 cpw8(Cmd, RxOn | TxOn);
1043 }
1044
1045 static void cp_init_hw (struct cp_private *cp)
1046 {
1047 struct net_device *dev = cp->dev;
1048 dma_addr_t ring_dma;
1049
1050 cp_reset_hw(cp);
1051
1052 cpw8_f (Cfg9346, Cfg9346_Unlock);
1053
1054 /* Restore our idea of the MAC address. */
1055 cpw32_f (MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0)));
1056 cpw32_f (MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4)));
1057
1058 cp_start_hw(cp);
1059 cpw8(TxThresh, 0x06); /* XXX convert magic num to a constant */
1060
1061 __cp_set_rx_mode(dev);
1062 cpw32_f (TxConfig, IFG | (TX_DMA_BURST << TxDMAShift));
1063
1064 cpw8(Config1, cpr8(Config1) | DriverLoaded | PMEnable);
1065 /* Disable Wake-on-LAN. Can be turned on with ETHTOOL_SWOL */
1066 cpw8(Config3, PARMEnable);
1067 cp->wol_enabled = 0;
1068
1069 cpw8(Config5, cpr8(Config5) & PMEStatus);
1070
1071 cpw32_f(HiTxRingAddr, 0);
1072 cpw32_f(HiTxRingAddr + 4, 0);
1073
1074 ring_dma = cp->ring_dma;
1075 cpw32_f(RxRingAddr, ring_dma & 0xffffffff);
1076 cpw32_f(RxRingAddr + 4, (ring_dma >> 16) >> 16);
1077
1078 ring_dma += sizeof(struct cp_desc) * CP_RX_RING_SIZE;
1079 cpw32_f(TxRingAddr, ring_dma & 0xffffffff);
1080 cpw32_f(TxRingAddr + 4, (ring_dma >> 16) >> 16);
1081
1082 cpw16(MultiIntr, 0);
1083
1084 cpw16_f(IntrMask, cp_intr_mask);
1085
1086 cpw8_f(Cfg9346, Cfg9346_Lock);
1087 }
1088
1089 static int cp_refill_rx (struct cp_private *cp)
1090 {
1091 unsigned i;
1092
1093 for (i = 0; i < CP_RX_RING_SIZE; i++) {
1094 struct sk_buff *skb;
1095
1096 skb = dev_alloc_skb(cp->rx_buf_sz + RX_OFFSET);
1097 if (!skb)
1098 goto err_out;
1099
1100 skb->dev = cp->dev;
1101 skb_reserve(skb, RX_OFFSET);
1102
1103 cp->rx_skb[i].mapping = pci_map_single(cp->pdev,
1104 skb->data, cp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1105 cp->rx_skb[i].skb = skb;
1106
1107 cp->rx_ring[i].opts2 = 0;
1108 cp->rx_ring[i].addr = cpu_to_le64(cp->rx_skb[i].mapping);
1109 if (i == (CP_RX_RING_SIZE - 1))
1110 cp->rx_ring[i].opts1 =
1111 cpu_to_le32(DescOwn | RingEnd | cp->rx_buf_sz);
1112 else
1113 cp->rx_ring[i].opts1 =
1114 cpu_to_le32(DescOwn | cp->rx_buf_sz);
1115 }
1116
1117 return 0;
1118
1119 err_out:
1120 cp_clean_rings(cp);
1121 return -ENOMEM;
1122 }
1123
1124 static void cp_init_rings_index (struct cp_private *cp)
1125 {
1126 cp->rx_tail = 0;
1127 cp->tx_head = cp->tx_tail = 0;
1128 }
1129
1130 static int cp_init_rings (struct cp_private *cp)
1131 {
1132 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1133 cp->tx_ring[CP_TX_RING_SIZE - 1].opts1 = cpu_to_le32(RingEnd);
1134
1135 cp_init_rings_index(cp);
1136
1137 return cp_refill_rx (cp);
1138 }
1139
1140 static int cp_alloc_rings (struct cp_private *cp)
1141 {
1142 void *mem;
1143
1144 mem = pci_alloc_consistent(cp->pdev, CP_RING_BYTES, &cp->ring_dma);
1145 if (!mem)
1146 return -ENOMEM;
1147
1148 cp->rx_ring = mem;
1149 cp->tx_ring = &cp->rx_ring[CP_RX_RING_SIZE];
1150
1151 return cp_init_rings(cp);
1152 }
1153
1154 static void cp_clean_rings (struct cp_private *cp)
1155 {
1156 unsigned i;
1157
1158 for (i = 0; i < CP_RX_RING_SIZE; i++) {
1159 if (cp->rx_skb[i].skb) {
1160 pci_unmap_single(cp->pdev, cp->rx_skb[i].mapping,
1161 cp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1162 dev_kfree_skb(cp->rx_skb[i].skb);
1163 }
1164 }
1165
1166 for (i = 0; i < CP_TX_RING_SIZE; i++) {
1167 if (cp->tx_skb[i].skb) {
1168 struct sk_buff *skb = cp->tx_skb[i].skb;
1169
1170 pci_unmap_single(cp->pdev, cp->tx_skb[i].mapping,
1171 cp->tx_skb[i].len, PCI_DMA_TODEVICE);
1172 if (le32_to_cpu(cp->tx_ring[i].opts1) & LastFrag)
1173 dev_kfree_skb(skb);
1174 cp->net_stats.tx_dropped++;
1175 }
1176 }
1177
1178 memset(cp->rx_ring, 0, sizeof(struct cp_desc) * CP_RX_RING_SIZE);
1179 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1180
1181 memset(&cp->rx_skb, 0, sizeof(struct ring_info) * CP_RX_RING_SIZE);
1182 memset(&cp->tx_skb, 0, sizeof(struct ring_info) * CP_TX_RING_SIZE);
1183 }
1184
1185 static void cp_free_rings (struct cp_private *cp)
1186 {
1187 cp_clean_rings(cp);
1188 pci_free_consistent(cp->pdev, CP_RING_BYTES, cp->rx_ring, cp->ring_dma);
1189 cp->rx_ring = NULL;
1190 cp->tx_ring = NULL;
1191 }
1192
1193 static int cp_open (struct net_device *dev)
1194 {
1195 struct cp_private *cp = netdev_priv(dev);
1196 int rc;
1197
1198 if (netif_msg_ifup(cp))
1199 printk(KERN_DEBUG "%s: enabling interface\n", dev->name);
1200
1201 rc = cp_alloc_rings(cp);
1202 if (rc)
1203 return rc;
1204
1205 cp_init_hw(cp);
1206
1207 rc = request_irq(dev->irq, cp_interrupt, SA_SHIRQ, dev->name, dev);
1208 if (rc)
1209 goto err_out_hw;
1210
1211 netif_carrier_off(dev);
1212 mii_check_media(&cp->mii_if, netif_msg_link(cp), TRUE);
1213 netif_start_queue(dev);
1214
1215 return 0;
1216
1217 err_out_hw:
1218 cp_stop_hw(cp);
1219 cp_free_rings(cp);
1220 return rc;
1221 }
1222
1223 static int cp_close (struct net_device *dev)
1224 {
1225 struct cp_private *cp = netdev_priv(dev);
1226 unsigned long flags;
1227
1228 if (netif_msg_ifdown(cp))
1229 printk(KERN_DEBUG "%s: disabling interface\n", dev->name);
1230
1231 spin_lock_irqsave(&cp->lock, flags);
1232
1233 netif_stop_queue(dev);
1234 netif_carrier_off(dev);
1235
1236 cp_stop_hw(cp);
1237
1238 spin_unlock_irqrestore(&cp->lock, flags);
1239
1240 synchronize_irq(dev->irq);
1241 free_irq(dev->irq, dev);
1242
1243 cp_free_rings(cp);
1244 return 0;
1245 }
1246
1247 #ifdef BROKEN
1248 static int cp_change_mtu(struct net_device *dev, int new_mtu)
1249 {
1250 struct cp_private *cp = netdev_priv(dev);
1251 int rc;
1252 unsigned long flags;
1253
1254 /* check for invalid MTU, according to hardware limits */
1255 if (new_mtu < CP_MIN_MTU || new_mtu > CP_MAX_MTU)
1256 return -EINVAL;
1257
1258 /* if network interface not up, no need for complexity */
1259 if (!netif_running(dev)) {
1260 dev->mtu = new_mtu;
1261 cp_set_rxbufsize(cp); /* set new rx buf size */
1262 return 0;
1263 }
1264
1265 spin_lock_irqsave(&cp->lock, flags);
1266
1267 cp_stop_hw(cp); /* stop h/w and free rings */
1268 cp_clean_rings(cp);
1269
1270 dev->mtu = new_mtu;
1271 cp_set_rxbufsize(cp); /* set new rx buf size */
1272
1273 rc = cp_init_rings(cp); /* realloc and restart h/w */
1274 cp_start_hw(cp);
1275
1276 spin_unlock_irqrestore(&cp->lock, flags);
1277
1278 return rc;
1279 }
1280 #endif /* BROKEN */
1281
1282 static const char mii_2_8139_map[8] = {
1283 BasicModeCtrl,
1284 BasicModeStatus,
1285 0,
1286 0,
1287 NWayAdvert,
1288 NWayLPAR,
1289 NWayExpansion,
1290 0
1291 };
1292
1293 static int mdio_read(struct net_device *dev, int phy_id, int location)
1294 {
1295 struct cp_private *cp = netdev_priv(dev);
1296
1297 return location < 8 && mii_2_8139_map[location] ?
1298 readw(cp->regs + mii_2_8139_map[location]) : 0;
1299 }
1300
1301
1302 static void mdio_write(struct net_device *dev, int phy_id, int location,
1303 int value)
1304 {
1305 struct cp_private *cp = netdev_priv(dev);
1306
1307 if (location == 0) {
1308 cpw8(Cfg9346, Cfg9346_Unlock);
1309 cpw16(BasicModeCtrl, value);
1310 cpw8(Cfg9346, Cfg9346_Lock);
1311 } else if (location < 8 && mii_2_8139_map[location])
1312 cpw16(mii_2_8139_map[location], value);
1313 }
1314
1315 /* Set the ethtool Wake-on-LAN settings */
1316 static int netdev_set_wol (struct cp_private *cp,
1317 const struct ethtool_wolinfo *wol)
1318 {
1319 u8 options;
1320
1321 options = cpr8 (Config3) & ~(LinkUp | MagicPacket);
1322 /* If WOL is being disabled, no need for complexity */
1323 if (wol->wolopts) {
1324 if (wol->wolopts & WAKE_PHY) options |= LinkUp;
1325 if (wol->wolopts & WAKE_MAGIC) options |= MagicPacket;
1326 }
1327
1328 cpw8 (Cfg9346, Cfg9346_Unlock);
1329 cpw8 (Config3, options);
1330 cpw8 (Cfg9346, Cfg9346_Lock);
1331
1332 options = 0; /* Paranoia setting */
1333 options = cpr8 (Config5) & ~(UWF | MWF | BWF);
1334 /* If WOL is being disabled, no need for complexity */
1335 if (wol->wolopts) {
1336 if (wol->wolopts & WAKE_UCAST) options |= UWF;
1337 if (wol->wolopts & WAKE_BCAST) options |= BWF;
1338 if (wol->wolopts & WAKE_MCAST) options |= MWF;
1339 }
1340
1341 cpw8 (Config5, options);
1342
1343 cp->wol_enabled = (wol->wolopts) ? 1 : 0;
1344
1345 return 0;
1346 }
1347
1348 /* Get the ethtool Wake-on-LAN settings */
1349 static void netdev_get_wol (struct cp_private *cp,
1350 struct ethtool_wolinfo *wol)
1351 {
1352 u8 options;
1353
1354 wol->wolopts = 0; /* Start from scratch */
1355 wol->supported = WAKE_PHY | WAKE_BCAST | WAKE_MAGIC |
1356 WAKE_MCAST | WAKE_UCAST;
1357 /* We don't need to go on if WOL is disabled */
1358 if (!cp->wol_enabled) return;
1359
1360 options = cpr8 (Config3);
1361 if (options & LinkUp) wol->wolopts |= WAKE_PHY;
1362 if (options & MagicPacket) wol->wolopts |= WAKE_MAGIC;
1363
1364 options = 0; /* Paranoia setting */
1365 options = cpr8 (Config5);
1366 if (options & UWF) wol->wolopts |= WAKE_UCAST;
1367 if (options & BWF) wol->wolopts |= WAKE_BCAST;
1368 if (options & MWF) wol->wolopts |= WAKE_MCAST;
1369 }
1370
1371 static void cp_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1372 {
1373 struct cp_private *cp = netdev_priv(dev);
1374
1375 strcpy (info->driver, DRV_NAME);
1376 strcpy (info->version, DRV_VERSION);
1377 strcpy (info->bus_info, pci_name(cp->pdev));
1378 }
1379
1380 static int cp_get_regs_len(struct net_device *dev)
1381 {
1382 return CP_REGS_SIZE;
1383 }
1384
1385 static int cp_get_stats_count (struct net_device *dev)
1386 {
1387 return CP_NUM_STATS;
1388 }
1389
1390 static int cp_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1391 {
1392 struct cp_private *cp = netdev_priv(dev);
1393 int rc;
1394 unsigned long flags;
1395
1396 spin_lock_irqsave(&cp->lock, flags);
1397 rc = mii_ethtool_gset(&cp->mii_if, cmd);
1398 spin_unlock_irqrestore(&cp->lock, flags);
1399
1400 return rc;
1401 }
1402
1403 static int cp_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1404 {
1405 struct cp_private *cp = netdev_priv(dev);
1406 int rc;
1407 unsigned long flags;
1408
1409 spin_lock_irqsave(&cp->lock, flags);
1410 rc = mii_ethtool_sset(&cp->mii_if, cmd);
1411 spin_unlock_irqrestore(&cp->lock, flags);
1412
1413 return rc;
1414 }
1415
1416 static int cp_nway_reset(struct net_device *dev)
1417 {
1418 struct cp_private *cp = netdev_priv(dev);
1419 return mii_nway_restart(&cp->mii_if);
1420 }
1421
1422 static u32 cp_get_msglevel(struct net_device *dev)
1423 {
1424 struct cp_private *cp = netdev_priv(dev);
1425 return cp->msg_enable;
1426 }
1427
1428 static void cp_set_msglevel(struct net_device *dev, u32 value)
1429 {
1430 struct cp_private *cp = netdev_priv(dev);
1431 cp->msg_enable = value;
1432 }
1433
1434 static u32 cp_get_rx_csum(struct net_device *dev)
1435 {
1436 struct cp_private *cp = netdev_priv(dev);
1437 return (cpr16(CpCmd) & RxChkSum) ? 1 : 0;
1438 }
1439
1440 static int cp_set_rx_csum(struct net_device *dev, u32 data)
1441 {
1442 struct cp_private *cp = netdev_priv(dev);
1443 u16 cmd = cp->cpcmd, newcmd;
1444
1445 newcmd = cmd;
1446
1447 if (data)
1448 newcmd |= RxChkSum;
1449 else
1450 newcmd &= ~RxChkSum;
1451
1452 if (newcmd != cmd) {
1453 unsigned long flags;
1454
1455 spin_lock_irqsave(&cp->lock, flags);
1456 cp->cpcmd = newcmd;
1457 cpw16_f(CpCmd, newcmd);
1458 spin_unlock_irqrestore(&cp->lock, flags);
1459 }
1460
1461 return 0;
1462 }
1463
1464 static void cp_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1465 void *p)
1466 {
1467 struct cp_private *cp = netdev_priv(dev);
1468 unsigned long flags;
1469
1470 if (regs->len < CP_REGS_SIZE)
1471 return /* -EINVAL */;
1472
1473 regs->version = CP_REGS_VER;
1474
1475 spin_lock_irqsave(&cp->lock, flags);
1476 memcpy_fromio(p, cp->regs, CP_REGS_SIZE);
1477 spin_unlock_irqrestore(&cp->lock, flags);
1478 }
1479
1480 static void cp_get_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1481 {
1482 struct cp_private *cp = netdev_priv(dev);
1483 unsigned long flags;
1484
1485 spin_lock_irqsave (&cp->lock, flags);
1486 netdev_get_wol (cp, wol);
1487 spin_unlock_irqrestore (&cp->lock, flags);
1488 }
1489
1490 static int cp_set_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1491 {
1492 struct cp_private *cp = netdev_priv(dev);
1493 unsigned long flags;
1494 int rc;
1495
1496 spin_lock_irqsave (&cp->lock, flags);
1497 rc = netdev_set_wol (cp, wol);
1498 spin_unlock_irqrestore (&cp->lock, flags);
1499
1500 return rc;
1501 }
1502
1503 static void cp_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
1504 {
1505 switch (stringset) {
1506 case ETH_SS_STATS:
1507 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
1508 break;
1509 default:
1510 BUG();
1511 break;
1512 }
1513 }
1514
1515 static void cp_get_ethtool_stats (struct net_device *dev,
1516 struct ethtool_stats *estats, u64 *tmp_stats)
1517 {
1518 struct cp_private *cp = netdev_priv(dev);
1519 struct cp_dma_stats *nic_stats;
1520 dma_addr_t dma;
1521 int i;
1522
1523 nic_stats = pci_alloc_consistent(cp->pdev, sizeof(*nic_stats), &dma);
1524 if (!nic_stats)
1525 return;
1526
1527 /* begin NIC statistics dump */
1528 cpw32(StatsAddr + 4, (u64)dma >> 32);
1529 cpw32(StatsAddr, ((u64)dma & DMA_32BIT_MASK) | DumpStats);
1530 cpr32(StatsAddr);
1531
1532 for (i = 0; i < 1000; i++) {
1533 if ((cpr32(StatsAddr) & DumpStats) == 0)
1534 break;
1535 udelay(10);
1536 }
1537 cpw32(StatsAddr, 0);
1538 cpw32(StatsAddr + 4, 0);
1539 cpr32(StatsAddr);
1540
1541 i = 0;
1542 tmp_stats[i++] = le64_to_cpu(nic_stats->tx_ok);
1543 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok);
1544 tmp_stats[i++] = le64_to_cpu(nic_stats->tx_err);
1545 tmp_stats[i++] = le32_to_cpu(nic_stats->rx_err);
1546 tmp_stats[i++] = le16_to_cpu(nic_stats->rx_fifo);
1547 tmp_stats[i++] = le16_to_cpu(nic_stats->frame_align);
1548 tmp_stats[i++] = le32_to_cpu(nic_stats->tx_ok_1col);
1549 tmp_stats[i++] = le32_to_cpu(nic_stats->tx_ok_mcol);
1550 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok_phys);
1551 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok_bcast);
1552 tmp_stats[i++] = le32_to_cpu(nic_stats->rx_ok_mcast);
1553 tmp_stats[i++] = le16_to_cpu(nic_stats->tx_abort);
1554 tmp_stats[i++] = le16_to_cpu(nic_stats->tx_underrun);
1555 tmp_stats[i++] = cp->cp_stats.rx_frags;
1556 BUG_ON(i != CP_NUM_STATS);
1557
1558 pci_free_consistent(cp->pdev, sizeof(*nic_stats), nic_stats, dma);
1559 }
1560
1561 static struct ethtool_ops cp_ethtool_ops = {
1562 .get_drvinfo = cp_get_drvinfo,
1563 .get_regs_len = cp_get_regs_len,
1564 .get_stats_count = cp_get_stats_count,
1565 .get_settings = cp_get_settings,
1566 .set_settings = cp_set_settings,
1567 .nway_reset = cp_nway_reset,
1568 .get_link = ethtool_op_get_link,
1569 .get_msglevel = cp_get_msglevel,
1570 .set_msglevel = cp_set_msglevel,
1571 .get_rx_csum = cp_get_rx_csum,
1572 .set_rx_csum = cp_set_rx_csum,
1573 .get_tx_csum = ethtool_op_get_tx_csum,
1574 .set_tx_csum = ethtool_op_set_tx_csum, /* local! */
1575 .get_sg = ethtool_op_get_sg,
1576 .set_sg = ethtool_op_set_sg,
1577 .get_tso = ethtool_op_get_tso,
1578 .set_tso = ethtool_op_set_tso,
1579 .get_regs = cp_get_regs,
1580 .get_wol = cp_get_wol,
1581 .set_wol = cp_set_wol,
1582 .get_strings = cp_get_strings,
1583 .get_ethtool_stats = cp_get_ethtool_stats,
1584 .get_perm_addr = ethtool_op_get_perm_addr,
1585 .get_eeprom_len = cp_get_eeprom_len,
1586 .get_eeprom = cp_get_eeprom,
1587 .set_eeprom = cp_set_eeprom,
1588 };
1589
1590 static int cp_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
1591 {
1592 struct cp_private *cp = netdev_priv(dev);
1593 int rc;
1594 unsigned long flags;
1595
1596 if (!netif_running(dev))
1597 return -EINVAL;
1598
1599 spin_lock_irqsave(&cp->lock, flags);
1600 rc = generic_mii_ioctl(&cp->mii_if, if_mii(rq), cmd, NULL);
1601 spin_unlock_irqrestore(&cp->lock, flags);
1602 return rc;
1603 }
1604
1605 /* Serial EEPROM section. */
1606
1607 /* EEPROM_Ctrl bits. */
1608 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1609 #define EE_CS 0x08 /* EEPROM chip select. */
1610 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1611 #define EE_WRITE_0 0x00
1612 #define EE_WRITE_1 0x02
1613 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1614 #define EE_ENB (0x80 | EE_CS)
1615
1616 /* Delay between EEPROM clock transitions.
1617 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1618 */
1619
1620 #define eeprom_delay() readl(ee_addr)
1621
1622 /* The EEPROM commands include the alway-set leading bit. */
1623 #define EE_EXTEND_CMD (4)
1624 #define EE_WRITE_CMD (5)
1625 #define EE_READ_CMD (6)
1626 #define EE_ERASE_CMD (7)
1627
1628 #define EE_EWDS_ADDR (0)
1629 #define EE_WRAL_ADDR (1)
1630 #define EE_ERAL_ADDR (2)
1631 #define EE_EWEN_ADDR (3)
1632
1633 #define CP_EEPROM_MAGIC PCI_DEVICE_ID_REALTEK_8139
1634
1635 static void eeprom_cmd_start(void __iomem *ee_addr)
1636 {
1637 writeb (EE_ENB & ~EE_CS, ee_addr);
1638 writeb (EE_ENB, ee_addr);
1639 eeprom_delay ();
1640 }
1641
1642 static void eeprom_cmd(void __iomem *ee_addr, int cmd, int cmd_len)
1643 {
1644 int i;
1645
1646 /* Shift the command bits out. */
1647 for (i = cmd_len - 1; i >= 0; i--) {
1648 int dataval = (cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1649 writeb (EE_ENB | dataval, ee_addr);
1650 eeprom_delay ();
1651 writeb (EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
1652 eeprom_delay ();
1653 }
1654 writeb (EE_ENB, ee_addr);
1655 eeprom_delay ();
1656 }
1657
1658 static void eeprom_cmd_end(void __iomem *ee_addr)
1659 {
1660 writeb (~EE_CS, ee_addr);
1661 eeprom_delay ();
1662 }
1663
1664 static void eeprom_extend_cmd(void __iomem *ee_addr, int extend_cmd,
1665 int addr_len)
1666 {
1667 int cmd = (EE_EXTEND_CMD << addr_len) | (extend_cmd << (addr_len - 2));
1668
1669 eeprom_cmd_start(ee_addr);
1670 eeprom_cmd(ee_addr, cmd, 3 + addr_len);
1671 eeprom_cmd_end(ee_addr);
1672 }
1673
1674 static u16 read_eeprom (void __iomem *ioaddr, int location, int addr_len)
1675 {
1676 int i;
1677 u16 retval = 0;
1678 void __iomem *ee_addr = ioaddr + Cfg9346;
1679 int read_cmd = location | (EE_READ_CMD << addr_len);
1680
1681 eeprom_cmd_start(ee_addr);
1682 eeprom_cmd(ee_addr, read_cmd, 3 + addr_len);
1683
1684 for (i = 16; i > 0; i--) {
1685 writeb (EE_ENB | EE_SHIFT_CLK, ee_addr);
1686 eeprom_delay ();
1687 retval =
1688 (retval << 1) | ((readb (ee_addr) & EE_DATA_READ) ? 1 :
1689 0);
1690 writeb (EE_ENB, ee_addr);
1691 eeprom_delay ();
1692 }
1693
1694 eeprom_cmd_end(ee_addr);
1695
1696 return retval;
1697 }
1698
1699 static void write_eeprom(void __iomem *ioaddr, int location, u16 val,
1700 int addr_len)
1701 {
1702 int i;
1703 void __iomem *ee_addr = ioaddr + Cfg9346;
1704 int write_cmd = location | (EE_WRITE_CMD << addr_len);
1705
1706 eeprom_extend_cmd(ee_addr, EE_EWEN_ADDR, addr_len);
1707
1708 eeprom_cmd_start(ee_addr);
1709 eeprom_cmd(ee_addr, write_cmd, 3 + addr_len);
1710 eeprom_cmd(ee_addr, val, 16);
1711 eeprom_cmd_end(ee_addr);
1712
1713 eeprom_cmd_start(ee_addr);
1714 for (i = 0; i < 20000; i++)
1715 if (readb(ee_addr) & EE_DATA_READ)
1716 break;
1717 eeprom_cmd_end(ee_addr);
1718
1719 eeprom_extend_cmd(ee_addr, EE_EWDS_ADDR, addr_len);
1720 }
1721
1722 static int cp_get_eeprom_len(struct net_device *dev)
1723 {
1724 struct cp_private *cp = netdev_priv(dev);
1725 int size;
1726
1727 spin_lock_irq(&cp->lock);
1728 size = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 256 : 128;
1729 spin_unlock_irq(&cp->lock);
1730
1731 return size;
1732 }
1733
1734 static int cp_get_eeprom(struct net_device *dev,
1735 struct ethtool_eeprom *eeprom, u8 *data)
1736 {
1737 struct cp_private *cp = netdev_priv(dev);
1738 unsigned int addr_len;
1739 u16 val;
1740 u32 offset = eeprom->offset >> 1;
1741 u32 len = eeprom->len;
1742 u32 i = 0;
1743
1744 eeprom->magic = CP_EEPROM_MAGIC;
1745
1746 spin_lock_irq(&cp->lock);
1747
1748 addr_len = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 8 : 6;
1749
1750 if (eeprom->offset & 1) {
1751 val = read_eeprom(cp->regs, offset, addr_len);
1752 data[i++] = (u8)(val >> 8);
1753 offset++;
1754 }
1755
1756 while (i < len - 1) {
1757 val = read_eeprom(cp->regs, offset, addr_len);
1758 data[i++] = (u8)val;
1759 data[i++] = (u8)(val >> 8);
1760 offset++;
1761 }
1762
1763 if (i < len) {
1764 val = read_eeprom(cp->regs, offset, addr_len);
1765 data[i] = (u8)val;
1766 }
1767
1768 spin_unlock_irq(&cp->lock);
1769 return 0;
1770 }
1771
1772 static int cp_set_eeprom(struct net_device *dev,
1773 struct ethtool_eeprom *eeprom, u8 *data)
1774 {
1775 struct cp_private *cp = netdev_priv(dev);
1776 unsigned int addr_len;
1777 u16 val;
1778 u32 offset = eeprom->offset >> 1;
1779 u32 len = eeprom->len;
1780 u32 i = 0;
1781
1782 if (eeprom->magic != CP_EEPROM_MAGIC)
1783 return -EINVAL;
1784
1785 spin_lock_irq(&cp->lock);
1786
1787 addr_len = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 8 : 6;
1788
1789 if (eeprom->offset & 1) {
1790 val = read_eeprom(cp->regs, offset, addr_len) & 0xff;
1791 val |= (u16)data[i++] << 8;
1792 write_eeprom(cp->regs, offset, val, addr_len);
1793 offset++;
1794 }
1795
1796 while (i < len - 1) {
1797 val = (u16)data[i++];
1798 val |= (u16)data[i++] << 8;
1799 write_eeprom(cp->regs, offset, val, addr_len);
1800 offset++;
1801 }
1802
1803 if (i < len) {
1804 val = read_eeprom(cp->regs, offset, addr_len) & 0xff00;
1805 val |= (u16)data[i];
1806 write_eeprom(cp->regs, offset, val, addr_len);
1807 }
1808
1809 spin_unlock_irq(&cp->lock);
1810 return 0;
1811 }
1812
1813 /* Put the board into D3cold state and wait for WakeUp signal */
1814 static void cp_set_d3_state (struct cp_private *cp)
1815 {
1816 pci_enable_wake (cp->pdev, 0, 1); /* Enable PME# generation */
1817 pci_set_power_state (cp->pdev, PCI_D3hot);
1818 }
1819
1820 static int cp_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1821 {
1822 struct net_device *dev;
1823 struct cp_private *cp;
1824 int rc;
1825 void __iomem *regs;
1826 resource_size_t pciaddr;
1827 unsigned int addr_len, i, pci_using_dac;
1828 u8 pci_rev;
1829
1830 #ifndef MODULE
1831 static int version_printed;
1832 if (version_printed++ == 0)
1833 printk("%s", version);
1834 #endif
1835
1836 pci_read_config_byte(pdev, PCI_REVISION_ID, &pci_rev);
1837
1838 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
1839 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pci_rev < 0x20) {
1840 printk(KERN_ERR PFX "pci dev %s (id %04x:%04x rev %02x) is not an 8139C+ compatible chip\n",
1841 pci_name(pdev), pdev->vendor, pdev->device, pci_rev);
1842 printk(KERN_ERR PFX "Try the \"8139too\" driver instead.\n");
1843 return -ENODEV;
1844 }
1845
1846 dev = alloc_etherdev(sizeof(struct cp_private));
1847 if (!dev)
1848 return -ENOMEM;
1849 SET_MODULE_OWNER(dev);
1850 SET_NETDEV_DEV(dev, &pdev->dev);
1851
1852 cp = netdev_priv(dev);
1853 cp->pdev = pdev;
1854 cp->dev = dev;
1855 cp->msg_enable = (debug < 0 ? CP_DEF_MSG_ENABLE : debug);
1856 spin_lock_init (&cp->lock);
1857 cp->mii_if.dev = dev;
1858 cp->mii_if.mdio_read = mdio_read;
1859 cp->mii_if.mdio_write = mdio_write;
1860 cp->mii_if.phy_id = CP_INTERNAL_PHY;
1861 cp->mii_if.phy_id_mask = 0x1f;
1862 cp->mii_if.reg_num_mask = 0x1f;
1863 cp_set_rxbufsize(cp);
1864
1865 rc = pci_enable_device(pdev);
1866 if (rc)
1867 goto err_out_free;
1868
1869 rc = pci_set_mwi(pdev);
1870 if (rc)
1871 goto err_out_disable;
1872
1873 rc = pci_request_regions(pdev, DRV_NAME);
1874 if (rc)
1875 goto err_out_mwi;
1876
1877 pciaddr = pci_resource_start(pdev, 1);
1878 if (!pciaddr) {
1879 rc = -EIO;
1880 printk(KERN_ERR PFX "no MMIO resource for pci dev %s\n",
1881 pci_name(pdev));
1882 goto err_out_res;
1883 }
1884 if (pci_resource_len(pdev, 1) < CP_REGS_SIZE) {
1885 rc = -EIO;
1886 printk(KERN_ERR PFX "MMIO resource (%llx) too small on pci dev %s\n",
1887 (unsigned long long)pci_resource_len(pdev, 1), pci_name(pdev));
1888 goto err_out_res;
1889 }
1890
1891 /* Configure DMA attributes. */
1892 if ((sizeof(dma_addr_t) > 4) &&
1893 !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK) &&
1894 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1895 pci_using_dac = 1;
1896 } else {
1897 pci_using_dac = 0;
1898
1899 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1900 if (rc) {
1901 printk(KERN_ERR PFX "No usable DMA configuration, "
1902 "aborting.\n");
1903 goto err_out_res;
1904 }
1905 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1906 if (rc) {
1907 printk(KERN_ERR PFX "No usable consistent DMA configuration, "
1908 "aborting.\n");
1909 goto err_out_res;
1910 }
1911 }
1912
1913 cp->cpcmd = (pci_using_dac ? PCIDAC : 0) |
1914 PCIMulRW | RxChkSum | CpRxOn | CpTxOn;
1915
1916 regs = ioremap(pciaddr, CP_REGS_SIZE);
1917 if (!regs) {
1918 rc = -EIO;
1919 printk(KERN_ERR PFX "Cannot map PCI MMIO (%llx@%llx) on pci dev %s\n",
1920 (unsigned long long)pci_resource_len(pdev, 1),
1921 (unsigned long long)pciaddr, pci_name(pdev));
1922 goto err_out_res;
1923 }
1924 dev->base_addr = (unsigned long) regs;
1925 cp->regs = regs;
1926
1927 cp_stop_hw(cp);
1928
1929 /* read MAC address from EEPROM */
1930 addr_len = read_eeprom (regs, 0, 8) == 0x8129 ? 8 : 6;
1931 for (i = 0; i < 3; i++)
1932 ((u16 *) (dev->dev_addr))[i] =
1933 le16_to_cpu (read_eeprom (regs, i + 7, addr_len));
1934 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1935
1936 dev->open = cp_open;
1937 dev->stop = cp_close;
1938 dev->set_multicast_list = cp_set_rx_mode;
1939 dev->hard_start_xmit = cp_start_xmit;
1940 dev->get_stats = cp_get_stats;
1941 dev->do_ioctl = cp_ioctl;
1942 dev->poll = cp_rx_poll;
1943 #ifdef CONFIG_NET_POLL_CONTROLLER
1944 dev->poll_controller = cp_poll_controller;
1945 #endif
1946 dev->weight = 16; /* arbitrary? from NAPI_HOWTO.txt. */
1947 #ifdef BROKEN
1948 dev->change_mtu = cp_change_mtu;
1949 #endif
1950 dev->ethtool_ops = &cp_ethtool_ops;
1951 #if 0
1952 dev->tx_timeout = cp_tx_timeout;
1953 dev->watchdog_timeo = TX_TIMEOUT;
1954 #endif
1955
1956 #if CP_VLAN_TAG_USED
1957 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1958 dev->vlan_rx_register = cp_vlan_rx_register;
1959 dev->vlan_rx_kill_vid = cp_vlan_rx_kill_vid;
1960 #endif
1961
1962 if (pci_using_dac)
1963 dev->features |= NETIF_F_HIGHDMA;
1964
1965 #if 0 /* disabled by default until verified */
1966 dev->features |= NETIF_F_TSO;
1967 #endif
1968
1969 dev->irq = pdev->irq;
1970
1971 rc = register_netdev(dev);
1972 if (rc)
1973 goto err_out_iomap;
1974
1975 printk (KERN_INFO "%s: RTL-8139C+ at 0x%lx, "
1976 "%02x:%02x:%02x:%02x:%02x:%02x, "
1977 "IRQ %d\n",
1978 dev->name,
1979 dev->base_addr,
1980 dev->dev_addr[0], dev->dev_addr[1],
1981 dev->dev_addr[2], dev->dev_addr[3],
1982 dev->dev_addr[4], dev->dev_addr[5],
1983 dev->irq);
1984
1985 pci_set_drvdata(pdev, dev);
1986
1987 /* enable busmastering and memory-write-invalidate */
1988 pci_set_master(pdev);
1989
1990 if (cp->wol_enabled) cp_set_d3_state (cp);
1991
1992 return 0;
1993
1994 err_out_iomap:
1995 iounmap(regs);
1996 err_out_res:
1997 pci_release_regions(pdev);
1998 err_out_mwi:
1999 pci_clear_mwi(pdev);
2000 err_out_disable:
2001 pci_disable_device(pdev);
2002 err_out_free:
2003 free_netdev(dev);
2004 return rc;
2005 }
2006
2007 static void cp_remove_one (struct pci_dev *pdev)
2008 {
2009 struct net_device *dev = pci_get_drvdata(pdev);
2010 struct cp_private *cp = netdev_priv(dev);
2011
2012 BUG_ON(!dev);
2013 unregister_netdev(dev);
2014 iounmap(cp->regs);
2015 if (cp->wol_enabled) pci_set_power_state (pdev, PCI_D0);
2016 pci_release_regions(pdev);
2017 pci_clear_mwi(pdev);
2018 pci_disable_device(pdev);
2019 pci_set_drvdata(pdev, NULL);
2020 free_netdev(dev);
2021 }
2022
2023 #ifdef CONFIG_PM
2024 static int cp_suspend (struct pci_dev *pdev, pm_message_t state)
2025 {
2026 struct net_device *dev;
2027 struct cp_private *cp;
2028 unsigned long flags;
2029
2030 dev = pci_get_drvdata (pdev);
2031 cp = netdev_priv(dev);
2032
2033 if (!dev || !netif_running (dev)) return 0;
2034
2035 netif_device_detach (dev);
2036 netif_stop_queue (dev);
2037
2038 spin_lock_irqsave (&cp->lock, flags);
2039
2040 /* Disable Rx and Tx */
2041 cpw16 (IntrMask, 0);
2042 cpw8 (Cmd, cpr8 (Cmd) & (~RxOn | ~TxOn));
2043
2044 spin_unlock_irqrestore (&cp->lock, flags);
2045
2046 pci_save_state(pdev);
2047 pci_enable_wake(pdev, pci_choose_state(pdev, state), cp->wol_enabled);
2048 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2049
2050 return 0;
2051 }
2052
2053 static int cp_resume (struct pci_dev *pdev)
2054 {
2055 struct net_device *dev = pci_get_drvdata (pdev);
2056 struct cp_private *cp = netdev_priv(dev);
2057 unsigned long flags;
2058
2059 if (!netif_running(dev))
2060 return 0;
2061
2062 netif_device_attach (dev);
2063
2064 pci_set_power_state(pdev, PCI_D0);
2065 pci_restore_state(pdev);
2066 pci_enable_wake(pdev, PCI_D0, 0);
2067
2068 /* FIXME: sh*t may happen if the Rx ring buffer is depleted */
2069 cp_init_rings_index (cp);
2070 cp_init_hw (cp);
2071 netif_start_queue (dev);
2072
2073 spin_lock_irqsave (&cp->lock, flags);
2074
2075 mii_check_media(&cp->mii_if, netif_msg_link(cp), FALSE);
2076
2077 spin_unlock_irqrestore (&cp->lock, flags);
2078
2079 return 0;
2080 }
2081 #endif /* CONFIG_PM */
2082
2083 static struct pci_driver cp_driver = {
2084 .name = DRV_NAME,
2085 .id_table = cp_pci_tbl,
2086 .probe = cp_init_one,
2087 .remove = cp_remove_one,
2088 #ifdef CONFIG_PM
2089 .resume = cp_resume,
2090 .suspend = cp_suspend,
2091 #endif
2092 };
2093
2094 static int __init cp_init (void)
2095 {
2096 #ifdef MODULE
2097 printk("%s", version);
2098 #endif
2099 return pci_module_init (&cp_driver);
2100 }
2101
2102 static void __exit cp_exit (void)
2103 {
2104 pci_unregister_driver (&cp_driver);
2105 }
2106
2107 module_init(cp_init);
2108 module_exit(cp_exit);
Software Suspend 2 for 2.6.18.y (mirror)