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[PATCH] sgiioc4: fixup use of mmio ops
[linux-2.6/suspend2-2.6.18.git] / drivers / ide / pci / alim15x3.c
blob351dab2fcacf730f0c070cf772383270efa186ab
1 /*
2 * linux/drivers/ide/pci/alim15x3.c Version 0.17 2003/01/02
3 *
4 * Copyright (C) 1998-2000 Michel Aubry, Maintainer
5 * Copyright (C) 1998-2000 Andrzej Krzysztofowicz, Maintainer
6 * Copyright (C) 1999-2000 CJ, cjtsai@ali.com.tw, Maintainer
7 *
8 * Copyright (C) 1998-2000 Andre Hedrick (andre@linux-ide.org)
9 * May be copied or modified under the terms of the GNU General Public License
10 * Copyright (C) 2002 Alan Cox <alan@redhat.com>
11 * ALi (now ULi M5228) support by Clear Zhang <Clear.Zhang@ali.com.tw>
12 *
13 * (U)DMA capable version of ali 1533/1543(C), 1535(D)
14 *
15 **********************************************************************
16 * 9/7/99 --Parts from the above author are included and need to be
17 * converted into standard interface, once I finish the thought.
18 *
19 * Recent changes
20 * Don't use LBA48 mode on ALi <= 0xC4
21 * Don't poke 0x79 with a non ALi northbridge
22 * Don't flip undefined bits on newer chipsets (fix Fujitsu laptop hang)
23 * Allow UDMA6 on revisions > 0xC4
24 *
25 * Documentation
26 * Chipset documentation available under NDA only
27 *
28 */
29
30 #include <linux/module.h>
31 #include <linux/types.h>
32 #include <linux/kernel.h>
33 #include <linux/pci.h>
34 #include <linux/delay.h>
35 #include <linux/hdreg.h>
36 #include <linux/ide.h>
37 #include <linux/init.h>
38
39 #include <asm/io.h>
40
41 #define DISPLAY_ALI_TIMINGS
42
43 /*
44 * ALi devices are not plug in. Otherwise these static values would
45 * need to go. They ought to go away anyway
46 */
47
48 static u8 m5229_revision;
49 static u8 chip_is_1543c_e;
50 static struct pci_dev *isa_dev;
51
52 #if defined(DISPLAY_ALI_TIMINGS) && defined(CONFIG_PROC_FS)
53 #include <linux/stat.h>
54 #include <linux/proc_fs.h>
55
56 static u8 ali_proc = 0;
57
58 static struct pci_dev *bmide_dev;
59
60 static char *fifo[4] = {
61 "FIFO Off",
62 "FIFO On ",
63 "DMA mode",
64 "PIO mode" };
65
66 static char *udmaT[8] = {
67 "1.5T",
68 " 2T",
69 "2.5T",
70 " 3T",
71 "3.5T",
72 " 4T",
73 " 6T",
74 " 8T"
75 };
76
77 static char *channel_status[8] = {
78 "OK ",
79 "busy ",
80 "DRQ ",
81 "DRQ busy ",
82 "error ",
83 "error busy ",
84 "error DRQ ",
85 "error DRQ busy"
86 };
87
88 /**
89 * ali_get_info - generate proc file for ALi IDE
90 * @buffer: buffer to fill
91 * @addr: address of user start in buffer
92 * @offset: offset into 'file'
93 * @count: buffer count
94 *
95 * Walks the Ali devices and outputs summary data on the tuning and
96 * anything else that will help with debugging
97 */
98
99 static int ali_get_info (char *buffer, char **addr, off_t offset, int count)
100 {
101 unsigned long bibma;
102 u8 reg53h, reg5xh, reg5yh, reg5xh1, reg5yh1, c0, c1, rev, tmp;
103 char *q, *p = buffer;
104
105 /* fetch rev. */
106 pci_read_config_byte(bmide_dev, 0x08, &rev);
107 if (rev >= 0xc1) /* M1543C or newer */
108 udmaT[7] = " ???";
109 else
110 fifo[3] = " ??? ";
111
112 /* first fetch bibma: */
113
114 bibma = pci_resource_start(bmide_dev, 4);
115
116 /*
117 * at that point bibma+0x2 et bibma+0xa are byte
118 * registers to investigate:
119 */
120 c0 = inb(bibma + 0x02);
121 c1 = inb(bibma + 0x0a);
122
123 p += sprintf(p,
124 "\n Ali M15x3 Chipset.\n");
125 p += sprintf(p,
126 " ------------------\n");
127 pci_read_config_byte(bmide_dev, 0x78, &reg53h);
128 p += sprintf(p, "PCI Clock: %d.\n", reg53h);
129
130 pci_read_config_byte(bmide_dev, 0x53, &reg53h);
131 p += sprintf(p,
132 "CD_ROM FIFO:%s, CD_ROM DMA:%s\n",
133 (reg53h & 0x02) ? "Yes" : "No ",
134 (reg53h & 0x01) ? "Yes" : "No " );
135 pci_read_config_byte(bmide_dev, 0x74, &reg53h);
136 p += sprintf(p,
137 "FIFO Status: contains %d Words, runs%s%s\n\n",
138 (reg53h & 0x3f),
139 (reg53h & 0x40) ? " OVERWR" : "",
140 (reg53h & 0x80) ? " OVERRD." : "." );
141
142 p += sprintf(p,
143 "-------------------primary channel"
144 "-------------------secondary channel"
145 "---------\n\n");
146
147 pci_read_config_byte(bmide_dev, 0x09, &reg53h);
148 p += sprintf(p,
149 "channel status: %s"
150 " %s\n",
151 (reg53h & 0x20) ? "On " : "Off",
152 (reg53h & 0x10) ? "On " : "Off" );
153
154 p += sprintf(p,
155 "both channels togth: %s"
156 " %s\n",
157 (c0&0x80) ? "No " : "Yes",
158 (c1&0x80) ? "No " : "Yes" );
159
160 pci_read_config_byte(bmide_dev, 0x76, &reg53h);
161 p += sprintf(p,
162 "Channel state: %s %s\n",
163 channel_status[reg53h & 0x07],
164 channel_status[(reg53h & 0x70) >> 4] );
165
166 pci_read_config_byte(bmide_dev, 0x58, &reg5xh);
167 pci_read_config_byte(bmide_dev, 0x5c, &reg5yh);
168 p += sprintf(p,
169 "Add. Setup Timing: %dT"
170 " %dT\n",
171 (reg5xh & 0x07) ? (reg5xh & 0x07) : 8,
172 (reg5yh & 0x07) ? (reg5yh & 0x07) : 8 );
173
174 pci_read_config_byte(bmide_dev, 0x59, &reg5xh);
175 pci_read_config_byte(bmide_dev, 0x5d, &reg5yh);
176 p += sprintf(p,
177 "Command Act. Count: %dT"
178 " %dT\n"
179 "Command Rec. Count: %dT"
180 " %dT\n\n",
181 (reg5xh & 0x70) ? ((reg5xh & 0x70) >> 4) : 8,
182 (reg5yh & 0x70) ? ((reg5yh & 0x70) >> 4) : 8,
183 (reg5xh & 0x0f) ? (reg5xh & 0x0f) : 16,
184 (reg5yh & 0x0f) ? (reg5yh & 0x0f) : 16 );
185
186 p += sprintf(p,
187 "----------------drive0-----------drive1"
188 "------------drive0-----------drive1------\n\n");
189 p += sprintf(p,
190 "DMA enabled: %s %s"
191 " %s %s\n",
192 (c0&0x20) ? "Yes" : "No ",
193 (c0&0x40) ? "Yes" : "No ",
194 (c1&0x20) ? "Yes" : "No ",
195 (c1&0x40) ? "Yes" : "No " );
196
197 pci_read_config_byte(bmide_dev, 0x54, &reg5xh);
198 pci_read_config_byte(bmide_dev, 0x55, &reg5yh);
199 q = "FIFO threshold: %2d Words %2d Words"
200 " %2d Words %2d Words\n";
201 if (rev < 0xc1) {
202 if ((rev == 0x20) &&
203 (pci_read_config_byte(bmide_dev, 0x4f, &tmp), (tmp &= 0x20))) {
204 p += sprintf(p, q, 8, 8, 8, 8);
205 } else {
206 p += sprintf(p, q,
207 (reg5xh & 0x03) + 12,
208 ((reg5xh & 0x30)>>4) + 12,
209 (reg5yh & 0x03) + 12,
210 ((reg5yh & 0x30)>>4) + 12 );
211 }
212 } else {
213 int t1 = (tmp = (reg5xh & 0x03)) ? (tmp << 3) : 4;
214 int t2 = (tmp = ((reg5xh & 0x30)>>4)) ? (tmp << 3) : 4;
215 int t3 = (tmp = (reg5yh & 0x03)) ? (tmp << 3) : 4;
216 int t4 = (tmp = ((reg5yh & 0x30)>>4)) ? (tmp << 3) : 4;
217 p += sprintf(p, q, t1, t2, t3, t4);
218 }
219
220 #if 0
221 p += sprintf(p,
222 "FIFO threshold: %2d Words %2d Words"
223 " %2d Words %2d Words\n",
224 (reg5xh & 0x03) + 12,
225 ((reg5xh & 0x30)>>4) + 12,
226 (reg5yh & 0x03) + 12,
227 ((reg5yh & 0x30)>>4) + 12 );
228 #endif
229
230 p += sprintf(p,
231 "FIFO mode: %s %s %s %s\n",
232 fifo[((reg5xh & 0x0c) >> 2)],
233 fifo[((reg5xh & 0xc0) >> 6)],
234 fifo[((reg5yh & 0x0c) >> 2)],
235 fifo[((reg5yh & 0xc0) >> 6)] );
236
237 pci_read_config_byte(bmide_dev, 0x5a, &reg5xh);
238 pci_read_config_byte(bmide_dev, 0x5b, &reg5xh1);
239 pci_read_config_byte(bmide_dev, 0x5e, &reg5yh);
240 pci_read_config_byte(bmide_dev, 0x5f, &reg5yh1);
241
242 p += sprintf(p,/*
243 "------------------drive0-----------drive1"
244 "------------drive0-----------drive1------\n")*/
245 "Dt RW act. Cnt %2dT %2dT"
246 " %2dT %2dT\n"
247 "Dt RW rec. Cnt %2dT %2dT"
248 " %2dT %2dT\n\n",
249 (reg5xh & 0x70) ? ((reg5xh & 0x70) >> 4) : 8,
250 (reg5xh1 & 0x70) ? ((reg5xh1 & 0x70) >> 4) : 8,
251 (reg5yh & 0x70) ? ((reg5yh & 0x70) >> 4) : 8,
252 (reg5yh1 & 0x70) ? ((reg5yh1 & 0x70) >> 4) : 8,
253 (reg5xh & 0x0f) ? (reg5xh & 0x0f) : 16,
254 (reg5xh1 & 0x0f) ? (reg5xh1 & 0x0f) : 16,
255 (reg5yh & 0x0f) ? (reg5yh & 0x0f) : 16,
256 (reg5yh1 & 0x0f) ? (reg5yh1 & 0x0f) : 16 );
257
258 p += sprintf(p,
259 "-----------------------------------UDMA Timings"
260 "--------------------------------\n\n");
261
262 pci_read_config_byte(bmide_dev, 0x56, &reg5xh);
263 pci_read_config_byte(bmide_dev, 0x57, &reg5yh);
264 p += sprintf(p,
265 "UDMA: %s %s"
266 " %s %s\n"
267 "UDMA timings: %s %s"
268 " %s %s\n\n",
269 (reg5xh & 0x08) ? "OK" : "No",
270 (reg5xh & 0x80) ? "OK" : "No",
271 (reg5yh & 0x08) ? "OK" : "No",
272 (reg5yh & 0x80) ? "OK" : "No",
273 udmaT[(reg5xh & 0x07)],
274 udmaT[(reg5xh & 0x70) >> 4],
275 udmaT[reg5yh & 0x07],
276 udmaT[(reg5yh & 0x70) >> 4] );
277
278 return p-buffer; /* => must be less than 4k! */
279 }
280 #endif /* defined(DISPLAY_ALI_TIMINGS) && defined(CONFIG_PROC_FS) */
281
282 /**
283 * ali15x3_tune_drive - set up a drive
284 * @drive: drive to tune
285 * @pio: unused
286 *
287 * Select the best PIO timing for the drive in question. Then
288 * program the controller for this drive set up
289 */
290
291 static void ali15x3_tune_drive (ide_drive_t *drive, u8 pio)
292 {
293 ide_pio_data_t d;
294 ide_hwif_t *hwif = HWIF(drive);
295 struct pci_dev *dev = hwif->pci_dev;
296 int s_time, a_time, c_time;
297 u8 s_clc, a_clc, r_clc;
298 unsigned long flags;
299 int bus_speed = system_bus_clock();
300 int port = hwif->channel ? 0x5c : 0x58;
301 int portFIFO = hwif->channel ? 0x55 : 0x54;
302 u8 cd_dma_fifo = 0;
303 int unit = drive->select.b.unit & 1;
304
305 pio = ide_get_best_pio_mode(drive, pio, 5, &d);
306 s_time = ide_pio_timings[pio].setup_time;
307 a_time = ide_pio_timings[pio].active_time;
308 if ((s_clc = (s_time * bus_speed + 999) / 1000) >= 8)
309 s_clc = 0;
310 if ((a_clc = (a_time * bus_speed + 999) / 1000) >= 8)
311 a_clc = 0;
312 c_time = ide_pio_timings[pio].cycle_time;
313
314 #if 0
315 if ((r_clc = ((c_time - s_time - a_time) * bus_speed + 999) / 1000) >= 16)
316 r_clc = 0;
317 #endif
318
319 if (!(r_clc = (c_time * bus_speed + 999) / 1000 - a_clc - s_clc)) {
320 r_clc = 1;
321 } else {
322 if (r_clc >= 16)
323 r_clc = 0;
324 }
325 local_irq_save(flags);
326
327 /*
328 * PIO mode => ATA FIFO on, ATAPI FIFO off
329 */
330 pci_read_config_byte(dev, portFIFO, &cd_dma_fifo);
331 if (drive->media==ide_disk) {
332 if (unit) {
333 pci_write_config_byte(dev, portFIFO, (cd_dma_fifo & 0x0F) | 0x50);
334 } else {
335 pci_write_config_byte(dev, portFIFO, (cd_dma_fifo & 0xF0) | 0x05);
336 }
337 } else {
338 if (unit) {
339 pci_write_config_byte(dev, portFIFO, cd_dma_fifo & 0x0F);
340 } else {
341 pci_write_config_byte(dev, portFIFO, cd_dma_fifo & 0xF0);
342 }
343 }
344
345 pci_write_config_byte(dev, port, s_clc);
346 pci_write_config_byte(dev, port+drive->select.b.unit+2, (a_clc << 4) | r_clc);
347 local_irq_restore(flags);
348
349 /*
350 * setup active rec
351 * { 70, 165, 365 }, PIO Mode 0
352 * { 50, 125, 208 }, PIO Mode 1
353 * { 30, 100, 110 }, PIO Mode 2
354 * { 30, 80, 70 }, PIO Mode 3 with IORDY
355 * { 25, 70, 25 }, PIO Mode 4 with IORDY ns
356 * { 20, 50, 30 } PIO Mode 5 with IORDY (nonstandard)
357 */
358
359 }
360
361 /**
362 * ali15x3_can_ultra - check for ultra DMA support
363 * @drive: drive to do the check
364 *
365 * Check the drive and controller revisions. Return 0 if UDMA is
366 * not available, or 1 if UDMA can be used. The actual rules for
367 * the ALi are
368 * No UDMA on revisions <= 0x20
369 * Disk only for revisions < 0xC2
370 * Not WDC drives for revisions < 0xC2
371 *
372 * FIXME: WDC ifdef needs to die
373 */
374
375 static u8 ali15x3_can_ultra (ide_drive_t *drive)
376 {
377 #ifndef CONFIG_WDC_ALI15X3
378 struct hd_driveid *id = drive->id;
379 #endif /* CONFIG_WDC_ALI15X3 */
380
381 if (m5229_revision <= 0x20) {
382 return 0;
383 } else if ((m5229_revision < 0xC2) &&
384 #ifndef CONFIG_WDC_ALI15X3
385 ((chip_is_1543c_e && strstr(id->model, "WDC ")) ||
386 (drive->media!=ide_disk))) {
387 #else /* CONFIG_WDC_ALI15X3 */
388 (drive->media!=ide_disk)) {
389 #endif /* CONFIG_WDC_ALI15X3 */
390 return 0;
391 } else {
392 return 1;
393 }
394 }
395
396 /**
397 * ali15x3_ratemask - generate DMA mode list
398 * @drive: drive to compute against
399 *
400 * Generate a list of the available DMA modes for the drive.
401 * FIXME: this function contains lots of bogus masking we can dump
402 *
403 * Return the highest available mode (UDMA33, UDMA66, UDMA100,..)
404 */
405
406 static u8 ali15x3_ratemask (ide_drive_t *drive)
407 {
408 u8 mode = 0, can_ultra = ali15x3_can_ultra(drive);
409
410 if (m5229_revision > 0xC4 && can_ultra) {
411 mode = 4;
412 } else if (m5229_revision == 0xC4 && can_ultra) {
413 mode = 3;
414 } else if (m5229_revision >= 0xC2 && can_ultra) {
415 mode = 2;
416 } else if (can_ultra) {
417 return 1;
418 } else {
419 return 0;
420 }
421
422 /*
423 * If the drive sees no suitable cable then UDMA 33
424 * is the highest permitted mode
425 */
426
427 if (!eighty_ninty_three(drive))
428 mode = min(mode, (u8)1);
429 return mode;
430 }
431
432 /**
433 * ali15x3_tune_chipset - set up chiset for new speed
434 * @drive: drive to configure for
435 * @xferspeed: desired speed
436 *
437 * Configure the hardware for the desired IDE transfer mode.
438 * We also do the needed drive configuration through helpers
439 */
440
441 static int ali15x3_tune_chipset (ide_drive_t *drive, u8 xferspeed)
442 {
443 ide_hwif_t *hwif = HWIF(drive);
444 struct pci_dev *dev = hwif->pci_dev;
445 u8 speed = ide_rate_filter(ali15x3_ratemask(drive), xferspeed);
446 u8 speed1 = speed;
447 u8 unit = (drive->select.b.unit & 0x01);
448 u8 tmpbyte = 0x00;
449 int m5229_udma = (hwif->channel) ? 0x57 : 0x56;
450
451 if (speed == XFER_UDMA_6)
452 speed1 = 0x47;
453
454 if (speed < XFER_UDMA_0) {
455 u8 ultra_enable = (unit) ? 0x7f : 0xf7;
456 /*
457 * clear "ultra enable" bit
458 */
459 pci_read_config_byte(dev, m5229_udma, &tmpbyte);
460 tmpbyte &= ultra_enable;
461 pci_write_config_byte(dev, m5229_udma, tmpbyte);
462
463 if (speed < XFER_SW_DMA_0)
464 ali15x3_tune_drive(drive, speed);
465 } else {
466 pci_read_config_byte(dev, m5229_udma, &tmpbyte);
467 tmpbyte &= (0x0f << ((1-unit) << 2));
468 /*
469 * enable ultra dma and set timing
470 */
471 tmpbyte |= ((0x08 | ((4-speed1)&0x07)) << (unit << 2));
472 pci_write_config_byte(dev, m5229_udma, tmpbyte);
473 if (speed >= XFER_UDMA_3) {
474 pci_read_config_byte(dev, 0x4b, &tmpbyte);
475 tmpbyte |= 1;
476 pci_write_config_byte(dev, 0x4b, tmpbyte);
477 }
478 }
479 return (ide_config_drive_speed(drive, speed));
480 }
481
482
483 /**
484 * config_chipset_for_dma - set up DMA mode
485 * @drive: drive to configure for
486 *
487 * Place a drive into DMA mode and tune the chipset for
488 * the selected speed.
489 *
490 * Returns true if DMA mode can be used
491 */
492
493 static int config_chipset_for_dma (ide_drive_t *drive)
494 {
495 u8 speed = ide_dma_speed(drive, ali15x3_ratemask(drive));
496
497 if (!(speed))
498 return 0;
499
500 (void) ali15x3_tune_chipset(drive, speed);
501 return ide_dma_enable(drive);
502 }
503
504 /**
505 * ali15x3_config_drive_for_dma - configure for DMA
506 * @drive: drive to configure
507 *
508 * Configure a drive for DMA operation. If DMA is not possible we
509 * drop the drive into PIO mode instead.
510 *
511 * FIXME: exactly what are we trying to return here
512 */
513
514 static int ali15x3_config_drive_for_dma(ide_drive_t *drive)
515 {
516 ide_hwif_t *hwif = HWIF(drive);
517 struct hd_driveid *id = drive->id;
518
519 if ((m5229_revision<=0x20) && (drive->media!=ide_disk))
520 return hwif->ide_dma_off_quietly(drive);
521
522 drive->init_speed = 0;
523
524 if ((id != NULL) && ((id->capability & 1) != 0) && drive->autodma) {
525 /* Consult the list of known "bad" drives */
526 if (__ide_dma_bad_drive(drive))
527 goto ata_pio;
528 if ((id->field_valid & 4) && (m5229_revision >= 0xC2)) {
529 if (id->dma_ultra & hwif->ultra_mask) {
530 /* Force if Capable UltraDMA */
531 int dma = config_chipset_for_dma(drive);
532 if ((id->field_valid & 2) && !dma)
533 goto try_dma_modes;
534 }
535 } else if (id->field_valid & 2) {
536 try_dma_modes:
537 if ((id->dma_mword & hwif->mwdma_mask) ||
538 (id->dma_1word & hwif->swdma_mask)) {
539 /* Force if Capable regular DMA modes */
540 if (!config_chipset_for_dma(drive))
541 goto no_dma_set;
542 }
543 } else if (__ide_dma_good_drive(drive) &&
544 (id->eide_dma_time < 150)) {
545 /* Consult the list of known "good" drives */
546 if (!config_chipset_for_dma(drive))
547 goto no_dma_set;
548 } else {
549 goto ata_pio;
550 }
551 } else {
552 ata_pio:
553 hwif->tuneproc(drive, 255);
554 no_dma_set:
555 return hwif->ide_dma_off_quietly(drive);
556 }
557 return hwif->ide_dma_on(drive);
558 }
559
560 /**
561 * ali15x3_dma_setup - begin a DMA phase
562 * @drive: target device
563 *
564 * Returns 1 if the DMA cannot be performed, zero on success.
565 */
566
567 static int ali15x3_dma_setup(ide_drive_t *drive)
568 {
569 if (m5229_revision < 0xC2 && drive->media != ide_disk) {
570 if (rq_data_dir(drive->hwif->hwgroup->rq))
571 return 1; /* try PIO instead of DMA */
572 }
573 return ide_dma_setup(drive);
574 }
575
576 /**
577 * init_chipset_ali15x3 - Initialise an ALi IDE controller
578 * @dev: PCI device
579 * @name: Name of the controller
580 *
581 * This function initializes the ALI IDE controller and where
582 * appropriate also sets up the 1533 southbridge.
583 */
584
585 static unsigned int __devinit init_chipset_ali15x3 (struct pci_dev *dev, const char *name)
586 {
587 unsigned long flags;
588 u8 tmpbyte;
589 struct pci_dev *north = pci_find_slot(0, PCI_DEVFN(0,0));
590
591 pci_read_config_byte(dev, PCI_REVISION_ID, &m5229_revision);
592
593 isa_dev = pci_find_device(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, NULL);
594
595 #if defined(DISPLAY_ALI_TIMINGS) && defined(CONFIG_PROC_FS)
596 if (!ali_proc) {
597 ali_proc = 1;
598 bmide_dev = dev;
599 ide_pci_create_host_proc("ali", ali_get_info);
600 }
601 #endif /* defined(DISPLAY_ALI_TIMINGS) && defined(CONFIG_PROC_FS) */
602
603 local_irq_save(flags);
604
605 if (m5229_revision < 0xC2) {
606 /*
607 * revision 0x20 (1543-E, 1543-F)
608 * revision 0xC0, 0xC1 (1543C-C, 1543C-D, 1543C-E)
609 * clear CD-ROM DMA write bit, m5229, 0x4b, bit 7
610 */
611 pci_read_config_byte(dev, 0x4b, &tmpbyte);
612 /*
613 * clear bit 7
614 */
615 pci_write_config_byte(dev, 0x4b, tmpbyte & 0x7F);
616 local_irq_restore(flags);
617 return 0;
618 }
619
620 /*
621 * 1543C-B?, 1535, 1535D, 1553
622 * Note 1: not all "motherboard" support this detection
623 * Note 2: if no udma 66 device, the detection may "error".
624 * but in this case, we will not set the device to
625 * ultra 66, the detection result is not important
626 */
627
628 /*
629 * enable "Cable Detection", m5229, 0x4b, bit3
630 */
631 pci_read_config_byte(dev, 0x4b, &tmpbyte);
632 pci_write_config_byte(dev, 0x4b, tmpbyte | 0x08);
633
634 /*
635 * We should only tune the 1533 enable if we are using an ALi
636 * North bridge. We might have no north found on some zany
637 * box without a device at 0:0.0. The ALi bridge will be at
638 * 0:0.0 so if we didn't find one we know what is cooking.
639 */
640 if (north && north->vendor != PCI_VENDOR_ID_AL) {
641 local_irq_restore(flags);
642 return 0;
643 }
644
645 if (m5229_revision < 0xC5 && isa_dev)
646 {
647 /*
648 * set south-bridge's enable bit, m1533, 0x79
649 */
650
651 pci_read_config_byte(isa_dev, 0x79, &tmpbyte);
652 if (m5229_revision == 0xC2) {
653 /*
654 * 1543C-B0 (m1533, 0x79, bit 2)
655 */
656 pci_write_config_byte(isa_dev, 0x79, tmpbyte | 0x04);
657 } else if (m5229_revision >= 0xC3) {
658 /*
659 * 1553/1535 (m1533, 0x79, bit 1)
660 */
661 pci_write_config_byte(isa_dev, 0x79, tmpbyte | 0x02);
662 }
663 }
664 local_irq_restore(flags);
665 return 0;
666 }
667
668 /**
669 * ata66_ali15x3 - check for UDMA 66 support
670 * @hwif: IDE interface
671 *
672 * This checks if the controller and the cable are capable
673 * of UDMA66 transfers. It doesn't check the drives.
674 * But see note 2 below!
675 *
676 * FIXME: frobs bits that are not defined on newer ALi devicea
677 */
678
679 static unsigned int __devinit ata66_ali15x3 (ide_hwif_t *hwif)
680 {
681 struct pci_dev *dev = hwif->pci_dev;
682 unsigned int ata66 = 0;
683 u8 cable_80_pin[2] = { 0, 0 };
684
685 unsigned long flags;
686 u8 tmpbyte;
687
688 local_irq_save(flags);
689
690 if (m5229_revision >= 0xC2) {
691 /*
692 * Ultra66 cable detection (from Host View)
693 * m5229, 0x4a, bit0: primary, bit1: secondary 80 pin
694 */
695 pci_read_config_byte(dev, 0x4a, &tmpbyte);
696 /*
697 * 0x4a, bit0 is 0 => primary channel
698 * has 80-pin (from host view)
699 */
700 if (!(tmpbyte & 0x01)) cable_80_pin[0] = 1;
701 /*
702 * 0x4a, bit1 is 0 => secondary channel
703 * has 80-pin (from host view)
704 */
705 if (!(tmpbyte & 0x02)) cable_80_pin[1] = 1;
706 /*
707 * Allow ata66 if cable of current channel has 80 pins
708 */
709 ata66 = (hwif->channel)?cable_80_pin[1]:cable_80_pin[0];
710 } else {
711 /*
712 * check m1533, 0x5e, bit 1~4 == 1001 => & 00011110 = 00010010
713 */
714 pci_read_config_byte(isa_dev, 0x5e, &tmpbyte);
715 chip_is_1543c_e = ((tmpbyte & 0x1e) == 0x12) ? 1: 0;
716 }
717
718 /*
719 * CD_ROM DMA on (m5229, 0x53, bit0)
720 * Enable this bit even if we want to use PIO
721 * PIO FIFO off (m5229, 0x53, bit1)
722 * The hardware will use 0x54h and 0x55h to control PIO FIFO
723 * (Not on later devices it seems)
724 *
725 * 0x53 changes meaning on later revs - we must no touch
726 * bit 1 on them. Need to check if 0x20 is the right break
727 */
728
729 pci_read_config_byte(dev, 0x53, &tmpbyte);
730
731 if(m5229_revision <= 0x20)
732 tmpbyte = (tmpbyte & (~0x02)) | 0x01;
733 else if (m5229_revision == 0xc7)
734 tmpbyte |= 0x03;
735 else
736 tmpbyte |= 0x01;
737
738 pci_write_config_byte(dev, 0x53, tmpbyte);
739
740 local_irq_restore(flags);
741
742 return(ata66);
743 }
744
745 /**
746 * init_hwif_common_ali15x3 - Set up ALI IDE hardware
747 * @hwif: IDE interface
748 *
749 * Initialize the IDE structure side of the ALi 15x3 driver.
750 */
751
752 static void __devinit init_hwif_common_ali15x3 (ide_hwif_t *hwif)
753 {
754 hwif->autodma = 0;
755 hwif->tuneproc = &ali15x3_tune_drive;
756 hwif->speedproc = &ali15x3_tune_chipset;
757
758 /* don't use LBA48 DMA on ALi devices before rev 0xC5 */
759 hwif->no_lba48_dma = (m5229_revision <= 0xC4) ? 1 : 0;
760
761 if (!hwif->dma_base) {
762 hwif->drives[0].autotune = 1;
763 hwif->drives[1].autotune = 1;
764 return;
765 }
766
767 hwif->atapi_dma = 1;
768
769 if (m5229_revision > 0x20)
770 hwif->ultra_mask = 0x7f;
771 hwif->mwdma_mask = 0x07;
772 hwif->swdma_mask = 0x07;
773
774 if (m5229_revision >= 0x20) {
775 /*
776 * M1543C or newer for DMAing
777 */
778 hwif->ide_dma_check = &ali15x3_config_drive_for_dma;
779 hwif->dma_setup = &ali15x3_dma_setup;
780 if (!noautodma)
781 hwif->autodma = 1;
782 if (!(hwif->udma_four))
783 hwif->udma_four = ata66_ali15x3(hwif);
784 }
785 hwif->drives[0].autodma = hwif->autodma;
786 hwif->drives[1].autodma = hwif->autodma;
787 }
788
789 /**
790 * init_hwif_ali15x3 - Initialize the ALI IDE x86 stuff
791 * @hwif: interface to configure
792 *
793 * Obtain the IRQ tables for an ALi based IDE solution on the PC
794 * class platforms. This part of the code isn't applicable to the
795 * Sparc systems
796 */
797
798 static void __devinit init_hwif_ali15x3 (ide_hwif_t *hwif)
799 {
800 u8 ideic, inmir;
801 s8 irq_routing_table[] = { -1, 9, 3, 10, 4, 5, 7, 6,
802 1, 11, 0, 12, 0, 14, 0, 15 };
803 int irq = -1;
804
805 if (hwif->pci_dev->device == PCI_DEVICE_ID_AL_M5229)
806 hwif->irq = hwif->channel ? 15 : 14;
807
808 if (isa_dev) {
809 /*
810 * read IDE interface control
811 */
812 pci_read_config_byte(isa_dev, 0x58, &ideic);
813
814 /* bit0, bit1 */
815 ideic = ideic & 0x03;
816
817 /* get IRQ for IDE Controller */
818 if ((hwif->channel && ideic == 0x03) ||
819 (!hwif->channel && !ideic)) {
820 /*
821 * get SIRQ1 routing table
822 */
823 pci_read_config_byte(isa_dev, 0x44, &inmir);
824 inmir = inmir & 0x0f;
825 irq = irq_routing_table[inmir];
826 } else if (hwif->channel && !(ideic & 0x01)) {
827 /*
828 * get SIRQ2 routing table
829 */
830 pci_read_config_byte(isa_dev, 0x75, &inmir);
831 inmir = inmir & 0x0f;
832 irq = irq_routing_table[inmir];
833 }
834 if(irq >= 0)
835 hwif->irq = irq;
836 }
837
838 init_hwif_common_ali15x3(hwif);
839 }
840
841 /**
842 * init_dma_ali15x3 - set up DMA on ALi15x3
843 * @hwif: IDE interface
844 * @dmabase: DMA interface base PCI address
845 *
846 * Set up the DMA functionality on the ALi 15x3. For the ALi
847 * controllers this is generic so we can let the generic code do
848 * the actual work.
849 */
850
851 static void __devinit init_dma_ali15x3 (ide_hwif_t *hwif, unsigned long dmabase)
852 {
853 if (m5229_revision < 0x20)
854 return;
855 if (!(hwif->channel))
856 hwif->OUTB(hwif->INB(dmabase+2) & 0x60, dmabase+2);
857 ide_setup_dma(hwif, dmabase, 8);
858 }
859
860 static ide_pci_device_t ali15x3_chipset __devinitdata = {
861 .name = "ALI15X3",
862 .init_chipset = init_chipset_ali15x3,
863 .init_hwif = init_hwif_ali15x3,
864 .init_dma = init_dma_ali15x3,
865 .channels = 2,
866 .autodma = AUTODMA,
867 .bootable = ON_BOARD,
868 };
869
870 /**
871 * alim15x3_init_one - set up an ALi15x3 IDE controller
872 * @dev: PCI device to set up
873 *
874 * Perform the actual set up for an ALi15x3 that has been found by the
875 * hot plug layer.
876 */
877
878 static int __devinit alim15x3_init_one(struct pci_dev *dev, const struct pci_device_id *id)
879 {
880 static struct pci_device_id ati_rs100[] = {
881 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100) },
882 { },
883 };
884
885 ide_pci_device_t *d = &ali15x3_chipset;
886
887 if (pci_dev_present(ati_rs100))
888 printk(KERN_WARNING "alim15x3: ATI Radeon IGP Northbridge is not yet fully tested.\n");
889
890 #if defined(CONFIG_SPARC64)
891 d->init_hwif = init_hwif_common_ali15x3;
892 #endif /* CONFIG_SPARC64 */
893 return ide_setup_pci_device(dev, d);
894 }
895
896
897 static struct pci_device_id alim15x3_pci_tbl[] = {
898 { PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M5229, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
899 { PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M5228, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
900 { 0, },
901 };
902 MODULE_DEVICE_TABLE(pci, alim15x3_pci_tbl);
903
904 static struct pci_driver driver = {
905 .name = "ALI15x3_IDE",
906 .id_table = alim15x3_pci_tbl,
907 .probe = alim15x3_init_one,
908 };
909
910 static int ali15x3_ide_init(void)
911 {
912 return ide_pci_register_driver(&driver);
913 }
914
915 module_init(ali15x3_ide_init);
916
917 MODULE_AUTHOR("Michael Aubry, Andrzej Krzysztofowicz, CJ, Andre Hedrick, Alan Cox");
918 MODULE_DESCRIPTION("PCI driver module for ALi 15x3 IDE");
919 MODULE_LICENSE("GPL");
Software Suspend 2 for 2.6.18.y (mirror)