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[PATCH] v4l: 771: the wm8775 is a wolfson microelectronics 24 bit 96khz adc with 4
[linux-2.6/suspend2-2.6.18.git] / drivers / scsi / sata_sil24.c
blobe6c8e89c226f5a4d24ef3d85873af02d38e35d42
1 /*
2 * sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers
3 *
4 * Copyright 2005 Tejun Heo
5 *
6 * Based on preview driver from Silicon Image.
7 *
8 * NOTE: No NCQ/ATAPI support yet. The preview driver didn't support
9 * NCQ nor ATAPI, and, unfortunately, I couldn't find out how to make
10 * those work. Enabling those shouldn't be difficult. Basic
11 * structure is all there (in libata-dev tree). If you have any
12 * information about this hardware, please contact me or linux-ide.
13 * Info is needed on...
14 *
15 * - How to issue tagged commands and turn on sactive on issue accordingly.
16 * - Where to put an ATAPI command and how to tell the device to send it.
17 * - How to enable/use 64bit.
18 *
19 * This program is free software; you can redistribute it and/or modify it
20 * under the terms of the GNU General Public License as published by the
21 * Free Software Foundation; either version 2, or (at your option) any
22 * later version.
23 *
24 * This program is distributed in the hope that it will be useful, but
25 * WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
27 * General Public License for more details.
28 *
29 */
30
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/pci.h>
34 #include <linux/blkdev.h>
35 #include <linux/delay.h>
36 #include <linux/interrupt.h>
37 #include <linux/dma-mapping.h>
38 #include <linux/device.h>
39 #include <scsi/scsi_host.h>
40 #include "scsi.h"
41 #include <linux/libata.h>
42 #include <asm/io.h>
43
44 #define DRV_NAME "sata_sil24"
45 #define DRV_VERSION "0.22" /* Silicon Image's preview driver was 0.10 */
46
47 /*
48 * Port request block (PRB) 32 bytes
49 */
50 struct sil24_prb {
51 u16 ctrl;
52 u16 prot;
53 u32 rx_cnt;
54 u8 fis[6 * 4];
55 };
56
57 /*
58 * Scatter gather entry (SGE) 16 bytes
59 */
60 struct sil24_sge {
61 u64 addr;
62 u32 cnt;
63 u32 flags;
64 };
65
66 /*
67 * Port multiplier
68 */
69 struct sil24_port_multiplier {
70 u32 diag;
71 u32 sactive;
72 };
73
74 enum {
75 /*
76 * Global controller registers (128 bytes @ BAR0)
77 */
78 /* 32 bit regs */
79 HOST_SLOT_STAT = 0x00, /* 32 bit slot stat * 4 */
80 HOST_CTRL = 0x40,
81 HOST_IRQ_STAT = 0x44,
82 HOST_PHY_CFG = 0x48,
83 HOST_BIST_CTRL = 0x50,
84 HOST_BIST_PTRN = 0x54,
85 HOST_BIST_STAT = 0x58,
86 HOST_MEM_BIST_STAT = 0x5c,
87 HOST_FLASH_CMD = 0x70,
88 /* 8 bit regs */
89 HOST_FLASH_DATA = 0x74,
90 HOST_TRANSITION_DETECT = 0x75,
91 HOST_GPIO_CTRL = 0x76,
92 HOST_I2C_ADDR = 0x78, /* 32 bit */
93 HOST_I2C_DATA = 0x7c,
94 HOST_I2C_XFER_CNT = 0x7e,
95 HOST_I2C_CTRL = 0x7f,
96
97 /* HOST_SLOT_STAT bits */
98 HOST_SSTAT_ATTN = (1 << 31),
99
100 /*
101 * Port registers
102 * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2)
103 */
104 PORT_REGS_SIZE = 0x2000,
105 PORT_PRB = 0x0000, /* (32 bytes PRB + 16 bytes SGEs * 6) * 31 (3968 bytes) */
106
107 PORT_PM = 0x0f80, /* 8 bytes PM * 16 (128 bytes) */
108 /* 32 bit regs */
109 PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */
110 PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */
111 PORT_IRQ_STAT = 0x1008, /* high: status, low: interrupt */
112 PORT_IRQ_ENABLE_SET = 0x1010, /* write: enable-set */
113 PORT_IRQ_ENABLE_CLR = 0x1014, /* write: enable-clear */
114 PORT_ACTIVATE_UPPER_ADDR= 0x101c,
115 PORT_EXEC_FIFO = 0x1020, /* command execution fifo */
116 PORT_CMD_ERR = 0x1024, /* command error number */
117 PORT_FIS_CFG = 0x1028,
118 PORT_FIFO_THRES = 0x102c,
119 /* 16 bit regs */
120 PORT_DECODE_ERR_CNT = 0x1040,
121 PORT_DECODE_ERR_THRESH = 0x1042,
122 PORT_CRC_ERR_CNT = 0x1044,
123 PORT_CRC_ERR_THRESH = 0x1046,
124 PORT_HSHK_ERR_CNT = 0x1048,
125 PORT_HSHK_ERR_THRESH = 0x104a,
126 /* 32 bit regs */
127 PORT_PHY_CFG = 0x1050,
128 PORT_SLOT_STAT = 0x1800,
129 PORT_CMD_ACTIVATE = 0x1c00, /* 64 bit cmd activate * 31 (248 bytes) */
130 PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */
131 PORT_PSD_DIAG = 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */
132 PORT_SCONTROL = 0x1f00,
133 PORT_SSTATUS = 0x1f04,
134 PORT_SERROR = 0x1f08,
135 PORT_SACTIVE = 0x1f0c,
136
137 /* PORT_CTRL_STAT bits */
138 PORT_CS_PORT_RST = (1 << 0), /* port reset */
139 PORT_CS_DEV_RST = (1 << 1), /* device reset */
140 PORT_CS_INIT = (1 << 2), /* port initialize */
141 PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */
142 PORT_CS_RESUME = (1 << 6), /* port resume */
143 PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */
144 PORT_CS_PM_EN = (1 << 13), /* port multiplier enable */
145 PORT_CS_RDY = (1 << 31), /* port ready to accept commands */
146
147 /* PORT_IRQ_STAT/ENABLE_SET/CLR */
148 /* bits[11:0] are masked */
149 PORT_IRQ_COMPLETE = (1 << 0), /* command(s) completed */
150 PORT_IRQ_ERROR = (1 << 1), /* command execution error */
151 PORT_IRQ_PORTRDY_CHG = (1 << 2), /* port ready change */
152 PORT_IRQ_PWR_CHG = (1 << 3), /* power management change */
153 PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */
154 PORT_IRQ_COMWAKE = (1 << 5), /* COMWAKE received */
155 PORT_IRQ_UNK_FIS = (1 << 6), /* Unknown FIS received */
156 PORT_IRQ_SDB_FIS = (1 << 11), /* SDB FIS received */
157
158 /* bits[27:16] are unmasked (raw) */
159 PORT_IRQ_RAW_SHIFT = 16,
160 PORT_IRQ_MASKED_MASK = 0x7ff,
161 PORT_IRQ_RAW_MASK = (0x7ff << PORT_IRQ_RAW_SHIFT),
162
163 /* ENABLE_SET/CLR specific, intr steering - 2 bit field */
164 PORT_IRQ_STEER_SHIFT = 30,
165 PORT_IRQ_STEER_MASK = (3 << PORT_IRQ_STEER_SHIFT),
166
167 /* PORT_CMD_ERR constants */
168 PORT_CERR_DEV = 1, /* Error bit in D2H Register FIS */
169 PORT_CERR_SDB = 2, /* Error bit in SDB FIS */
170 PORT_CERR_DATA = 3, /* Error in data FIS not detected by dev */
171 PORT_CERR_SEND = 4, /* Initial cmd FIS transmission failure */
172 PORT_CERR_INCONSISTENT = 5, /* Protocol mismatch */
173 PORT_CERR_DIRECTION = 6, /* Data direction mismatch */
174 PORT_CERR_UNDERRUN = 7, /* Ran out of SGEs while writing */
175 PORT_CERR_OVERRUN = 8, /* Ran out of SGEs while reading */
176 PORT_CERR_PKT_PROT = 11, /* DIR invalid in 1st PIO setup of ATAPI */
177 PORT_CERR_SGT_BOUNDARY = 16, /* PLD ecode 00 - SGT not on qword boundary */
178 PORT_CERR_SGT_TGTABRT = 17, /* PLD ecode 01 - target abort */
179 PORT_CERR_SGT_MSTABRT = 18, /* PLD ecode 10 - master abort */
180 PORT_CERR_SGT_PCIPERR = 19, /* PLD ecode 11 - PCI parity err while fetching SGT */
181 PORT_CERR_CMD_BOUNDARY = 24, /* ctrl[15:13] 001 - PRB not on qword boundary */
182 PORT_CERR_CMD_TGTABRT = 25, /* ctrl[15:13] 010 - target abort */
183 PORT_CERR_CMD_MSTABRT = 26, /* ctrl[15:13] 100 - master abort */
184 PORT_CERR_CMD_PCIPERR = 27, /* ctrl[15:13] 110 - PCI parity err while fetching PRB */
185 PORT_CERR_XFR_UNDEF = 32, /* PSD ecode 00 - undefined */
186 PORT_CERR_XFR_TGTABRT = 33, /* PSD ecode 01 - target abort */
187 PORT_CERR_XFR_MSGABRT = 34, /* PSD ecode 10 - master abort */
188 PORT_CERR_XFR_PCIPERR = 35, /* PSD ecode 11 - PCI prity err during transfer */
189 PORT_CERR_SENDSERVICE = 36, /* FIS received while sending service */
190
191 /*
192 * Other constants
193 */
194 SGE_TRM = (1 << 31), /* Last SGE in chain */
195 PRB_SOFT_RST = (1 << 7), /* Soft reset request (ign BSY?) */
196
197 /* board id */
198 BID_SIL3124 = 0,
199 BID_SIL3132 = 1,
200 BID_SIL3131 = 2,
201
202 IRQ_STAT_4PORTS = 0xf,
203 };
204
205 struct sil24_cmd_block {
206 struct sil24_prb prb;
207 struct sil24_sge sge[LIBATA_MAX_PRD];
208 };
209
210 /*
211 * ap->private_data
212 *
213 * The preview driver always returned 0 for status. We emulate it
214 * here from the previous interrupt.
215 */
216 struct sil24_port_priv {
217 struct sil24_cmd_block *cmd_block; /* 32 cmd blocks */
218 dma_addr_t cmd_block_dma; /* DMA base addr for them */
219 struct ata_taskfile tf; /* Cached taskfile registers */
220 };
221
222 /* ap->host_set->private_data */
223 struct sil24_host_priv {
224 void __iomem *host_base; /* global controller control (128 bytes @BAR0) */
225 void __iomem *port_base; /* port registers (4 * 8192 bytes @BAR2) */
226 };
227
228 static u8 sil24_check_status(struct ata_port *ap);
229 static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg);
230 static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val);
231 static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
232 static void sil24_phy_reset(struct ata_port *ap);
233 static void sil24_qc_prep(struct ata_queued_cmd *qc);
234 static int sil24_qc_issue(struct ata_queued_cmd *qc);
235 static void sil24_irq_clear(struct ata_port *ap);
236 static void sil24_eng_timeout(struct ata_port *ap);
237 static irqreturn_t sil24_interrupt(int irq, void *dev_instance, struct pt_regs *regs);
238 static int sil24_port_start(struct ata_port *ap);
239 static void sil24_port_stop(struct ata_port *ap);
240 static void sil24_host_stop(struct ata_host_set *host_set);
241 static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
242
243 static struct pci_device_id sil24_pci_tbl[] = {
244 { 0x1095, 0x3124, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3124 },
245 { 0x1095, 0x3132, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3132 },
246 { 0x1095, 0x3131, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3131 },
247 { 0x1095, 0x3531, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3131 },
248 { } /* terminate list */
249 };
250
251 static struct pci_driver sil24_pci_driver = {
252 .name = DRV_NAME,
253 .id_table = sil24_pci_tbl,
254 .probe = sil24_init_one,
255 .remove = ata_pci_remove_one, /* safe? */
256 };
257
258 static Scsi_Host_Template sil24_sht = {
259 .module = THIS_MODULE,
260 .name = DRV_NAME,
261 .ioctl = ata_scsi_ioctl,
262 .queuecommand = ata_scsi_queuecmd,
263 .eh_strategy_handler = ata_scsi_error,
264 .can_queue = ATA_DEF_QUEUE,
265 .this_id = ATA_SHT_THIS_ID,
266 .sg_tablesize = LIBATA_MAX_PRD,
267 .max_sectors = ATA_MAX_SECTORS,
268 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
269 .emulated = ATA_SHT_EMULATED,
270 .use_clustering = ATA_SHT_USE_CLUSTERING,
271 .proc_name = DRV_NAME,
272 .dma_boundary = ATA_DMA_BOUNDARY,
273 .slave_configure = ata_scsi_slave_config,
274 .bios_param = ata_std_bios_param,
275 .ordered_flush = 1, /* NCQ not supported yet */
276 };
277
278 static const struct ata_port_operations sil24_ops = {
279 .port_disable = ata_port_disable,
280
281 .check_status = sil24_check_status,
282 .check_altstatus = sil24_check_status,
283 .dev_select = ata_noop_dev_select,
284
285 .tf_read = sil24_tf_read,
286
287 .phy_reset = sil24_phy_reset,
288
289 .qc_prep = sil24_qc_prep,
290 .qc_issue = sil24_qc_issue,
291
292 .eng_timeout = sil24_eng_timeout,
293
294 .irq_handler = sil24_interrupt,
295 .irq_clear = sil24_irq_clear,
296
297 .scr_read = sil24_scr_read,
298 .scr_write = sil24_scr_write,
299
300 .port_start = sil24_port_start,
301 .port_stop = sil24_port_stop,
302 .host_stop = sil24_host_stop,
303 };
304
305 /*
306 * Use bits 30-31 of host_flags to encode available port numbers.
307 * Current maxium is 4.
308 */
309 #define SIL24_NPORTS2FLAG(nports) ((((unsigned)(nports) - 1) & 0x3) << 30)
310 #define SIL24_FLAG2NPORTS(flag) ((((flag) >> 30) & 0x3) + 1)
311
312 static struct ata_port_info sil24_port_info[] = {
313 /* sil_3124 */
314 {
315 .sht = &sil24_sht,
316 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
317 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO |
318 ATA_FLAG_PIO_DMA | SIL24_NPORTS2FLAG(4),
319 .pio_mask = 0x1f, /* pio0-4 */
320 .mwdma_mask = 0x07, /* mwdma0-2 */
321 .udma_mask = 0x3f, /* udma0-5 */
322 .port_ops = &sil24_ops,
323 },
324 /* sil_3132 */
325 {
326 .sht = &sil24_sht,
327 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
328 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO |
329 ATA_FLAG_PIO_DMA | SIL24_NPORTS2FLAG(2),
330 .pio_mask = 0x1f, /* pio0-4 */
331 .mwdma_mask = 0x07, /* mwdma0-2 */
332 .udma_mask = 0x3f, /* udma0-5 */
333 .port_ops = &sil24_ops,
334 },
335 /* sil_3131/sil_3531 */
336 {
337 .sht = &sil24_sht,
338 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
339 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO |
340 ATA_FLAG_PIO_DMA | SIL24_NPORTS2FLAG(1),
341 .pio_mask = 0x1f, /* pio0-4 */
342 .mwdma_mask = 0x07, /* mwdma0-2 */
343 .udma_mask = 0x3f, /* udma0-5 */
344 .port_ops = &sil24_ops,
345 },
346 };
347
348 static inline void sil24_update_tf(struct ata_port *ap)
349 {
350 struct sil24_port_priv *pp = ap->private_data;
351 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
352 struct sil24_prb __iomem *prb = port;
353 u8 fis[6 * 4];
354
355 memcpy_fromio(fis, prb->fis, 6 * 4);
356 ata_tf_from_fis(fis, &pp->tf);
357 }
358
359 static u8 sil24_check_status(struct ata_port *ap)
360 {
361 struct sil24_port_priv *pp = ap->private_data;
362 return pp->tf.command;
363 }
364
365 static int sil24_scr_map[] = {
366 [SCR_CONTROL] = 0,
367 [SCR_STATUS] = 1,
368 [SCR_ERROR] = 2,
369 [SCR_ACTIVE] = 3,
370 };
371
372 static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg)
373 {
374 void __iomem *scr_addr = (void __iomem *)ap->ioaddr.scr_addr;
375 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
376 void __iomem *addr;
377 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
378 return readl(scr_addr + sil24_scr_map[sc_reg] * 4);
379 }
380 return 0xffffffffU;
381 }
382
383 static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val)
384 {
385 void __iomem *scr_addr = (void __iomem *)ap->ioaddr.scr_addr;
386 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
387 void __iomem *addr;
388 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
389 writel(val, scr_addr + sil24_scr_map[sc_reg] * 4);
390 }
391 }
392
393 static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
394 {
395 struct sil24_port_priv *pp = ap->private_data;
396 *tf = pp->tf;
397 }
398
399 static void sil24_phy_reset(struct ata_port *ap)
400 {
401 __sata_phy_reset(ap);
402 /*
403 * No ATAPI yet. Just unconditionally indicate ATA device.
404 * If ATAPI device is attached, it will fail ATA_CMD_ID_ATA
405 * and libata core will ignore the device.
406 */
407 if (!(ap->flags & ATA_FLAG_PORT_DISABLED))
408 ap->device[0].class = ATA_DEV_ATA;
409 }
410
411 static inline void sil24_fill_sg(struct ata_queued_cmd *qc,
412 struct sil24_cmd_block *cb)
413 {
414 struct sil24_sge *sge = cb->sge;
415 struct scatterlist *sg;
416 unsigned int idx = 0;
417
418 ata_for_each_sg(sg, qc) {
419 sge->addr = cpu_to_le64(sg_dma_address(sg));
420 sge->cnt = cpu_to_le32(sg_dma_len(sg));
421 if (ata_sg_is_last(sg, qc))
422 sge->flags = cpu_to_le32(SGE_TRM);
423 else
424 sge->flags = 0;
425
426 sge++;
427 idx++;
428 }
429 }
430
431 static void sil24_qc_prep(struct ata_queued_cmd *qc)
432 {
433 struct ata_port *ap = qc->ap;
434 struct sil24_port_priv *pp = ap->private_data;
435 struct sil24_cmd_block *cb = pp->cmd_block + qc->tag;
436 struct sil24_prb *prb = &cb->prb;
437
438 switch (qc->tf.protocol) {
439 case ATA_PROT_PIO:
440 case ATA_PROT_DMA:
441 case ATA_PROT_NODATA:
442 break;
443 default:
444 /* ATAPI isn't supported yet */
445 BUG();
446 }
447
448 ata_tf_to_fis(&qc->tf, prb->fis, 0);
449
450 if (qc->flags & ATA_QCFLAG_DMAMAP)
451 sil24_fill_sg(qc, cb);
452 }
453
454 static int sil24_qc_issue(struct ata_queued_cmd *qc)
455 {
456 struct ata_port *ap = qc->ap;
457 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
458 struct sil24_port_priv *pp = ap->private_data;
459 dma_addr_t paddr = pp->cmd_block_dma + qc->tag * sizeof(*pp->cmd_block);
460
461 writel((u32)paddr, port + PORT_CMD_ACTIVATE);
462 return 0;
463 }
464
465 static void sil24_irq_clear(struct ata_port *ap)
466 {
467 /* unused */
468 }
469
470 static int __sil24_reset_controller(void __iomem *port)
471 {
472 int cnt;
473 u32 tmp;
474
475 /* Reset controller state. Is this correct? */
476 writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
477 readl(port + PORT_CTRL_STAT); /* sync */
478
479 /* Max ~100ms */
480 for (cnt = 0; cnt < 1000; cnt++) {
481 udelay(100);
482 tmp = readl(port + PORT_CTRL_STAT);
483 if (!(tmp & PORT_CS_DEV_RST))
484 break;
485 }
486
487 if (tmp & PORT_CS_DEV_RST)
488 return -1;
489 return 0;
490 }
491
492 static void sil24_reset_controller(struct ata_port *ap)
493 {
494 printk(KERN_NOTICE DRV_NAME
495 " ata%u: resetting controller...\n", ap->id);
496 if (__sil24_reset_controller((void __iomem *)ap->ioaddr.cmd_addr))
497 printk(KERN_ERR DRV_NAME
498 " ata%u: failed to reset controller\n", ap->id);
499 }
500
501 static void sil24_eng_timeout(struct ata_port *ap)
502 {
503 struct ata_queued_cmd *qc;
504
505 qc = ata_qc_from_tag(ap, ap->active_tag);
506 if (!qc) {
507 printk(KERN_ERR "ata%u: BUG: timeout without command\n",
508 ap->id);
509 return;
510 }
511
512 /*
513 * hack alert! We cannot use the supplied completion
514 * function from inside the ->eh_strategy_handler() thread.
515 * libata is the only user of ->eh_strategy_handler() in
516 * any kernel, so the default scsi_done() assumes it is
517 * not being called from the SCSI EH.
518 */
519 printk(KERN_ERR "ata%u: command timeout\n", ap->id);
520 qc->scsidone = scsi_finish_command;
521 ata_qc_complete(qc, AC_ERR_OTHER);
522
523 sil24_reset_controller(ap);
524 }
525
526 static void sil24_error_intr(struct ata_port *ap, u32 slot_stat)
527 {
528 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag);
529 struct sil24_port_priv *pp = ap->private_data;
530 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
531 u32 irq_stat, cmd_err, sstatus, serror;
532 unsigned int err_mask;
533
534 irq_stat = readl(port + PORT_IRQ_STAT);
535 writel(irq_stat, port + PORT_IRQ_STAT); /* clear irq */
536
537 if (!(irq_stat & PORT_IRQ_ERROR)) {
538 /* ignore non-completion, non-error irqs for now */
539 printk(KERN_WARNING DRV_NAME
540 "ata%u: non-error exception irq (irq_stat %x)\n",
541 ap->id, irq_stat);
542 return;
543 }
544
545 cmd_err = readl(port + PORT_CMD_ERR);
546 sstatus = readl(port + PORT_SSTATUS);
547 serror = readl(port + PORT_SERROR);
548 if (serror)
549 writel(serror, port + PORT_SERROR);
550
551 printk(KERN_ERR DRV_NAME " ata%u: error interrupt on port%d\n"
552 " stat=0x%x irq=0x%x cmd_err=%d sstatus=0x%x serror=0x%x\n",
553 ap->id, ap->port_no, slot_stat, irq_stat, cmd_err, sstatus, serror);
554
555 if (cmd_err == PORT_CERR_DEV || cmd_err == PORT_CERR_SDB) {
556 /*
557 * Device is reporting error, tf registers are valid.
558 */
559 sil24_update_tf(ap);
560 err_mask = ac_err_mask(pp->tf.command);
561 } else {
562 /*
563 * Other errors. libata currently doesn't have any
564 * mechanism to report these errors. Just turn on
565 * ATA_ERR.
566 */
567 err_mask = AC_ERR_OTHER;
568 }
569
570 if (qc)
571 ata_qc_complete(qc, err_mask);
572
573 sil24_reset_controller(ap);
574 }
575
576 static inline void sil24_host_intr(struct ata_port *ap)
577 {
578 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag);
579 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
580 u32 slot_stat;
581
582 slot_stat = readl(port + PORT_SLOT_STAT);
583 if (!(slot_stat & HOST_SSTAT_ATTN)) {
584 struct sil24_port_priv *pp = ap->private_data;
585 /*
586 * !HOST_SSAT_ATTN guarantees successful completion,
587 * so reading back tf registers is unnecessary for
588 * most commands. TODO: read tf registers for
589 * commands which require these values on successful
590 * completion (EXECUTE DEVICE DIAGNOSTIC, CHECK POWER,
591 * DEVICE RESET and READ PORT MULTIPLIER (any more?).
592 */
593 sil24_update_tf(ap);
594
595 if (qc)
596 ata_qc_complete(qc, ac_err_mask(pp->tf.command));
597 } else
598 sil24_error_intr(ap, slot_stat);
599 }
600
601 static irqreturn_t sil24_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
602 {
603 struct ata_host_set *host_set = dev_instance;
604 struct sil24_host_priv *hpriv = host_set->private_data;
605 unsigned handled = 0;
606 u32 status;
607 int i;
608
609 status = readl(hpriv->host_base + HOST_IRQ_STAT);
610
611 if (status == 0xffffffff) {
612 printk(KERN_ERR DRV_NAME ": IRQ status == 0xffffffff, "
613 "PCI fault or device removal?\n");
614 goto out;
615 }
616
617 if (!(status & IRQ_STAT_4PORTS))
618 goto out;
619
620 spin_lock(&host_set->lock);
621
622 for (i = 0; i < host_set->n_ports; i++)
623 if (status & (1 << i)) {
624 struct ata_port *ap = host_set->ports[i];
625 if (ap && !(ap->flags & ATA_FLAG_PORT_DISABLED)) {
626 sil24_host_intr(host_set->ports[i]);
627 handled++;
628 } else
629 printk(KERN_ERR DRV_NAME
630 ": interrupt from disabled port %d\n", i);
631 }
632
633 spin_unlock(&host_set->lock);
634 out:
635 return IRQ_RETVAL(handled);
636 }
637
638 static inline void sil24_cblk_free(struct sil24_port_priv *pp, struct device *dev)
639 {
640 const size_t cb_size = sizeof(*pp->cmd_block);
641
642 dma_free_coherent(dev, cb_size, pp->cmd_block, pp->cmd_block_dma);
643 }
644
645 static int sil24_port_start(struct ata_port *ap)
646 {
647 struct device *dev = ap->host_set->dev;
648 struct sil24_port_priv *pp;
649 struct sil24_cmd_block *cb;
650 size_t cb_size = sizeof(*cb);
651 dma_addr_t cb_dma;
652 int rc = -ENOMEM;
653
654 pp = kzalloc(sizeof(*pp), GFP_KERNEL);
655 if (!pp)
656 goto err_out;
657
658 pp->tf.command = ATA_DRDY;
659
660 cb = dma_alloc_coherent(dev, cb_size, &cb_dma, GFP_KERNEL);
661 if (!cb)
662 goto err_out_pp;
663 memset(cb, 0, cb_size);
664
665 rc = ata_pad_alloc(ap, dev);
666 if (rc)
667 goto err_out_pad;
668
669 pp->cmd_block = cb;
670 pp->cmd_block_dma = cb_dma;
671
672 ap->private_data = pp;
673
674 return 0;
675
676 err_out_pad:
677 sil24_cblk_free(pp, dev);
678 err_out_pp:
679 kfree(pp);
680 err_out:
681 return rc;
682 }
683
684 static void sil24_port_stop(struct ata_port *ap)
685 {
686 struct device *dev = ap->host_set->dev;
687 struct sil24_port_priv *pp = ap->private_data;
688
689 sil24_cblk_free(pp, dev);
690 kfree(pp);
691 }
692
693 static void sil24_host_stop(struct ata_host_set *host_set)
694 {
695 struct sil24_host_priv *hpriv = host_set->private_data;
696
697 iounmap(hpriv->host_base);
698 iounmap(hpriv->port_base);
699 kfree(hpriv);
700 }
701
702 static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
703 {
704 static int printed_version = 0;
705 unsigned int board_id = (unsigned int)ent->driver_data;
706 struct ata_port_info *pinfo = &sil24_port_info[board_id];
707 struct ata_probe_ent *probe_ent = NULL;
708 struct sil24_host_priv *hpriv = NULL;
709 void __iomem *host_base = NULL;
710 void __iomem *port_base = NULL;
711 int i, rc;
712
713 if (!printed_version++)
714 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
715
716 rc = pci_enable_device(pdev);
717 if (rc)
718 return rc;
719
720 rc = pci_request_regions(pdev, DRV_NAME);
721 if (rc)
722 goto out_disable;
723
724 rc = -ENOMEM;
725 /* ioremap mmio registers */
726 host_base = ioremap(pci_resource_start(pdev, 0),
727 pci_resource_len(pdev, 0));
728 if (!host_base)
729 goto out_free;
730 port_base = ioremap(pci_resource_start(pdev, 2),
731 pci_resource_len(pdev, 2));
732 if (!port_base)
733 goto out_free;
734
735 /* allocate & init probe_ent and hpriv */
736 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
737 if (!probe_ent)
738 goto out_free;
739
740 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
741 if (!hpriv)
742 goto out_free;
743
744 memset(probe_ent, 0, sizeof(*probe_ent));
745 probe_ent->dev = pci_dev_to_dev(pdev);
746 INIT_LIST_HEAD(&probe_ent->node);
747
748 probe_ent->sht = pinfo->sht;
749 probe_ent->host_flags = pinfo->host_flags;
750 probe_ent->pio_mask = pinfo->pio_mask;
751 probe_ent->udma_mask = pinfo->udma_mask;
752 probe_ent->port_ops = pinfo->port_ops;
753 probe_ent->n_ports = SIL24_FLAG2NPORTS(pinfo->host_flags);
754
755 probe_ent->irq = pdev->irq;
756 probe_ent->irq_flags = SA_SHIRQ;
757 probe_ent->mmio_base = port_base;
758 probe_ent->private_data = hpriv;
759
760 memset(hpriv, 0, sizeof(*hpriv));
761 hpriv->host_base = host_base;
762 hpriv->port_base = port_base;
763
764 /*
765 * Configure the device
766 */
767 /*
768 * FIXME: This device is certainly 64-bit capable. We just
769 * don't know how to use it. After fixing 32bit activation in
770 * this function, enable 64bit masks here.
771 */
772 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
773 if (rc) {
774 dev_printk(KERN_ERR, &pdev->dev,
775 "32-bit DMA enable failed\n");
776 goto out_free;
777 }
778 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
779 if (rc) {
780 dev_printk(KERN_ERR, &pdev->dev,
781 "32-bit consistent DMA enable failed\n");
782 goto out_free;
783 }
784
785 /* GPIO off */
786 writel(0, host_base + HOST_FLASH_CMD);
787
788 /* Mask interrupts during initialization */
789 writel(0, host_base + HOST_CTRL);
790
791 for (i = 0; i < probe_ent->n_ports; i++) {
792 void __iomem *port = port_base + i * PORT_REGS_SIZE;
793 unsigned long portu = (unsigned long)port;
794 u32 tmp;
795 int cnt;
796
797 probe_ent->port[i].cmd_addr = portu + PORT_PRB;
798 probe_ent->port[i].scr_addr = portu + PORT_SCONTROL;
799
800 ata_std_ports(&probe_ent->port[i]);
801
802 /* Initial PHY setting */
803 writel(0x20c, port + PORT_PHY_CFG);
804
805 /* Clear port RST */
806 tmp = readl(port + PORT_CTRL_STAT);
807 if (tmp & PORT_CS_PORT_RST) {
808 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
809 readl(port + PORT_CTRL_STAT); /* sync */
810 for (cnt = 0; cnt < 10; cnt++) {
811 msleep(10);
812 tmp = readl(port + PORT_CTRL_STAT);
813 if (!(tmp & PORT_CS_PORT_RST))
814 break;
815 }
816 if (tmp & PORT_CS_PORT_RST)
817 dev_printk(KERN_ERR, &pdev->dev,
818 "failed to clear port RST\n");
819 }
820
821 /* Zero error counters. */
822 writel(0x8000, port + PORT_DECODE_ERR_THRESH);
823 writel(0x8000, port + PORT_CRC_ERR_THRESH);
824 writel(0x8000, port + PORT_HSHK_ERR_THRESH);
825 writel(0x0000, port + PORT_DECODE_ERR_CNT);
826 writel(0x0000, port + PORT_CRC_ERR_CNT);
827 writel(0x0000, port + PORT_HSHK_ERR_CNT);
828
829 /* FIXME: 32bit activation? */
830 writel(0, port + PORT_ACTIVATE_UPPER_ADDR);
831 writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_STAT);
832
833 /* Configure interrupts */
834 writel(0xffff, port + PORT_IRQ_ENABLE_CLR);
835 writel(PORT_IRQ_COMPLETE | PORT_IRQ_ERROR | PORT_IRQ_SDB_FIS,
836 port + PORT_IRQ_ENABLE_SET);
837
838 /* Clear interrupts */
839 writel(0x0fff0fff, port + PORT_IRQ_STAT);
840 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
841
842 /* Clear port multiplier enable and resume bits */
843 writel(PORT_CS_PM_EN | PORT_CS_RESUME, port + PORT_CTRL_CLR);
844
845 /* Reset itself */
846 if (__sil24_reset_controller(port))
847 dev_printk(KERN_ERR, &pdev->dev,
848 "failed to reset controller\n");
849 }
850
851 /* Turn on interrupts */
852 writel(IRQ_STAT_4PORTS, host_base + HOST_CTRL);
853
854 pci_set_master(pdev);
855
856 /* FIXME: check ata_device_add return value */
857 ata_device_add(probe_ent);
858
859 kfree(probe_ent);
860 return 0;
861
862 out_free:
863 if (host_base)
864 iounmap(host_base);
865 if (port_base)
866 iounmap(port_base);
867 kfree(probe_ent);
868 kfree(hpriv);
869 pci_release_regions(pdev);
870 out_disable:
871 pci_disable_device(pdev);
872 return rc;
873 }
874
875 static int __init sil24_init(void)
876 {
877 return pci_module_init(&sil24_pci_driver);
878 }
879
880 static void __exit sil24_exit(void)
881 {
882 pci_unregister_driver(&sil24_pci_driver);
883 }
884
885 MODULE_AUTHOR("Tejun Heo");
886 MODULE_DESCRIPTION("Silicon Image 3124/3132 SATA low-level driver");
887 MODULE_LICENSE("GPL");
888 MODULE_DEVICE_TABLE(pci, sil24_pci_tbl);
889
890 module_init(sil24_init);
891 module_exit(sil24_exit);
Software Suspend 2 for 2.6.18.y (mirror)