arch/m68k/q40/config.c

   1 /*
   2  *  arch/m68k/q40/config.c
   3  *
   4  *  Copyright (C) 1999 Richard Zidlicky
   5  *
   6  * originally based on:
   7  *
   8  *  linux/bvme/config.c
   9  *
  10  * This file is subject to the terms and conditions of the GNU General Public
  11  * License.  See the file README.legal in the main directory of this archive
  12  * for more details.
  13  */
  14
  15 #include <linux/config.h>
  16 #include <linux/types.h>
  17 #include <linux/kernel.h>
  18 #include <linux/mm.h>
  19 #include <linux/tty.h>
  20 #include <linux/console.h>
  21 #include <linux/linkage.h>
  22 #include <linux/init.h>
  23 #include <linux/major.h>
  24 #include <linux/serial_reg.h>
  25 #include <linux/rtc.h>
  26 #include <linux/vt_kern.h>
  27
  28 #include <asm/io.h>
  29 #include <asm/rtc.h>
  30 #include <asm/bootinfo.h>
  31 #include <asm/system.h>
  32 #include <asm/pgtable.h>
  33 #include <asm/setup.h>
  34 #include <asm/irq.h>
  35 #include <asm/traps.h>
  36 #include <asm/machdep.h>
  37 #include <asm/q40_master.h>
  38
  39 extern irqreturn_t q40_process_int (int level, struct pt_regs *regs);
  40 extern irqreturn_t (*q40_default_handler[]) (int, void *, struct pt_regs *);  /* added just for debugging */
  41 extern void q40_init_IRQ (void);
  42 extern void q40_free_irq (unsigned int, void *);
  43 extern int  show_q40_interrupts (struct seq_file *, void *);
  44 extern void q40_enable_irq (unsigned int);
  45 extern void q40_disable_irq (unsigned int);
  46 static void q40_get_model(char *model);
  47 static int  q40_get_hardware_list(char *buffer);
  48 extern int  q40_request_irq(unsigned int irq, irqreturn_t (*handler)(int, void *, struct pt_regs *), unsigned long flags, const char *devname, void *dev_id);
  49 extern void q40_sched_init(irqreturn_t (*handler)(int, void *, struct pt_regs *));
  50
  51 extern unsigned long q40_gettimeoffset (void);
  52 extern int q40_hwclk (int, struct rtc_time *);
  53 extern unsigned int q40_get_ss (void);
  54 extern int q40_set_clock_mmss (unsigned long);
  55 static int q40_get_rtc_pll(struct rtc_pll_info *pll);
  56 static int q40_set_rtc_pll(struct rtc_pll_info *pll);
  57 extern void q40_reset (void);
  58 void q40_halt(void);
  59 extern void q40_waitbut(void);
  60 void q40_set_vectors (void);
  61
  62 extern void q40_mksound(unsigned int /*freq*/, unsigned int /*ticks*/ );
  63
  64 extern char m68k_debug_device[];
  65 static void q40_mem_console_write(struct console *co, const char *b,
  66                                     unsigned int count);
  67
  68 extern int ql_ticks;
  69
  70 static struct console q40_console_driver = {
  71         .name =         "debug",
  72         .flags =        CON_PRINTBUFFER,
  73         .index =        -1,
  74 };
  75
  76
  77 /* early debugging function:*/
  78 extern char *q40_mem_cptr; /*=(char *)0xff020000;*/
  79 static int _cpleft;
  80
  81 static void q40_mem_console_write(struct console *co, const char *s,
  82                                   unsigned int count)
  83 {
  84   char *p=(char *)s;
  85
  86   if (count<_cpleft)
  87     while (count-- >0){
  88       *q40_mem_cptr=*p++;
  89       q40_mem_cptr+=4;
  90       _cpleft--;
  91     }
  92 }
  93 #if 0
  94 void printq40(char *str)
  95 {
  96   int l=strlen(str);
  97   char *p=q40_mem_cptr;
  98
  99   while (l-- >0 && _cpleft-- >0)
 100     {
 101       *p=*str++;
 102       p+=4;
 103     }
 104   q40_mem_cptr=p;
 105 }
 106 #endif
 107
 108 static int halted=0;
 109
 110 #ifdef CONFIG_HEARTBEAT
 111 static void q40_heartbeat(int on)
 112 {
 113   if (halted) return;
 114
 115   if (on)
 116     Q40_LED_ON();
 117   else
 118     Q40_LED_OFF();
 119 }
 120 #endif
 121
 122 void q40_reset(void)
 123 {
 124         halted=1;
 125         printk ("\n\n*******************************************\n"
 126                 "Called q40_reset : press the RESET button!! \n"
 127                 "*******************************************\n");
 128         Q40_LED_ON();
 129         while(1) ;
 130 }
 131 void q40_halt(void)
 132 {
 133         halted=1;
 134         printk ("\n\n*******************\n"
 135                     "  Called q40_halt\n"
 136                     "*******************\n");
 137         Q40_LED_ON();
 138         while(1) ;
 139 }
 140
 141 static void q40_get_model(char *model)
 142 {
 143     sprintf(model, "Q40");
 144 }
 145
 146 /* No hardware options on Q40? */
 147
 148 static int q40_get_hardware_list(char *buffer)
 149 {
 150     *buffer = '\0';
 151     return 0;
 152 }
 153
 154 static unsigned int serports[]={0x3f8,0x2f8,0x3e8,0x2e8,0};
 155 void q40_disable_irqs(void)
 156 {
 157   unsigned i,j;
 158
 159   j=0;
 160   while((i=serports[j++])) outb(0,i+UART_IER);
 161   master_outb(0,EXT_ENABLE_REG);
 162   master_outb(0,KEY_IRQ_ENABLE_REG);
 163 }
 164
 165 void __init config_q40(void)
 166 {
 167     mach_sched_init      = q40_sched_init;
 168
 169     mach_init_IRQ        = q40_init_IRQ;
 170     mach_gettimeoffset   = q40_gettimeoffset;
 171     mach_hwclk           = q40_hwclk;
 172     mach_get_ss          = q40_get_ss;
 173     mach_get_rtc_pll     = q40_get_rtc_pll;
 174     mach_set_rtc_pll     = q40_set_rtc_pll;
 175     mach_set_clock_mmss  = q40_set_clock_mmss;
 176
 177     mach_reset           = q40_reset;
 178     mach_free_irq        = q40_free_irq;
 179     mach_process_int     = q40_process_int;
 180     mach_get_irq_list    = show_q40_interrupts;
 181     mach_request_irq     = q40_request_irq;
 182     enable_irq           = q40_enable_irq;
 183     disable_irq          = q40_disable_irq;
 184     mach_default_handler = &q40_default_handler;
 185     mach_get_model       = q40_get_model;
 186     mach_get_hardware_list = q40_get_hardware_list;
 187
 188 #if defined(CONFIG_INPUT_M68K_BEEP) || defined(CONFIG_INPUT_M68K_BEEP_MODULE)
 189     mach_beep            = q40_mksound;
 190 #endif
 191 #ifdef CONFIG_HEARTBEAT
 192     mach_heartbeat = q40_heartbeat;
 193 #endif
 194     mach_halt = q40_halt;
 195
 196     /* disable a few things that SMSQ might have left enabled */
 197     q40_disable_irqs();
 198
 199     /* no DMA at all, but ide-scsi requires it.. make sure
 200      * all physical RAM fits into the boundary - otherwise
 201      * allocator may play costly and useless tricks */
 202     mach_max_dma_address = 1024*1024*1024;
 203
 204     /* useful for early debugging stages - writes kernel messages into SRAM */
 205     if (!strncmp( m68k_debug_device,"mem",3 ))
 206       {
 207         /*printk("using NVRAM debug, q40_mem_cptr=%p\n",q40_mem_cptr);*/
 208         _cpleft=2000-((long)q40_mem_cptr-0xff020000)/4;
 209         q40_console_driver.write = q40_mem_console_write;
 210         register_console(&q40_console_driver);
 211       }
 212 }
 213
 214
 215 int q40_parse_bootinfo(const struct bi_record *rec)
 216 {
 217   return 1;
 218 }
 219
 220
 221 static inline unsigned char bcd2bin (unsigned char b)
 222 {
 223         return ((b>>4)*10 + (b&15));
 224 }
 225
 226 static inline unsigned char bin2bcd (unsigned char b)
 227 {
 228         return (((b/10)*16) + (b%10));
 229 }
 230
 231
 232 unsigned long q40_gettimeoffset (void)
 233 {
 234     return 5000*(ql_ticks!=0);
 235 }
 236
 237
 238 /*
 239  * Looks like op is non-zero for setting the clock, and zero for
 240  * reading the clock.
 241  *
 242  *  struct hwclk_time {
 243  *         unsigned        sec;       0..59
 244  *         unsigned        min;       0..59
 245  *         unsigned        hour;      0..23
 246  *         unsigned        day;       1..31
 247  *         unsigned        mon;       0..11
 248  *         unsigned        year;      00...
 249  *         int             wday;      0..6, 0 is Sunday, -1 means unknown/don't set
 250  * };
 251  */
 252
 253 int q40_hwclk(int op, struct rtc_time *t)
 254 {
 255         if (op)
 256         {       /* Write.... */
 257                 Q40_RTC_CTRL |= Q40_RTC_WRITE;
 258
 259                 Q40_RTC_SECS = bin2bcd(t->tm_sec);
 260                 Q40_RTC_MINS = bin2bcd(t->tm_min);
 261                 Q40_RTC_HOUR = bin2bcd(t->tm_hour);
 262                 Q40_RTC_DATE = bin2bcd(t->tm_mday);
 263                 Q40_RTC_MNTH = bin2bcd(t->tm_mon + 1);
 264                 Q40_RTC_YEAR = bin2bcd(t->tm_year%100);
 265                 if (t->tm_wday >= 0)
 266                         Q40_RTC_DOW = bin2bcd(t->tm_wday+1);
 267
 268                 Q40_RTC_CTRL &= ~(Q40_RTC_WRITE);
 269         }
 270         else
 271         {       /* Read....  */
 272           Q40_RTC_CTRL |= Q40_RTC_READ;
 273
 274           t->tm_year = bcd2bin (Q40_RTC_YEAR);
 275           t->tm_mon  = bcd2bin (Q40_RTC_MNTH)-1;
 276           t->tm_mday = bcd2bin (Q40_RTC_DATE);
 277           t->tm_hour = bcd2bin (Q40_RTC_HOUR);
 278           t->tm_min  = bcd2bin (Q40_RTC_MINS);
 279           t->tm_sec  = bcd2bin (Q40_RTC_SECS);
 280
 281           Q40_RTC_CTRL &= ~(Q40_RTC_READ);
 282
 283           if (t->tm_year < 70)
 284             t->tm_year += 100;
 285           t->tm_wday = bcd2bin(Q40_RTC_DOW)-1;
 286
 287         }
 288
 289         return 0;
 290 }
 291
 292 unsigned int q40_get_ss(void)
 293 {
 294         return bcd2bin(Q40_RTC_SECS);
 295 }
 296
 297 /*
 298  * Set the minutes and seconds from seconds value 'nowtime'.  Fail if
 299  * clock is out by > 30 minutes.  Logic lifted from atari code.
 300  */
 301
 302 int q40_set_clock_mmss (unsigned long nowtime)
 303 {
 304         int retval = 0;
 305         short real_seconds = nowtime % 60, real_minutes = (nowtime / 60) % 60;
 306
 307         int rtc_minutes;
 308
 309
 310         rtc_minutes = bcd2bin (Q40_RTC_MINS);
 311
 312         if ((rtc_minutes < real_minutes
 313                 ? real_minutes - rtc_minutes
 314                         : rtc_minutes - real_minutes) < 30)
 315         {
 316                 Q40_RTC_CTRL |= Q40_RTC_WRITE;
 317                 Q40_RTC_MINS = bin2bcd(real_minutes);
 318                 Q40_RTC_SECS = bin2bcd(real_seconds);
 319                 Q40_RTC_CTRL &= ~(Q40_RTC_WRITE);
 320         }
 321         else
 322                 retval = -1;
 323
 324
 325         return retval;
 326 }
 327
 328
 329 /* get and set PLL calibration of RTC clock */
 330 #define Q40_RTC_PLL_MASK ((1<<5)-1)
 331 #define Q40_RTC_PLL_SIGN (1<<5)
 332
 333 static int q40_get_rtc_pll(struct rtc_pll_info *pll)
 334 {
 335         int tmp=Q40_RTC_CTRL;
 336         pll->pll_value = tmp & Q40_RTC_PLL_MASK;
 337         if (tmp & Q40_RTC_PLL_SIGN)
 338                 pll->pll_value = -pll->pll_value;
 339         pll->pll_max=31;
 340         pll->pll_min=-31;
 341         pll->pll_posmult=512;
 342         pll->pll_negmult=256;
 343         pll->pll_clock=125829120;
 344         return 0;
 345 }
 346
 347 static int q40_set_rtc_pll(struct rtc_pll_info *pll)
 348 {
 349         if (!pll->pll_ctrl){
 350                 /* the docs are a bit unclear so I am doublesetting */
 351                 /* RTC_WRITE here ... */
 352                 int tmp = (pll->pll_value & 31) | (pll->pll_value<0 ? 32 : 0) |
 353                           Q40_RTC_WRITE;
 354                 Q40_RTC_CTRL |= Q40_RTC_WRITE;
 355                 Q40_RTC_CTRL = tmp;
 356                 Q40_RTC_CTRL &= ~(Q40_RTC_WRITE);
 357                 return 0;
 358         } else
 359                 return -EINVAL;
 360 }